xf86-video-intel: src/common.h src/i810_driver.c src/i830_display.c src/i830_driver.c src/i830_lvds.c src/i830_memory.c src/i830_quirks.c src/i965_render.c src/i965_video.c
Zhenyu Wang
zhen at kemper.freedesktop.org
Wed Jul 2 19:48:35 PDT 2008
src/common.h | 20 ++++++++++----------
src/i810_driver.c | 8 ++++----
src/i830_display.c | 6 +++---
src/i830_driver.c | 22 ++++++++++++----------
src/i830_lvds.c | 8 ++++----
src/i830_memory.c | 4 ++--
src/i830_quirks.c | 4 ++--
src/i965_render.c | 2 +-
src/i965_video.c | 2 +-
9 files changed, 39 insertions(+), 37 deletions(-)
New commits:
commit a34a4e3f6420e2b06bbdaa124fe0ccb1bc6a0bd9
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Jul 3 01:03:14 2008 +0800
Fix official name for GM45 chipset
diff --git a/src/common.h b/src/common.h
index b67b20b..57db6cb 100644
--- a/src/common.h
+++ b/src/common.h
@@ -303,9 +303,9 @@ extern int I810_DEBUG;
#define PCI_CHIP_Q33_G_BRIDGE 0x29D0
#endif
-#ifndef PCI_CHIP_IGD_GM
-#define PCI_CHIP_IGD_GM 0x2A42
-#define PCI_CHIP_IGD_GM_BRIDGE 0x2A40
+#ifndef PCI_CHIP_GM45_GM
+#define PCI_CHIP_GM45_GM 0x2A42
+#define PCI_CHIP_GM45_BRIDGE 0x2A40
#endif
#ifndef PCI_CHIP_IGD_E_G
@@ -354,26 +354,26 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
-#define IS_IGD_GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
+#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_IGD_GM(pI810) || IS_G4X(pI810))
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_GM45(pI810) || IS_G4X(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* mark chipsets without overlay hw */
-#define OVERLAY_NOEXIST(pI810) (IS_IGD_GM(pI810) || IS_G4X(pI810))
+#define OVERLAY_NOEXIST(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
/* chipsets require graphics mem for hardware status page */
-#define HWS_NEED_GFX(pI810) (IS_G33CLASS(pI810) || IS_IGD_GM(pI810) || IS_G4X(pI810))
+#define HWS_NEED_GFX(pI810) (IS_G33CLASS(pI810) || IS_GM45(pI810) || IS_G4X(pI810))
/* chipsets require status page in non stolen memory */
-#define HWS_NEED_NONSTOLEN(pI810) (IS_IGD_GM(pI810) || IS_G4X(pI810))
-#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_IGD_GM(pI810) || IS_G4X(pI810))
+#define HWS_NEED_NONSTOLEN(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
+#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
diff --git a/src/i810_driver.c b/src/i810_driver.c
index de4f3cb..8540646 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -152,7 +152,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
@@ -208,7 +208,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
- {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_GM45_GM, "Mobile Intel® GM45 Express Chipset"},
{PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"},
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
@@ -241,7 +241,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
- {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, RES_SHARED_VGA},
{PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA},
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
@@ -808,7 +808,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_G33_G:
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
- case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_GM45_GM:
case PCI_CHIP_IGD_E_G:
case PCI_CHIP_G45_G:
case PCI_CHIP_Q45_G:
diff --git a/src/i830_display.c b/src/i830_display.c
index abe9875..df3a6be 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -668,7 +668,7 @@ i830_enable_fb_compression(xf86CrtcPtr crtc)
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_IGD_GM(pI830))
+ if (IS_GM45(pI830))
return i830_enable_fb_compression2(crtc);
i830_enable_fb_compression_8xx(crtc);
@@ -680,7 +680,7 @@ i830_disable_fb_compression(xf86CrtcPtr crtc)
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_IGD_GM(pI830))
+ if (IS_GM45(pI830))
return i830_disable_fb_compression2(crtc);
i830_disable_fb_compression_8xx(crtc);
@@ -1209,7 +1209,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
break;
}
- if (IS_I965G(pI830) && !IS_IGD_GM(pI830))
+ if (IS_I965G(pI830) && !IS_GM45(pI830))
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
} else {
if (is_lvds) {
diff --git a/src/i830_driver.c b/src/i830_driver.c
index dff7d51..0a49d3a 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -251,7 +251,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
- {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_GM45_GM, "Mobile Intel® GM45 Express Chipset"},
{PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"},
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
@@ -278,7 +278,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
- {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, RES_SHARED_VGA},
{PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA},
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
@@ -653,7 +653,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- if (IS_IGD_GM(pI830) || IS_G4X(pI830)) {
+ if (IS_GM45(pI830) || IS_G4X(pI830)) {
gttaddr = pI830->MMIOAddr + MB(2);
pI830->GTTMapSize = MB(2);
} else {
@@ -973,7 +973,7 @@ i830_init_clock_gating(ScrnInfoPtr pScrn)
/* Disable clock gating reported to work incorrectly according to the specs.
*/
- if (IS_IGD_GM(pI830)) {
+ if (IS_GM45(pI830)) {
OUTREG(RENCLK_GATE_D1, 0);
OUTREG(RENCLK_GATE_D2, 0);
OUTREG(RAMCLK_GATE_D, 0);
@@ -1218,7 +1218,9 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
case PCI_CHIP_Q33_G:
chipname = "Q33";
break;
- case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_GM45_GM:
+ chipname = "Mobile Intel® GM45 Express Chipset";
+ break;
case PCI_CHIP_IGD_E_G:
chipname = "Intel Integrated Graphics Device";
break;
@@ -1985,7 +1987,7 @@ i830_set_dsparb(ScrnInfoPtr pScrn)
* FIFO RAM entries equally between planes A and B.
*/
if (IS_I9XX(pI830)) {
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
OUTREG(DSPARB, (127 << DSPARB_CSTART_SHIFT) |
(64 << DSPARB_BSTART_SHIFT));
else
@@ -2143,7 +2145,7 @@ SaveHWState(ScrnInfoPtr pScrn)
pI830->saveRAMCLK_GATE_D = INREG(RAMCLK_GATE_D);
}
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
pI830->savePWRCTXA = INREG(PWRCTXA);
if (IS_MOBILE(pI830) && !IS_I830(pI830))
@@ -2213,7 +2215,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(RAMCLK_GATE_D, pI830->saveRAMCLK_GATE_D);
}
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
OUTREG(PWRCTXA, pI830->savePWRCTXA);
/*
@@ -2623,7 +2625,7 @@ i830_try_memory_allocation(ScrnInfoPtr pScrn)
if (!i830_allocate_2d_memory(pScrn))
goto failed;
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
if (!i830_allocate_pwrctx(pScrn))
goto failed;
@@ -3036,7 +3038,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
* alone in that case.
* Also make sure the DRM can handle the swap.
*/
- if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_IGD_GM(pI830) &&
+ if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_GM45(pI830) &&
(!pI830->directRenderingEnabled ||
(pI830->directRenderingEnabled && pI830->drmMinor >= 10))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "adjusting plane->pipe mappings "
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index b5e0c45..d1bbb3a 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -134,7 +134,7 @@ i830_set_lvds_backlight_method(xf86OutputPtr output)
if (i830_kernel_backlight_available(output)) {
method = BCM_KERNEL;
- } else if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
+ } else if (IS_I965GM(pI830) || IS_GM45(pI830)) {
blc_pwm_ctl2 = INREG(BLC_PWM_CTL2);
if (blc_pwm_ctl2 & BLM_LEGACY_MODE2)
method = BCM_COMBO;
@@ -182,7 +182,7 @@ i830_lvds_get_backlight_max_native(xf86OutputPtr output)
uint32_t pwm_ctl = INREG(BLC_PWM_CTL);
int val;
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_GM45(pI830)) {
val = ((pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK2) >>
BACKLIGHT_MODULATION_FREQ_SHIFT2);
} else {
@@ -453,7 +453,7 @@ i830_lvds_save (xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
pI830->saveBLC_PWM_CTL2 = INREG(BLC_PWM_CTL2);
pI830->savePP_ON = INREG(LVDSPP_ON);
pI830->savePP_OFF = INREG(LVDSPP_OFF);
@@ -470,7 +470,7 @@ i830_lvds_restore(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
OUTREG(BLC_PWM_CTL2, pI830->saveBLC_PWM_CTL2);
OUTREG(BLC_PWM_CTL, pI830->saveBLC_PWM_CTL);
OUTREG(LVDSPP_ON, pI830->savePP_ON);
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 6e7a838..0a2faeb 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1282,7 +1282,7 @@ static void i830_setup_fb_compression(ScrnInfoPtr pScrn)
goto out;
}
- if (IS_IGD_GM(pI830)) {
+ if (IS_GM45(pI830)) {
/* Update i830_display.c too if compression ratio changes */
compressed_size = fb_height * (pScrn->displayWidth / 4);
} else {
@@ -1309,7 +1309,7 @@ static void i830_setup_fb_compression(ScrnInfoPtr pScrn)
goto out;
}
- if (!IS_IGD_GM(pI830)) {
+ if (!IS_GM45(pI830)) {
pI830->compressed_ll_buffer =
i830_allocate_memory(pScrn, "compressed ll buffer",
FBC_LL_SIZE + FBC_LL_PAD, KB(4),
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index f7659f0..e81b27c 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -266,9 +266,9 @@ static i830_quirk i830_quirk_list[] = {
{ PCI_CHIP_I965_GM, 0x144d, 0xc510, quirk_ignore_tv },
/* HP Compaq 6730s has no TV output */
- { PCI_CHIP_IGD_GM, 0x103c, 0x30e8, quirk_ignore_tv },
+ { PCI_CHIP_GM45_GM, 0x103c, 0x30e8, quirk_ignore_tv },
/* HP Pavilion ze4944ea needs pipe A force quirk (See LP: #242389) */
- { PCI_CHIP_IGD_GM, 0x103c, 0x3084, quirk_pipea_force },
+ { PCI_CHIP_GM45_GM, 0x103c, 0x3084, quirk_pipea_force },
/* Thinkpad R31 needs pipe A force quirk */
{ PCI_CHIP_I830_M, 0x1014, 0x0505, quirk_pipea_force },
diff --git a/src/i965_render.c b/src/i965_render.c
index a3c7f49..a13aec2 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1035,7 +1035,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_IGD_GM(pI830) || IS_G4X(pI830))
+ if (IS_GM45(pI830) || IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
diff --git a/src/i965_video.c b/src/i965_video.c
index 4572e13..4c79259 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -584,7 +584,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_IGD_GM(pI830) || IS_G4X(pI830))
+ if (IS_GM45(pI830) || IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
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