xf86-video-intel: Branch 'intel-batchbuffer' - 30 commits - configure.ac .gitignore man/intel.man src/brw_structs.h src/common.h src/i810_dri.c src/i810_driver.c src/i810_reg.h src/i830_3d.c src/i830_crt.c src/i830_display.c src/i830_dri.c src/i830_driver.c src/i830.h src/i830_i2c.c src/i830_lvds.c src/i830_quirks.c src/i830_sdvo.c src/i830_tv.c src/i830_video.c src/i965_render.c src/i965_video.c src/ivch/ivch.c
Dave Airlie
airlied at kemper.freedesktop.org
Mon Jan 21 20:03:03 PST 2008
.gitignore | 1
configure.ac | 1
man/intel.man | 87 ++++++++++++++++++++++++++------
src/brw_structs.h | 12 +++-
src/common.h | 26 +++++++--
src/i810_dri.c | 28 +++++-----
src/i810_driver.c | 14 +++--
src/i810_reg.h | 5 +
src/i830.h | 21 ++++---
src/i830_3d.c | 134 +++++++++++++++++++++++++++++++++++++++++++++++---
src/i830_crt.c | 41 ++++++++-------
src/i830_display.c | 20 ++++---
src/i830_dri.c | 28 +++++-----
src/i830_driver.c | 142 +++++++++++++++++++++++++++++++++++++++--------------
src/i830_i2c.c | 2
src/i830_lvds.c | 79 +++++++++++++++++++----------
src/i830_quirks.c | 20 +++++--
src/i830_sdvo.c | 6 +-
src/i830_tv.c | 2
src/i830_video.c | 2
src/i965_render.c | 6 +-
src/i965_video.c | 6 +-
src/ivch/ivch.c | 1
23 files changed, 507 insertions(+), 177 deletions(-)
New commits:
commit a8130b7b2b30c482de820606c9e790c5dec1c3c3
Merge: 8b598e9... f54bba7...
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Jan 22 14:55:22 2008 +1100
Merge branch 'master' into intel-batchbuffer
Conflicts:
src/i830_3d.c
src/i965_render.c
src/i965_video.c
diff --cc src/i830.h
index cbc1b93,9adbaf7..923704c
--- a/src/i830.h
+++ b/src/i830.h
@@@ -854,8 -836,7 +856,9 @@@ extern const int I830CopyROP[16]
#define QUIRK_IGNORE_TV 0x00000001
#define QUIRK_IGNORE_LVDS 0x00000002
#define QUIRK_IGNORE_MACMINI_LVDS 0x00000004
+ #define QUIRK_PIPEA_FORCE 0x00000008
extern void i830_fixup_devices(ScrnInfoPtr);
+#include "intel_batchbuffer.h"
+
#endif /* _I830_H_ */
diff --cc src/i830_3d.c
index 777cf3d,45e02c4..be6cf6b
--- a/src/i830_3d.c
+++ b/src/i830_3d.c
@@@ -38,32 -38,31 +38,31 @@@ void I830EmitInvarientState( ScrnInfoPt
{
I830Ptr pI830 = I830PTR(pScrn);
- BEGIN_BATCH(40);
- BEGIN_LP_RING(58);
++ BEGIN_BATCH(58);
- OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
- OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
- OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
- OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
+ OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
+ OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
+ OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
+ OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
- OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD);
- OUT_RING(0);
+ OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
+ OUT_BATCH(0);
- OUT_RING(_3DSTATE_DFLT_SPEC_CMD);
- OUT_RING(0);
+ OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
+ OUT_BATCH(0);
- OUT_RING(_3DSTATE_DFLT_Z_CMD);
- OUT_RING(0);
+ OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
+ OUT_BATCH(0);
- OUT_RING(_3DSTATE_FOG_MODE_CMD);
- OUT_RING(FOGFUNC_ENABLE |
+ OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
+ OUT_BATCH(FOGFUNC_ENABLE |
FOG_LINEAR_CONST |
FOGSRC_INDEX_Z |
ENABLE_FOG_DENSITY);
- OUT_RING(0);
- OUT_RING(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
-
- OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
+ OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
MAP_UNIT(0) |
DISABLE_TEX_STREAM_BUMP |
ENABLE_TEX_STREAM_COORD_SET |
@@@ -88,22 -87,16 +87,17 @@@
TEX_STREAM_COORD_SET(3) |
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
- OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
- OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
- OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
- OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
- OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
- OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
- OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
- OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
-
- OUT_RING(_3DSTATE_RASTER_RULES_CMD |
+ OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
+ OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
+ OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
+ OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
+ OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
+ OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
+ OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
+ OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
+
- OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
- OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
- TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
- TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
- TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
+
+ OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
@@@ -113,23 -106,147 +107,147 @@@
TRI_FAN_PROVOKE_VRTX(2) |
TRI_STRIP_PROVOKE_VRTX(2));
- OUT_RING(_3DSTATE_SCISSOR_ENABLE_CMD |
+ OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD |
DISABLE_SCISSOR_RECT);
- OUT_RING(_3DSTATE_SCISSOR_RECT_0_CMD);
- OUT_RING(0);
- OUT_RING(0);
+ OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
- OUT_RING(_3DSTATE_VERTEX_TRANSFORM);
- OUT_RING(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
+ OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
+ OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
- OUT_RING(_3DSTATE_W_STATE_CMD);
- OUT_RING(MAGIC_W_STATE_DWORD1);
- OUT_RING(0x3f800000 /* 1.0 in IEEE float */ );
+ OUT_BATCH(_3DSTATE_W_STATE_CMD);
+ OUT_BATCH(MAGIC_W_STATE_DWORD1);
+ OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
-
- OUT_RING(_3DSTATE_COLOR_FACTOR_CMD);
- OUT_RING(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
+ OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
+ OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
- OUT_RING(_3DSTATE_MAP_COORD_SETBIND_CMD);
- OUT_RING(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
++ OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
++ OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
+ TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
+ TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
+ TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
+
+ /* copy from mesa */
- OUT_RING(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
++ OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
+ DISABLE_INDPT_ALPHA_BLEND |
+ ENABLE_ALPHA_BLENDFUNC |
+ ABLENDFUNC_ADD);
+
- OUT_RING(_3DSTATE_FOG_COLOR_CMD |
++ OUT_BATCH(_3DSTATE_FOG_COLOR_CMD |
+ FOG_COLOR_RED(0) |
+ FOG_COLOR_GREEN(0) |
+ FOG_COLOR_BLUE(0));
+
- OUT_RING(_3DSTATE_CONST_BLEND_COLOR_CMD);
- OUT_RING(0);
++ OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
++ OUT_BATCH(0);
+
- OUT_RING(_3DSTATE_MODES_1_CMD |
++ OUT_BATCH(_3DSTATE_MODES_1_CMD |
+ ENABLE_COLR_BLND_FUNC |
+ BLENDFUNC_ADD |
+ ENABLE_SRC_BLND_FACTOR |
+ SRC_BLND_FACT(BLENDFACTOR_ONE) |
+ ENABLE_DST_BLND_FACTOR |
+ DST_BLND_FACT(BLENDFACTOR_ZERO));
- OUT_RING(_3DSTATE_MODES_2_CMD |
++ OUT_BATCH(_3DSTATE_MODES_2_CMD |
+ ENABLE_GLOBAL_DEPTH_BIAS |
+ GLOBAL_DEPTH_BIAS(0) |
+ ENABLE_ALPHA_TEST_FUNC|
+ ALPHA_TEST_FUNC(0) | /* always */
+ ALPHA_REF_VALUE(0));
- OUT_RING(_3DSTATE_MODES_3_CMD |
++ OUT_BATCH(_3DSTATE_MODES_3_CMD |
+ ENABLE_DEPTH_TEST_FUNC |
+ DEPTH_TEST_FUNC(0x2) | /* COMPAREFUNC_LESS */
+ ENABLE_ALPHA_SHADE_MODE |
+ ALPHA_SHADE_MODE(SHADE_MODE_LINEAR)
+ | ENABLE_FOG_SHADE_MODE |
+ FOG_SHADE_MODE(SHADE_MODE_LINEAR) |
+ ENABLE_SPEC_SHADE_MODE |
+ SPEC_SHADE_MODE(SHADE_MODE_LINEAR) |
+ ENABLE_COLOR_SHADE_MODE |
+ COLOR_SHADE_MODE(SHADE_MODE_LINEAR)
+ | ENABLE_CULL_MODE | CULLMODE_NONE);
+
- OUT_RING(_3DSTATE_MODES_4_CMD |
++ OUT_BATCH(_3DSTATE_MODES_4_CMD |
+ ENABLE_LOGIC_OP_FUNC |
+ LOGIC_OP_FUNC(LOGICOP_COPY) |
+ ENABLE_STENCIL_TEST_MASK |
+ STENCIL_TEST_MASK(0xff) |
+ ENABLE_STENCIL_WRITE_MASK |
+ STENCIL_WRITE_MASK(0xff));
+
- OUT_RING(_3DSTATE_STENCIL_TEST_CMD |
++ OUT_BATCH(_3DSTATE_STENCIL_TEST_CMD |
+ ENABLE_STENCIL_PARMS |
+ STENCIL_FAIL_OP(0) | /* STENCILOP_KEEP */
+ STENCIL_PASS_DEPTH_FAIL_OP(0) | /* STENCILOP_KEEP */
+ STENCIL_PASS_DEPTH_PASS_OP(0) | /* STENCILOP_KEEP */
+ ENABLE_STENCIL_TEST_FUNC |
+ STENCIL_TEST_FUNC(0) | /* COMPAREFUNC_ALWAYS */
+ ENABLE_STENCIL_REF_VALUE |
+ STENCIL_REF_VALUE(0));
+
- OUT_RING(_3DSTATE_MODES_5_CMD |
++ OUT_BATCH(_3DSTATE_MODES_5_CMD |
+ FLUSH_TEXTURE_CACHE |
+ ENABLE_SPRITE_POINT_TEX |
+ SPRITE_POINT_TEX_OFF |
+ ENABLE_FIXED_LINE_WIDTH |
+ FIXED_LINE_WIDTH(0x2) | /* 1.0 */
+ ENABLE_FIXED_POINT_WIDTH |
+ FIXED_POINT_WIDTH(1));
+
- OUT_RING(_3DSTATE_ENABLES_1_CMD |
++ OUT_BATCH(_3DSTATE_ENABLES_1_CMD |
+ DISABLE_LOGIC_OP |
+ DISABLE_STENCIL_TEST |
+ DISABLE_DEPTH_BIAS |
+ DISABLE_SPEC_ADD |
+ DISABLE_FOG |
+ DISABLE_ALPHA_TEST |
+ ENABLE_COLOR_BLEND |
+ DISABLE_DEPTH_TEST);
- OUT_RING(_3DSTATE_ENABLES_2_CMD |
++ OUT_BATCH(_3DSTATE_ENABLES_2_CMD |
+ DISABLE_STENCIL_WRITE |
+ ENABLE_TEX_CACHE |
+ DISABLE_DITHER |
+ ENABLE_COLOR_MASK |
+ ENABLE_COLOR_WRITE |
+ DISABLE_DEPTH_WRITE);
+
- OUT_RING(_3DSTATE_STIPPLE);
++ OUT_BATCH(_3DSTATE_STIPPLE);
+
+ /* Set default blend state */
- OUT_RING(_3DSTATE_MAP_BLEND_OP_CMD(0) |
++ OUT_BATCH(_3DSTATE_MAP_BLEND_OP_CMD(0) |
+ TEXPIPE_COLOR |
+ ENABLE_TEXOUTPUT_WRT_SEL |
+ TEXOP_OUTPUT_CURRENT |
+ DISABLE_TEX_CNTRL_STAGE |
+ TEXOP_SCALE_1X |
+ TEXOP_MODIFY_PARMS |
+ TEXOP_LAST_STAGE | TEXBLENDOP_ARG1);
- OUT_RING(_3DSTATE_MAP_BLEND_OP_CMD(0) |
++ OUT_BATCH(_3DSTATE_MAP_BLEND_OP_CMD(0) |
+ TEXPIPE_ALPHA |
+ ENABLE_TEXOUTPUT_WRT_SEL |
+ TEXOP_OUTPUT_CURRENT |
+ TEXOP_SCALE_1X |
+ TEXOP_MODIFY_PARMS | TEXBLENDOP_ARG1);
- OUT_RING(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
++ OUT_BATCH(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
+ TEXPIPE_COLOR |
+ TEXBLEND_ARG1 |
+ TEXBLENDARG_MODIFY_PARMS |
+ TEXBLENDARG_DIFFUSE);
- OUT_RING(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
++ OUT_BATCH(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
+ TEXPIPE_ALPHA |
+ TEXBLEND_ARG1 |
+ TEXBLENDARG_MODIFY_PARMS |
+ TEXBLENDARG_DIFFUSE);
+
- OUT_RING(_3DSTATE_AA_CMD |
++ OUT_BATCH(_3DSTATE_AA_CMD |
+ AA_LINE_ECAAR_WIDTH_ENABLE |
+ AA_LINE_ECAAR_WIDTH_1_0 |
+ AA_LINE_REGION_WIDTH_ENABLE |
+ AA_LINE_REGION_WIDTH_1_0 |
+ AA_LINE_DISABLE);
+
- ADVANCE_LP_RING();
+ ADVANCE_BATCH();
}
diff --cc src/i965_render.c
index 142200e,4b1d7f3..79ba9d9
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@@ -971,21 -923,24 +971,25 @@@ i965_prepare_composite(int op, PictureP
* rendering pipe
*/
{
- BEGIN_LP_RING(2);
- OUT_RING(MI_FLUSH |
- MI_STATE_INSTRUCTION_CACHE_FLUSH |
- BRW_MI_GLOBAL_SNAPSHOT_RESET);
- OUT_RING(MI_NOOP);
- ADVANCE_LP_RING();
+ BEGIN_BATCH(2);
+ OUT_BATCH(MI_FLUSH |
+ MI_STATE_INSTRUCTION_CACHE_FLUSH |
+ BRW_MI_GLOBAL_SNAPSHOT_RESET);
+ OUT_BATCH(MI_NOOP);
+ ADVANCE_BATCH();
}
{
- BEGIN_LP_RING(12);
+ BEGIN_BATCH(12);
/* Match Mesa driver setup */
- OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
- if (IS_IGD_GM(pI830))
- OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
- else
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
++ if (IS_IGD_GM(pI830)) {
++ OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
++ } else {
++ OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
++ }
- OUT_RING(BRW_CS_URB_STATE | 0);
- OUT_RING((0 << 4) | /* URB Entry Allocation Size */
+ OUT_BATCH(BRW_CS_URB_STATE | 0);
+ OUT_BATCH((0 << 4) | /* URB Entry Allocation Size */
(0 << 0)); /* Number of URB Entries */
/* Zero out the two base address registers so all offsets are
diff --cc src/i965_video.c
index 867e936,928b52b..6d04613
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@@ -507,13 -507,16 +507,17 @@@ I965DisplayVideoTextured(ScrnInfoPtr pS
/* brw_debug (pScrn, "before base address modify"); */
{
- BEGIN_LP_RING(12);
+ BEGIN_BATCH(12);
/* Match Mesa driver setup */
- OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
- if (IS_IGD_GM(pI830))
- OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
- else
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
++ if (IS_IGD_GM(pI830)) {
++ OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
++ } else {
++ OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
++ }
/* Mesa does this. Who knows... */
- OUT_RING(BRW_CS_URB_STATE | 0);
- OUT_RING((0 << 4) | /* URB Entry Allocation Size */
+ OUT_BATCH(BRW_CS_URB_STATE | 0);
+ OUT_BATCH((0 << 4) | /* URB Entry Allocation Size */
(0 << 0)); /* Number of URB Entries */
/* Zero out the two base address registers so all offsets are
commit f54bba7600647c76fe3bd2d0133edc06dbea6a05
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Tue Jan 22 00:48:23 2008 +0800
Add missing i830M and 845G pci ids info
diff --git a/src/common.h b/src/common.h
index 7737194..3a11e59 100644
--- a/src/common.h
+++ b/src/common.h
@@ -298,6 +298,16 @@ extern int I810_DEBUG;
#define PCI_CHIP_I815_BRIDGE 0x1130
#endif
+#ifndef PCI_CHIP_I830_M
+#define PCI_CHIP_I830_M 0x3577
+#define PCI_CHIP_I830_M_BRIDGE 0x3575
+#endif
+
+#ifndef PCI_CHIP_845_G
+#define PCI_CHIP_845_G 0x2562
+#define PCI_CHIP_845_G_BRIDGE 0x2560
+#endif
+
#ifndef PCI_CHIP_I855_GM
#define PCI_CHIP_I855_GM 0x3582
#define PCI_CHIP_I855_GM_BRIDGE 0x3580
commit 633dbd28218fd8a746c1735fd44a14f35bd07faa
Author: Julien Cristau <jcristau at debian.org>
Date: Thu Jan 17 22:34:21 2008 +0800
Bug 14032: i810, set default depth to 16
X fails to start without an xorg.conf on i810, because the default depth set by
the server (32) is not supported by the driver. I think the driver should
default to 16 bits (it supports 24, but when I tested it that didn't seem to
work very well, and dri is disabled at 24 bits depth anyway) instead of letting
the server use 32 and failing later on.
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 1ecb04a..53121a6 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -954,7 +954,7 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
pScrn->monitor = pScrn->confScreen->monitor;
flags24 = Support24bppFb | PreferConvert32to24 | SupportConvert32to24;
- if (!xf86SetDepthBpp(pScrn, 0, 0, 0, flags24)) {
+ if (!xf86SetDepthBpp(pScrn, 16, 0, 16, flags24)) {
return FALSE;
} else {
switch (pScrn->depth) {
commit 4fec18e07f2b23306e885d63c74661ae0e4b04d9
Author: Jesse Barnes <jesse.barnes at intel.com>
Date: Fri Jan 11 10:28:59 2008 -0800
Turn on backlight when LVDS panel is powered up
In some configurations, the LVDS may be off at startup along with the
backlight. So when turning the LVDS on for the first time, we may also need to
set the backlight to a non-zero value. So try to use the saved value if
possible, but if it's zero, make the backlight full brightness when turning on
the LVDS.
Note that this is slightly sub-optimal for configurations where zero is a valid backlight brightness.
Fixes fdo bz #13958.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index 50ecb60..ef8fa4a 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -372,6 +372,17 @@ i830SetLVDSPanelPower(xf86OutputPtr output, Bool on)
CARD32 pp_status;
if (on) {
+ /*
+ * If we're going from off->on we may need to turn on the backlight.
+ * We should use the saved value whenever possible, but on some
+ * machines 0 is a valid backlight value (due to an external backlight
+ * controller for example), so on them, when turning LVDS back on,
+ * they'll always re-maximize the brightness.
+ */
+ if (!(INREG(PP_CONTROL) & POWER_TARGET_ON) &&
+ dev_priv->backlight_duty_cycle == 0)
+ dev_priv->backlight_duty_cycle = dev_priv->backlight_max;
+
OUTREG(PP_CONTROL, INREG(PP_CONTROL) | POWER_TARGET_ON);
do {
pp_status = INREG(PP_STATUS);
commit b5cf8faf8102e6313c23de87a680cc327ac95478
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Thu Jan 10 14:25:18 2008 -0800
Remove unnecessary quirk code in CRT probing
Since we return early in the CRTC DPMS code, keeping the pipes & clocks
enabled, this code is no longer necessary. As an added bonus, VGA connections
should be reported correctly even when the pipe A quirk is active.
Updates fix for fdo bz #11432.
diff --git a/src/i830_crt.c b/src/i830_crt.c
index 3f0fc46..82a774a 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -381,13 +381,6 @@ i830_crt_detect(xf86OutputPtr output)
out:
i830ReleaseLoadDetectPipe (output, dpms_mode);
- /* Needed for some machines where the BIOS pokes at pipe A */
- if (pI830->quirk_flag & QUIRK_PIPEA_FORCE) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Overriding VGA detection, "
- "forcing pipe A on.\n");
- status = XF86OutputStatusConnected;
- }
-
return status;
}
commit 3c22ed633be2ac96eea7bc533839e956f1f31b84
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Wed Jan 9 09:47:38 2008 -0800
Add pipe A force enable quirk
On some platforms, the firmware may read & write GPU registers on lid close,
suspend/resume time or during various SMM events. If one of the graphics pipes
is disabled at that time, the GPU may hang due to the programming dependencies
of the various registers.
This patch adds a quirk to force the driver to keep pipe A enabled if
necessary, through user configuration in xorg.conf or via a platform specific
quirk. Leaving the pipe enabled comes at a power cost however, so the quirk
should only be enabled when strictly necessary.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=11432.
diff --git a/man/intel.man b/man/intel.man
index d46e3f9..e5736e5 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -175,6 +175,13 @@ Default: "EXA".
.BI "Option \*qModeDebug\*q \*q" boolean \*q
Enable printing of additional debugging information about modesetting to
the server log.
+.TP
+.BI "Option \*qForceEnablePipeA\*q \*q" boolean \*q
+Force the driver to leave pipe A enabled. May be necessary in configurations
+where the BIOS accesses pipe registers during display hotswitch or lid close,
+causing a crash. If you find that your platform needs this option, please file
+a bug against xf86-video-intel at http://bugs.freedesktop.org which includes
+the output of 'lspci -v' and 'lspci -vn'.
.SH OUTPUT CONFIGURATION
On 830M and better chipsets, the driver supports runtime configuration of
diff --git a/src/i830.h b/src/i830.h
index dcb87cc..9adbaf7 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -836,6 +836,7 @@ extern const int I830CopyROP[16];
#define QUIRK_IGNORE_TV 0x00000001
#define QUIRK_IGNORE_LVDS 0x00000002
#define QUIRK_IGNORE_MACMINI_LVDS 0x00000004
+#define QUIRK_PIPEA_FORCE 0x00000008
extern void i830_fixup_devices(ScrnInfoPtr);
#endif /* _I830_H_ */
diff --git a/src/i830_crt.c b/src/i830_crt.c
index cd71dc5..3f0fc46 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -380,6 +380,14 @@ i830_crt_detect(xf86OutputPtr output)
out:
i830ReleaseLoadDetectPipe (output, dpms_mode);
+
+ /* Needed for some machines where the BIOS pokes at pipe A */
+ if (pI830->quirk_flag & QUIRK_PIPEA_FORCE) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Overriding VGA detection, "
+ "forcing pipe A on.\n");
+ status = XF86OutputStatusConnected;
+ }
+
return status;
}
diff --git a/src/i830_display.c b/src/i830_display.c
index 0e42624..d16871d 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -724,6 +724,10 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
/* Give the overlay scaler a chance to disable if it's on this pipe */
i830_crtc_dpms_video(crtc, FALSE);
+ /* May need to leave pipe A on */
+ if ((pipe == 0) && (pI830->quirk_flag & QUIRK_PIPEA_FORCE))
+ return;
+
/* Disable the VGA plane that we never use */
OUTREG(VGACNTRL, VGA_DISP_DISABLE);
@@ -1176,14 +1180,6 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
i830PrintPll("chosen", &clock);
}
- if (dpll & DPLL_VCO_ENABLE)
- {
- OUTREG(fp_reg, fp);
- OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
- POSTING_READ(dpll_reg);
- usleep(150);
- }
-
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
* This is an exception to the general rule that mode_set doesn't turn
* things on.
@@ -1192,6 +1188,14 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
{
CARD32 lvds = INREG(LVDS);
+ if (dpll & DPLL_VCO_ENABLE)
+ {
+ OUTREG(fp_reg, fp);
+ OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+ POSTING_READ(dpll_reg);
+ usleep(150);
+ }
+
lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
/* Set the B0-B3 data pairs corresponding to whether we're going to
* set the DPLLs for dual-channel mode or not.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 32d4602..32cecff 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -298,6 +298,7 @@ typedef enum {
OPTION_INTELTEXPOOL,
#endif
OPTION_TRIPLEBUFFER,
+ OPTION_FORCEENABLEPIPEA
} I830Opts;
static OptionInfoRec I830Options[] = {
@@ -320,6 +321,7 @@ static OptionInfoRec I830Options[] = {
{OPTION_INTELTEXPOOL,"Legacy3D", OPTV_BOOLEAN, {0}, FALSE},
#endif
{OPTION_TRIPLEBUFFER, "TripleBuffer", OPTV_BOOLEAN, {0}, FALSE},
+ {OPTION_FORCEENABLEPIPEA, "ForceEnablePipeA", OPTV_BOOLEAN, {0}, FALSE},
{-1, NULL, OPTV_NONE, {0}, FALSE}
};
/* *INDENT-ON* */
@@ -1193,6 +1195,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
pI830->debug_modes = FALSE;
}
+ if (xf86ReturnOptValBool(pI830->Options, OPTION_FORCEENABLEPIPEA, FALSE))
+ pI830->quirk_flag |= QUIRK_PIPEA_FORCE;
+
/* We have to use PIO to probe, because we haven't mapped yet. */
I830SetPIOAccess(pI830);
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 323962c..8fbdbfe 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -39,6 +39,11 @@ typedef struct {
void (*hook)(I830Ptr);
} i830_quirk, *i830_quirk_ptr;
+static void quirk_pipea_force (I830Ptr pI830)
+{
+ pI830->quirk_flag |= QUIRK_PIPEA_FORCE;
+}
+
static void quirk_ignore_tv (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_TV;
@@ -86,6 +91,10 @@ static i830_quirk i830_quirk_list[] = {
/* Samsung Q35 has no TV output */
{ PCI_CHIP_I945_GM, 0x144d, 0xc504, quirk_ignore_tv },
+
+ /* Dell Inspiron 510m needs pipe A force quirk */
+ { PCI_CHIP_I855_GM, 0x1028, 0x0164, quirk_pipea_force },
+
{ 0, 0, 0, NULL },
};
commit d3b41bcf231a6ffd289c128c06aa619f554a776c
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:28:25 2008 +0800
Disable frame buffer compression on new chipset now.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 2183b1d..32d4602 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2510,7 +2510,8 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
}
/* Enable FB compression if possible */
- if (i830_fb_compression_supported(pI830) && !IS_I965GM(pI830))
+ if (i830_fb_compression_supported(pI830) && !IS_I965GM(pI830)
+ && !IS_IGD_GM(pI830))
pI830->fb_compression = TRUE;
else
pI830->fb_compression = FALSE;
commit 2f0c0427dc4113bac64cda07c6365df1f0637697
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:27:42 2008 +0800
Update PIPELINE_SELECT instruction and surface state format for new chipset
diff --git a/src/brw_structs.h b/src/brw_structs.h
index 28d8e12..d4fc5c6 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
@@ -832,9 +832,8 @@ struct brw_wm_unit_state
unsigned int program_computes_depth:1;
unsigned int program_uses_killpixel:1;
unsigned int legacy_line_rast: 1;
- unsigned int pad1:1;
- unsigned int max_threads:6;
- unsigned int pad2:1;
+ unsigned int transposed_urb_read:1;
+ unsigned int max_threads:7;
} wm5;
float global_depth_offset_constant;
@@ -977,6 +976,13 @@ struct brw_surface_state
unsigned int min_array_elt:9;
unsigned int min_lod:4;
} ss4;
+
+ struct {
+ unsigned int pad:20;
+ unsigned int y_offset:4;
+ unsigned int pad2:1;
+ unsigned int x_offset:7;
+ } ss5;
};
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 26f9db4..bed3901 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -2284,6 +2284,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BRW_STATE_SIP BRW_3D(0, 1, 2)
#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4)
+#define NEW_PIPELINE_SELECT BRW_3D(1, 1, 4)
+
#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0)
#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0)
diff --git a/src/i965_render.c b/src/i965_render.c
index ad3b53e..4b1d7f3 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -907,6 +907,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
src_sampler_offset) >> 5;
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
+ wm_state->wm5.transposed_urb_read = 0;
wm_state->wm5.thread_dispatch_enable = 1;
/* just use 16-pixel dispatch (4 subspans), don't need to change kernel
* start point
@@ -933,7 +934,10 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_LP_RING(12);
/* Match Mesa driver setup */
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ if (IS_IGD_GM(pI830))
+ OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
OUT_RING(BRW_CS_URB_STATE | 0);
OUT_RING((0 << 4) | /* URB Entry Allocation Size */
diff --git a/src/i965_video.c b/src/i965_video.c
index 0357270..928b52b 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -509,7 +509,10 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_LP_RING(12);
/* Match Mesa driver setup */
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ if (IS_IGD_GM(pI830))
+ OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
/* Mesa does this. Who knows... */
OUT_RING(BRW_CS_URB_STATE | 0);
commit 139e9affdd49dcbe08e260a0a2bd001de16566e6
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:26:57 2008 +0800
GTT access change for new integrated graphics device
diff --git a/src/i810_reg.h b/src/i810_reg.h
index a6663a4..26f9db4 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -539,6 +539,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PGETBL_SIZE_512KB (0 << 1)
#define PGETBL_SIZE_256KB (1 << 1)
#define PGETBL_SIZE_128KB (2 << 1)
+#define PGETBL_SIZE_1MB (3 << 1)
+#define PGETBL_SIZE_2MB (4 << 1)
+#define PGETBL_SIZE_1_5MB (5 << 1)
#define G33_PGETBL_SIZE_MASK (3 << 8)
#define G33_PGETBL_SIZE_1M (1 << 8)
#define G33_PGETBL_SIZE_2M (2 << 8)
diff --git a/src/i830_driver.c b/src/i830_driver.c
index eeb5ed0..2183b1d 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -455,6 +455,15 @@ I830DetectMemory(ScrnInfoPtr pScrn)
case PGETBL_SIZE_128KB:
gtt_size = 128;
break;
+ case PGETBL_SIZE_1MB:
+ gtt_size = 1024;
+ break;
+ case PGETBL_SIZE_2MB:
+ gtt_size = 2048;
+ break;
+ case PGETBL_SIZE_1_5MB:
+ gtt_size = 1024 + 512;
+ break;
default:
FatalError("Unknown GTT size value: %08x\n", (int)INREG(PGETBL_CTL));
}
@@ -509,11 +518,11 @@ I830DetectMemory(ScrnInfoPtr pScrn)
memsize = MB(64) - KB(range);
break;
case G33_GMCH_GMS_STOLEN_128M:
- if (IS_G33CLASS(pI830))
+ if (IS_I9XX(pI830))
memsize = MB(128) - KB(range);
break;
case G33_GMCH_GMS_STOLEN_256M:
- if (IS_G33CLASS(pI830))
+ if (IS_I9XX(pI830))
memsize = MB(256) - KB(range);
break;
}
@@ -599,8 +608,13 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- gttaddr = pI830->MMIOAddr + (512 * 1024);
- pI830->GTTMapSize = 512 * 1024;
+ if (IS_IGD_GM(pI830)) {
+ gttaddr = pI830->MMIOAddr + MB(2);
+ pI830->GTTMapSize = MB(2);
+ } else {
+ gttaddr = pI830->MMIOAddr + KB(512);
+ pI830->GTTMapSize = KB(512);
+ }
}
else
{
commit 4f288ff2d1e7d28bf49167f073fbce21492a7c32
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:25:47 2008 +0800
Add new integrated graphics chipset ids
diff --git a/src/common.h b/src/common.h
index daab52c..7737194 100644
--- a/src/common.h
+++ b/src/common.h
@@ -384,6 +384,11 @@ extern int I810_DEBUG;
#define PCI_CHIP_Q33_G_BRIDGE 0x29D0
#endif
+#ifndef PCI_CHIP_IGD_GM
+#define PCI_CHIP_IGD_GM 0x2A42
+#define PCI_CHIP_IGD_GM_BRIDGE 0x2A40
+#endif
+
#if XSERVER_LIBPCIACCESS
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
#define VENDOR_ID(p) (p)->vendor_id
@@ -415,14 +420,15 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
+#define IS_IGD_GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_IGD_GM(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810))
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 8ae35b6..1ecb04a 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -152,6 +152,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
{ 0, 0, 0 },
};
@@ -204,6 +205,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
+ {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
{-1, NULL}
};
@@ -233,6 +235,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
@@ -796,6 +799,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_G33_G:
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
+ case PCI_CHIP_IGD_GM:
xf86SetEntitySharable(usedChips[i]);
/* Allocate an entity private if necessary */
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 9a59be1..eeb5ed0 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -244,6 +244,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
+ {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
{-1, NULL}
};
@@ -267,6 +268,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED}
};
@@ -1263,6 +1265,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
case PCI_CHIP_Q33_G:
chipname = "Q33";
break;
+ case PCI_CHIP_IGD_GM:
+ chipname = "Intel Integrated Graphics Device";
+ break;
default:
chipname = "unknown chipset";
break;
@@ -2783,7 +2788,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
* alone in that case.
* Also make sure the DRM can handle the swap.
*/
- if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) &&
+ if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_IGD_GM(pI830) &&
(!pI830->directRenderingEnabled ||
(pI830->directRenderingEnabled && pI830->drmMinor >= 10))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "adjusting plane->pipe mappings "
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index cf0e345..50ecb60 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -113,7 +113,7 @@ i830_set_lvds_backlight_method(xf86OutputPtr output)
if (i830_kernel_backlight_available(output)) {
method = BCM_KERNEL;
- } else if (IS_I965GM(pI830)) {
+ } else if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
blc_pwm_ctl2 = INREG(BLC_PWM_CTL2);
if (blc_pwm_ctl2 & BLM_LEGACY_MODE2)
method = BCM_LEGACY;
@@ -161,7 +161,7 @@ i830_lvds_get_backlight_max_native(xf86OutputPtr output)
CARD32 pwm_ctl = INREG(BLC_PWM_CTL);
int val;
- if (IS_I965GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
val = ((pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK2) >>
BACKLIGHT_MODULATION_FREQ_SHIFT2);
} else {
@@ -413,7 +413,7 @@ i830_lvds_save (xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830))
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
pI830->saveBLC_PWM_CTL2 = INREG(BLC_PWM_CTL2);
pI830->savePP_ON = INREG(LVDSPP_ON);
pI830->savePP_OFF = INREG(LVDSPP_OFF);
@@ -429,7 +429,7 @@ i830_lvds_restore(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830))
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
OUTREG(BLC_PWM_CTL2, pI830->saveBLC_PWM_CTL2);
OUTREG(BLC_PWM_CTL, pI830->saveBLC_PWM_CTL);
OUTREG(LVDSPP_ON, pI830->savePP_ON);
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 6b7037e..4b04994 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -727,7 +727,7 @@ i830_sdvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
}
/* Set the SDVO control regs. */
- if (IS_I965GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
sdvox = SDVO_BORDER_ENABLE;
} else {
sdvox = INREG(dev_priv->output_device);
commit f089942689df622b1af00569eade4883a84eb7a3
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Jan 3 11:28:18 2008 +0800
Change origin i965G_1 to chipset market name G35.
diff --git a/src/common.h b/src/common.h
index 40ea038..daab52c 100644
--- a/src/common.h
+++ b/src/common.h
@@ -339,9 +339,9 @@ extern int I810_DEBUG;
#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
#endif
-#ifndef PCI_CHIP_I965_G_1
-#define PCI_CHIP_I965_G_1 0x2982
-#define PCI_CHIP_I965_G_1_BRIDGE 0x2980
+#ifndef PCI_CHIP_G35_G
+#define PCI_CHIP_G35_G 0x2982
+#define PCI_CHIP_G35_G_BRIDGE 0x2980
#endif
#ifndef PCI_CHIP_I965_Q
@@ -416,7 +416,7 @@ extern int I810_DEBUG;
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G_1 || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
diff --git a/src/i810_driver.c b/src/i810_driver.c
index a6c13ed..8ae35b6 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -144,7 +144,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I965_G_1, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ),
@@ -196,7 +196,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
{PCI_CHIP_I965_G, "965G"},
- {PCI_CHIP_I965_G_1, "965G"},
+ {PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{PCI_CHIP_I965_GM, "965GM"},
@@ -225,7 +225,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
- {PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
+ {PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, RES_SHARED_VGA},
@@ -788,7 +788,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
case PCI_CHIP_I965_G:
- case PCI_CHIP_I965_G_1:
+ case PCI_CHIP_G35_G:
case PCI_CHIP_I965_Q:
case PCI_CHIP_I946_GZ:
case PCI_CHIP_I965_GM:
diff --git a/src/i830_driver.c b/src/i830_driver.c
index ca4544d..9a59be1 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -236,7 +236,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
{PCI_CHIP_I965_G, "965G"},
- {PCI_CHIP_I965_G_1, "965G"},
+ {PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{PCI_CHIP_I965_GM, "965GM"},
@@ -259,7 +259,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
- {PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
+ {PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, RES_SHARED_VGA},
@@ -1237,9 +1237,11 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
chipname = "945GME";
break;
case PCI_CHIP_I965_G:
- case PCI_CHIP_I965_G_1:
chipname = "965G";
break;
+ case PCI_CHIP_G35_G:
+ chipname = "G35";
+ break;
case PCI_CHIP_I965_Q:
chipname = "965Q";
break;
commit 71143200ed66cb9dcc1f9edf98128be80b05619c
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Fri Jan 4 15:01:25 2008 -0800
Don't modify low bit of BLC_PWM_CTL when using combo backlight control
On some platforms, the low bit of BLC_PWM_CTL is wired as a 'max brightness'
flag, rather than a regular part of the backlight duty cycle. So when in the
combo mode, divide the total number of backlight levels available by two
(tossing one bit) and adjust the programming in the set_brightness routine.
Note that platforms with this behavior may need quirks added so that they work
by default.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index c58a7e0..cf0e345 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -234,6 +234,12 @@ i830_lvds_set_backlight_combo(xf86OutputPtr output, int level)
#endif
}
+ /*
+ * Don't set the lowest bit in combo configs since it can act as a flag for
+ * max brightness.
+ */
+ level <<= 1;
+
blc_pwm_ctl = INREG(BLC_PWM_CTL);
blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
OUTREG(BLC_PWM_CTL, blc_pwm_ctl | (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
@@ -248,7 +254,17 @@ i830_lvds_get_backlight_combo(xf86OutputPtr output)
blc_pwm_ctl = INREG(BLC_PWM_CTL);
blc_pwm_ctl &= BACKLIGHT_DUTY_CYCLE_MASK;
- return blc_pwm_ctl;
+
+ /* Since we don't use the low bit when using combo, the value is halved */
+
+ return blc_pwm_ctl >> 1;
+}
+
+static int
+i830_lvds_get_backlight_max_combo(xf86OutputPtr output)
+{
+ /* Since we don't set the low bit when using combo, the range is halved */
+ return i830_lvds_get_backlight_max_native(output) >> 1;
}
/*
@@ -661,7 +677,7 @@ i830_lvds_set_backlight_control(xf86OutputPtr output)
dev_priv->set_backlight = i830_lvds_set_backlight_combo;
dev_priv->get_backlight = i830_lvds_get_backlight_combo;
dev_priv->backlight_max =
- i830_lvds_get_backlight_max_native(output);
+ i830_lvds_get_backlight_max_combo(output);
break;
case BCM_KERNEL:
dev_priv->set_backlight = i830_lvds_set_backlight_kernel;
@@ -1003,7 +1019,7 @@ i830_lvds_init(ScrnInfoPtr pScrn)
case BCM_COMBO:
dev_priv->set_backlight = i830_lvds_set_backlight_combo;
dev_priv->get_backlight = i830_lvds_get_backlight_combo;
- dev_priv->backlight_max = i830_lvds_get_backlight_max_native(output);
+ dev_priv->backlight_max = i830_lvds_get_backlight_max_combo(output);
break;
case BCM_KERNEL:
dev_priv->set_backlight = i830_lvds_set_backlight_kernel;
commit b434bf4029d1a405216454629bcea717c779ae5a
Author: hulifox008 <hulifox008 at 163.com>
Date: Fri Jan 4 02:46:54 2008 -0800
Fix copy'n'paste-o in unused airlied i2c code.
diff --git a/src/i830_i2c.c b/src/i830_i2c.c
index da8f38e..d80229d 100644
--- a/src/i830_i2c.c
+++ b/src/i830_i2c.c
@@ -88,7 +88,7 @@ static void i830_getscl(I2CBusPtr b, int *state)
OUTREG(b->DriverPrivate.uval, GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK);
OUTREG(b->DriverPrivate.uval, 0);
val = INREG(b->DriverPrivate.uval);
- *state = ((val & GPIO_DATA_VAL_IN) != 0);
+ *state = ((val & GPIO_CLOCK_VAL_IN) != 0);
}
static int i830_getsda(I2CBusPtr b)
commit f2ffc0f6e038357dda268363e52c11ada1d0b810
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Thu Jan 3 11:16:15 2008 -0800
Fix compilation error when not using DRI
This patch complements 88f8b688e2316ae4a1f7485f0010ce90de54783a which
added uint64_t typed variables to avoid unsigned long overflows in
32-bit architectures but didn't include <stdint.h> with the required
definition.
When XF86DRI and _XF86DRI_SERVER_ are defined this header gets
indirectly included through "i830_dri.h", thanks to "i830_common.h"
which masquerades this problem as released in 2.1.0 and that manifests
with :
In file included from i810_driver.c:88:
i830.h:137: error: expected specifier-qualifier-list before 'uint64_t'
i830.h:240: error: expected specifier-qualifier-list before 'uint64_t'
Patch from Carlo Marcelo Arenas Belon <carenas at sajinet.com.pe>
diff --git a/src/i830.h b/src/i830.h
index fe4d6c5..dcb87cc 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -40,6 +40,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define I830DEBUG
#endif
+#include <stdint.h>
+
#ifndef REMAP_RESERVED
#define REMAP_RESERVED 0
#endif
commit 83d304c61ad5fdc58b0a9309dbd1e5a3f6cd9b01
Author: Nanhai Zou <nanhai.zou at intel.com>
Date: Wed Jan 2 10:50:44 2008 +0800
TV: fix 576p refresh rate
diff --git a/src/i830_tv.c b/src/i830_tv.c
index 14f4089..9add367 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -580,7 +580,7 @@ const static tv_mode_t tv_modes[] = {
{
.name = "576p",
.clock = 107520,
- .refresh = 59.94,
+ .refresh = 50.0,
.oversample = TV_OVERSAMPLE_4X,
.component_only = 1,
commit 96246c27cb836bae8ee02c46c68a1f2102efd14b
Author: Joakim <elupus at ecce.se>
Date: Thu Dec 27 17:09:02 2007 +0800
Aopen Minipc 965GM LVDS quirk
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 87d9a8a..323962c 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -58,28 +58,29 @@ static void quirk_mac_mini (I830Ptr pI830)
static i830_quirk i830_quirk_list[] = {
/* Aopen mini pc */
{ PCI_CHIP_I945_GM, 0xa0a0, SUBSYS_ANY, quirk_ignore_lvds },
+ { PCI_CHIP_I965_GM, 0xa0a0, SUBSYS_ANY, quirk_ignore_lvds },
{ PCI_CHIP_I965_GM, 0x8086, 0x1999, quirk_ignore_lvds },
/* Apple Mac mini has no lvds, but macbook pro does */
{ PCI_CHIP_I945_GM, 0x8086, 0x7270, quirk_mac_mini },
-
+
/* Dell Latitude X1 */
{ PCI_CHIP_I915_GM, 0x1028, 0x01a3, quirk_ignore_tv },
/* Dell XPS 1330 */
{ PCI_CHIP_I965_GM, 0x1028, 0x0209, quirk_ignore_tv },
-
+
/* Lenovo X60s has no TV output */
{ PCI_CHIP_I945_GM, 0x17aa, 0x201a, quirk_ignore_tv },
/* Lenovo T61 has no TV output */
{ PCI_CHIP_I965_GM, 0x17aa, 0x20b5, quirk_ignore_tv },
/* Lenovo 3000 v200 */
{ PCI_CHIP_I965_GM, 0x17aa, 0x3c18, quirk_ignore_tv },
-
+
/* Panasonic Toughbook CF-Y4 has no TV output */
{ PCI_CHIP_I915_GM, 0x10f7, 0x8338, quirk_ignore_tv },
/* Panasonic Toughbook CF-Y7 has no TV output */
{ PCI_CHIP_I965_GM, 0x10f7, 0x8338, quirk_ignore_tv },
-
+
/* Toshiba Satellite U300 has no TV output */
{ PCI_CHIP_I965_GM, 0x1179, 0xff50, quirk_ignore_tv },
commit f69b48fe24ef94dac44b8123884ca71df675be4b
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Tue Dec 18 18:10:33 2007 -0800
Unconditionally restore pipe configuration
This is a partial fix for #13196, which covers both leaving pipes disabled at
server exit time and problems with restoring the pipe configuration on certain
chipsets. It restores the pipe configuration unconditionally (previously we
made sure the PLL was running and we weren't in VGA mode) but also adds some
additional PLL settle time to the PLL register write paths.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 7818ee4..ca4544d 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1991,6 +1991,13 @@ SaveHWState(ScrnInfoPtr pScrn)
return TRUE;
}
+/* Wait for the PLL to settle down after programming */
+static void
+i830_dpll_settle(void)
+{
+ usleep(10000); /* 10 ms *should* be plenty */
+}
+
static Bool
RestoreHWState(ScrnInfoPtr pScrn)
{
@@ -2025,6 +2032,23 @@ RestoreHWState(ScrnInfoPtr pScrn)
if (!IS_I830(pI830) && !IS_845G(pI830))
OUTREG(PFIT_CONTROL, pI830->savePFIT_CONTROL);
+ /*
+ * Pipe regs
+ * To restore the saved state, we first need to program the PLL regs,
+ * followed by the pipe configuration and finally the display plane
+ * configuration. The VGA registers can program one, both or neither
+ * of the PLL regs, depending on their VGA_MOD_DIS bit value.
+ */
+
+ /*
+ * Since either or both pipes may use the VGA clocks, make sure the
+ * regs are valid.
+ */
+ OUTREG(VCLK_DIVISOR_VGA0, pI830->saveVCLK_DIVISOR_VGA0);
+ OUTREG(VCLK_DIVISOR_VGA1, pI830->saveVCLK_DIVISOR_VGA1);
+ OUTREG(VCLK_POST_DIV, pI830->saveVCLK_POST_DIV);
+
+ /* If the pipe A PLL is active, we can restore the pipe & plane config */
if (pI830->saveDPLL_A & DPLL_VCO_ENABLE)
{
OUTREG(DPLL_A, pI830->saveDPLL_A & ~DPLL_VCO_ENABLE);
@@ -2033,13 +2057,14 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(FPA0, pI830->saveFPA0);
OUTREG(FPA1, pI830->saveFPA1);
OUTREG(DPLL_A, pI830->saveDPLL_A);
- usleep(150);
+ i830_dpll_settle();
if (IS_I965G(pI830))
OUTREG(DPLL_A_MD, pI830->saveDPLL_A_MD);
else
OUTREG(DPLL_A, pI830->saveDPLL_A);
- usleep(150);
+ i830_dpll_settle();
+ /* Restore mode config */
OUTREG(HTOTAL_A, pI830->saveHTOTAL_A);
OUTREG(HBLANK_A, pI830->saveHBLANK_A);
OUTREG(HSYNC_A, pI830->saveHSYNC_A);
@@ -2058,20 +2083,31 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(DSPASURF, pI830->saveDSPASURF);
OUTREG(DSPATILEOFF, pI830->saveDSPATILEOFF);
}
+
+ OUTREG(PIPEACONF, pI830->savePIPEACONF);
+ i830WaitForVblank(pScrn);
+
/*
- * Make sure the DPLL is active and not in VGA mode or the
- * write of PIPEnCONF may cause a crash
+ * Program Pipe A's plane
+ * The corresponding display plane may be disabled, and should only be
+ * enabled if pipe A is actually on (otherwise we have a bug in the initial
+ * state).
*/
- if ((pI830->saveDPLL_A & DPLL_VCO_ENABLE) &&
- (pI830->saveDPLL_A & DPLL_VGA_MODE_DIS))
- OUTREG(PIPEACONF, pI830->savePIPEACONF);
- i830WaitForVblank(pScrn);
- OUTREG(DSPACNTR, pI830->saveDSPACNTR);
- OUTREG(DSPABASE, INREG(DSPABASE));
- i830WaitForVblank(pScrn);
-
+ if (pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_A) {
+ OUTREG(DSPACNTR, pI830->saveDSPACNTR);
+ OUTREG(DSPABASE, INREG(DSPABASE));
+ i830WaitForVblank(pScrn);
+ }
+ if (pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_A) {
+ OUTREG(DSPBCNTR, pI830->saveDSPBCNTR);
+ OUTREG(DSPBBASE, INREG(DSPBBASE));
+ i830WaitForVblank(pScrn);
+ }
+
+ /* See note about pipe programming above */
if(xf86_config->num_crtc == 2)
{
+ /* If the pipe B PLL is active, we can restore the pipe & plane config */
if (pI830->saveDPLL_B & DPLL_VCO_ENABLE)
{
OUTREG(DPLL_B, pI830->saveDPLL_B & ~DPLL_VCO_ENABLE);
@@ -2080,13 +2116,14 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(FPB0, pI830->saveFPB0);
OUTREG(FPB1, pI830->saveFPB1);
OUTREG(DPLL_B, pI830->saveDPLL_B);
- usleep(150);
+ i830_dpll_settle();
if (IS_I965G(pI830))
OUTREG(DPLL_B_MD, pI830->saveDPLL_B_MD);
else
OUTREG(DPLL_B, pI830->saveDPLL_B);
- usleep(150);
+ i830_dpll_settle();
+ /* Restore mode config */
OUTREG(HTOTAL_B, pI830->saveHTOTAL_B);
OUTREG(HBLANK_B, pI830->saveHBLANK_B);
OUTREG(HSYNC_B, pI830->saveHSYNC_B);
@@ -2105,18 +2142,28 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(DSPBTILEOFF, pI830->saveDSPBTILEOFF);
}
+ OUTREG(PIPEBCONF, pI830->savePIPEBCONF);
+ i830WaitForVblank(pScrn);
+
/*
- * See PIPEnCONF note above
+ * Program Pipe B's plane
+ * Note that pipe B may be disabled, and in that case, the plane
+ * should also be disabled or we must have had a bad initial state.
*/
- if ((pI830->saveDPLL_B & DPLL_VCO_ENABLE) &&
- (pI830->saveDPLL_B & DPLL_VGA_MODE_DIS))
- OUTREG(PIPEBCONF, pI830->savePIPEBCONF);
- i830WaitForVblank(pScrn);
- OUTREG(DSPBCNTR, pI830->saveDSPBCNTR);
- OUTREG(DSPBBASE, INREG(DSPBBASE));
- i830WaitForVblank(pScrn);
+ if (pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_B) {
+ OUTREG(DSPACNTR, pI830->saveDSPACNTR);
+ OUTREG(DSPABASE, INREG(DSPABASE));
+ i830WaitForVblank(pScrn);
+ }
+ if (pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_B) {
+ OUTREG(DSPBCNTR, pI830->saveDSPBCNTR);
+ OUTREG(DSPBBASE, INREG(DSPBBASE));
+ i830WaitForVblank(pScrn);
+ }
}
+ OUTREG(VGACNTRL, pI830->saveVGACNTRL);
+
/* Restore outputs */
for (i = 0; i < xf86_config->num_output; i++) {
xf86OutputPtr output = xf86_config->output[i];
@@ -2124,12 +2171,6 @@ RestoreHWState(ScrnInfoPtr pScrn)
output->funcs->restore(output);
}
- OUTREG(VGACNTRL, pI830->saveVGACNTRL);
-
- OUTREG(VCLK_DIVISOR_VGA0, pI830->saveVCLK_DIVISOR_VGA0);
- OUTREG(VCLK_DIVISOR_VGA1, pI830->saveVCLK_DIVISOR_VGA1);
- OUTREG(VCLK_POST_DIV, pI830->saveVCLK_POST_DIV);
-
i830_restore_palette(pI830, PIPE_A);
i830_restore_palette(pI830, PIPE_B);
commit 4757a218d733af12d04674455fc6e1fad48a1cd0
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Tue Dec 18 19:37:46 2007 +0100
Always set pPriv->buf to NULL after freeing the memory it pointed to.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=13108 .
diff --git a/src/i830_video.c b/src/i830_video.c
index 5325bbd..9688aaa 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -2574,6 +2574,7 @@ I830VideoBlockHandler(int i, pointer blockData, pointer pTimeout,
*/
I830Sync(pScrn);
i830_free_memory(pScrn, pPriv->buf);
+ pPriv->buf = NULL;
pPriv->videoStatus = 0;
}
}
@@ -2686,6 +2687,7 @@ I830FreeSurface(XF86SurfacePtr surface)
/* Sync before freeing the buffer, because the pages will be unbound. */
I830Sync(pScrn);
i830_free_memory(surface->pScrn, pPriv->buf);
+ pPriv->buf = NULL;
xfree(surface->pitches);
xfree(surface->offsets);
xfree(surface->devPrivate.ptr);
commit 5cbb4110116f6d4187fd27660a78203caa1da46b
Author: Adam Jackson <ajax at redhat.com>
Date: Thu Dec 13 15:10:43 2007 -0500
i830_sdvo_mode_valid: Fix return values to match what we actually check.
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 2767715..6b7037e 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -900,10 +900,10 @@ i830_sdvo_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
return MODE_NO_DBLESCAN;
if (dev_priv->pixel_clock_min > pMode->Clock)
- return MODE_CLOCK_HIGH;
+ return MODE_CLOCK_LOW;
if (dev_priv->pixel_clock_max < pMode->Clock)
- return MODE_CLOCK_LOW;
+ return MODE_CLOCK_HIGH;
return MODE_OK;
}
commit e03bc385e924222d3d5f3c9a8d65e1ef63b858dc
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Tue Dec 11 13:28:01 2007 -0800
Add cscope files to .gitignore
diff --git a/.gitignore b/.gitignore
index 410a074..998021b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -25,3 +25,4 @@ missing
stamp-h1
i810.4
intel.4
+cscope.*
commit e720ae4476c3f986f623ce0f0ab9775b8b9b7e05
Author: Jesse Barnes <jbarnes at jbarnes-mobile.amr.corp.intel.com>
Date: Mon Dec 10 13:00:14 2007 -0800
CRT hotplug detection improvements
Patch from Hong Liu.
Fixup CRT detection by making sure the pipe is enabled before CRT
detection actually occurs. Fixes bugs Hong was seeing on G35 and other
machines.
diff --git a/src/i830_crt.c b/src/i830_crt.c
index d7762a0..cd71dc5 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -349,34 +349,38 @@ i830_crt_detect(xf86OutputPtr output)
I830Ptr pI830 = I830PTR(pScrn);
xf86CrtcPtr crtc;
int dpms_mode;
-
+ xf86OutputStatus status;
+ Bool connected;
+
+ crtc = i830GetLoadDetectPipe (output, NULL, &dpms_mode);
+ if (!crtc)
+ return XF86OutputStatusUnknown;
+
if (IS_I945G(pI830) || IS_I945GM(pI830) || IS_I965G(pI830) ||
IS_G33CLASS(pI830)) {
if (i830_crt_detect_hotplug(output))
- return XF86OutputStatusConnected;
+ status = XF86OutputStatusConnected;
else
- return XF86OutputStatusDisconnected;
+ status = XF86OutputStatusDisconnected;
+
+ goto out;
}
- if (i830_crt_detect_ddc(output))
- return XF86OutputStatusConnected;
+ if (i830_crt_detect_ddc(output)) {
+ status = XF86OutputStatusConnected;
+ goto out;
+ }
/* Use the load-detect method if we have no other way of telling. */
- crtc = i830GetLoadDetectPipe (output, NULL, &dpms_mode);
-
- if (crtc)
- {
- Bool connected;
-
- connected = i830_crt_detect_load (crtc, output);
- i830ReleaseLoadDetectPipe (output, dpms_mode);
- if (connected)
- return XF86OutputStatusConnected;
- else
- return XF86OutputStatusDisconnected;
- }
+ connected = i830_crt_detect_load (crtc, output);
+ if (connected)
+ status = XF86OutputStatusConnected;
+ else
+ status = XF86OutputStatusDisconnected;
- return XF86OutputStatusUnknown;
+out:
+ i830ReleaseLoadDetectPipe (output, dpms_mode);
+ return status;
}
static void
commit d9df93578b74785c08ba860b4c9aa23b0c89c91c
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 16:41:24 2007 +1000
ivch: fails on address mismatch as I seem to get this on my 865 system
diff --git a/src/ivch/ivch.c b/src/ivch/ivch.c
index ac57ff3..eb5dc21 100644
--- a/src/ivch/ivch.c
+++ b/src/ivch/ivch.c
@@ -188,6 +188,7 @@ ivch_init(I2CBusPtr b, I2CSlaveAddr addr)
"ivch detect failed due to address mismatch "
"(%d vs %d)\n",
(temp & VR00_BASE_ADDRESS_MASK), priv->d.SlaveAddr >> 1);
+ goto out;
}
if (!xf86I2CDevInit(&priv->d)) {
commit cd6f83519c69f72f146fea59afbd6a3542da783a
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Mon Dec 10 05:49:58 2007 +0800
Fix tv quirk for Dell Latitude X1
which is actually 915GM, reported by
Andreas Schildbach <andreas at schildbach.de>
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 1ed6503..87d9a8a 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -64,7 +64,7 @@ static i830_quirk i830_quirk_list[] = {
{ PCI_CHIP_I945_GM, 0x8086, 0x7270, quirk_mac_mini },
/* Dell Latitude X1 */
- { PCI_CHIP_I945_GM, 0x1028, 0x01a3, quirk_ignore_tv },
+ { PCI_CHIP_I915_GM, 0x1028, 0x01a3, quirk_ignore_tv },
/* Dell XPS 1330 */
{ PCI_CHIP_I965_GM, 0x1028, 0x0209, quirk_ignore_tv },
commit 13ec9c8141a9f794258869a04a6bab59dac5eefa
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Sun Dec 9 00:52:13 2007 +0800
exa: fix rendering issue on some 855GM laptops
This trys to initialize more 3d states on i830 like mesa
code, which fixes exa rendering failure for some 855GM users.
diff --git a/src/i830_3d.c b/src/i830_3d.c
index 563dcef..45e02c4 100644
--- a/src/i830_3d.c
+++ b/src/i830_3d.c
@@ -38,7 +38,7 @@ void I830EmitInvarientState( ScrnInfoPtr pScrn )
{
I830Ptr pI830 = I830PTR(pScrn);
- BEGIN_LP_RING(40);
+ BEGIN_LP_RING(58);
OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
@@ -62,7 +62,6 @@ void I830EmitInvarientState( ScrnInfoPtr pScrn )
OUT_RING(0);
OUT_RING(0);
-
OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
MAP_UNIT(0) |
DISABLE_TEX_STREAM_BUMP |
@@ -97,12 +96,6 @@ void I830EmitInvarientState( ScrnInfoPtr pScrn )
OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
- OUT_RING(_3DSTATE_MAP_COORD_SETBIND_CMD);
- OUT_RING(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
- TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
- TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
- TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
-
OUT_RING(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
@@ -127,9 +120,133 @@ void I830EmitInvarientState( ScrnInfoPtr pScrn )
OUT_RING(MAGIC_W_STATE_DWORD1);
OUT_RING(0x3f800000 /* 1.0 in IEEE float */ );
-
OUT_RING(_3DSTATE_COLOR_FACTOR_CMD);
OUT_RING(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
+ OUT_RING(_3DSTATE_MAP_COORD_SETBIND_CMD);
+ OUT_RING(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
+ TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
+ TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
+ TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
+
+ /* copy from mesa */
+ OUT_RING(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
+ DISABLE_INDPT_ALPHA_BLEND |
+ ENABLE_ALPHA_BLENDFUNC |
+ ABLENDFUNC_ADD);
+
+ OUT_RING(_3DSTATE_FOG_COLOR_CMD |
+ FOG_COLOR_RED(0) |
+ FOG_COLOR_GREEN(0) |
+ FOG_COLOR_BLUE(0));
+
+ OUT_RING(_3DSTATE_CONST_BLEND_COLOR_CMD);
+ OUT_RING(0);
+
+ OUT_RING(_3DSTATE_MODES_1_CMD |
+ ENABLE_COLR_BLND_FUNC |
+ BLENDFUNC_ADD |
+ ENABLE_SRC_BLND_FACTOR |
+ SRC_BLND_FACT(BLENDFACTOR_ONE) |
+ ENABLE_DST_BLND_FACTOR |
+ DST_BLND_FACT(BLENDFACTOR_ZERO));
+ OUT_RING(_3DSTATE_MODES_2_CMD |
+ ENABLE_GLOBAL_DEPTH_BIAS |
+ GLOBAL_DEPTH_BIAS(0) |
+ ENABLE_ALPHA_TEST_FUNC|
+ ALPHA_TEST_FUNC(0) | /* always */
+ ALPHA_REF_VALUE(0));
+ OUT_RING(_3DSTATE_MODES_3_CMD |
+ ENABLE_DEPTH_TEST_FUNC |
+ DEPTH_TEST_FUNC(0x2) | /* COMPAREFUNC_LESS */
+ ENABLE_ALPHA_SHADE_MODE |
+ ALPHA_SHADE_MODE(SHADE_MODE_LINEAR)
+ | ENABLE_FOG_SHADE_MODE |
+ FOG_SHADE_MODE(SHADE_MODE_LINEAR) |
+ ENABLE_SPEC_SHADE_MODE |
+ SPEC_SHADE_MODE(SHADE_MODE_LINEAR) |
+ ENABLE_COLOR_SHADE_MODE |
+ COLOR_SHADE_MODE(SHADE_MODE_LINEAR)
+ | ENABLE_CULL_MODE | CULLMODE_NONE);
+
+ OUT_RING(_3DSTATE_MODES_4_CMD |
+ ENABLE_LOGIC_OP_FUNC |
+ LOGIC_OP_FUNC(LOGICOP_COPY) |
+ ENABLE_STENCIL_TEST_MASK |
+ STENCIL_TEST_MASK(0xff) |
+ ENABLE_STENCIL_WRITE_MASK |
+ STENCIL_WRITE_MASK(0xff));
+
+ OUT_RING(_3DSTATE_STENCIL_TEST_CMD |
+ ENABLE_STENCIL_PARMS |
+ STENCIL_FAIL_OP(0) | /* STENCILOP_KEEP */
+ STENCIL_PASS_DEPTH_FAIL_OP(0) | /* STENCILOP_KEEP */
+ STENCIL_PASS_DEPTH_PASS_OP(0) | /* STENCILOP_KEEP */
+ ENABLE_STENCIL_TEST_FUNC |
+ STENCIL_TEST_FUNC(0) | /* COMPAREFUNC_ALWAYS */
+ ENABLE_STENCIL_REF_VALUE |
+ STENCIL_REF_VALUE(0));
+
+ OUT_RING(_3DSTATE_MODES_5_CMD |
+ FLUSH_TEXTURE_CACHE |
+ ENABLE_SPRITE_POINT_TEX |
+ SPRITE_POINT_TEX_OFF |
+ ENABLE_FIXED_LINE_WIDTH |
+ FIXED_LINE_WIDTH(0x2) | /* 1.0 */
+ ENABLE_FIXED_POINT_WIDTH |
+ FIXED_POINT_WIDTH(1));
+
+ OUT_RING(_3DSTATE_ENABLES_1_CMD |
+ DISABLE_LOGIC_OP |
+ DISABLE_STENCIL_TEST |
+ DISABLE_DEPTH_BIAS |
+ DISABLE_SPEC_ADD |
+ DISABLE_FOG |
+ DISABLE_ALPHA_TEST |
+ ENABLE_COLOR_BLEND |
+ DISABLE_DEPTH_TEST);
+ OUT_RING(_3DSTATE_ENABLES_2_CMD |
+ DISABLE_STENCIL_WRITE |
+ ENABLE_TEX_CACHE |
+ DISABLE_DITHER |
+ ENABLE_COLOR_MASK |
+ ENABLE_COLOR_WRITE |
+ DISABLE_DEPTH_WRITE);
+
+ OUT_RING(_3DSTATE_STIPPLE);
+
+ /* Set default blend state */
+ OUT_RING(_3DSTATE_MAP_BLEND_OP_CMD(0) |
+ TEXPIPE_COLOR |
+ ENABLE_TEXOUTPUT_WRT_SEL |
+ TEXOP_OUTPUT_CURRENT |
+ DISABLE_TEX_CNTRL_STAGE |
+ TEXOP_SCALE_1X |
+ TEXOP_MODIFY_PARMS |
+ TEXOP_LAST_STAGE | TEXBLENDOP_ARG1);
+ OUT_RING(_3DSTATE_MAP_BLEND_OP_CMD(0) |
+ TEXPIPE_ALPHA |
+ ENABLE_TEXOUTPUT_WRT_SEL |
+ TEXOP_OUTPUT_CURRENT |
+ TEXOP_SCALE_1X |
+ TEXOP_MODIFY_PARMS | TEXBLENDOP_ARG1);
+ OUT_RING(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
+ TEXPIPE_COLOR |
+ TEXBLEND_ARG1 |
+ TEXBLENDARG_MODIFY_PARMS |
+ TEXBLENDARG_DIFFUSE);
+ OUT_RING(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
+ TEXPIPE_ALPHA |
+ TEXBLEND_ARG1 |
+ TEXBLENDARG_MODIFY_PARMS |
+ TEXBLENDARG_DIFFUSE);
+
+ OUT_RING(_3DSTATE_AA_CMD |
+ AA_LINE_ECAAR_WIDTH_ENABLE |
+ AA_LINE_ECAAR_WIDTH_1_0 |
+ AA_LINE_REGION_WIDTH_ENABLE |
+ AA_LINE_REGION_WIDTH_1_0 |
+ AA_LINE_DISABLE);
+
ADVANCE_LP_RING();
}
commit e2d9fd6425584119f28768d85c4b7d106ecf8742
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Fri Dec 7 16:30:46 2007 -0800
Describe output properties in more detail
Add descriptions for LVDS and TV output properties and also mention the EDID
property a new output configuration section.
diff --git a/man/intel.man b/man/intel.man
index 6245736..d46e3f9 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -176,31 +176,77 @@ Default: "EXA".
Enable printing of additional debugging information about modesetting to
the server log.
+.SH OUTPUT CONFIGURATION
+On 830M and better chipsets, the driver supports runtime configuration of
+detected outputs. You can use the
+.B xrandr
+tool to control outputs on the command line. Each output listed below may have
+one or more properties associated with it (like a binary EDID block if one is
+found). Some outputs have unique properties which are described below.
+
+.SS "VGA"
+VGA output port (typically exposed via an HD15 connector).
+
+.SS "LVDS"
+Low Voltage Differential Signalling output (typically a laptop LCD panel). Available properties:
+
.PP
-The 830M and newer driver supports the following outputs through RandR 1.2:
+.B BACKLIGHT
+- current backlight level (adjustable)
+.TP 2
+By adjusting the BACKLIGHT property, the brightness on the LVDS output can be adjusted. In some cases, this property may be unavailable (for example if your platform uses an external microcontroller to control the backlight).
+
.PP
-.TP
-.BI "VGA"
-Analog VGA output
-.TP
-.BI "LVDS"
-Laptop panel. Properties:
- BACKLIGHT - set backlight level
- BACKLIGHT_CONTROL - set backlight level control method (i.e. use kernel interfaces, native LVDS power register, legacy register, or combination)
-.TP
-.BI "TV"
-Integrated TV output
-.TP
-.BI "TMDS-1"
+.B BACKLIGHT_CONTROL
+- method used to control backlight
+.TP 2
+The driver will attempt to automatically detect the backlight control method for your platform. If this fails however, you can select another method which may allow you to control your backlight. Available methods include:
+.PP
+.B NATIVE
+.TP 4
+Intel chipsets include backlight control registers, which on some platforms may be wired to control the backlight directly. This method uses those registers.
+.PP
+.B LEGACY
+.TP 4
+The legacy backlight control registers exist in PCI configuration space, and have fewer available backlight levels than the native registers. However, some platforms are wired this way and so need to use this method.
+.PP
+.B COMBO
+.TP 4
+This method attempts to use the native registers where possible, resorting to the legacy, configuration space registers only to enable the backlight if needed. On platforms that have both wired this can be a good choice as it allows the fine grained backlight control of the native interface.
+.PP
+.B KERNEL
+.TP 4
+On some system, the kernel may provide a backlight control driver. In that case, using the kernel interfaces is preferable, as the same driver may respond to hotkey events or external APIs.
+
+.SS "TV"
+Integrated TV output. Available properties include:
+
+.PP
+.B BOTTOM, RIGHT, TOP, LEFT
+- margins
+.TP 2
+Adjusting these properties allows you to control the placement of your TV output buffer on the screen.
+
+.PP
+.B TV_FORMAT
+- output standard
+.TP 2
+This property allows you to control the output standard used on your TV output port. You can select between NTSC-M, NTSC-443, NTSC-J, PAL-M, PAL-N, and PAL.
+
+.SS "TMDS-1"
First DVI SDVO output
-.TP
-.BI "TMDS-2"
+
+.SS "TMDS-2"
Second DVI SDVO output
+
.PP
SDVO and DVO TV outputs are not supported by the driver at this time.
+
.PP
See __xconfigfile__(__filemansuffix__) for information on associating Monitor
-sections with these outputs for configuration.
+sections with these outputs for configuration. Associating Monitor sections
+with each output can be helpful if you need to ignore a specific output, for
+example, or statically configure an extended desktop monitor layout.
.SH "SEE ALSO"
__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
commit 6f92200db39a790c95c1fac64baf0bd41a70e481
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Wed Dec 5 08:10:17 2007 -0800
Fix backlight setting save/restore
We need to save the current backlight value at LVDS init time, as well as when
we change the DPMS setting. Also, since 0 is a valid backlight value, don't
set the backlight value to maximum at startup if the value happens to be zero.
These fixes should make the backlight user experience much more consistent and
hopefully less frustrating.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index 602a55d..c58a7e0 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -363,6 +363,12 @@ i830SetLVDSPanelPower(xf86OutputPtr output, Bool on)
dev_priv->set_backlight(output, dev_priv->backlight_duty_cycle);
} else {
+ /*
+ * Only save the current backlight value if we're going from
+ * on to off.
+ */
+ if (INREG(PP_CONTROL) & POWER_TARGET_ON)
+ dev_priv->backlight_duty_cycle = dev_priv->get_backlight(output);
dev_priv->set_backlight(output, 0);
OUTREG(PP_CONTROL, INREG(PP_CONTROL) & ~POWER_TARGET_ON);
@@ -399,12 +405,6 @@ i830_lvds_save (xf86OutputPtr output)
pI830->savePP_CYCLE = INREG(PP_CYCLE);
pI830->saveBLC_PWM_CTL = INREG(BLC_PWM_CTL);
dev_priv->backlight_duty_cycle = dev_priv->get_backlight(output);
-
- /*
- * If the light is off at server startup, just make it full brightness
- */
- if (dev_priv->backlight_duty_cycle == 0)
- dev_priv->backlight_duty_cycle = dev_priv->backlight_max;
}
static void
@@ -1015,7 +1015,7 @@ i830_lvds_init(ScrnInfoPtr pScrn)
break;
}
- dev_priv->backlight_duty_cycle = dev_priv->backlight_max;
+ dev_priv->backlight_duty_cycle = dev_priv->get_backlight(output);
return;
commit 4c1fa5235555c9ef3de1eebd006c4e91283362bf
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Tue Dec 4 18:27:24 2007 -0800
Add BCM_ to backlight control method enums
Avoids polluting the global namespace with such generic terms.
diff --git a/src/i830.h b/src/i830.h
index 2c1ac86..fe4d6c5 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -321,29 +321,29 @@ enum last_3d {
* so they can choose an ideal one for their platform (assuming our quirk
* code picks the wrong one).
*
- * Four different methods are available:
- * NATIVE: only ever touch the native backlight control registers
+ * Four different backlight control methods are available:
+ * BCM_NATIVE: only ever touch the native backlight control registers
* This method may be susceptible to problem (2) above if the firmware
* modifies the legacy registers.
- * LEGACY: only ever touch the legacy backlight control registers
+ * BCM_LEGACY: only ever touch the legacy backlight control registers
* This method may be susceptible to problem (1) above if the firmware
* also modifies the legacy registers.
- * COMBO: try to use both sets
+ * BCM_COMBO: try to use both sets
* In this case, the driver will try to modify both sets of registers
* if needed. To avoid problem (2) above it may set the LBB register
* to a non-zero value if the brightness is to be increased. It's still
* susceptible to problem (1), but to a lesser extent than the LEGACY only
* method.
- * KERNEL: use kernel methods for controlling the backlight
+ * BCM_KERNEL: use kernel methods for controlling the backlight
* This is only available on some platforms, but where present this can
* provide the best user experience.
*/
enum backlight_control {
- NATIVE = 0,
- LEGACY,
- COMBO,
- KERNEL,
+ BCM_NATIVE = 0,
+ BCM_LEGACY,
+ BCM_COMBO,
+ BCM_KERNEL,
};
typedef struct _I830Rec {
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index da1fc46..602a55d 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -109,18 +109,18 @@ i830_set_lvds_backlight_method(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
CARD32 blc_pwm_ctl, blc_pwm_ctl2;
- enum backlight_control method = NATIVE; /* Default to native */
+ enum backlight_control method = BCM_NATIVE; /* Default to native */
if (i830_kernel_backlight_available(output)) {
- method = KERNEL;
+ method = BCM_KERNEL;
} else if (IS_I965GM(pI830)) {
blc_pwm_ctl2 = INREG(BLC_PWM_CTL2);
if (blc_pwm_ctl2 & BLM_LEGACY_MODE2)
- method = LEGACY;
+ method = BCM_LEGACY;
} else {
blc_pwm_ctl = INREG(BLC_PWM_CTL);
if (blc_pwm_ctl & BLM_LEGACY_MODE)
- method = LEGACY;
+ method = BCM_LEGACY;
}
pI830->backlight_control_method = method;
@@ -646,24 +646,24 @@ i830_lvds_set_backlight_control(xf86OutputPtr output)
struct i830_lvds_priv *dev_priv = intel_output->dev_priv;
switch (pI830->backlight_control_method) {
- case NATIVE:
+ case BCM_NATIVE:
dev_priv->set_backlight = i830_lvds_set_backlight_native;
dev_priv->get_backlight = i830_lvds_get_backlight_native;
dev_priv->backlight_max =
i830_lvds_get_backlight_max_native(output);
break;
- case LEGACY:
+ case BCM_LEGACY:
dev_priv->set_backlight = i830_lvds_set_backlight_legacy;
dev_priv->get_backlight = i830_lvds_get_backlight_legacy;
dev_priv->backlight_max = 0xff;
break;
- case COMBO:
+ case BCM_COMBO:
dev_priv->set_backlight = i830_lvds_set_backlight_combo;
dev_priv->get_backlight = i830_lvds_get_backlight_combo;
dev_priv->backlight_max =
i830_lvds_get_backlight_max_native(output);
break;
- case KERNEL:
+ case BCM_KERNEL:
dev_priv->set_backlight = i830_lvds_set_backlight_kernel;
dev_priv->get_backlight = i830_lvds_get_backlight_kernel;
dev_priv->backlight_max =
@@ -990,22 +990,22 @@ i830_lvds_init(ScrnInfoPtr pScrn)
i830_set_lvds_backlight_method(output);
switch (pI830->backlight_control_method) {
- case NATIVE:
+ case BCM_NATIVE:
dev_priv->set_backlight = i830_lvds_set_backlight_native;
dev_priv->get_backlight = i830_lvds_get_backlight_native;
dev_priv->backlight_max = i830_lvds_get_backlight_max_native(output);
break;
- case LEGACY:
+ case BCM_LEGACY:
dev_priv->set_backlight = i830_lvds_set_backlight_legacy;
dev_priv->get_backlight = i830_lvds_get_backlight_legacy;
dev_priv->backlight_max = 0xff;
break;
- case COMBO:
+ case BCM_COMBO:
dev_priv->set_backlight = i830_lvds_set_backlight_combo;
dev_priv->get_backlight = i830_lvds_get_backlight_combo;
dev_priv->backlight_max = i830_lvds_get_backlight_max_native(output);
break;
- case KERNEL:
+ case BCM_KERNEL:
dev_priv->set_backlight = i830_lvds_set_backlight_kernel;
dev_priv->get_backlight = i830_lvds_get_backlight_kernel;
dev_priv->backlight_max = i830_lvds_get_backlight_max_kernel(output);
commit 30d74f1b1f30e751d2c47aa63a4a2043e71467dc
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Tue Dec 4 18:23:44 2007 -0800
Use "LEGACY" backlight method if backlight control is such
This may regress the user experience a bit (fewer backlight levels) on machines
where both the LBB and native registers work, but it's better that it work for
everyone than work extra well for some and not at all for others.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index a3a56f7..da1fc46 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -116,11 +116,11 @@ i830_set_lvds_backlight_method(xf86OutputPtr output)
} else if (IS_I965GM(pI830)) {
blc_pwm_ctl2 = INREG(BLC_PWM_CTL2);
if (blc_pwm_ctl2 & BLM_LEGACY_MODE2)
- method = COMBO;
+ method = LEGACY;
} else {
blc_pwm_ctl = INREG(BLC_PWM_CTL);
if (blc_pwm_ctl & BLM_LEGACY_MODE)
- method = COMBO;
+ method = LEGACY;
}
pI830->backlight_control_method = method;
commit 0e554e6dd4da56be24d2f971ff4cd4d585936724
Author: Eric Anholt <eric at anholt.net>
Date: Tue Dec 4 10:32:45 2007 -0800
Remove extra have_libpciaccess=no that broke tools build with old servers.
diff --git a/configure.ac b/configure.ac
index 20aebb4..334a1f4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -121,7 +121,6 @@ else
have_libpciaccess=yes,
have_libpciaccess=no)
fi
-have_libpciaccess=no
AM_CONDITIONAL(XSERVER_LIBPCIACCESS, test "x$XSERVER_LIBPCIACCESS" = xyes)
AM_CONDITIONAL(LIBPCIACCESS,
test "x$XSERVER_LIBPCIACCESS" = xyes -o "x$have_libpciaccess" = xyes)
commit 75ef3e669dac1259d282dcc8f54b197fc19f22b3
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Nov 28 22:13:55 2007 +0800
Replace ALLOCATE_LOCAL/DEALLOCATE_LOCAL with xalloc/xfree
diff --git a/src/i810_dri.c b/src/i810_dri.c
index e5e1565..136a705 100644
--- a/src/i810_dri.c
+++ b/src/i810_dri.c
@@ -1208,7 +1208,7 @@ I810DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I810Ptr pI810 = I810PTR(pScrn);
BoxPtr pboxTmp, pboxNext, pboxBase;
- DDXPointPtr pptTmp, pptNew2;
+ DDXPointPtr pptTmp, pptNew2 = NULL;
int xdir, ydir;
int screenwidth = pScrn->virtualX;
@@ -1231,12 +1231,12 @@ I810DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
if (nbox > 1) {
/* Keep ordering in each band, reverse order of bands */
- pboxNew1 = (BoxPtr) ALLOCATE_LOCAL(sizeof(BoxRec) * nbox);
+ pboxNew1 = (BoxPtr) xalloc(sizeof(BoxRec) * nbox);
if (!pboxNew1)
return;
- pptNew1 = (DDXPointPtr) ALLOCATE_LOCAL(sizeof(DDXPointRec) * nbox);
+ pptNew1 = (DDXPointPtr) xalloc(sizeof(DDXPointRec) * nbox);
if (!pptNew1) {
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pboxNew1);
return;
}
pboxBase = pboxNext = pbox + nbox - 1;
@@ -1267,16 +1267,16 @@ I810DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
if (nbox > 1) {
/*reverse orderof rects in each band */
- pboxNew2 = (BoxPtr) ALLOCATE_LOCAL(sizeof(BoxRec) * nbox);
- pptNew2 = (DDXPointPtr) ALLOCATE_LOCAL(sizeof(DDXPointRec) * nbox);
+ pboxNew2 = (BoxPtr) xalloc(sizeof(BoxRec) * nbox);
+ pptNew2 = (DDXPointPtr) xalloc(sizeof(DDXPointRec) * nbox);
if (!pboxNew2 || !pptNew2) {
if (pptNew2)
- DEALLOCATE_LOCAL(pptNew2);
+ xfree(pptNew2);
if (pboxNew2)
- DEALLOCATE_LOCAL(pboxNew2);
+ xfree(pboxNew2);
if (pboxNew1) {
- DEALLOCATE_LOCAL(pptNew1);
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pptNew1);
+ xfree(pboxNew1);
}
return;
}
@@ -1341,12 +1341,12 @@ I810DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
I810EmitFlush(pScrn);
if (pboxNew2) {
- DEALLOCATE_LOCAL(pptNew2);
- DEALLOCATE_LOCAL(pboxNew2);
+ xfree(pptNew2);
+ xfree(pboxNew2);
}
if (pboxNew1) {
- DEALLOCATE_LOCAL(pptNew1);
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pptNew1);
+ xfree(pboxNew1);
}
if (pI810->AccelInfoRec)
diff --git a/src/i830_dri.c b/src/i830_dri.c
index b223b02..f52a7c3 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -1249,7 +1249,7 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
BoxPtr pboxTmp, pboxNext, pboxBase;
- DDXPointPtr pptTmp, pptNew2;
+ DDXPointPtr pptTmp, pptNew2 = NULL;
int xdir, ydir;
#if 0
@@ -1277,12 +1277,12 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
if (nbox > 1) {
/* Keep ordering in each band, reverse order of bands */
- pboxNew1 = (BoxPtr) ALLOCATE_LOCAL(sizeof(BoxRec) * nbox);
+ pboxNew1 = (BoxPtr) xalloc(sizeof(BoxRec) * nbox);
if (!pboxNew1)
return;
- pptNew1 = (DDXPointPtr) ALLOCATE_LOCAL(sizeof(DDXPointRec) * nbox);
+ pptNew1 = (DDXPointPtr) xalloc(sizeof(DDXPointRec) * nbox);
if (!pptNew1) {
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pboxNew1);
return;
}
pboxBase = pboxNext = pbox + nbox - 1;
@@ -1313,16 +1313,16 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
if (nbox > 1) {
/*reverse orderof rects in each band */
- pboxNew2 = (BoxPtr) ALLOCATE_LOCAL(sizeof(BoxRec) * nbox);
- pptNew2 = (DDXPointPtr) ALLOCATE_LOCAL(sizeof(DDXPointRec) * nbox);
+ pboxNew2 = (BoxPtr) xalloc(sizeof(BoxRec) * nbox);
+ pptNew2 = (DDXPointPtr) xalloc(sizeof(DDXPointRec) * nbox);
if (!pboxNew2 || !pptNew2) {
if (pptNew2)
- DEALLOCATE_LOCAL(pptNew2);
+ xfree(pptNew2);
if (pboxNew2)
- DEALLOCATE_LOCAL(pboxNew2);
+ xfree(pboxNew2);
if (pboxNew1) {
- DEALLOCATE_LOCAL(pptNew1);
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pptNew1);
+ xfree(pboxNew1);
}
return;
}
@@ -1393,12 +1393,12 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
I830EmitFlush(pScrn);
if (pboxNew2) {
- DEALLOCATE_LOCAL(pptNew2);
- DEALLOCATE_LOCAL(pboxNew2);
+ xfree(pptNew2);
+ xfree(pboxNew2);
}
if (pboxNew1) {
- DEALLOCATE_LOCAL(pptNew1);
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pptNew1);
+ xfree(pboxNew1);
}
i830MarkSync(pScrn);
}
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