xf86-video-intel: Branch 'xf86-video-intel-2.2-branch' - 14 commits - src/brw_structs.h src/common.h src/i810_driver.c src/i810_reg.h src/i830_driver.c src/i830_i2c.c src/i830_lvds.c src/i830_sdvo.c src/i965_render.c src/i965_video.c
Jesse Barnes
jbarnes at kemper.freedesktop.org
Mon Jan 21 09:43:56 PST 2008
src/brw_structs.h | 12 +++++++++---
src/common.h | 26 +++++++++++++++++++++-----
src/i810_driver.c | 14 +++++++++-----
src/i810_reg.h | 5 +++++
src/i830_driver.c | 40 +++++++++++++++++++++++++++++++---------
src/i830_i2c.c | 2 +-
src/i830_lvds.c | 19 +++++++++++++++----
src/i830_sdvo.c | 2 +-
src/i965_render.c | 6 +++++-
src/i965_video.c | 5 ++++-
10 files changed, 101 insertions(+), 30 deletions(-)
New commits:
commit c35ab31893c9b2cf93e0b0d3c4d93b5830d39b29
Merge: 79ea745... f54bba7...
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Mon Jan 21 09:43:38 2008 -0800
Merge branch 'master' into xf86-video-intel-2.2-branch
commit f54bba7600647c76fe3bd2d0133edc06dbea6a05
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Tue Jan 22 00:48:23 2008 +0800
Add missing i830M and 845G pci ids info
diff --git a/src/common.h b/src/common.h
index 7737194..3a11e59 100644
--- a/src/common.h
+++ b/src/common.h
@@ -298,6 +298,16 @@ extern int I810_DEBUG;
#define PCI_CHIP_I815_BRIDGE 0x1130
#endif
+#ifndef PCI_CHIP_I830_M
+#define PCI_CHIP_I830_M 0x3577
+#define PCI_CHIP_I830_M_BRIDGE 0x3575
+#endif
+
+#ifndef PCI_CHIP_845_G
+#define PCI_CHIP_845_G 0x2562
+#define PCI_CHIP_845_G_BRIDGE 0x2560
+#endif
+
#ifndef PCI_CHIP_I855_GM
#define PCI_CHIP_I855_GM 0x3582
#define PCI_CHIP_I855_GM_BRIDGE 0x3580
commit 633dbd28218fd8a746c1735fd44a14f35bd07faa
Author: Julien Cristau <jcristau at debian.org>
Date: Thu Jan 17 22:34:21 2008 +0800
Bug 14032: i810, set default depth to 16
X fails to start without an xorg.conf on i810, because the default depth set by
the server (32) is not supported by the driver. I think the driver should
default to 16 bits (it supports 24, but when I tested it that didn't seem to
work very well, and dri is disabled at 24 bits depth anyway) instead of letting
the server use 32 and failing later on.
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 1ecb04a..53121a6 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -954,7 +954,7 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
pScrn->monitor = pScrn->confScreen->monitor;
flags24 = Support24bppFb | PreferConvert32to24 | SupportConvert32to24;
- if (!xf86SetDepthBpp(pScrn, 0, 0, 0, flags24)) {
+ if (!xf86SetDepthBpp(pScrn, 16, 0, 16, flags24)) {
return FALSE;
} else {
switch (pScrn->depth) {
commit 4fec18e07f2b23306e885d63c74661ae0e4b04d9
Author: Jesse Barnes <jesse.barnes at intel.com>
Date: Fri Jan 11 10:28:59 2008 -0800
Turn on backlight when LVDS panel is powered up
In some configurations, the LVDS may be off at startup along with the
backlight. So when turning the LVDS on for the first time, we may also need to
set the backlight to a non-zero value. So try to use the saved value if
possible, but if it's zero, make the backlight full brightness when turning on
the LVDS.
Note that this is slightly sub-optimal for configurations where zero is a valid backlight brightness.
Fixes fdo bz #13958.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index 50ecb60..ef8fa4a 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -372,6 +372,17 @@ i830SetLVDSPanelPower(xf86OutputPtr output, Bool on)
CARD32 pp_status;
if (on) {
+ /*
+ * If we're going from off->on we may need to turn on the backlight.
+ * We should use the saved value whenever possible, but on some
+ * machines 0 is a valid backlight value (due to an external backlight
+ * controller for example), so on them, when turning LVDS back on,
+ * they'll always re-maximize the brightness.
+ */
+ if (!(INREG(PP_CONTROL) & POWER_TARGET_ON) &&
+ dev_priv->backlight_duty_cycle == 0)
+ dev_priv->backlight_duty_cycle = dev_priv->backlight_max;
+
OUTREG(PP_CONTROL, INREG(PP_CONTROL) | POWER_TARGET_ON);
do {
pp_status = INREG(PP_STATUS);
commit b5cf8faf8102e6313c23de87a680cc327ac95478
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Thu Jan 10 14:25:18 2008 -0800
Remove unnecessary quirk code in CRT probing
Since we return early in the CRTC DPMS code, keeping the pipes & clocks
enabled, this code is no longer necessary. As an added bonus, VGA connections
should be reported correctly even when the pipe A quirk is active.
Updates fix for fdo bz #11432.
diff --git a/src/i830_crt.c b/src/i830_crt.c
index 3f0fc46..82a774a 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -381,13 +381,6 @@ i830_crt_detect(xf86OutputPtr output)
out:
i830ReleaseLoadDetectPipe (output, dpms_mode);
- /* Needed for some machines where the BIOS pokes at pipe A */
- if (pI830->quirk_flag & QUIRK_PIPEA_FORCE) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Overriding VGA detection, "
- "forcing pipe A on.\n");
- status = XF86OutputStatusConnected;
- }
-
return status;
}
commit 3c22ed633be2ac96eea7bc533839e956f1f31b84
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Wed Jan 9 09:47:38 2008 -0800
Add pipe A force enable quirk
On some platforms, the firmware may read & write GPU registers on lid close,
suspend/resume time or during various SMM events. If one of the graphics pipes
is disabled at that time, the GPU may hang due to the programming dependencies
of the various registers.
This patch adds a quirk to force the driver to keep pipe A enabled if
necessary, through user configuration in xorg.conf or via a platform specific
quirk. Leaving the pipe enabled comes at a power cost however, so the quirk
should only be enabled when strictly necessary.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=11432.
diff --git a/man/intel.man b/man/intel.man
index d46e3f9..e5736e5 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -175,6 +175,13 @@ Default: "EXA".
.BI "Option \*qModeDebug\*q \*q" boolean \*q
Enable printing of additional debugging information about modesetting to
the server log.
+.TP
+.BI "Option \*qForceEnablePipeA\*q \*q" boolean \*q
+Force the driver to leave pipe A enabled. May be necessary in configurations
+where the BIOS accesses pipe registers during display hotswitch or lid close,
+causing a crash. If you find that your platform needs this option, please file
+a bug against xf86-video-intel at http://bugs.freedesktop.org which includes
+the output of 'lspci -v' and 'lspci -vn'.
.SH OUTPUT CONFIGURATION
On 830M and better chipsets, the driver supports runtime configuration of
diff --git a/src/i830.h b/src/i830.h
index dcb87cc..9adbaf7 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -836,6 +836,7 @@ extern const int I830CopyROP[16];
#define QUIRK_IGNORE_TV 0x00000001
#define QUIRK_IGNORE_LVDS 0x00000002
#define QUIRK_IGNORE_MACMINI_LVDS 0x00000004
+#define QUIRK_PIPEA_FORCE 0x00000008
extern void i830_fixup_devices(ScrnInfoPtr);
#endif /* _I830_H_ */
diff --git a/src/i830_crt.c b/src/i830_crt.c
index cd71dc5..3f0fc46 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -380,6 +380,14 @@ i830_crt_detect(xf86OutputPtr output)
out:
i830ReleaseLoadDetectPipe (output, dpms_mode);
+
+ /* Needed for some machines where the BIOS pokes at pipe A */
+ if (pI830->quirk_flag & QUIRK_PIPEA_FORCE) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Overriding VGA detection, "
+ "forcing pipe A on.\n");
+ status = XF86OutputStatusConnected;
+ }
+
return status;
}
diff --git a/src/i830_display.c b/src/i830_display.c
index 0e42624..d16871d 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -724,6 +724,10 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
/* Give the overlay scaler a chance to disable if it's on this pipe */
i830_crtc_dpms_video(crtc, FALSE);
+ /* May need to leave pipe A on */
+ if ((pipe == 0) && (pI830->quirk_flag & QUIRK_PIPEA_FORCE))
+ return;
+
/* Disable the VGA plane that we never use */
OUTREG(VGACNTRL, VGA_DISP_DISABLE);
@@ -1176,14 +1180,6 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
i830PrintPll("chosen", &clock);
}
- if (dpll & DPLL_VCO_ENABLE)
- {
- OUTREG(fp_reg, fp);
- OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
- POSTING_READ(dpll_reg);
- usleep(150);
- }
-
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
* This is an exception to the general rule that mode_set doesn't turn
* things on.
@@ -1192,6 +1188,14 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
{
CARD32 lvds = INREG(LVDS);
+ if (dpll & DPLL_VCO_ENABLE)
+ {
+ OUTREG(fp_reg, fp);
+ OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+ POSTING_READ(dpll_reg);
+ usleep(150);
+ }
+
lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
/* Set the B0-B3 data pairs corresponding to whether we're going to
* set the DPLLs for dual-channel mode or not.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 32d4602..32cecff 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -298,6 +298,7 @@ typedef enum {
OPTION_INTELTEXPOOL,
#endif
OPTION_TRIPLEBUFFER,
+ OPTION_FORCEENABLEPIPEA
} I830Opts;
static OptionInfoRec I830Options[] = {
@@ -320,6 +321,7 @@ static OptionInfoRec I830Options[] = {
{OPTION_INTELTEXPOOL,"Legacy3D", OPTV_BOOLEAN, {0}, FALSE},
#endif
{OPTION_TRIPLEBUFFER, "TripleBuffer", OPTV_BOOLEAN, {0}, FALSE},
+ {OPTION_FORCEENABLEPIPEA, "ForceEnablePipeA", OPTV_BOOLEAN, {0}, FALSE},
{-1, NULL, OPTV_NONE, {0}, FALSE}
};
/* *INDENT-ON* */
@@ -1193,6 +1195,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
pI830->debug_modes = FALSE;
}
+ if (xf86ReturnOptValBool(pI830->Options, OPTION_FORCEENABLEPIPEA, FALSE))
+ pI830->quirk_flag |= QUIRK_PIPEA_FORCE;
+
/* We have to use PIO to probe, because we haven't mapped yet. */
I830SetPIOAccess(pI830);
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 323962c..8fbdbfe 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -39,6 +39,11 @@ typedef struct {
void (*hook)(I830Ptr);
} i830_quirk, *i830_quirk_ptr;
+static void quirk_pipea_force (I830Ptr pI830)
+{
+ pI830->quirk_flag |= QUIRK_PIPEA_FORCE;
+}
+
static void quirk_ignore_tv (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_TV;
@@ -86,6 +91,10 @@ static i830_quirk i830_quirk_list[] = {
/* Samsung Q35 has no TV output */
{ PCI_CHIP_I945_GM, 0x144d, 0xc504, quirk_ignore_tv },
+
+ /* Dell Inspiron 510m needs pipe A force quirk */
+ { PCI_CHIP_I855_GM, 0x1028, 0x0164, quirk_pipea_force },
+
{ 0, 0, 0, NULL },
};
commit d3b41bcf231a6ffd289c128c06aa619f554a776c
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:28:25 2008 +0800
Disable frame buffer compression on new chipset now.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 2183b1d..32d4602 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2510,7 +2510,8 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
}
/* Enable FB compression if possible */
- if (i830_fb_compression_supported(pI830) && !IS_I965GM(pI830))
+ if (i830_fb_compression_supported(pI830) && !IS_I965GM(pI830)
+ && !IS_IGD_GM(pI830))
pI830->fb_compression = TRUE;
else
pI830->fb_compression = FALSE;
commit 2f0c0427dc4113bac64cda07c6365df1f0637697
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:27:42 2008 +0800
Update PIPELINE_SELECT instruction and surface state format for new chipset
diff --git a/src/brw_structs.h b/src/brw_structs.h
index 28d8e12..d4fc5c6 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
@@ -832,9 +832,8 @@ struct brw_wm_unit_state
unsigned int program_computes_depth:1;
unsigned int program_uses_killpixel:1;
unsigned int legacy_line_rast: 1;
- unsigned int pad1:1;
- unsigned int max_threads:6;
- unsigned int pad2:1;
+ unsigned int transposed_urb_read:1;
+ unsigned int max_threads:7;
} wm5;
float global_depth_offset_constant;
@@ -977,6 +976,13 @@ struct brw_surface_state
unsigned int min_array_elt:9;
unsigned int min_lod:4;
} ss4;
+
+ struct {
+ unsigned int pad:20;
+ unsigned int y_offset:4;
+ unsigned int pad2:1;
+ unsigned int x_offset:7;
+ } ss5;
};
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 26f9db4..bed3901 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -2284,6 +2284,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BRW_STATE_SIP BRW_3D(0, 1, 2)
#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4)
+#define NEW_PIPELINE_SELECT BRW_3D(1, 1, 4)
+
#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0)
#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0)
diff --git a/src/i965_render.c b/src/i965_render.c
index ad3b53e..4b1d7f3 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -907,6 +907,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
src_sampler_offset) >> 5;
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
+ wm_state->wm5.transposed_urb_read = 0;
wm_state->wm5.thread_dispatch_enable = 1;
/* just use 16-pixel dispatch (4 subspans), don't need to change kernel
* start point
@@ -933,7 +934,10 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_LP_RING(12);
/* Match Mesa driver setup */
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ if (IS_IGD_GM(pI830))
+ OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
OUT_RING(BRW_CS_URB_STATE | 0);
OUT_RING((0 << 4) | /* URB Entry Allocation Size */
diff --git a/src/i965_video.c b/src/i965_video.c
index 0357270..928b52b 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -509,7 +509,10 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_LP_RING(12);
/* Match Mesa driver setup */
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ if (IS_IGD_GM(pI830))
+ OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
/* Mesa does this. Who knows... */
OUT_RING(BRW_CS_URB_STATE | 0);
commit 139e9affdd49dcbe08e260a0a2bd001de16566e6
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:26:57 2008 +0800
GTT access change for new integrated graphics device
diff --git a/src/i810_reg.h b/src/i810_reg.h
index a6663a4..26f9db4 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -539,6 +539,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PGETBL_SIZE_512KB (0 << 1)
#define PGETBL_SIZE_256KB (1 << 1)
#define PGETBL_SIZE_128KB (2 << 1)
+#define PGETBL_SIZE_1MB (3 << 1)
+#define PGETBL_SIZE_2MB (4 << 1)
+#define PGETBL_SIZE_1_5MB (5 << 1)
#define G33_PGETBL_SIZE_MASK (3 << 8)
#define G33_PGETBL_SIZE_1M (1 << 8)
#define G33_PGETBL_SIZE_2M (2 << 8)
diff --git a/src/i830_driver.c b/src/i830_driver.c
index eeb5ed0..2183b1d 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -455,6 +455,15 @@ I830DetectMemory(ScrnInfoPtr pScrn)
case PGETBL_SIZE_128KB:
gtt_size = 128;
break;
+ case PGETBL_SIZE_1MB:
+ gtt_size = 1024;
+ break;
+ case PGETBL_SIZE_2MB:
+ gtt_size = 2048;
+ break;
+ case PGETBL_SIZE_1_5MB:
+ gtt_size = 1024 + 512;
+ break;
default:
FatalError("Unknown GTT size value: %08x\n", (int)INREG(PGETBL_CTL));
}
@@ -509,11 +518,11 @@ I830DetectMemory(ScrnInfoPtr pScrn)
memsize = MB(64) - KB(range);
break;
case G33_GMCH_GMS_STOLEN_128M:
- if (IS_G33CLASS(pI830))
+ if (IS_I9XX(pI830))
memsize = MB(128) - KB(range);
break;
case G33_GMCH_GMS_STOLEN_256M:
- if (IS_G33CLASS(pI830))
+ if (IS_I9XX(pI830))
memsize = MB(256) - KB(range);
break;
}
@@ -599,8 +608,13 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- gttaddr = pI830->MMIOAddr + (512 * 1024);
- pI830->GTTMapSize = 512 * 1024;
+ if (IS_IGD_GM(pI830)) {
+ gttaddr = pI830->MMIOAddr + MB(2);
+ pI830->GTTMapSize = MB(2);
+ } else {
+ gttaddr = pI830->MMIOAddr + KB(512);
+ pI830->GTTMapSize = KB(512);
+ }
}
else
{
commit 4f288ff2d1e7d28bf49167f073fbce21492a7c32
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:25:47 2008 +0800
Add new integrated graphics chipset ids
diff --git a/src/common.h b/src/common.h
index daab52c..7737194 100644
--- a/src/common.h
+++ b/src/common.h
@@ -384,6 +384,11 @@ extern int I810_DEBUG;
#define PCI_CHIP_Q33_G_BRIDGE 0x29D0
#endif
+#ifndef PCI_CHIP_IGD_GM
+#define PCI_CHIP_IGD_GM 0x2A42
+#define PCI_CHIP_IGD_GM_BRIDGE 0x2A40
+#endif
+
#if XSERVER_LIBPCIACCESS
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
#define VENDOR_ID(p) (p)->vendor_id
@@ -415,14 +420,15 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
+#define IS_IGD_GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_IGD_GM(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810))
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 8ae35b6..1ecb04a 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -152,6 +152,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
{ 0, 0, 0 },
};
@@ -204,6 +205,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
+ {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
{-1, NULL}
};
@@ -233,6 +235,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
@@ -796,6 +799,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_G33_G:
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
+ case PCI_CHIP_IGD_GM:
xf86SetEntitySharable(usedChips[i]);
/* Allocate an entity private if necessary */
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 9a59be1..eeb5ed0 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -244,6 +244,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
+ {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
{-1, NULL}
};
@@ -267,6 +268,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED}
};
@@ -1263,6 +1265,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
case PCI_CHIP_Q33_G:
chipname = "Q33";
break;
+ case PCI_CHIP_IGD_GM:
+ chipname = "Intel Integrated Graphics Device";
+ break;
default:
chipname = "unknown chipset";
break;
@@ -2783,7 +2788,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
* alone in that case.
* Also make sure the DRM can handle the swap.
*/
- if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) &&
+ if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_IGD_GM(pI830) &&
(!pI830->directRenderingEnabled ||
(pI830->directRenderingEnabled && pI830->drmMinor >= 10))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "adjusting plane->pipe mappings "
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index cf0e345..50ecb60 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -113,7 +113,7 @@ i830_set_lvds_backlight_method(xf86OutputPtr output)
if (i830_kernel_backlight_available(output)) {
method = BCM_KERNEL;
- } else if (IS_I965GM(pI830)) {
+ } else if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
blc_pwm_ctl2 = INREG(BLC_PWM_CTL2);
if (blc_pwm_ctl2 & BLM_LEGACY_MODE2)
method = BCM_LEGACY;
@@ -161,7 +161,7 @@ i830_lvds_get_backlight_max_native(xf86OutputPtr output)
CARD32 pwm_ctl = INREG(BLC_PWM_CTL);
int val;
- if (IS_I965GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
val = ((pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK2) >>
BACKLIGHT_MODULATION_FREQ_SHIFT2);
} else {
@@ -413,7 +413,7 @@ i830_lvds_save (xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830))
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
pI830->saveBLC_PWM_CTL2 = INREG(BLC_PWM_CTL2);
pI830->savePP_ON = INREG(LVDSPP_ON);
pI830->savePP_OFF = INREG(LVDSPP_OFF);
@@ -429,7 +429,7 @@ i830_lvds_restore(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830))
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
OUTREG(BLC_PWM_CTL2, pI830->saveBLC_PWM_CTL2);
OUTREG(BLC_PWM_CTL, pI830->saveBLC_PWM_CTL);
OUTREG(LVDSPP_ON, pI830->savePP_ON);
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 6b7037e..4b04994 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -727,7 +727,7 @@ i830_sdvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
}
/* Set the SDVO control regs. */
- if (IS_I965GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
sdvox = SDVO_BORDER_ENABLE;
} else {
sdvox = INREG(dev_priv->output_device);
commit f089942689df622b1af00569eade4883a84eb7a3
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Jan 3 11:28:18 2008 +0800
Change origin i965G_1 to chipset market name G35.
diff --git a/src/common.h b/src/common.h
index 40ea038..daab52c 100644
--- a/src/common.h
+++ b/src/common.h
@@ -339,9 +339,9 @@ extern int I810_DEBUG;
#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
#endif
-#ifndef PCI_CHIP_I965_G_1
-#define PCI_CHIP_I965_G_1 0x2982
-#define PCI_CHIP_I965_G_1_BRIDGE 0x2980
+#ifndef PCI_CHIP_G35_G
+#define PCI_CHIP_G35_G 0x2982
+#define PCI_CHIP_G35_G_BRIDGE 0x2980
#endif
#ifndef PCI_CHIP_I965_Q
@@ -416,7 +416,7 @@ extern int I810_DEBUG;
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G_1 || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
diff --git a/src/i810_driver.c b/src/i810_driver.c
index a6c13ed..8ae35b6 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -144,7 +144,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I965_G_1, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ),
@@ -196,7 +196,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
{PCI_CHIP_I965_G, "965G"},
- {PCI_CHIP_I965_G_1, "965G"},
+ {PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{PCI_CHIP_I965_GM, "965GM"},
@@ -225,7 +225,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
- {PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
+ {PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, RES_SHARED_VGA},
@@ -788,7 +788,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
case PCI_CHIP_I965_G:
- case PCI_CHIP_I965_G_1:
+ case PCI_CHIP_G35_G:
case PCI_CHIP_I965_Q:
case PCI_CHIP_I946_GZ:
case PCI_CHIP_I965_GM:
diff --git a/src/i830_driver.c b/src/i830_driver.c
index ca4544d..9a59be1 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -236,7 +236,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
{PCI_CHIP_I965_G, "965G"},
- {PCI_CHIP_I965_G_1, "965G"},
+ {PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{PCI_CHIP_I965_GM, "965GM"},
@@ -259,7 +259,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
- {PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
+ {PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, RES_SHARED_VGA},
@@ -1237,9 +1237,11 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
chipname = "945GME";
break;
case PCI_CHIP_I965_G:
- case PCI_CHIP_I965_G_1:
chipname = "965G";
break;
+ case PCI_CHIP_G35_G:
+ chipname = "G35";
+ break;
case PCI_CHIP_I965_Q:
chipname = "965Q";
break;
commit 71143200ed66cb9dcc1f9edf98128be80b05619c
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Fri Jan 4 15:01:25 2008 -0800
Don't modify low bit of BLC_PWM_CTL when using combo backlight control
On some platforms, the low bit of BLC_PWM_CTL is wired as a 'max brightness'
flag, rather than a regular part of the backlight duty cycle. So when in the
combo mode, divide the total number of backlight levels available by two
(tossing one bit) and adjust the programming in the set_brightness routine.
Note that platforms with this behavior may need quirks added so that they work
by default.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index c58a7e0..cf0e345 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -234,6 +234,12 @@ i830_lvds_set_backlight_combo(xf86OutputPtr output, int level)
#endif
}
+ /*
+ * Don't set the lowest bit in combo configs since it can act as a flag for
+ * max brightness.
+ */
+ level <<= 1;
+
blc_pwm_ctl = INREG(BLC_PWM_CTL);
blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
OUTREG(BLC_PWM_CTL, blc_pwm_ctl | (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
@@ -248,7 +254,17 @@ i830_lvds_get_backlight_combo(xf86OutputPtr output)
blc_pwm_ctl = INREG(BLC_PWM_CTL);
blc_pwm_ctl &= BACKLIGHT_DUTY_CYCLE_MASK;
- return blc_pwm_ctl;
+
+ /* Since we don't use the low bit when using combo, the value is halved */
+
+ return blc_pwm_ctl >> 1;
+}
+
+static int
+i830_lvds_get_backlight_max_combo(xf86OutputPtr output)
+{
+ /* Since we don't set the low bit when using combo, the range is halved */
+ return i830_lvds_get_backlight_max_native(output) >> 1;
}
/*
@@ -661,7 +677,7 @@ i830_lvds_set_backlight_control(xf86OutputPtr output)
dev_priv->set_backlight = i830_lvds_set_backlight_combo;
dev_priv->get_backlight = i830_lvds_get_backlight_combo;
dev_priv->backlight_max =
- i830_lvds_get_backlight_max_native(output);
+ i830_lvds_get_backlight_max_combo(output);
break;
case BCM_KERNEL:
dev_priv->set_backlight = i830_lvds_set_backlight_kernel;
@@ -1003,7 +1019,7 @@ i830_lvds_init(ScrnInfoPtr pScrn)
case BCM_COMBO:
dev_priv->set_backlight = i830_lvds_set_backlight_combo;
dev_priv->get_backlight = i830_lvds_get_backlight_combo;
- dev_priv->backlight_max = i830_lvds_get_backlight_max_native(output);
+ dev_priv->backlight_max = i830_lvds_get_backlight_max_combo(output);
break;
case BCM_KERNEL:
dev_priv->set_backlight = i830_lvds_set_backlight_kernel;
commit b434bf4029d1a405216454629bcea717c779ae5a
Author: hulifox008 <hulifox008 at 163.com>
Date: Fri Jan 4 02:46:54 2008 -0800
Fix copy'n'paste-o in unused airlied i2c code.
diff --git a/src/i830_i2c.c b/src/i830_i2c.c
index da8f38e..d80229d 100644
--- a/src/i830_i2c.c
+++ b/src/i830_i2c.c
@@ -88,7 +88,7 @@ static void i830_getscl(I2CBusPtr b, int *state)
OUTREG(b->DriverPrivate.uval, GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK);
OUTREG(b->DriverPrivate.uval, 0);
val = INREG(b->DriverPrivate.uval);
- *state = ((val & GPIO_DATA_VAL_IN) != 0);
+ *state = ((val & GPIO_CLOCK_VAL_IN) != 0);
}
static int i830_getsda(I2CBusPtr b)
commit f2ffc0f6e038357dda268363e52c11ada1d0b810
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Thu Jan 3 11:16:15 2008 -0800
Fix compilation error when not using DRI
This patch complements 88f8b688e2316ae4a1f7485f0010ce90de54783a which
added uint64_t typed variables to avoid unsigned long overflows in
32-bit architectures but didn't include <stdint.h> with the required
definition.
When XF86DRI and _XF86DRI_SERVER_ are defined this header gets
indirectly included through "i830_dri.h", thanks to "i830_common.h"
which masquerades this problem as released in 2.1.0 and that manifests
with :
In file included from i810_driver.c:88:
i830.h:137: error: expected specifier-qualifier-list before 'uint64_t'
i830.h:240: error: expected specifier-qualifier-list before 'uint64_t'
Patch from Carlo Marcelo Arenas Belon <carenas at sajinet.com.pe>
diff --git a/src/i830.h b/src/i830.h
index fe4d6c5..dcb87cc 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -40,6 +40,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define I830DEBUG
#endif
+#include <stdint.h>
+
#ifndef REMAP_RESERVED
#define REMAP_RESERVED 0
#endif
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