xf86-video-intel: 4 commits - src/brw_structs.h src/common.h src/i810_driver.c src/i810_reg.h src/i830_driver.c src/i830_lvds.c src/i830_sdvo.c src/i965_render.c src/i965_video.c
Zhenyu Wang
zhen at kemper.freedesktop.org
Tue Jan 8 21:45:02 PST 2008
src/brw_structs.h | 12 +++++++++---
src/common.h | 10 ++++++++--
src/i810_driver.c | 4 ++++
src/i810_reg.h | 5 +++++
src/i830_driver.c | 32 ++++++++++++++++++++++++++------
src/i830_lvds.c | 8 ++++----
src/i830_sdvo.c | 2 +-
src/i965_render.c | 6 +++++-
src/i965_video.c | 5 ++++-
9 files changed, 66 insertions(+), 18 deletions(-)
New commits:
commit d3b41bcf231a6ffd289c128c06aa619f554a776c
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:28:25 2008 +0800
Disable frame buffer compression on new chipset now.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 2183b1d..32d4602 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2510,7 +2510,8 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
}
/* Enable FB compression if possible */
- if (i830_fb_compression_supported(pI830) && !IS_I965GM(pI830))
+ if (i830_fb_compression_supported(pI830) && !IS_I965GM(pI830)
+ && !IS_IGD_GM(pI830))
pI830->fb_compression = TRUE;
else
pI830->fb_compression = FALSE;
commit 2f0c0427dc4113bac64cda07c6365df1f0637697
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:27:42 2008 +0800
Update PIPELINE_SELECT instruction and surface state format for new chipset
diff --git a/src/brw_structs.h b/src/brw_structs.h
index 28d8e12..d4fc5c6 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
@@ -832,9 +832,8 @@ struct brw_wm_unit_state
unsigned int program_computes_depth:1;
unsigned int program_uses_killpixel:1;
unsigned int legacy_line_rast: 1;
- unsigned int pad1:1;
- unsigned int max_threads:6;
- unsigned int pad2:1;
+ unsigned int transposed_urb_read:1;
+ unsigned int max_threads:7;
} wm5;
float global_depth_offset_constant;
@@ -977,6 +976,13 @@ struct brw_surface_state
unsigned int min_array_elt:9;
unsigned int min_lod:4;
} ss4;
+
+ struct {
+ unsigned int pad:20;
+ unsigned int y_offset:4;
+ unsigned int pad2:1;
+ unsigned int x_offset:7;
+ } ss5;
};
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 26f9db4..bed3901 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -2284,6 +2284,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BRW_STATE_SIP BRW_3D(0, 1, 2)
#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4)
+#define NEW_PIPELINE_SELECT BRW_3D(1, 1, 4)
+
#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0)
#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0)
diff --git a/src/i965_render.c b/src/i965_render.c
index ad3b53e..4b1d7f3 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -907,6 +907,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
src_sampler_offset) >> 5;
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
+ wm_state->wm5.transposed_urb_read = 0;
wm_state->wm5.thread_dispatch_enable = 1;
/* just use 16-pixel dispatch (4 subspans), don't need to change kernel
* start point
@@ -933,7 +934,10 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_LP_RING(12);
/* Match Mesa driver setup */
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ if (IS_IGD_GM(pI830))
+ OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
OUT_RING(BRW_CS_URB_STATE | 0);
OUT_RING((0 << 4) | /* URB Entry Allocation Size */
diff --git a/src/i965_video.c b/src/i965_video.c
index 0357270..928b52b 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -509,7 +509,10 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_LP_RING(12);
/* Match Mesa driver setup */
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ if (IS_IGD_GM(pI830))
+ OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
/* Mesa does this. Who knows... */
OUT_RING(BRW_CS_URB_STATE | 0);
commit 139e9affdd49dcbe08e260a0a2bd001de16566e6
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:26:57 2008 +0800
GTT access change for new integrated graphics device
diff --git a/src/i810_reg.h b/src/i810_reg.h
index a6663a4..26f9db4 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -539,6 +539,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PGETBL_SIZE_512KB (0 << 1)
#define PGETBL_SIZE_256KB (1 << 1)
#define PGETBL_SIZE_128KB (2 << 1)
+#define PGETBL_SIZE_1MB (3 << 1)
+#define PGETBL_SIZE_2MB (4 << 1)
+#define PGETBL_SIZE_1_5MB (5 << 1)
#define G33_PGETBL_SIZE_MASK (3 << 8)
#define G33_PGETBL_SIZE_1M (1 << 8)
#define G33_PGETBL_SIZE_2M (2 << 8)
diff --git a/src/i830_driver.c b/src/i830_driver.c
index eeb5ed0..2183b1d 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -455,6 +455,15 @@ I830DetectMemory(ScrnInfoPtr pScrn)
case PGETBL_SIZE_128KB:
gtt_size = 128;
break;
+ case PGETBL_SIZE_1MB:
+ gtt_size = 1024;
+ break;
+ case PGETBL_SIZE_2MB:
+ gtt_size = 2048;
+ break;
+ case PGETBL_SIZE_1_5MB:
+ gtt_size = 1024 + 512;
+ break;
default:
FatalError("Unknown GTT size value: %08x\n", (int)INREG(PGETBL_CTL));
}
@@ -509,11 +518,11 @@ I830DetectMemory(ScrnInfoPtr pScrn)
memsize = MB(64) - KB(range);
break;
case G33_GMCH_GMS_STOLEN_128M:
- if (IS_G33CLASS(pI830))
+ if (IS_I9XX(pI830))
memsize = MB(128) - KB(range);
break;
case G33_GMCH_GMS_STOLEN_256M:
- if (IS_G33CLASS(pI830))
+ if (IS_I9XX(pI830))
memsize = MB(256) - KB(range);
break;
}
@@ -599,8 +608,13 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- gttaddr = pI830->MMIOAddr + (512 * 1024);
- pI830->GTTMapSize = 512 * 1024;
+ if (IS_IGD_GM(pI830)) {
+ gttaddr = pI830->MMIOAddr + MB(2);
+ pI830->GTTMapSize = MB(2);
+ } else {
+ gttaddr = pI830->MMIOAddr + KB(512);
+ pI830->GTTMapSize = KB(512);
+ }
}
else
{
commit 4f288ff2d1e7d28bf49167f073fbce21492a7c32
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:25:47 2008 +0800
Add new integrated graphics chipset ids
diff --git a/src/common.h b/src/common.h
index daab52c..7737194 100644
--- a/src/common.h
+++ b/src/common.h
@@ -384,6 +384,11 @@ extern int I810_DEBUG;
#define PCI_CHIP_Q33_G_BRIDGE 0x29D0
#endif
+#ifndef PCI_CHIP_IGD_GM
+#define PCI_CHIP_IGD_GM 0x2A42
+#define PCI_CHIP_IGD_GM_BRIDGE 0x2A40
+#endif
+
#if XSERVER_LIBPCIACCESS
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
#define VENDOR_ID(p) (p)->vendor_id
@@ -415,14 +420,15 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
+#define IS_IGD_GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_IGD_GM(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810))
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 8ae35b6..1ecb04a 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -152,6 +152,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
{ 0, 0, 0 },
};
@@ -204,6 +205,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
+ {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
{-1, NULL}
};
@@ -233,6 +235,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
@@ -796,6 +799,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_G33_G:
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
+ case PCI_CHIP_IGD_GM:
xf86SetEntitySharable(usedChips[i]);
/* Allocate an entity private if necessary */
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 9a59be1..eeb5ed0 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -244,6 +244,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
+ {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
{-1, NULL}
};
@@ -267,6 +268,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED}
};
@@ -1263,6 +1265,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
case PCI_CHIP_Q33_G:
chipname = "Q33";
break;
+ case PCI_CHIP_IGD_GM:
+ chipname = "Intel Integrated Graphics Device";
+ break;
default:
chipname = "unknown chipset";
break;
@@ -2783,7 +2788,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
* alone in that case.
* Also make sure the DRM can handle the swap.
*/
- if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) &&
+ if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_IGD_GM(pI830) &&
(!pI830->directRenderingEnabled ||
(pI830->directRenderingEnabled && pI830->drmMinor >= 10))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "adjusting plane->pipe mappings "
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index cf0e345..50ecb60 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -113,7 +113,7 @@ i830_set_lvds_backlight_method(xf86OutputPtr output)
if (i830_kernel_backlight_available(output)) {
method = BCM_KERNEL;
- } else if (IS_I965GM(pI830)) {
+ } else if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
blc_pwm_ctl2 = INREG(BLC_PWM_CTL2);
if (blc_pwm_ctl2 & BLM_LEGACY_MODE2)
method = BCM_LEGACY;
@@ -161,7 +161,7 @@ i830_lvds_get_backlight_max_native(xf86OutputPtr output)
CARD32 pwm_ctl = INREG(BLC_PWM_CTL);
int val;
- if (IS_I965GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
val = ((pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK2) >>
BACKLIGHT_MODULATION_FREQ_SHIFT2);
} else {
@@ -413,7 +413,7 @@ i830_lvds_save (xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830))
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
pI830->saveBLC_PWM_CTL2 = INREG(BLC_PWM_CTL2);
pI830->savePP_ON = INREG(LVDSPP_ON);
pI830->savePP_OFF = INREG(LVDSPP_OFF);
@@ -429,7 +429,7 @@ i830_lvds_restore(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830))
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
OUTREG(BLC_PWM_CTL2, pI830->saveBLC_PWM_CTL2);
OUTREG(BLC_PWM_CTL, pI830->saveBLC_PWM_CTL);
OUTREG(LVDSPP_ON, pI830->savePP_ON);
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 6b7037e..4b04994 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -727,7 +727,7 @@ i830_sdvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
}
/* Set the SDVO control regs. */
- if (IS_I965GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
sdvox = SDVO_BORDER_ENABLE;
} else {
sdvox = INREG(dev_priv->output_device);
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