xf86-video-intel: Branch 'xf86-video-intel-2.6-branch' - 2 commits - src/i830_display.c src/i830_driver.c src/i830_exa.c

[Zhenyu Wang]

 src/i830_display.c |    4 ----
 src/i830_driver.c  |   25 -------------------------
 src/i830_exa.c     |   19 +++++++++++++------
 3 files changed, 13 insertions(+), 35 deletions(-)

New commits:
commit fac43181af0ad59fa6d06e26d369d886ce221c10
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date:   Wed Dec 31 22:56:57 2008 +0800

    UXA: Fallback to dri_bo_map() if pin failed
    
    This fixes VT switch issue with UXA after Eric's
    aae4008096399a0e84abc7c016b35092caf9db25 on 2D side.
    (cherry picked from commit 1f61e97904dfe5f8c08bb9f284cfdfe878f7e541)

diff --git a/src/i830_exa.c b/src/i830_exa.c
index 636aa0a..aeffedd 100644
--- a/src/i830_exa.c
+++ b/src/i830_exa.c
@@ -785,11 +785,15 @@ i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access)
 	    i830->need_sync = FALSE;
 	}
 
-	if (drm_intel_bo_pin(bo, 4096) != 0)
-	    return FALSE;
-
-	drm_intel_gem_bo_start_gtt_access(bo, access == UXA_ACCESS_RW);
-	pixmap->devPrivate.ptr = pI830->FbBase + bo->offset;
+	if (drm_intel_bo_pin(bo, 4096) != 0) {
+	    /* happen in vt switched */
+	    if (dri_bo_map(bo, access == UXA_ACCESS_RW) != 0)
+		return FALSE;
+	    pixmap->devPrivate.ptr = bo->virtual;
+	} else {
+	    drm_intel_gem_bo_start_gtt_access(bo, access == UXA_ACCESS_RW);
+	    pixmap->devPrivate.ptr = pI830->FbBase + bo->offset;
+	}
     }
     return TRUE;
 }
@@ -804,7 +808,10 @@ i830_uxa_finish_access (PixmapPtr pixmap)
 	ScrnInfoPtr scrn = xf86Screens[screen->myNum];
 	I830Ptr i830 = I830PTR(scrn);
 
-	drm_intel_bo_unpin(bo);
+	if (bo->virtual)
+	    dri_bo_unmap(bo);
+	else
+	    drm_intel_bo_unpin(bo);
 
 	pixmap->devPrivate.ptr = NULL;
 	if (bo == i830->front_buffer->bo)
commit 8dfbd9ea1733768bf528e04a660a1ac478c3249e
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Dec 29 13:42:44 2008 -0800

    Don't touch the pipestat regs for detecting FIFO underrun. The kernel owns them.
    
    Since we don't perform any synchronization with the kernel on these regs, we
    could race with the kernel to write stale values and end up not having vblank
    interrupts enabled when somebody was waiting on one.
    (cherry picked from commit 830bf916724afd21b7947f797c22a8c8aab7a0a4)

diff --git a/src/i830_display.c b/src/i830_display.c
index 2e5d55a..7a9999a 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1202,7 +1202,6 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
     int dspstride_reg = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
     int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
     int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
-    int pipestat_reg = (pipe == 0) ? PIPEASTAT : PIPEBSTAT;
     int i, num_outputs = 0;
     int refclk;
     intel_clock_t clock;
@@ -1514,9 +1513,6 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 #endif
     
     i830WaitForVblank(pScrn);
-
-    /* Clear any FIFO underrun status that may have occurred normally */
-    OUTREG(pipestat_reg, INREG(pipestat_reg) | FIFO_UNDERRUN);
 }
 
 
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 90fa507..beb134d 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2495,10 +2495,6 @@ RestoreHWState(ScrnInfoPtr pScrn)
        OUTREG(FBC_CONTROL, pI830->saveFBC_CONTROL);
    }
 
-   /* Clear any FIFO underrun status that may have occurred normally */
-   OUTREG(PIPEASTAT, INREG(PIPEASTAT) | FIFO_UNDERRUN);
-   OUTREG(PIPEBSTAT, INREG(PIPEBSTAT) | FIFO_UNDERRUN);
-
    vgaHWRestore(pScrn, vgaReg, VGA_SR_FONTS);
    vgaHWLock(hwp);
 
@@ -2631,7 +2627,6 @@ I830BlockHandler(int i,
     ScreenPtr pScreen = screenInfo.screens[i];
     ScrnInfoPtr pScrn = xf86Screens[i];
     I830Ptr pI830 = I830PTR(pScrn);
-    xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 
     pScreen->BlockHandler = pI830->BlockHandler;
 
@@ -2668,26 +2663,6 @@ I830BlockHandler(int i,
     if (pI830->accel == ACCEL_UXA)
 	i830_uxa_block_handler (pScreen);
 #endif
-    /*
-     * Check for FIFO underruns at block time (which amounts to just
-     * periodically).  If this happens, it means our DSPARB or some other
-     * memory arbitration setting is wrong for the current configuration
-     * (except for mode setting, where it may occur naturally).
-     * Check & ack the condition.
-     */
-    if (!pI830->use_drm_mode && pScrn->vtSema && !DSPARB_HWCONTROL(pI830)) {
-	if (xf86_config->crtc[0]->enabled &&
-		(INREG(PIPEASTAT) & FIFO_UNDERRUN)) {
-	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "underrun on pipe A!\n");
-	    OUTREG(PIPEASTAT, INREG(PIPEASTAT) | FIFO_UNDERRUN);
-	}
-	if (xf86_config->num_crtc > 1 &&
-		xf86_config->crtc[1]->enabled &&
-		(INREG(PIPEBSTAT) & FIFO_UNDERRUN)) {
-	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "underrun on pipe B!\n");
-	    OUTREG(PIPEBSTAT, INREG(PIPEBSTAT) | FIFO_UNDERRUN);
-	}
-    }
 
     I830VideoBlockHandler(i, blockData, pTimeout, pReadmask);
 }