xf86-video-ati: Branch 'master' - 2 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Tue Dec 16 22:03:59 PST 2008
src/legacy_output.c | 17 +++++++++++------
src/radeon_exa_render.c | 29 +++++++++++++++++------------
src/radeon_textured_videofuncs.c | 2 +-
3 files changed, 29 insertions(+), 19 deletions(-)
New commits:
commit b2b43905a5385a8bb0b59b8e50952863d8dacb59
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Wed Dec 17 00:59:52 2008 -0500
Pre-avivo: fix FP setup
- make sure to clear various shadow timing bits
- crtc1 select bit was set wrong.
- should fix bugs like 19100
diff --git a/src/legacy_output.c b/src/legacy_output.c
index e5ddf1f..f9b0dff 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -947,12 +947,19 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ save->fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
+ RADEON_FP_DFP_SYNC_SEL |
+ RADEON_FP_CRT_SYNC_SEL |
+ RADEON_FP_CRTC_LOCK_8DOT |
+ RADEON_FP_USE_SHADOW_EN |
+ RADEON_FP_CRTC_USE_SHADOW_VEND |
+ RADEON_FP_CRT_SYNC_ALT);
+
if (pScrn->rgbBits == 8)
save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
else
save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
-
if (IsPrimary) {
if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) {
save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
@@ -961,7 +968,7 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
else
save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
} else
- save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
+ save->fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
} else {
if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) {
save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
@@ -1037,16 +1044,14 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
else
save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
- } else {
+ } else
save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
- }
} else {
if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
- } else {
+ } else
save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
- }
}
if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
commit 3754cc23abac99880eda87d06aa42e16081b6c8a
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Wed Dec 17 00:56:19 2008 -0500
R2xx: switch EXA composite to rects rather quads
For conistency with Xv path and to reduce potential diagonal tearing
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index b5f0197..55e55be 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -2016,41 +2016,46 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
RADEON_CP_VC_CNTL_MAOS_ENABLE |
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
(3 << RADEON_CP_VC_CNTL_NUM_SHIFT));
- } else {
- if (IS_R300_3D || IS_R500_3D)
- BEGIN_RING(4 * vtx_count + 4);
- else
- BEGIN_RING(4 * vtx_count + 2);
-
+ } else if (IS_R300_3D || IS_R500_3D) {
+ BEGIN_RING(4 * vtx_count + 4);
OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
4 * vtx_count));
OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST |
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
+ } else {
+ BEGIN_RING(3 * vtx_count + 2);
+ OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
+ 3 * vtx_count));
+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
+ RADEON_CP_VC_CNTL_PRIM_WALK_RING |
+ (3 << RADEON_CP_VC_CNTL_NUM_SHIFT));
}
#else /* ACCEL_CP */
if (IS_R300_3D || IS_R500_3D)
BEGIN_ACCEL(2 + vtx_count * 4);
- else if (info->ChipFamily < CHIP_FAMILY_R200)
- BEGIN_ACCEL(1 + vtx_count * 3);
else
- BEGIN_ACCEL(1 + vtx_count * 4);
+ BEGIN_ACCEL(1 + vtx_count * 3);
if (info->ChipFamily < CHIP_FAMILY_R200)
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
RADEON_VF_RADEON_MODE |
(3 << RADEON_VF_NUM_VERTICES_SHIFT)));
- else
+ else if (IS_R300_3D || IS_R500_3D)
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
RADEON_VF_PRIM_WALK_DATA |
(4 << RADEON_VF_NUM_VERTICES_SHIFT)));
+ else
+ OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
+ RADEON_VF_PRIM_WALK_DATA |
+ (3 << RADEON_VF_NUM_VERTICES_SHIFT)));
#endif
if (info->accel_state->has_mask) {
- if (info->ChipFamily >= CHIP_FAMILY_R200) {
+ if (IS_R300_3D || IS_R500_3D) {
VTX_OUT_MASK((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0],
xFixedToFloat(maskTopLeft.x) / info->accel_state->texW[1], xFixedToFloat(maskTopLeft.y) / info->accel_state->texH[1]);
@@ -2065,7 +2070,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0],
xFixedToFloat(maskTopRight.x) / info->accel_state->texW[1], xFixedToFloat(maskTopRight.y) / info->accel_state->texH[1]);
} else {
- if (info->ChipFamily >= CHIP_FAMILY_R200) {
+ if (IS_R300_3D || IS_R500_3D) {
VTX_OUT((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]);
}
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 44f7228..410430c 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -1591,7 +1591,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]);
} else {
/*
- * Just render a quad (using three coords).
+ * Just render a rect (using three coords).
*/
VTX_OUT((float)dstX, (float)(dstY + dsth),
(float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]);
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