xf86-video-ati: Branch 'master' - 13 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Thu Dec 4 09:29:22 PST 2008
src/radeon_commonfuncs.c | 41 ---
src/radeon_exa_render.c | 40 ++-
src/radeon_reg.h | 200 +++++++--------
src/radeon_textured_video.c | 58 +++-
src/radeon_textured_videofuncs.c | 489 +++++++++++++++++++++++++++++++++------
src/radeon_video.h | 4
6 files changed, 608 insertions(+), 224 deletions(-)
New commits:
commit 9eccd0ad0827a1b8ec9abb2cebf5768d204a5ce9
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Dec 4 12:28:12 2008 -0500
Fix up US setup after r3xx bicubic merge
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index dba197e..c7d42bc 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -496,44 +496,9 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
}
FINISH_ACCEL();
- /* pre-load FS tex instructions */
- if (IS_R300_3D) {
- BEGIN_ACCEL(2);
- /* tex inst for src texture */
- OUT_ACCEL_REG(R300_US_TEX_INST(0),
- (R300_TEX_SRC_ADDR(0) |
- R300_TEX_DST_ADDR(0) |
- R300_TEX_ID(0) |
- R300_TEX_INST(R300_TEX_INST_LD)));
-
- /* tex inst for mask texture */
- OUT_ACCEL_REG(R300_US_TEX_INST(1),
- (R300_TEX_SRC_ADDR(1) |
- R300_TEX_DST_ADDR(1) |
- R300_TEX_ID(1) |
- R300_TEX_INST(R300_TEX_INST_LD)));
- FINISH_ACCEL();
- }
-
- if (IS_R300_3D) {
- BEGIN_ACCEL(8);
- OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0)));
- } else {
+ if (IS_R300_3D)
+ BEGIN_ACCEL(4);
+ else {
BEGIN_ACCEL(6);
OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index b797200..a74abb6 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1413,8 +1413,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
/* setup the rasterizer, load FS */
- BEGIN_ACCEL(10);
if (pMask) {
+ BEGIN_ACCEL(16);
/* 4 components: 2 for tex0, 2 for tex1 */
OUT_ACCEL_REG(R300_RS_COUNT,
((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -1434,7 +1434,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_TEX_START(0) |
R300_TEX_SIZE(1) |
R300_RGBA_OUT));
+
+
} else {
+ BEGIN_ACCEL(15);
/* 2 components: 2 for tex0 */
OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -1453,14 +1456,45 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_TEX_START(0) |
R300_TEX_SIZE(0) |
R300_RGBA_OUT));
+
}
+ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0)));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0)));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0)));
+
OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
/* shader output swizzling */
OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
- /* tex inst for src texture is pre-loaded in RADEONInit3DEngine() */
- /* tex inst for mask texture is pre-loaded in RADEONInit3DEngine() */
+ /* tex inst for src texture */
+ OUT_ACCEL_REG(R300_US_TEX_INST(0),
+ (R300_TEX_SRC_ADDR(0) |
+ R300_TEX_DST_ADDR(0) |
+ R300_TEX_ID(0) |
+ R300_TEX_INST(R300_TEX_INST_LD)));
+
+ if (pMask) {
+ /* tex inst for mask texture */
+ OUT_ACCEL_REG(R300_US_TEX_INST(1),
+ (R300_TEX_SRC_ADDR(1) |
+ R300_TEX_DST_ADDR(1) |
+ R300_TEX_ID(1) |
+ R300_TEX_INST(R300_TEX_INST_LD)));
+ }
/* RGB inst
* temp addresses for texture inputs
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index ecc34a8..151dab6 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -435,7 +435,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(3) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
-
+
/* MUL temp2.rg, temp2.rrr0, const0.rgb */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
commit e13fba853ba19e6b0f081b9b3d9fa76c38a0f82b
Merge: d296337... 79bbdd9...
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Dec 4 12:25:29 2008 -0500
Merge branch 'bicubic' of git://git.infradead.org/users/drzeus/xf86-video-ati
commit 79bbdd984c925e37f5b3db2605339f1a21377fcf
Author: Pierre Ossman <pierre at ossman.eu>
Date: Wed Dec 3 20:33:36 2008 +0100
Change the XV_BICUBIC attribute to a tristate, where the third state
automatically turns the filter on and off as appropriate.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 318df49..cf6999c 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -229,9 +229,20 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
return BadAlloc;
}
- /* Bicubic filter loading */
+ /* Bicubic filter setup */
+ pPriv->bicubic_enabled = (pPriv->bicubic_state != BICUBIC_OFF);
if (!(IS_R300_3D || IS_R500_3D))
pPriv->bicubic_enabled = FALSE;
+ if (pPriv->bicubic_enabled && (pPriv->bicubic_state == BICUBIC_AUTO)) {
+ /*
+ * Applying the bicubic filter with a scale of less than 200%
+ * results in a blurred picture, so disable the filter.
+ */
+ if ((src_w > drw_w / 2) || (src_h > drw_h / 2))
+ pPriv->bicubic_enabled = FALSE;
+ }
+
+ /* Bicubic filter loading */
if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) {
pPriv->bicubic_offset = radeon_legacy_allocate_memory(pScrn,
&pPriv->bicubic_memory,
@@ -370,7 +381,7 @@ static XF86VideoFormatRec Formats[NUM_FORMATS] =
static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] =
{
- {XvSettable | XvGettable, 0, 1, "XV_BICUBIC"},
+ {XvSettable | XvGettable, 0, 2, "XV_BICUBIC"},
{0, 0, 0, NULL}
};
@@ -398,7 +409,7 @@ RADEONGetTexPortAttribute(ScrnInfoPtr pScrn,
if (info->accelOn) RADEON_SYNC(info, pScrn);
if (attribute == xvBicubic)
- *value = pPriv->bicubic_enabled ? 1 : 0;
+ *value = pPriv->bicubic_state;
else
return BadMatch;
@@ -417,7 +428,7 @@ RADEONSetTexPortAttribute(ScrnInfoPtr pScrn,
RADEON_SYNC(info, pScrn);
if (attribute == xvBicubic)
- pPriv->bicubic_enabled = ClipValue (value, 0, 1);
+ pPriv->bicubic_state = ClipValue (value, 0, 2);
else
return BadMatch;
@@ -480,7 +491,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
pPriv->videoStatus = 0;
pPriv->currentBuffer = 0;
pPriv->doubleBuffer = 0;
- pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_R300);
+ pPriv->bicubic_state = BICUBIC_AUTO;
/* gotta uninit this someplace, XXX: shouldn't be necessary for textured */
REGION_NULL(pScreen, &pPriv->clip);
diff --git a/src/radeon_video.h b/src/radeon_video.h
index 11b8029..448377b 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -95,6 +95,10 @@ typedef struct {
int bicubic_offset;
Bool bicubic_enabled;
uint32_t bicubic_src_offset;
+ int bicubic_state;
+#define BICUBIC_OFF 0
+#define BICUBIC_ON 1
+#define BICUBIC_AUTO 2
Atom device_id, location_id, instance_id;
commit bbdf821c179242266fd86edf9e688a6be9cf985f
Author: Pierre Ossman <pierre at ossman.eu>
Date: Wed Dec 3 19:42:50 2008 +0100
Make the R300 bicubic shader program a bit easier to understand by
having comments that describe the operation, not how it has to be
implemented in the hardware.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 284d8ce..6a66335 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -394,7 +394,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_TEX_SRC_ADDR(1) |
R300_TEX_DST_ADDR(2)));
- /* MAD temp1.r, temp1.ggg0, 1.0, 0.0 */
+ /* MOV temp1.r, temp1.ggg0 */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
@@ -417,7 +417,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_TEX_SRC_ADDR(1) |
R300_TEX_DST_ADDR(1)));
- /* MAD temp3.rg, temp2.ggg0, const0.rgb0, 0.0 */
+ /* MUL temp3.rg, temp2.ggg0, const0.rgb0 */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
@@ -434,7 +434,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- /* MAD temp2.rg, temp2.rrr0, const0.rgb, 0.0 */
+ /* MUL temp2.rg, temp2.rrr0, const0.rgb */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
@@ -518,7 +518,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(1) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- /* MAD temp1.rg, temp0.rgb0, 1.0, temp1.rgb0 */
+ /* ADD temp1.rg, temp0.rgb0, temp1.rgb0 */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(7), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
@@ -534,7 +534,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(1) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- /* MAD temp2.rg, temp0.rgb0, 1.0, temp3.rgb0 */
+ /* ADD temp2.rg, temp0.rgb0, temp3.rgb0 */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(8), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
@@ -550,7 +550,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(2) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- /* MAD temp3.rg, temp0.rgb0, 1.0, temp5.rgb0 */
+ /* ADD temp3.rg, temp0.rgb0, temp5.rgb0 */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(9), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
@@ -566,7 +566,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(3) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- /* MAD temp0.rg, temp0.rgb0, 1.0, temp4.rgb0 */
+ /* ADD temp0.rg, temp0.rgb0, temp4.rgb0 */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(10), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
@@ -608,7 +608,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(0)));
- /* MAD temp3.rgba, temp1.bbbb, srcp(temp4.rgba - temp3.rgba), temp3.rgba */
+ /* LRP temp3, temp1.bbbb, temp4, temp3 ->
+ * - PRESUB temps, temp4 - temp3
+ * - MAD temp3, temp1.bbbb, temps, temp3 */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(11), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
@@ -629,7 +631,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_ADDRD(3) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A)));
- /* MAD temp0.rgba, temp1.bbbb, srcp(temp5.rgba - temp0.rgba), temp0.rgba NOP*/
+ /* LRP temp0, temp1.bbbb, temp5, temp0 ->
+ * - PRESUB temps, temp5 - temp0
+ * - MAD temp0, temp1.bbbb, temps, temp0 */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(12), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
@@ -651,7 +655,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A)));
- /* MAD output, temp2.bbbb, srcp(temp3.rgba - temp0.rgba), temp0.rgba */
+ /* LRP output, temp2.bbbb, temp3, temp0 ->
+ * - PRESUB temps, temp3 - temp0
+ * - MAD output, temp2.bbbb, temps, temp0 */
OUT_ACCEL_REG(R300_US_ALU_RGB_INST(13), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
commit 8f4b22932c91f1d51fcbf1d1a99d852fcdaafdcc
Author: Pierre Ossman <pierre at ossman.eu>
Date: Wed Dec 3 19:31:31 2008 +0100
Now that we have a bicubic code path that messes up the pixel shader,
we need to restore it in the non-bicubic code.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 4d34f8f..284d8ce 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -683,7 +683,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_ACCEL();
} else {
- BEGIN_ACCEL(8);
+ BEGIN_ACCEL(11);
/* 2 components: 2 for tex0 */
OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -693,6 +693,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
+ /* Indirection levels */
+ OUT_ACCEL_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) |
+ R300_FIRST_TEX));
+
OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(1) |
R300_TEX_CODE_OFFSET(0) |
@@ -704,7 +708,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_TEX_SIZE(0) |
R300_RGBA_OUT));
- /* tex inst is preloaded in RADEONInit3DEngine() */
+ /* tex inst */
+ OUT_ACCEL_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) |
+ R300_TEX_DST_ADDR(0) |
+ R300_TEX_ID(0) |
+ R300_TEX_INST(R300_TEX_INST_LD)));
/* ALU inst */
/* RGB */
commit 0851daa6e7db77e440188d774ef8b3236146bcb9
Author: Pierre Ossman <pierre at ossman.eu>
Date: Wed Dec 3 19:17:36 2008 +0100
Fix macros so that they are safe to use with expressions as parameters.
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 19f9869..672d1b5 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4143,7 +4143,7 @@
#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204
/* PVS instructions */
/* Opcode and dst instruction */
-#define R300_PVS_DST_OPCODE(x) (x << 0)
+#define R300_PVS_DST_OPCODE(x) ((x) << 0)
/* Vector ops */
# define R300_VECTOR_NO_OP 0
# define R300_VE_DOT_PRODUCT 1
@@ -4211,7 +4211,7 @@
# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1
#define R300_PVS_DST_MATH_INST (1 << 6)
#define R300_PVS_DST_MACRO_INST (1 << 7)
-#define R300_PVS_DST_REG_TYPE(x) (x << 8)
+#define R300_PVS_DST_REG_TYPE(x) ((x) << 8)
# define R300_PVS_DST_REG_TEMPORARY 0
# define R300_PVS_DST_REG_A0 1
# define R300_PVS_DST_REG_OUT 2
@@ -4219,7 +4219,7 @@
# define R300_PVS_DST_REG_ALT_TEMPORARY 4
# define R300_PVS_DST_REG_INPUT 5
#define R300_PVS_DST_ADDR_MODE_1 (1 << 12)
-#define R300_PVS_DST_OFFSET(x) (x << 13)
+#define R300_PVS_DST_OFFSET(x) ((x) << 13)
#define R300_PVS_DST_WE_X (1 << 20)
#define R300_PVS_DST_WE_Y (1 << 21)
#define R300_PVS_DST_WE_Z (1 << 22)
@@ -4229,10 +4229,10 @@
#define R300_PVS_DST_PRED_ENABLE (1 << 26)
#define R300_PVS_DST_PRED_SENSE (1 << 27)
#define R300_PVS_DST_DUAL_MATH_OP (1 << 28)
-#define R300_PVS_DST_ADDR_SEL(x) (x << 29)
+#define R300_PVS_DST_ADDR_SEL(x) ((x) << 29)
#define R300_PVS_DST_ADDR_MODE_0 (1 << 31)
/* src operand instruction */
-#define R300_PVS_SRC_REG_TYPE(x) (x << 0)
+#define R300_PVS_SRC_REG_TYPE(x) ((x) << 0)
# define R300_PVS_SRC_REG_TEMPORARY 0
# define R300_PVS_SRC_REG_INPUT 1
# define R300_PVS_SRC_REG_CONSTANT 2
@@ -4240,11 +4240,11 @@
#define R300_SPARE_0 (1 << 2)
#define R300_PVS_SRC_ABS_XYZW (1 << 3)
#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4)
-#define R300_PVS_SRC_OFFSET(x) (x << 5)
-#define R300_PVS_SRC_SWIZZLE_X(x) (x << 13)
-#define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16)
-#define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19)
-#define R300_PVS_SRC_SWIZZLE_W(x) (x << 22)
+#define R300_PVS_SRC_OFFSET(x) ((x) << 5)
+#define R300_PVS_SRC_SWIZZLE_X(x) ((x) << 13)
+#define R300_PVS_SRC_SWIZZLE_Y(x) ((x) << 16)
+#define R300_PVS_SRC_SWIZZLE_Z(x) ((x) << 19)
+#define R300_PVS_SRC_SWIZZLE_W(x) ((x) << 22)
# define R300_PVS_SRC_SELECT_X 0
# define R300_PVS_SRC_SELECT_Y 1
# define R300_PVS_SRC_SELECT_Z 2
@@ -4255,7 +4255,7 @@
#define R300_PVS_SRC_NEG_Y (1 << 26)
#define R300_PVS_SRC_NEG_Z (1 << 27)
#define R300_PVS_SRC_NEG_W (1 << 28)
-#define R300_PVS_SRC_ADDR_SEL(x) (x << 29)
+#define R300_PVS_SRC_ADDR_SEL(x) ((x) << 29)
#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31)
#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc
@@ -4312,9 +4312,9 @@
#define R300_RS_IP_0 0x4310
#define R300_RS_IP_1 0x4314
-# define R300_RS_TEX_PTR(x) (x << 0)
-# define R300_RS_COL_PTR(x) (x << 6)
-# define R300_RS_COL_FMT(x) (x << 9)
+# define R300_RS_TEX_PTR(x) ((x) << 0)
+# define R300_RS_COL_PTR(x) ((x) << 6)
+# define R300_RS_COL_FMT(x) ((x) << 9)
# define R300_RS_COL_FMT_RGBA 0
# define R300_RS_COL_FMT_RGB0 2
# define R300_RS_COL_FMT_RGB1 3
@@ -4324,10 +4324,10 @@
# define R300_RS_COL_FMT_111A 8
# define R300_RS_COL_FMT_1110 9
# define R300_RS_COL_FMT_1111 10
-# define R300_RS_SEL_S(x) (x << 13)
-# define R300_RS_SEL_T(x) (x << 16)
-# define R300_RS_SEL_R(x) (x << 19)
-# define R300_RS_SEL_Q(x) (x << 22)
+# define R300_RS_SEL_S(x) ((x) << 13)
+# define R300_RS_SEL_T(x) ((x) << 16)
+# define R300_RS_SEL_R(x) ((x) << 19)
+# define R300_RS_SEL_Q(x) ((x) << 22)
# define R300_RS_SEL_C0 0
# define R300_RS_SEL_C1 1
# define R300_RS_SEL_C2 2
@@ -4335,21 +4335,21 @@
# define R300_RS_SEL_K0 4
# define R300_RS_SEL_K1 5
#define R300_RS_INST_COUNT 0x4304
-# define R300_INST_COUNT_RS(x) (x << 0)
+# define R300_INST_COUNT_RS(x) ((x) << 0)
# define R300_RS_W_EN (1 << 4)
-# define R300_TX_OFFSET_RS(x) (x << 5)
+# define R300_TX_OFFSET_RS(x) ((x) << 5)
#define R300_RS_INST_0 0x4330
#define R300_RS_INST_1 0x4334
-# define R300_INST_TEX_ID(x) (x << 0)
+# define R300_INST_TEX_ID(x) ((x) << 0)
# define R300_RS_INST_TEX_CN_WRITE (1 << 3)
-# define R300_INST_TEX_ADDR(x) (x << 6)
+# define R300_INST_TEX_ADDR(x) ((x) << 6)
#define R300_TX_INVALTAGS 0x4100
#define R300_TX_FILTER0_0 0x4400
#define R300_TX_FILTER0_1 0x4404
-# define R300_TX_CLAMP_S(x) (x << 0)
-# define R300_TX_CLAMP_T(x) (x << 3)
-# define R300_TX_CLAMP_R(x) (x << 6)
+# define R300_TX_CLAMP_S(x) ((x) << 0)
+# define R300_TX_CLAMP_T(x) ((x) << 3)
+# define R300_TX_CLAMP_R(x) ((x) << 6)
# define R300_TX_CLAMP_WRAP 0
# define R300_TX_CLAMP_MIRROR 1
# define R300_TX_CLAMP_CLAMP_LAST 2
@@ -4513,15 +4513,15 @@
# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
#define R300_US_PIXSIZE 0x4604
#define R300_US_CODE_OFFSET 0x4608
-# define R300_ALU_CODE_OFFSET(x) (x << 0)
-# define R300_ALU_CODE_SIZE(x) (x << 6)
-# define R300_TEX_CODE_OFFSET(x) (x << 13)
-# define R300_TEX_CODE_SIZE(x) (x << 18)
+# define R300_ALU_CODE_OFFSET(x) ((x) << 0)
+# define R300_ALU_CODE_SIZE(x) ((x) << 6)
+# define R300_TEX_CODE_OFFSET(x) ((x) << 13)
+# define R300_TEX_CODE_SIZE(x) ((x) << 18)
#define R300_US_CODE_ADDR_0 0x4610
-# define R300_ALU_START(x) (x << 0)
-# define R300_ALU_SIZE(x) (x << 6)
-# define R300_TEX_START(x) (x << 12)
-# define R300_TEX_SIZE(x) (x << 17)
+# define R300_ALU_START(x) ((x) << 0)
+# define R300_ALU_SIZE(x) ((x) << 6)
+# define R300_TEX_START(x) ((x) << 12)
+# define R300_TEX_SIZE(x) ((x) << 17)
# define R300_RGBA_OUT (1 << 22)
# define R300_W_OUT (1 << 23)
#define R300_US_CODE_ADDR_1 0x4614
@@ -4531,10 +4531,10 @@
#define R300_US_TEX_INST_1 0x4624
#define R300_US_TEX_INST_2 0x4628
#define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4)
-# define R300_TEX_SRC_ADDR(x) (x << 0)
-# define R300_TEX_DST_ADDR(x) (x << 6)
-# define R300_TEX_ID(x) (x << 11)
-# define R300_TEX_INST(x) (x << 15)
+# define R300_TEX_SRC_ADDR(x) ((x) << 0)
+# define R300_TEX_DST_ADDR(x) ((x) << 6)
+# define R300_TEX_ID(x) ((x) << 11)
+# define R300_TEX_INST(x) ((x) << 15)
# define R300_TEX_INST_NOP 0
# define R300_TEX_INST_LD 1
# define R300_TEX_INST_TEXKILL 2
@@ -4546,15 +4546,15 @@
#define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
-# define R300_ALU_RGB_ADDR0(x) (x << 0)
-# define R300_ALU_RGB_ADDR1(x) (x << 6)
-# define R300_ALU_RGB_ADDR2(x) (x << 12)
+# define R300_ALU_RGB_ADDR0(x) ((x) << 0)
+# define R300_ALU_RGB_ADDR1(x) ((x) << 6)
+# define R300_ALU_RGB_ADDR2(x) ((x) << 12)
# define R300_ALU_RGB_CONST(x) ((x) | (1 << 5))
/* ADDRD - where on the pixel stack the result of this instruction
will be written */
-# define R300_ALU_RGB_ADDRD(x) (x << 18)
-# define R300_ALU_RGB_WMASK(x) (x << 23)
-# define R300_ALU_RGB_OMASK(x) (x << 26)
+# define R300_ALU_RGB_ADDRD(x) ((x) << 18)
+# define R300_ALU_RGB_WMASK(x) ((x) << 23)
+# define R300_ALU_RGB_OMASK(x) ((x) << 26)
# define R300_ALU_RGB_MASK_NONE 0
# define R300_ALU_RGB_MASK_R 1
# define R300_ALU_RGB_MASK_G 2
@@ -4568,7 +4568,7 @@
#define R300_US_ALU_RGB_INST_1 0x48c4
#define R300_US_ALU_RGB_INST_2 0x48c8
#define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4)
-# define R300_ALU_RGB_SEL_A(x) (x << 0)
+# define R300_ALU_RGB_SEL_A(x) ((x) << 0)
# define R300_ALU_RGB_SRC0_RGB 0
# define R300_ALU_RGB_SRC0_RRR 1
# define R300_ALU_RGB_SRC0_GGG 2
@@ -4601,21 +4601,21 @@
# define R300_ALU_RGB_SRC0_ABG 29
# define R300_ALU_RGB_SRC1_ABG 30
# define R300_ALU_RGB_SRC2_ABG 31
-# define R300_ALU_RGB_MOD_A(x) (x << 5)
+# define R300_ALU_RGB_MOD_A(x) ((x) << 5)
# define R300_ALU_RGB_MOD_NOP 0
# define R300_ALU_RGB_MOD_NEG 1
# define R300_ALU_RGB_MOD_ABS 2
# define R300_ALU_RGB_MOD_NAB 3
-# define R300_ALU_RGB_SEL_B(x) (x << 7)
-# define R300_ALU_RGB_MOD_B(x) (x << 12)
-# define R300_ALU_RGB_SEL_C(x) (x << 14)
-# define R300_ALU_RGB_MOD_C(x) (x << 19)
-# define R300_ALU_RGB_SRCP_OP(x) (x << 21)
+# define R300_ALU_RGB_SEL_B(x) ((x) << 7)
+# define R300_ALU_RGB_MOD_B(x) ((x) << 12)
+# define R300_ALU_RGB_SEL_C(x) ((x) << 14)
+# define R300_ALU_RGB_MOD_C(x) ((x) << 19)
+# define R300_ALU_RGB_SRCP_OP(x) ((x) << 21)
# define R300_ALU_RGB_SRCP_OP_1_MINUS_2RGB0 0
# define R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0 1
# define R300_ALU_RGB_SRCP_OP_RGB1_PLUS_RGB0 2
# define R300_ALU_RGB_SRCP_OP_1_MINUS_RGB0 3
-# define R300_ALU_RGB_OP(x) (x << 23)
+# define R300_ALU_RGB_OP(x) ((x) << 23)
# define R300_ALU_RGB_OP_MAD 0
# define R300_ALU_RGB_OP_DP3 1
# define R300_ALU_RGB_OP_DP4 2
@@ -4626,7 +4626,7 @@
# define R300_ALU_RGB_OP_CMP 8
# define R300_ALU_RGB_OP_FRC 9
# define R300_ALU_RGB_OP_SOP 10
-# define R300_ALU_RGB_OMOD(x) (x << 27)
+# define R300_ALU_RGB_OMOD(x) ((x) << 27)
# define R300_ALU_RGB_OMOD_NONE 0
# define R300_ALU_RGB_OMOD_MUL_2 1
# define R300_ALU_RGB_OMOD_MUL_4 2
@@ -4642,16 +4642,16 @@
#define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
-# define R300_ALU_ALPHA_ADDR0(x) (x << 0)
-# define R300_ALU_ALPHA_ADDR1(x) (x << 6)
-# define R300_ALU_ALPHA_ADDR2(x) (x << 12)
+# define R300_ALU_ALPHA_ADDR0(x) ((x) << 0)
+# define R300_ALU_ALPHA_ADDR1(x) ((x) << 6)
+# define R300_ALU_ALPHA_ADDR2(x) ((x) << 12)
# define R300_ALU_ALPHA_CONST(x) ((x) | (1 << 5))
/* ADDRD - where on the pixel stack the result of this instruction
will be written */
-# define R300_ALU_ALPHA_ADDRD(x) (x << 18)
-# define R300_ALU_ALPHA_WMASK(x) (x << 23)
-# define R300_ALU_ALPHA_OMASK(x) (x << 24)
-# define R300_ALU_ALPHA_OMASK_W(x) (x << 27)
+# define R300_ALU_ALPHA_ADDRD(x) ((x) << 18)
+# define R300_ALU_ALPHA_WMASK(x) ((x) << 23)
+# define R300_ALU_ALPHA_OMASK(x) ((x) << 24)
+# define R300_ALU_ALPHA_OMASK_W(x) ((x) << 27)
# define R300_ALU_ALPHA_MASK_NONE 0
# define R300_ALU_ALPHA_MASK_A 1
# define R300_ALU_ALPHA_TARGET_A (0 << 25)
@@ -4662,7 +4662,7 @@
#define R300_US_ALU_ALPHA_INST_1 0x49c4
#define R300_US_ALU_ALPHA_INST_2 0x49c8
#define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4)
-# define R300_ALU_ALPHA_SEL_A(x) (x << 0)
+# define R300_ALU_ALPHA_SEL_A(x) ((x) << 0)
# define R300_ALU_ALPHA_SRC0_R 0
# define R300_ALU_ALPHA_SRC0_G 1
# define R300_ALU_ALPHA_SRC0_B 2
@@ -4682,21 +4682,21 @@
# define R300_ALU_ALPHA_0_0 16
# define R300_ALU_ALPHA_1_0 17
# define R300_ALU_ALPHA_0_5 18
-# define R300_ALU_ALPHA_MOD_A(x) (x << 5)
+# define R300_ALU_ALPHA_MOD_A(x) ((x) << 5)
# define R300_ALU_ALPHA_MOD_NOP 0
# define R300_ALU_ALPHA_MOD_NEG 1
# define R300_ALU_ALPHA_MOD_ABS 2
# define R300_ALU_ALPHA_MOD_NAB 3
-# define R300_ALU_ALPHA_SEL_B(x) (x << 7)
-# define R300_ALU_ALPHA_MOD_B(x) (x << 12)
-# define R300_ALU_ALPHA_SEL_C(x) (x << 14)
-# define R300_ALU_ALPHA_MOD_C(x) (x << 19)
-# define R300_ALU_ALPHA_SRCP_OP(x) (x << 21)
+# define R300_ALU_ALPHA_SEL_B(x) ((x) << 7)
+# define R300_ALU_ALPHA_MOD_B(x) ((x) << 12)
+# define R300_ALU_ALPHA_SEL_C(x) ((x) << 14)
+# define R300_ALU_ALPHA_MOD_C(x) ((x) << 19)
+# define R300_ALU_ALPHA_SRCP_OP(x) ((x) << 21)
# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_2RGB0 0
# define R300_ALU_ALPHA_SRCP_OP_RGB1_MINUS_RGB0 1
# define R300_ALU_ALPHA_SRCP_OP_RGB1_PLUS_RGB0 2
# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_RGB0 3
-# define R300_ALU_ALPHA_OP(x) (x << 23)
+# define R300_ALU_ALPHA_OP(x) ((x) << 23)
# define R300_ALU_ALPHA_OP_MAD 0
# define R300_ALU_ALPHA_OP_DP 1
# define R300_ALU_ALPHA_OP_MIN 2
@@ -4708,7 +4708,7 @@
# define R300_ALU_ALPHA_OP_LN2 9
# define R300_ALU_ALPHA_OP_RCP 10
# define R300_ALU_ALPHA_OP_RSQ 11
-# define R300_ALU_ALPHA_OMOD(x) (x << 27)
+# define R300_ALU_ALPHA_OMOD(x) ((x) << 27)
# define R300_ALU_ALPHA_OMOD_NONE 0
# define R300_ALU_ALPHA_OMOD_MUL_2 1
# define R300_ALU_ALPHA_OMOD_MUL_4 2
@@ -4837,7 +4837,7 @@
# define R500_ALPHA_OP_COS 13
# define R500_ALPHA_OP_MDH 14
# define R500_ALPHA_OP_MDV 15
-# define R500_ALPHA_ADDRD(x) (x << 4)
+# define R500_ALPHA_ADDRD(x) ((x) << 4)
# define R500_ALPHA_ADDRD_REL (1 << 11)
# define R500_ALPHA_SEL_A_SRC0 (0 << 12)
# define R500_ALPHA_SEL_A_SRC1 (1 << 12)
@@ -4879,16 +4879,16 @@
# define R500_ALPHA_OMOD_DIV_4 (5 << 26)
# define R500_ALPHA_OMOD_DIV_8 (6 << 26)
# define R500_ALPHA_OMOD_DISABLE (7 << 26)
-# define R500_ALPHA_TARGET(x) (x << 29)
+# define R500_ALPHA_TARGET(x) ((x) << 29)
# define R500_ALPHA_W_OMASK (1 << 31)
#define R500_US_ALU_ALPHA_ADDR_0 0x9800
-# define R500_ALPHA_ADDR0(x) (x << 0)
+# define R500_ALPHA_ADDR0(x) ((x) << 0)
# define R500_ALPHA_ADDR0_CONST (1 << 8)
# define R500_ALPHA_ADDR0_REL (1 << 9)
-# define R500_ALPHA_ADDR1(x) (x << 10)
+# define R500_ALPHA_ADDR1(x) ((x) << 10)
# define R500_ALPHA_ADDR1_CONST (1 << 18)
# define R500_ALPHA_ADDR1_REL (1 << 19)
-# define R500_ALPHA_ADDR2(x) (x << 20)
+# define R500_ALPHA_ADDR2(x) ((x) << 20)
# define R500_ALPHA_ADDR2_CONST (1 << 28)
# define R500_ALPHA_ADDR2_REL (1 << 29)
# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30)
@@ -4909,7 +4909,7 @@
# define R500_ALU_RGBA_OP_SOP (10 << 0)
# define R500_ALU_RGBA_OP_MDH (11 << 0)
# define R500_ALU_RGBA_OP_MDV (12 << 0)
-# define R500_ALU_RGBA_ADDRD(x) (x << 4)
+# define R500_ALU_RGBA_ADDRD(x) ((x) << 4)
# define R500_ALU_RGBA_ADDRD_REL (1 << 11)
# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12)
# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12)
@@ -5032,16 +5032,16 @@
# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26)
# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26)
# define R500_ALU_RGB_OMOD_DISABLE (7 << 26)
-# define R500_ALU_RGB_TARGET(x) (x << 29)
+# define R500_ALU_RGB_TARGET(x) ((x) << 29)
# define R500_ALU_RGB_WMASK (1 << 31)
#define R500_US_ALU_RGB_ADDR_0 0x9000
-# define R500_RGB_ADDR0(x) (x << 0)
+# define R500_RGB_ADDR0(x) ((x) << 0)
# define R500_RGB_ADDR0_CONST (1 << 8)
# define R500_RGB_ADDR0_REL (1 << 9)
-# define R500_RGB_ADDR1(x) (x << 10)
+# define R500_RGB_ADDR1(x) ((x) << 10)
# define R500_RGB_ADDR1_CONST (1 << 18)
# define R500_RGB_ADDR1_REL (1 << 19)
-# define R500_RGB_ADDR2(x) (x << 20)
+# define R500_RGB_ADDR2(x) ((x) << 20)
# define R500_RGB_ADDR2_CONST (1 << 28)
# define R500_RGB_ADDR2_REL (1 << 29)
# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30)
@@ -5094,19 +5094,19 @@
# define R500_INST_STAT_WE_A (1 << 31)
/* note that these are 8 bit lengths, despite the offsets, at least for R500 */
#define R500_US_CODE_ADDR 0x4630
-# define R500_US_CODE_START_ADDR(x) (x << 0)
-# define R500_US_CODE_END_ADDR(x) (x << 16)
+# define R500_US_CODE_START_ADDR(x) ((x) << 0)
+# define R500_US_CODE_END_ADDR(x) ((x) << 16)
#define R500_US_CODE_OFFSET 0x4638
-# define R500_US_CODE_OFFSET_ADDR(x) (x << 0)
+# define R500_US_CODE_OFFSET_ADDR(x) ((x) << 0)
#define R500_US_CODE_RANGE 0x4634
-# define R500_US_CODE_RANGE_ADDR(x) (x << 0)
-# define R500_US_CODE_RANGE_SIZE(x) (x << 16)
+# define R500_US_CODE_RANGE_ADDR(x) ((x) << 0)
+# define R500_US_CODE_RANGE_SIZE(x) ((x) << 16)
#define R500_US_CONFIG 0x4600
# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
#define R500_US_FC_ADDR_0 0xa000
-# define R500_FC_BOOL_ADDR(x) (x << 0)
-# define R500_FC_INT_ADDR(x) (x << 8)
-# define R500_FC_JUMP_ADDR(x) (x << 16)
+# define R500_FC_BOOL_ADDR(x) ((x) << 0)
+# define R500_FC_INT_ADDR(x) ((x) << 8)
+# define R500_FC_JUMP_ADDR(x) ((x) << 16)
# define R500_FC_JUMP_GLOBAL (1 << 31)
#define R500_US_FC_BOOL_CONST 0x4620
# define R500_FC_KBOOL(x) (x)
@@ -5127,8 +5127,8 @@
# define R500_FC_A_OP_NONE (0 << 6)
# define R500_FC_A_OP_POP (1 << 6)
# define R500_FC_A_OP_PUSH (2 << 6)
-# define R500_FC_JUMP_FUNC(x) (x << 8)
-# define R500_FC_B_POP_CNT(x) (x << 16)
+# define R500_FC_JUMP_FUNC(x) ((x) << 8)
+# define R500_FC_B_POP_CNT(x) ((x) << 16)
# define R500_FC_B_OP0_NONE (0 << 24)
# define R500_FC_B_OP0_DECR (1 << 24)
# define R500_FC_B_OP0_INCR (2 << 24)
@@ -5137,14 +5137,14 @@
# define R500_FC_B_OP1_INCR (2 << 26)
# define R500_FC_IGNORE_UNCOVERED (1 << 28)
#define R500_US_FC_INT_CONST_0 0x4c00
-# define R500_FC_INT_CONST_KR(x) (x << 0)
-# define R500_FC_INT_CONST_KG(x) (x << 8)
-# define R500_FC_INT_CONST_KB(x) (x << 16)
+# define R500_FC_INT_CONST_KR(x) ((x) << 0)
+# define R500_FC_INT_CONST_KG(x) ((x) << 8)
+# define R500_FC_INT_CONST_KB(x) ((x) << 16)
/* _0 through _15 */
#define R500_US_FORMAT0_0 0x4640
-# define R500_FORMAT_TXWIDTH(x) (x << 0)
-# define R500_FORMAT_TXHEIGHT(x) (x << 11)
-# define R500_FORMAT_TXDEPTH(x) (x << 22)
+# define R500_FORMAT_TXWIDTH(x) ((x) << 0)
+# define R500_FORMAT_TXHEIGHT(x) ((x) << 11)
+# define R500_FORMAT_TXDEPTH(x) ((x) << 22)
/* _0 through _3 */
#define R500_US_OUT_FMT_0 0x46a4
# define R500_OUT_FMT_C4_8 (0 << 0)
@@ -5185,12 +5185,12 @@
# define R500_C3_SEL_R (1 << 14)
# define R500_C3_SEL_G (2 << 14)
# define R500_C3_SEL_B (3 << 14)
-# define R500_OUT_SIGN(x) (x << 16)
+# define R500_OUT_SIGN(x) ((x) << 16)
# define R500_ROUND_ADJ (1 << 20)
#define R500_US_PIXSIZE 0x4604
# define R500_PIX_SIZE(x) (x)
#define R500_US_TEX_ADDR_0 0x9800
-# define R500_TEX_SRC_ADDR(x) (x << 0)
+# define R500_TEX_SRC_ADDR(x) ((x) << 0)
# define R500_TEX_SRC_ADDR_REL (1 << 7)
# define R500_TEX_SRC_S_SWIZ_R (0 << 8)
# define R500_TEX_SRC_S_SWIZ_G (1 << 8)
@@ -5208,7 +5208,7 @@
# define R500_TEX_SRC_Q_SWIZ_G (1 << 14)
# define R500_TEX_SRC_Q_SWIZ_B (2 << 14)
# define R500_TEX_SRC_Q_SWIZ_A (3 << 14)
-# define R500_TEX_DST_ADDR(x) (x << 16)
+# define R500_TEX_DST_ADDR(x) ((x) << 16)
# define R500_TEX_DST_ADDR_REL (1 << 23)
# define R500_TEX_DST_R_SWIZ_R (0 << 24)
# define R500_TEX_DST_R_SWIZ_G (1 << 24)
@@ -5227,7 +5227,7 @@
# define R500_TEX_DST_A_SWIZ_B (2 << 30)
# define R500_TEX_DST_A_SWIZ_A (3 << 30)
#define R500_US_TEX_ADDR_DXDY_0 0xa000
-# define R500_DX_ADDR(x) (x << 0)
+# define R500_DX_ADDR(x) ((x) << 0)
# define R500_DX_ADDR_REL (1 << 7)
# define R500_DX_S_SWIZ_R (0 << 8)
# define R500_DX_S_SWIZ_G (1 << 8)
@@ -5245,7 +5245,7 @@
# define R500_DX_Q_SWIZ_G (1 << 14)
# define R500_DX_Q_SWIZ_B (2 << 14)
# define R500_DX_Q_SWIZ_A (3 << 14)
-# define R500_DY_ADDR(x) (x << 16)
+# define R500_DY_ADDR(x) ((x) << 16)
# define R500_DY_ADDR_REL (1 << 17)
# define R500_DY_S_SWIZ_R (0 << 24)
# define R500_DY_S_SWIZ_G (1 << 24)
@@ -5264,7 +5264,7 @@
# define R500_DY_Q_SWIZ_B (2 << 30)
# define R500_DY_Q_SWIZ_A (3 << 30)
#define R500_US_TEX_INST_0 0x9000
-# define R500_TEX_ID(x) (x << 16)
+# define R500_TEX_ID(x) ((x) << 16)
# define R500_TEX_INST_NOP (0 << 22)
# define R500_TEX_INST_LD (1 << 22)
# define R500_TEX_INST_TEXKILL (2 << 22)
commit e04bcb0066781f61e97787856261e3380036d304
Author: Pierre Ossman <pierre at ossman.eu>
Date: Wed Dec 3 19:16:03 2008 +0100
Fix node setup on R300 bicubic pixel shader. It was backwards and used
the wrong base for sizes.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 61cca6a..4d34f8f 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -366,20 +366,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_TEX_CODE_OFFSET(0) |
R300_TEX_CODE_SIZE(6)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
- R300_ALU_SIZE(1) |
+ /* Nodes are allocated highest first, but executed lowest first */
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0);
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_1, (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
R300_TEX_START(0) |
- R300_TEX_SIZE(1)));
+ R300_TEX_SIZE(0)));
OUT_ACCEL_REG(R300_US_CODE_ADDR_2, (R300_ALU_START(1) |
- R300_ALU_SIZE(10) |
+ R300_ALU_SIZE(9) |
R300_TEX_START(1) |
- R300_TEX_SIZE(1)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_1, (R300_ALU_START(11) |
- R300_ALU_SIZE(3) |
+ R300_TEX_SIZE(0)));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(11) |
+ R300_ALU_SIZE(2) |
R300_TEX_START(2) |
- R300_TEX_SIZE(4) |
+ R300_TEX_SIZE(3) |
R300_RGBA_OUT));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0);
/* ** BICUBIC FP ** */
commit fa496d7b0397d9be57db90d0860928e9ced73cca
Author: Pierre Ossman <pierre at ossman.eu>
Date: Mon Dec 1 08:29:29 2008 +0100
Fix comments for R500 fragment shader to reflect the code.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 855bf16..61cca6a 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -922,7 +922,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_R |
R500_ALU_RGBA_A_SWIZ_G));
- /* TEX temp1, temp3.zwxy, tex0, 1D */
+ /* TEX temp1, temp3.zwxy, tex0, 2D */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -945,7 +945,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp3, temp3.xyzw, tex0, 1D */
+ /* TEX temp3, temp3.xyzw, tex0, 2D */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -970,7 +970,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* MAD temp4, const1.0y0y, temp5.yyyy, temp4 */
+ /* MAD temp4, const0.0y0y, temp5.yyyy, temp4 */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -1036,7 +1036,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_R |
R500_ALU_RGBA_A_SWIZ_G));
- /* TEX temp4, temp0.zwzw, tex0, 1D */
+ /* TEX temp4, temp0.zwzw, tex0, 2D */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -1060,7 +1060,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp0, temp0.xyzw, tex0, 1D */
+ /* TEX temp0, temp0.xyzw, tex0, 2D */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -1209,7 +1209,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* Shader constants. */
OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0));
- /* const0 = {1 / texture[0].width, 0, 0, 0} */
+ /* const0 = {1 / texture[0].width, 1 / texture[0].height, 0, 0} */
OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w));
OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->h));
OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
commit 0d95fca114194664d9ab612c90d3222912cf41ff
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Sat Aug 30 12:38:43 2008 -0700
Fix indentation on IS_R300_3D Xv code.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 3292cca..855bf16 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -343,13 +343,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* setup pixel shader */
if (IS_R300_3D) {
- if (pPriv->bicubic_enabled) {
+ if (pPriv->bicubic_enabled) {
BEGIN_ACCEL(79);
/* 4 components: 2 for tex0 and 2 for tex1 */
- OUT_ACCEL_REG(R300_RS_COUNT,
- ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
+ OUT_ACCEL_REG(R300_RS_COUNT, ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
@@ -682,73 +681,67 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0);
FINISH_ACCEL();
- } else {
+ } else {
BEGIN_ACCEL(8);
- /* 2 components: 2 for tex0 */
- OUT_ACCEL_REG(R300_RS_COUNT,
+ /* 2 components: 2 for tex0 */
+ OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
- /* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
-
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
-
- OUT_ACCEL_REG(R300_US_CODE_OFFSET,
- (R300_ALU_CODE_OFFSET(0) |
- R300_ALU_CODE_SIZE(1) |
- R300_TEX_CODE_OFFSET(0) |
- R300_TEX_CODE_SIZE(1)));
-
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0) |
- R300_RGBA_OUT));
-
- /* tex inst is preloaded in RADEONInit3DEngine() */
-
- /* ALU inst */
- /* RGB */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
- (R300_ALU_RGB_ADDR0(0) |
- R300_ALU_RGB_ADDR1(0) |
- R300_ALU_RGB_ADDR2(0) |
- R300_ALU_RGB_ADDRD(0) |
- R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
- R300_ALU_RGB_MASK_G |
- R300_ALU_RGB_MASK_B)) |
- R300_ALU_RGB_TARGET_A));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
- (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
- R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
- R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
- R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
- R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
- R300_ALU_RGB_CLAMP));
- /* Alpha */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
- (R300_ALU_ALPHA_ADDR0(0) |
- R300_ALU_ALPHA_ADDR1(0) |
- R300_ALU_ALPHA_ADDR2(0) |
- R300_ALU_ALPHA_ADDRD(0) |
- R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
- R300_ALU_ALPHA_TARGET_A |
- R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
- (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) |
- R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) |
- R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
- R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
- R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
- R300_ALU_ALPHA_CLAMP));
- FINISH_ACCEL();
+ /* R300_INST_COUNT_RS - highest RS instruction used */
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
+
+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ R300_ALU_CODE_SIZE(1) |
+ R300_TEX_CODE_OFFSET(0) |
+ R300_TEX_CODE_SIZE(1)));
+
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0) |
+ R300_RGBA_OUT));
+
+ /* tex inst is preloaded in RADEONInit3DEngine() */
+
+ /* ALU inst */
+ /* RGB */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, (R300_ALU_RGB_ADDR0(0) |
+ R300_ALU_RGB_ADDR1(0) |
+ R300_ALU_RGB_ADDR2(0) |
+ R300_ALU_RGB_ADDRD(0) |
+ R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
+ R300_ALU_RGB_MASK_G |
+ R300_ALU_RGB_MASK_B)) |
+ R300_ALU_RGB_TARGET_A));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
+ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
+ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
+ R300_ALU_RGB_CLAMP));
+ /* Alpha */
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, (R300_ALU_ALPHA_ADDR0(0) |
+ R300_ALU_ALPHA_ADDR1(0) |
+ R300_ALU_ALPHA_ADDR2(0) |
+ R300_ALU_ALPHA_ADDRD(0) |
+ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
+ R300_ALU_ALPHA_TARGET_A |
+ R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) |
+ R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) |
+ R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
+ R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
+ R300_ALU_ALPHA_CLAMP));
+ FINISH_ACCEL();
}
} else {
if (pPriv->bicubic_enabled) {
commit 36a62b8c47def3f23a0b735875f59d23ed3c095a
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Sat Aug 30 11:15:20 2008 -0700
r3xx: Various Xv fixes.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index c7d0620..318df49 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -230,7 +230,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
}
/* Bicubic filter loading */
- if (!IS_R500_3D && !IS_R300_3D)
+ if (!(IS_R300_3D || IS_R500_3D))
pPriv->bicubic_enabled = FALSE;
if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) {
pPriv->bicubic_offset = radeon_legacy_allocate_memory(pScrn,
@@ -457,13 +457,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
pPortPriv =
(RADEONPortPrivPtr)(&adapt->pPortPrivates[num_texture_ports]);
- if (IS_R500_3D) {
- adapt->nAttributes = NUM_ATTRIBUTES;
- adapt->pAttributes = Attributes;
- } else {
- adapt->nAttributes = 0;
- adapt->pAttributes = NULL;
- }
+ adapt->pAttributes = Attributes;
+ adapt->nAttributes = NUM_ATTRIBUTES;
adapt->pImages = Images;
adapt->nImages = NUM_IMAGES;
adapt->PutVideo = NULL;
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 8c90f41..3292cca 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -681,9 +681,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(R300_US_ALU_CONST_B(1), 0);
OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0);
- FINISH_VIDEO();
+ FINISH_ACCEL();
} else {
- BEGIN_VIDEO(8);
+ BEGIN_ACCEL(8);
/* 2 components: 2 for tex0 */
OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
commit 01ed5462fad56f5b7bf867041d00443bdf81c653
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Thu Aug 7 18:08:54 2008 -0700
Switch to Mesa-style 24-bit float packing.
Seems like Mesa's got it right, so we should follow suit.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 8fc380e..c7d0620 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -80,6 +80,32 @@ static __inline__ uint32_t F_TO_DW(float val)
return tmp.l;
}
+/* Borrowed from Mesa */
+static __inline__ uint32_t F_TO_24(float val)
+{
+ float mantissa;
+ int exponent;
+ uint32_t float24 = 0;
+
+ if (val == 0.0)
+ return 0;
+
+ mantissa = frexpf(val, &exponent);
+
+ /* Handle -ve */
+ if (mantissa < 0) {
+ float24 |= (1 << 23);
+ mantissa = mantissa * -1.0;
+ }
+ /* Handle exponent, bias of 63 */
+ exponent += 62;
+ float24 |= (exponent << 16);
+ /* Kill 7 LSB of mantissa */
+ float24 |= (F_TO_DW(mantissa) & 0x7FFFFF) >> 7;
+
+ return float24;
+}
+
#define ACCEL_MMIO
#define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO
#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n))
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 8fb8798..8c90f41 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -90,45 +90,6 @@ do { \
#endif /* !ACCEL_CP */
-#ifndef __FLOAT_TO_S16E7__
-#define __FLOAT_TO_S16E7__
-
-static int float_to_s16e7(float in)
-{
- union {
- float f;
- int i;
- } x;
-
- int s, e, f, out; // sign, exponent, fraction
-
- x.f = in;
- s = (x.i & (1 << 31)) >> 31;
- e = (x.i & 0x7f800000) >> 23;
- f = (x.i & 0x007fffff);
-
- /* unbias the exponent */
- e = e - 127;
- if (e < -63)
- e = -63;
- else if (e > 63)
- e = 63;
-
- e += 63;
-
- /* prepend implicit 1 to fraction */
- f |= (1 << 23);
- /* cut mantissa to 16 bits */
- f = (f & 0xffff80) >> 8;
-
- out = s;
- out = (out << 7) | e;
- out = (out << 16) | f;
-
- return out;
-}
-#endif
-
static void
FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
@@ -710,13 +671,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A)));
/* Shader constants. */
- OUT_ACCEL_REG(R300_US_ALU_CONST_R(0), float_to_s16e7(1.0/(float)pPriv->w));
+ OUT_ACCEL_REG(R300_US_ALU_CONST_R(0), F_TO_24(1.0/(float)pPriv->w));
OUT_ACCEL_REG(R300_US_ALU_CONST_G(0), 0);
OUT_ACCEL_REG(R300_US_ALU_CONST_B(0), 0);
OUT_ACCEL_REG(R300_US_ALU_CONST_A(0), 0);
OUT_ACCEL_REG(R300_US_ALU_CONST_R(1), 0);
- OUT_ACCEL_REG(R300_US_ALU_CONST_G(1), float_to_s16e7(1.0/(float)pPriv->h));
+ OUT_ACCEL_REG(R300_US_ALU_CONST_G(1), F_TO_24(1.0/(float)pPriv->h));
OUT_ACCEL_REG(R300_US_ALU_CONST_B(1), 0);
OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0);
commit 85bbe889045aa434f71a3eb0ba8153b7d2cc5023
Author: Maciej Cencora <m.cencora at gmail.com>
Date: Thu Aug 7 07:06:46 2008 -0700
Enable bicubic Xv on r3xx+. Still some buggies in the actual display, but looks pretty good.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 35b332b..8fc380e 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -204,7 +204,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
}
/* Bicubic filter loading */
- if (!IS_R500_3D)
+ if (!IS_R500_3D && !IS_R300_3D)
pPriv->bicubic_enabled = FALSE;
if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) {
pPriv->bicubic_offset = radeon_legacy_allocate_memory(pScrn,
@@ -459,7 +459,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
pPriv->videoStatus = 0;
pPriv->currentBuffer = 0;
pPriv->doubleBuffer = 0;
- pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_RV515);
+ pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_R300);
/* gotta uninit this someplace, XXX: shouldn't be necessary for textured */
REGION_NULL(pScreen, &pPriv->clip);
commit bf6263cff50bb85c19ff6dfebb739333fa8aca18
Author: Maciej Cencora <m.cencora at gmail.com>
Date: Thu Aug 7 07:00:36 2008 -0700
Add r3xx-specific bicubic filtering code. FP, RS, mostly, everything else is shared with r5xx.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index c5ad0e1..8fb8798 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -90,6 +90,45 @@ do { \
#endif /* !ACCEL_CP */
+#ifndef __FLOAT_TO_S16E7__
+#define __FLOAT_TO_S16E7__
+
+static int float_to_s16e7(float in)
+{
+ union {
+ float f;
+ int i;
+ } x;
+
+ int s, e, f, out; // sign, exponent, fraction
+
+ x.f = in;
+ s = (x.i & (1 << 31)) >> 31;
+ e = (x.i & 0x7f800000) >> 23;
+ f = (x.i & 0x007fffff);
+
+ /* unbias the exponent */
+ e = e - 127;
+ if (e < -63)
+ e = -63;
+ else if (e > 63)
+ e = 63;
+
+ e += 63;
+
+ /* prepend implicit 1 to fraction */
+ f |= (1 << 23);
+ /* cut mantissa to 16 bits */
+ f = (f & 0xffff80) >> 8;
+
+ out = s;
+ out = (out << 7) | e;
+ out = (out << 16) | f;
+
+ return out;
+}
+#endif
+
static void
FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
@@ -343,7 +382,347 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* setup pixel shader */
if (IS_R300_3D) {
- BEGIN_ACCEL(9);
+ if (pPriv->bicubic_enabled) {
+ BEGIN_ACCEL(79);
+
+ /* 4 components: 2 for tex0 and 2 for tex1 */
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+
+ /* R300_INST_COUNT_RS - highest RS instruction used */
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+
+ /* Pixel stack frame size. */
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 5);
+
+ /* Indirection levels */
+ OUT_ACCEL_REG(R300_US_CONFIG, ((2 << R300_NLEVEL_SHIFT) |
+ R300_FIRST_TEX));
+
+ /* Set nodes. */
+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ R300_ALU_CODE_SIZE(14) |
+ R300_TEX_CODE_OFFSET(0) |
+ R300_TEX_CODE_SIZE(6)));
+
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
+ R300_ALU_SIZE(1) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(1)));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_2, (R300_ALU_START(1) |
+ R300_ALU_SIZE(10) |
+ R300_TEX_START(1) |
+ R300_TEX_SIZE(1)));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_1, (R300_ALU_START(11) |
+ R300_ALU_SIZE(3) |
+ R300_TEX_START(2) |
+ R300_TEX_SIZE(4) |
+ R300_RGBA_OUT));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0);
+
+ /* ** BICUBIC FP ** */
+
+ /* texcoord0 => temp0
+ * texcoord1 => temp1 */
+
+ // first node
+ /* TEX temp2, temp1.rrr0, tex1, 1D */
+ OUT_ACCEL_REG(R300_US_TEX_INST(0), (R300_TEX_INST(R300_TEX_INST_LD) |
+ R300_TEX_ID(1) |
+ R300_TEX_SRC_ADDR(1) |
+ R300_TEX_DST_ADDR(2)));
+
+ /* MAD temp1.r, temp1.ggg0, 1.0, 0.0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(1) |
+ R300_ALU_RGB_ADDRD(1) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDRD(1) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+
+ // second node
+ /* TEX temp1, temp1, tex1, 1D */
+ OUT_ACCEL_REG(R300_US_TEX_INST(1), (R300_TEX_INST(R300_TEX_INST_LD) |
+ R300_TEX_ID(1) |
+ R300_TEX_SRC_ADDR(1) |
+ R300_TEX_DST_ADDR(1)));
+
+ /* MAD temp3.rg, temp2.ggg0, const0.rgb0, 0.0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(2) |
+ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) |
+ R300_ALU_RGB_ADDRD(3) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(3) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+
+ /* MAD temp2.rg, temp2.rrr0, const0.rgb, 0.0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(2) |
+ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) |
+ R300_ALU_RGB_ADDRD(2) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(2) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+ /* MAD temp4.rg, temp1.ggg0, const1.rgb, temp3.rgb0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(3), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(1) |
+ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
+ R300_ALU_RGB_ADDR2(3) |
+ R300_ALU_RGB_ADDRD(4) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(4) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+ /* MAD temp5.rg, temp1.ggg0, const1.rgb, temp2.rgb0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(4), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(1) |
+ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
+ R300_ALU_RGB_ADDR2(2) |
+ R300_ALU_RGB_ADDRD(5) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(5) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+ /* MAD temp3.rg, temp1.rrr0, const1.rgb, temp3.rgb0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(5), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(1) |
+ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
+ R300_ALU_RGB_ADDR2(3) |
+ R300_ALU_RGB_ADDRD(3) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(3) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+ /* MAD temp1.rg, temp1.rrr0, const1.rgb, temp2.rgb0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(1) |
+ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
+ R300_ALU_RGB_ADDR2(2) |
+ R300_ALU_RGB_ADDRD(1) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(1) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+ /* MAD temp1.rg, temp0.rgb0, 1.0, temp1.rgb0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(7), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) |
+ R300_ALU_RGB_ADDR2(1) |
+ R300_ALU_RGB_ADDRD(1) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(1) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+ /* MAD temp2.rg, temp0.rgb0, 1.0, temp3.rgb0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(8), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) |
+ R300_ALU_RGB_ADDR2(3) |
+ R300_ALU_RGB_ADDRD(2) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(2) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+ /* MAD temp3.rg, temp0.rgb0, 1.0, temp5.rgb0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(9), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) |
+ R300_ALU_RGB_ADDR2(5) |
+ R300_ALU_RGB_ADDRD(3) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(3) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+ /* MAD temp0.rg, temp0.rgb0, 1.0, temp4.rgb0 */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(10), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(10), (R300_ALU_RGB_ADDR0(0) |
+ R300_ALU_RGB_ADDR2(4) |
+ R300_ALU_RGB_ADDRD(0) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(10), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(10), (R300_ALU_ALPHA_ADDRD(0) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+
+ // third node
+ /* TEX temp4, temp1.rg--, tex0, 1D */
+ OUT_ACCEL_REG(R300_US_TEX_INST(2), (R300_TEX_INST(R300_TEX_INST_LD) |
+ R300_TEX_ID(0) |
+ R300_TEX_SRC_ADDR(1) |
+ R300_TEX_DST_ADDR(4)));
+
+ /* TEX temp3, temp3.rg--, tex0, 1D */
+ OUT_ACCEL_REG(R300_US_TEX_INST(3), (R300_TEX_INST(R300_TEX_INST_LD) |
+ R300_TEX_ID(0) |
+ R300_TEX_SRC_ADDR(3) |
+ R300_TEX_DST_ADDR(3)));
+
+ /* TEX temp5, temp2.rg--, tex0, 1D */
+ OUT_ACCEL_REG(R300_US_TEX_INST(4), (R300_TEX_INST(R300_TEX_INST_LD) |
+ R300_TEX_ID(0) |
+ R300_TEX_SRC_ADDR(2) |
+ R300_TEX_DST_ADDR(5)));
+
+ /* TEX temp0, temp0.rg--, tex0, 1D */
+ OUT_ACCEL_REG(R300_US_TEX_INST(5), (R300_TEX_INST(R300_TEX_INST_LD) |
+ R300_TEX_ID(0) |
+ R300_TEX_SRC_ADDR(0) |
+ R300_TEX_DST_ADDR(0)));
+
+ /* MAD temp3.rgba, temp1.bbbb, srcp(temp4.rgba - temp3.rgba), temp3.rgba */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(11), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) |
+ R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(11), (R300_ALU_RGB_ADDR0(3) |
+ R300_ALU_RGB_ADDR1(4) |
+ R300_ALU_RGB_ADDR2(1) |
+ R300_ALU_RGB_ADDRD(3) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(11), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(11), (R300_ALU_ALPHA_ADDR0(3) |
+ R300_ALU_ALPHA_ADDR1(4) |
+ R300_ALU_ALPHA_ADDR2(1) |
+ R300_ALU_ALPHA_ADDRD(3) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A)));
+
+ /* MAD temp0.rgba, temp1.bbbb, srcp(temp5.rgba - temp0.rgba), temp0.rgba NOP*/
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(12), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) |
+ R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0) |
+ R300_ALU_RGB_INSERT_NOP));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(12), (R300_ALU_RGB_ADDR0(0) |
+ R300_ALU_RGB_ADDR1(5) |
+ R300_ALU_RGB_ADDR2(1) |
+ R300_ALU_RGB_ADDRD(0) |
+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(12), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(12), (R300_ALU_ALPHA_ADDR0(0) |
+ R300_ALU_ALPHA_ADDR1(5) |
+ R300_ALU_ALPHA_ADDR2(1) |
+ R300_ALU_ALPHA_ADDRD(0) |
+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A)));
+
+ /* MAD output, temp2.bbbb, srcp(temp3.rgba - temp0.rgba), temp0.rgba */
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(13), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) |
+ R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0)));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(13), (R300_ALU_RGB_ADDR0(0) |
+ R300_ALU_RGB_ADDR1(3) |
+ R300_ALU_RGB_ADDR2(2) |
+ R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(13), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) |
+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(13), (R300_ALU_ALPHA_ADDR0(0) |
+ R300_ALU_ALPHA_ADDR1(3) |
+ R300_ALU_ALPHA_ADDR2(2) |
+ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A)));
+
+ /* Shader constants. */
+ OUT_ACCEL_REG(R300_US_ALU_CONST_R(0), float_to_s16e7(1.0/(float)pPriv->w));
+ OUT_ACCEL_REG(R300_US_ALU_CONST_G(0), 0);
+ OUT_ACCEL_REG(R300_US_ALU_CONST_B(0), 0);
+ OUT_ACCEL_REG(R300_US_ALU_CONST_A(0), 0);
+
+ OUT_ACCEL_REG(R300_US_ALU_CONST_R(1), 0);
+ OUT_ACCEL_REG(R300_US_ALU_CONST_G(1), float_to_s16e7(1.0/(float)pPriv->h));
+ OUT_ACCEL_REG(R300_US_ALU_CONST_B(1), 0);
+ OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0);
+
+ FINISH_VIDEO();
+ } else {
+ BEGIN_VIDEO(8);
/* 2 components: 2 for tex0 */
OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -409,6 +788,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
R300_ALU_ALPHA_CLAMP));
FINISH_ACCEL();
+ }
} else {
if (pPriv->bicubic_enabled) {
BEGIN_ACCEL(7);
More information about the xorg-commit
mailing list