xf86-video-ati: Branch 'master' - 43 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Aug 25 11:31:12 PDT 2008
src/Makefile.am | 3
src/atombios_crtc.c | 3
src/bicubic_table.h | 646 +++++++++++++++++++++
src/bicubic_table.py | 72 ++
src/legacy_crtc.c | 19
src/radeon.h | 498 +++++++++-------
src/radeon_accel.c | 248 ++++----
src/radeon_accelfuncs.c | 348 +++++------
src/radeon_common.h | 496 ----------------
src/radeon_commonfuncs.c | 33 -
src/radeon_crtc.c | 110 ---
src/radeon_cursor.c | 47 -
src/radeon_dga.c | 49 -
src/radeon_dri.c | 711 ++++++++++++------------
src/radeon_dripriv.h | 63 --
src/radeon_driver.c | 352 ++++++-----
src/radeon_drm.h | 755 +++++++++++++++++++++++++
src/radeon_exa.c | 144 ++--
src/radeon_exa_funcs.c | 104 +--
src/radeon_exa_render.c | 186 +++---
src/radeon_memory.c | 118 ++++
src/radeon_probe.h | 8
src/radeon_reg.h | 28
src/radeon_render.c | 65 +-
src/radeon_sarea.h | 231 -------
src/radeon_textured_video.c | 124 +++-
src/radeon_textured_videofuncs.c | 1150 +++++++++++++++++++++++++++++----------
src/radeon_video.c | 180 ------
src/radeon_video.h | 25
29 files changed, 4070 insertions(+), 2746 deletions(-)
New commits:
commit 6cebfe257f7ddad855ee743e4eb899bd6fac7f46
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Jul 11 19:32:06 2008 -0400
Switch EXA path back to static cursor allocation
pre-AVIVO cards have address limits for the cursor offset
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 11fd498..22a33d6 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -335,21 +335,23 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes;
int align = IS_AVIVO_VARIANT ? 4096 : 256;
- for (c = 0; c < xf86_config->num_crtc; c++) {
- xf86CrtcPtr crtc = xf86_config->crtc[c];
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- radeon_crtc->cursor_offset =
- radeon_allocate_memory(pScrn, &radeon_crtc->cursor_mem, size_bytes, align);
-
- if (radeon_crtc->cursor_offset == 0)
- return FALSE;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for hardware cursor %d at offset 0x%08x\n",
- (size_bytes * xf86_config->num_crtc) / 1024,
- c,
- (unsigned int)radeon_crtc->cursor_offset);
+ if (!info->useEXA) {
+ for (c = 0; c < xf86_config->num_crtc; c++) {
+ xf86CrtcPtr crtc = xf86_config->crtc[c];
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+ radeon_crtc->cursor_offset =
+ radeon_allocate_memory(pScrn, &radeon_crtc->cursor_mem, size_bytes, align);
+
+ if (radeon_crtc->cursor_offset == 0)
+ return FALSE;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Will use %d kb for hardware cursor %d at offset 0x%08x\n",
+ (size_bytes * xf86_config->num_crtc) / 1024,
+ c,
+ (unsigned int)radeon_crtc->cursor_offset);
+ }
}
return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index a1b93b5..3945300 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -386,6 +386,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int cpp = info->CurrentLayout.pixel_bytes;
int screen_size;
int byteStride = pScrn->displayWidth * cpp;
@@ -413,6 +414,27 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Allocating from a screen of %ld kb\n",
info->accel_state->exa->memorySize / 1024);
+ /* Reserve static area for hardware cursor */
+ if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
+ int cursor_size = 64 * 4 * 64;
+ int align = IS_AVIVO_VARIANT ? 4096 : 256;
+ int c;
+
+ for (c = 0; c < xf86_config->num_crtc; c++) {
+ xf86CrtcPtr crtc = xf86_config->crtc[c];
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+ radeon_crtc->cursor_offset =
+ RADEON_ALIGN(info->accel_state->exa->offScreenBase, align);
+ info->accel_state->exa->offScreenBase = radeon_crtc->cursor_offset + cursor_size;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Will use %d kb for hardware cursor %d at offset 0x%08x\n",
+ (cursor_size * xf86_config->num_crtc) / 1024,
+ c,
+ (unsigned int)radeon_crtc->cursor_offset);
+ }
+ }
#if defined(XF86DRI)
if (info->directRenderingEnabled) {
commit 4dff54a3c8d7c9f2d6ec50354ff0b92f1b7fcbdf
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Jul 11 17:28:03 2008 -0400
Switch cursors over to generic allocator
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 13c2b9c..11fd498 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -327,49 +327,30 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
int width_bytes;
int height;
int size_bytes;
- uint32_t cursor_offset = 0;
int c;
size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
width = pScrn->displayWidth;
width_bytes = width * (pScrn->bitsPerPixel / 8);
height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes;
+ int align = IS_AVIVO_VARIANT ? 4096 : 256;
-#ifdef USE_XAA
- if (!info->useEXA) {
- int align = IS_AVIVO_VARIANT ? 4096 : 256;
- FBAreaPtr fbarea;
+ for (c = 0; c < xf86_config->num_crtc; c++) {
+ xf86CrtcPtr crtc = xf86_config->crtc[c];
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- fbarea = xf86AllocateOffscreenArea(pScreen, width, height,
- align, NULL, NULL, NULL);
+ radeon_crtc->cursor_offset =
+ radeon_allocate_memory(pScrn, &radeon_crtc->cursor_mem, size_bytes, align);
- if (!fbarea) {
- cursor_offset = 0;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Hardware cursor disabled"
- " due to insufficient offscreen memory\n");
+ if (radeon_crtc->cursor_offset == 0)
return FALSE;
- } else {
- cursor_offset = RADEON_ALIGN((fbarea->box.x1 +
- fbarea->box.y1 * width) *
- info->CurrentLayout.pixel_bytes,
- align);
- for (c = 0; c < xf86_config->num_crtc; c++) {
- xf86CrtcPtr crtc = xf86_config->crtc[c];
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- radeon_crtc->cursor_offset = cursor_offset + (c * size_bytes);
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using hardware cursor %d (scanline %u)\n", c,
- (unsigned)(radeon_crtc->cursor_offset / pScrn->displayWidth
- / info->CurrentLayout.pixel_bytes));
- }
-
- }
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Will use %d kb for hardware cursor %d at offset 0x%08x\n",
+ (size_bytes * xf86_config->num_crtc) / 1024,
+ c,
+ (unsigned int)radeon_crtc->cursor_offset);
}
-#endif
return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
(HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 8beaed7..a1b93b5 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -386,7 +386,6 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int cpp = info->CurrentLayout.pixel_bytes;
int screen_size;
int byteStride = pScrn->displayWidth * cpp;
@@ -415,30 +414,6 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
info->accel_state->exa->memorySize / 1024);
- /* Reserve static area for hardware cursor */
- if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
- int cursor_size = 64 * 4 * 64;
- int align = IS_AVIVO_VARIANT ? 4096 : 256;
- int c;
-
- for (c = 0; c < xf86_config->num_crtc; c++) {
- xf86CrtcPtr crtc = xf86_config->crtc[c];
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- radeon_crtc->cursor_offset =
- RADEON_ALIGN(info->accel_state->exa->offScreenBase, align);
- info->accel_state->exa->offScreenBase = radeon_crtc->cursor_offset + cursor_size;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for hardware cursor %d at offset 0x%08x\n",
- (cursor_size * xf86_config->num_crtc) / 1024,
- c,
- (unsigned int)radeon_crtc->cursor_offset);
- }
-
-
- }
-
#if defined(XF86DRI)
if (info->directRenderingEnabled) {
int depthCpp = (info->dri->depthBits - 8) / 4, l, next, depth_size;
diff --git a/src/radeon_memory.c b/src/radeon_memory.c
index d9e6403..178eed0 100644
--- a/src/radeon_memory.c
+++ b/src/radeon_memory.c
@@ -6,7 +6,6 @@
/* Driver data structures */
#include "radeon.h"
-
/* Allocates memory, either by resizing the allocation pointed to by mem_struct,
* or by freeing mem_struct (if non-NULL) and allocating a new space. The size
* is measured in bytes, and the offset from the beginning of card space is
@@ -20,9 +19,10 @@ radeon_allocate_memory(ScrnInfoPtr pScrn,
{
ScreenPtr pScreen;
RADEONInfoPtr info = RADEONPTR(pScrn);
- int offset = 0;
+ uint32_t offset = 0;
pScreen = screenInfo.screens[pScrn->scrnIndex];
+
#ifdef USE_EXA
if (info->useEXA) {
ExaOffscreenArea *area = *mem_struct;
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 8e01b0f..ce4ba93 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -184,6 +184,7 @@ typedef struct
typedef struct _RADEONCrtcPrivateRec {
void *crtc_rotate_mem;
+ void *cursor_mem;
int crtc_id;
int binding;
uint32_t cursor_offset;
commit 5b1978a4796bcc31ac2f01d303dc8f8f44323025
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Aug 25 10:05:28 2008 -0400
Bicubic fixes from the last cherry-pick
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index d210a2d..4005df9 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -213,9 +213,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
if (!IS_R500_3D)
pPriv->bicubic_enabled = FALSE;
if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) {
- pPriv->bicubic_offset = RADEONAllocateMemory(pScrn,
- &pPriv->bicubic_memory,
- sizeof(bicubic_tex_512));
+ pPriv->bicubic_offset = radeon_allocate_memory(pScrn,
+ &pPriv->bicubic_memory,
+ sizeof(bicubic_tex_512), 64);
pPriv->bicubic_src_offset = pPriv->bicubic_offset + info->fbLocation + pScrn->fbOffset;
if (pPriv->bicubic_offset == 0)
pPriv->bicubic_enabled = FALSE;
diff --git a/src/radeon_video.c b/src/radeon_video.c
index e86a7d4..598bf2b 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -1614,13 +1614,12 @@ RADEONSetupImageVideo(ScreenPtr pScreen)
pPriv->textured = FALSE;
- if(pPriv->theatre != NULL)
- {
+ if(pPriv->theatre != NULL) {
/* video decoder is present, extend capabilities */
adapt->nEncodings = 13;
adapt->pEncodings = InputVideoEncodings;
adapt->type |= XvVideoMask;
- adapt->nAttributes = NUM_DEC_ATTRIBUTES;
+ adapt->nAttributes = NUM_DEC_ATTRIBUTES;
adapt->PutVideo = RADEONPutVideo;
}
@@ -1636,8 +1635,19 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup)
unsigned char *RADEONMMIO = info->MMIO;
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
- if (pPriv->textured)
- return;
+ if (pPriv->textured) {
+ if (cleanup) {
+ if (pPriv->bicubic_memory != NULL) {
+ radeon_free_memory(pScrn, pPriv->bicubic_memory);
+ pPriv->bicubic_memory = NULL;
+ }
+ if (pPriv->video_memory != NULL) {
+ radeon_free_memory(pScrn, pPriv->video_memory);
+ pPriv->video_memory = NULL;
+ }
+ }
+ return;
+ }
REGION_EMPTY(pScrn->pScreen, &pPriv->clip);
@@ -1660,10 +1670,6 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup)
radeon_free_memory(pScrn, pPriv->video_memory);
pPriv->video_memory = NULL;
}
- if (pPriv->bicubic_memory != NULL) {
- RADEONFreeMemory(pScrn, pPriv->bicubic_memory);
- pPriv->bicubic_memory = NULL;
- }
pPriv->videoStatus = 0;
} else {
if(pPriv->videoStatus & CLIENT_VIDEO_ON) {
@@ -3129,10 +3135,6 @@ RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now)
radeon_free_memory(pScrn, pPriv->video_memory);
pPriv->video_memory = NULL;
}
- if (pPriv->bicubic_memory != NULL) {
- RADEONFreeMemory(pScrn, pPriv->bicubic_memory);
- pPriv->bicubic_memory = NULL;
- }
pPriv->videoStatus = 0;
info->VideoTimerCallback = NULL;
}
commit 7daba77ded1c718e93ae8c372a39a6e85228d513
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Jul 11 02:02:38 2008 -0400
Convert randr, Xv to a common allocator
diff --git a/src/Makefile.am b/src/Makefile.am
index 97c686b..c79b635 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -88,7 +88,7 @@ radeon_drv_la_LTLIBRARIES = radeon_drv.la
radeon_drv_la_LDFLAGS = -module -avoid-version
radeon_drv_ladir = @moduledir@/drivers
radeon_drv_la_SOURCES = \
- radeon_accel.c radeon_cursor.c radeon_dga.c \
+ radeon_accel.c radeon_cursor.c radeon_dga.c radeon_memory.c \
radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \
radeon_vip.c radeon_misc.c radeon_probe.c \
legacy_crtc.c legacy_output.c \
@@ -128,7 +128,6 @@ EXTRA_DIST = \
radeon_render.c \
radeon_accelfuncs.c \
radeon_textured_videofuncs.c \
- \
ati.h \
ativersion.h \
generic_bus.h \
diff --git a/src/radeon.h b/src/radeon.h
index 7ed39f8..6cce736 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1068,6 +1068,16 @@ extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
extern void RADEONInitVideo(ScreenPtr pScreen);
extern void RADEONResetVideo(ScrnInfoPtr pScrn);
+/* radeon_memory.c */
+extern uint32_t
+radeon_allocate_memory(ScrnInfoPtr pScrn,
+ void **mem_struct,
+ int size,
+ int align);
+extern void
+radeon_free_memory(ScrnInfoPtr pScrn,
+ void *mem_struct);
+
#ifdef XF86DRI
# ifdef USE_XAA
/* radeon_accelfuncs.c */
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index dce450c..69a87a4 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -394,44 +394,6 @@ radeon_crtc_unlock(xf86CrtcPtr crtc)
RADEON_SYNC(info, pScrn);
}
-#ifdef USE_XAA
-/**
- * Allocates memory from the XF86 linear allocator, but also purges
- * memory if possible to cause the allocation to succeed.
- */
-static FBLinearPtr
-radeon_xf86AllocateOffscreenLinear(ScreenPtr pScreen, int length,
- int granularity,
- MoveLinearCallbackProcPtr moveCB,
- RemoveLinearCallbackProcPtr removeCB,
- pointer privData)
-{
- FBLinearPtr linear;
- int max_size;
-
- linear = xf86AllocateOffscreenLinear(pScreen, length, granularity, moveCB,
- removeCB, privData);
- if (linear != NULL)
- return linear;
-
- /* The above allocation didn't succeed, so purge unlocked stuff and try
- * again.
- */
- xf86QueryLargestOffscreenLinear(pScreen, &max_size, granularity,
- PRIORITY_EXTREME);
-
- if (max_size < length)
- return NULL;
-
- xf86PurgeUnlockedOffscreenAreas(pScreen);
-
- linear = xf86AllocateOffscreenLinear(pScreen, length, granularity, moveCB,
- removeCB, privData);
-
- return linear;
-}
-#endif
-
/**
* Allocates memory for a locked-in-framebuffer shadow of the given
* width and height for this CRTC's rotated shadow framebuffer.
@@ -441,8 +403,6 @@ static void *
radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
{
ScrnInfoPtr pScrn = crtc->scrn;
- /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
- ScreenPtr pScreen = screenInfo.screens[pScrn->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
unsigned long rotate_pitch;
@@ -453,49 +413,14 @@ radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
rotate_pitch = pScrn->displayWidth * cpp;
size = rotate_pitch * height;
-#ifdef USE_EXA
/* We could get close to what we want here by just creating a pixmap like
* normal, but we have to lock it down in framebuffer, and there is no
* setter for offscreen area locking in EXA currently. So, we just
* allocate offscreen memory and fake up a pixmap header for it.
*/
- if (info->useEXA) {
- assert(radeon_crtc->rotate_mem_exa == NULL);
-
- radeon_crtc->rotate_mem_exa = exaOffscreenAlloc(pScreen, size, align,
- TRUE, NULL, NULL);
- if (radeon_crtc->rotate_mem_exa == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Couldn't allocate shadow memory for rotated CRTC\n");
- return NULL;
- }
- rotate_offset = radeon_crtc->rotate_mem_exa->offset;
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- /* The XFree86 linear allocator operates in units of screen pixels,
- * sadly.
- */
- size = (size + cpp - 1) / cpp;
- align = (align + cpp - 1) / cpp;
-
- assert(radeon_crtc->rotate_mem_xaa == NULL);
-
- radeon_crtc->rotate_mem_xaa =
- radeon_xf86AllocateOffscreenLinear(pScreen, size, align,
- NULL, NULL, NULL);
- if (radeon_crtc->rotate_mem_xaa == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Couldn't allocate shadow memory for rotated CRTC\n");
- return NULL;
- }
-#ifdef XF86DRI
- rotate_offset = info->dri->frontOffset +
- radeon_crtc->rotate_mem_xaa->offset * cpp;
-#endif
- }
-#endif /* USE_XAA */
+ rotate_offset = radeon_allocate_memory(pScrn, &radeon_crtc->crtc_rotate_mem, size, align);
+ if (rotate_offset == 0)
+ return NULL;
return info->FB + rotate_offset;
}
@@ -535,26 +460,14 @@ static void
radeon_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
{
ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
if (rotate_pixmap)
FreeScratchPixmapHeader(rotate_pixmap);
-
- if (data) {
-#ifdef USE_EXA
- if (info->useEXA && radeon_crtc->rotate_mem_exa != NULL) {
- exaOffscreenFree(pScrn->pScreen, radeon_crtc->rotate_mem_exa);
- radeon_crtc->rotate_mem_exa = NULL;
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- xf86FreeOffscreenLinear(radeon_crtc->rotate_mem_xaa);
- radeon_crtc->rotate_mem_xaa = NULL;
- }
-#endif /* USE_XAA */
- }
+
+ if (data)
+ radeon_free_memory(pScrn, radeon_crtc->crtc_rotate_mem);
+
}
static const xf86CrtcFuncsRec radeon_crtc_funcs = {
diff --git a/src/radeon_memory.c b/src/radeon_memory.c
new file mode 100644
index 0000000..d9e6403
--- /dev/null
+++ b/src/radeon_memory.c
@@ -0,0 +1,118 @@
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+/* Driver data structures */
+#include "radeon.h"
+
+
+/* Allocates memory, either by resizing the allocation pointed to by mem_struct,
+ * or by freeing mem_struct (if non-NULL) and allocating a new space. The size
+ * is measured in bytes, and the offset from the beginning of card space is
+ * returned.
+ */
+uint32_t
+radeon_allocate_memory(ScrnInfoPtr pScrn,
+ void **mem_struct,
+ int size,
+ int align)
+{
+ ScreenPtr pScreen;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ int offset = 0;
+
+ pScreen = screenInfo.screens[pScrn->scrnIndex];
+#ifdef USE_EXA
+ if (info->useEXA) {
+ ExaOffscreenArea *area = *mem_struct;
+
+ if (area != NULL) {
+ if (area->size >= size)
+ return area->offset;
+
+ exaOffscreenFree(pScrn->pScreen, area);
+ }
+
+ area = exaOffscreenAlloc(pScrn->pScreen, size, align, TRUE,
+ NULL, NULL);
+
+ *mem_struct = area;
+ if (area == NULL)
+ return 0;
+ offset = area->offset;
+ }
+#endif /* USE_EXA */
+#ifdef USE_XAA
+ if (!info->useEXA) {
+ FBLinearPtr linear = *mem_struct;
+ int cpp = info->CurrentLayout.bitsPerPixel / 8;
+
+ /* XAA allocates in units of pixels at the screen bpp, so adjust size
+ * appropriately.
+ */
+ size = (size + cpp - 1) / cpp;
+ align = (align + cpp - 1) / cpp;
+
+ if (linear) {
+ if(linear->size >= size)
+ return linear->offset * cpp;
+
+ if(xf86ResizeOffscreenLinear(linear, size))
+ return linear->offset * cpp;
+
+ xf86FreeOffscreenLinear(linear);
+ }
+
+ linear = xf86AllocateOffscreenLinear(pScreen, size, align,
+ NULL, NULL, NULL);
+ *mem_struct = linear;
+
+ if (!linear) {
+ int max_size;
+
+ xf86QueryLargestOffscreenLinear(pScreen, &max_size, align,
+ PRIORITY_EXTREME);
+
+ if (max_size < size)
+ return 0;
+
+ xf86PurgeUnlockedOffscreenAreas(pScreen);
+ linear = xf86AllocateOffscreenLinear(pScreen, size, align,
+ NULL, NULL, NULL);
+ *mem_struct = linear;
+ if (!linear)
+ return 0;
+ }
+ offset = linear->offset * cpp;
+ }
+#endif /* USE_XAA */
+
+ return offset;
+}
+
+void
+radeon_free_memory(ScrnInfoPtr pScrn,
+ void *mem_struct)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+#ifdef USE_EXA
+ if (info->useEXA) {
+ ExaOffscreenArea *area = mem_struct;
+
+ if (area != NULL)
+ exaOffscreenFree(pScrn->pScreen, area);
+ area = NULL;
+ }
+#endif /* USE_EXA */
+#ifdef USE_XAA
+ if (!info->useEXA) {
+ FBLinearPtr linear = mem_struct;
+
+ if (linear != NULL)
+ xf86FreeOffscreenLinear(linear);
+ linear = NULL;
+ }
+#endif /* USE_XAA */
+}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 3770abf..8e01b0f 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -183,12 +183,7 @@ typedef struct
} RADEONI2CBusRec, *RADEONI2CBusPtr;
typedef struct _RADEONCrtcPrivateRec {
-#ifdef USE_XAA
- FBLinearPtr rotate_mem_xaa;
-#endif
-#ifdef USE_EXA
- ExaOffscreenArea *rotate_mem_exa;
-#endif
+ void *crtc_rotate_mem;
int crtc_id;
int binding;
uint32_t cursor_offset;
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 9e6b37a..d210a2d 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -197,14 +197,14 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
dstPitch = (dstPitch + 15) & ~15;
if (pPriv->video_memory != NULL && size != pPriv->size) {
- RADEONFreeMemory(pScrn, pPriv->video_memory);
+ radeon_free_memory(pScrn, pPriv->video_memory);
pPriv->video_memory = NULL;
}
if (pPriv->video_memory == NULL) {
- pPriv->video_offset = RADEONAllocateMemory(pScrn,
- &pPriv->video_memory,
- size * 2);
+ pPriv->video_offset = radeon_allocate_memory(pScrn,
+ &pPriv->video_memory,
+ size * 2, 64);
if (pPriv->video_offset == 0)
return BadAlloc;
}
diff --git a/src/radeon_video.c b/src/radeon_video.c
index e71f0f8..e86a7d4 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -240,19 +240,6 @@ radeon_crtc_clip_video(ScrnInfoPtr pScrn,
#endif
}
-#ifdef USE_EXA
-static void
-ATIVideoSave(ScreenPtr pScreen, ExaOffscreenArea *area)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr;
-
- if (pPriv->video_memory == area)
- pPriv->video_memory = NULL;
-}
-#endif /* USE_EXA */
-
void RADEONInitVideo(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
@@ -1670,7 +1657,7 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup)
if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv);
}
if (pPriv->video_memory != NULL) {
- RADEONFreeMemory(pScrn, pPriv->video_memory);
+ radeon_free_memory(pScrn, pPriv->video_memory);
pPriv->video_memory = NULL;
}
if (pPriv->bicubic_memory != NULL) {
@@ -2426,114 +2413,6 @@ RADEONCopyMungedData(
}
}
-
-/* Allocates memory, either by resizing the allocation pointed to by mem_struct,
- * or by freeing mem_struct (if non-NULL) and allocating a new space. The size
- * is measured in bytes, and the offset from the beginning of card space is
- * returned.
- */
-uint32_t
-RADEONAllocateMemory(
- ScrnInfoPtr pScrn,
- void **mem_struct,
- int size
-){
- ScreenPtr pScreen;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int offset = 0;
-
- pScreen = screenInfo.screens[pScrn->scrnIndex];
-#ifdef USE_EXA
- if (info->useEXA) {
- ExaOffscreenArea *area = *mem_struct;
-
- if (area != NULL) {
- if (area->size >= size)
- return area->offset;
-
- exaOffscreenFree(pScrn->pScreen, area);
- }
-
- area = exaOffscreenAlloc(pScrn->pScreen, size, 64, TRUE, ATIVideoSave,
- NULL);
- *mem_struct = area;
- if (area == NULL)
- return 0;
- offset = area->offset;
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- FBLinearPtr linear = *mem_struct;
- int cpp = info->CurrentLayout.bitsPerPixel / 8;
-
- /* XAA allocates in units of pixels at the screen bpp, so adjust size
- * appropriately.
- */
- size = (size + cpp - 1) / cpp;
-
- if (linear) {
- if(linear->size >= size)
- return linear->offset * cpp;
-
- if(xf86ResizeOffscreenLinear(linear, size))
- return linear->offset * cpp;
-
- xf86FreeOffscreenLinear(linear);
- }
-
- linear = xf86AllocateOffscreenLinear(pScreen, size, 16,
- NULL, NULL, NULL);
- *mem_struct = linear;
-
- if (!linear) {
- int max_size;
-
- xf86QueryLargestOffscreenLinear(pScreen, &max_size, 16,
- PRIORITY_EXTREME);
-
- if(max_size < size)
- return 0;
-
- xf86PurgeUnlockedOffscreenAreas(pScreen);
- linear = xf86AllocateOffscreenLinear(pScreen, size, 16,
- NULL, NULL, NULL);
- *mem_struct = linear;
- if (!linear)
- return 0;
- }
- offset = linear->offset * cpp;
- }
-#endif /* USE_XAA */
-
- return offset;
-}
-
-void
-RADEONFreeMemory(
- ScrnInfoPtr pScrn,
- void *mem_struct
-){
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifdef USE_EXA
- if (info->useEXA) {
- ExaOffscreenArea *area = mem_struct;
-
- if (area != NULL)
- exaOffscreenFree(pScrn->pScreen, area);
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- FBLinearPtr linear = mem_struct;
-
- if (linear != NULL)
- xf86FreeOffscreenLinear(linear);
- }
-#endif /* USE_XAA */
-}
-
static void
RADEONDisplayVideo(
ScrnInfoPtr pScrn,
@@ -3052,9 +2931,9 @@ RADEONPutImage(
if (idconv == FOURCC_YV12 || id == FOURCC_I420) {
new_size += (dstPitch >> 1) * ((height + 1) & ~1);
}
- pPriv->video_offset = RADEONAllocateMemory(pScrn, &pPriv->video_memory,
- (pPriv->doubleBuffer ?
- (new_size * 2) : new_size));
+ pPriv->video_offset = radeon_allocate_memory(pScrn, &pPriv->video_memory,
+ (pPriv->doubleBuffer ?
+ (new_size * 2) : new_size), 64);
if (pPriv->video_offset == 0)
return BadAlloc;
@@ -3247,7 +3126,7 @@ RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now)
} else { /* FREE_TIMER */
if(pPriv->freeTime < now) {
if (pPriv->video_memory != NULL) {
- RADEONFreeMemory(pScrn, pPriv->video_memory);
+ radeon_free_memory(pScrn, pPriv->video_memory);
pPriv->video_memory = NULL;
}
if (pPriv->bicubic_memory != NULL) {
@@ -3286,7 +3165,7 @@ RADEONAllocateSurface(
pitch = ((w << 1) + 15) & ~15;
size = pitch * h;
- offset = RADEONAllocateMemory(pScrn, &surface_memory, size);
+ offset = radeon_allocate_memory(pScrn, &surface_memory, size, 64);
if (offset == 0)
return BadAlloc;
@@ -3294,18 +3173,18 @@ RADEONAllocateSurface(
surface->height = h;
if(!(surface->pitches = xalloc(sizeof(int)))) {
- RADEONFreeMemory(pScrn, surface_memory);
+ radeon_free_memory(pScrn, surface_memory);
return BadAlloc;
}
if(!(surface->offsets = xalloc(sizeof(int)))) {
xfree(surface->pitches);
- RADEONFreeMemory(pScrn, surface_memory);
+ radeon_free_memory(pScrn, surface_memory);
return BadAlloc;
}
if(!(pPriv = xalloc(sizeof(OffscreenPrivRec)))) {
xfree(surface->pitches);
xfree(surface->offsets);
- RADEONFreeMemory(pScrn, surface_memory);
+ radeon_free_memory(pScrn, surface_memory);
return BadAlloc;
}
@@ -3346,7 +3225,7 @@ RADEONFreeSurface(
if(pPriv->isOn)
RADEONStopSurface(surface);
- RADEONFreeMemory(pScrn, pPriv->surface_memory);
+ radeon_free_memory(pScrn, pPriv->surface_memory);
xfree(surface->pitches);
xfree(surface->offsets);
xfree(surface->devPrivate.ptr);
@@ -3620,9 +3499,9 @@ RADEONPutVideo(
if (pPriv->capture_vbi_data)
alloc_size += 2 * 2 * vbi_line_width * 21;
- pPriv->video_offset = RADEONAllocateMemory(pScrn, &pPriv->video_memory,
- (pPriv->doubleBuffer ?
- (new_size * 2) : new_size));
+ pPriv->video_offset = radeon_allocate_memory(pScrn, &pPriv->video_memory,
+ (pPriv->doubleBuffer ?
+ (new_size * 2) : new_size), 64);
if (pPriv->video_offset == 0)
return BadAlloc;
diff --git a/src/radeon_video.h b/src/radeon_video.h
index b9d900d..11b8029 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -86,9 +86,6 @@ typedef struct {
xf86CrtcPtr desired_crtc;
int size;
-#ifdef USE_EXA
- ExaOffscreenArea *off_screen;
-#endif
void *video_memory;
int video_offset;
@@ -122,11 +119,6 @@ void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
-uint32_t
-RADEONAllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size);
-void
-RADEONFreeMemory(ScrnInfoPtr pScrn, void *mem_struct);
-
int RADEONSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer);
int RADEONGetPortAttribute(ScrnInfoPtr, Atom ,INT32 *, pointer);
void RADEONStopVideo(ScrnInfoPtr, pointer, Bool);
commit 610fe1a937da78f4ac813ac919c158dde8f42442
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Jul 10 22:47:35 2008 -0400
Switch to using radeon_drm.h from the drm
modelled after Matthias' similar rhd change
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 8f5b40a..412a181 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -43,8 +43,7 @@
#ifdef XF86DRI
#define _XF86DRI_SERVER_
-#include "radeon_dri.h"
-#include "radeon_sarea.h"
+#include "radeon_drm.h"
#include "sarea.h"
#endif
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 14e4259..c16d0a3 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -48,8 +48,7 @@
#ifdef XF86DRI
#define _XF86DRI_SERVER_
-#include "radeon_dri.h"
-#include "radeon_sarea.h"
+#include "radeon_drm.h"
#include "sarea.h"
#ifdef DRM_IOCTL_MODESET_CTL
#include <sys/ioctl.h>
@@ -755,7 +754,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
RADEONInfoPtr info = RADEONPTR(pScrn);
int Base;
#ifdef XF86DRI
- RADEONSAREAPrivPtr pSAREAPriv;
+ drm_radeon_sarea_t *pSAREAPriv;
XF86DRISAREAPtr pSAREA;
#endif
@@ -973,7 +972,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
RADEONInfoPtr info = RADEONPTR(pScrn);
int Base;
#ifdef XF86DRI
- RADEONSAREAPrivPtr pSAREAPriv;
+ drm_radeon_sarea_t *pSAREAPriv;
XF86DRISAREAPtr pSAREA;
#endif
diff --git a/src/radeon.h b/src/radeon.h
index 06c7689..7ed39f8 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -72,9 +72,10 @@
/* DRI support */
#ifdef XF86DRI
#define _XF86DRI_SERVER_
-#include "radeon_dripriv.h"
#include "dri.h"
#include "GL/glxint.h"
+#include "xf86drm.h"
+
#ifdef DAMAGE
#include "damage.h"
#include "globals.h"
@@ -434,6 +435,21 @@ struct radeon_cp {
};
+typedef struct {
+ /* Nothing here yet */
+ int dummy;
+} RADEONConfigPrivRec, *RADEONConfigPrivPtr;
+
+typedef struct {
+#ifdef PER_CONTEXT_SAREA
+ drm_context_t ctx_id;
+ drm_handle_t sarea_handle;
+#else
+ /* Nothing here yet */
+ int dummy;
+#endif
+} RADEONDRIContextRec, *RADEONDRIContextPtr;
+
struct radeon_dri {
Bool noBackBuffer;
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 79ebf84..a6e332d 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -83,9 +83,7 @@
#include "radeon_version.h"
#ifdef XF86DRI
#define _XF86DRI_SERVER_
-#include "radeon_dri.h"
-#include "radeon_common.h"
-#include "radeon_sarea.h"
+#include "radeon_drm.h"
#endif
/* Line support */
@@ -373,7 +371,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
#ifdef XF86DRI
if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) {
- drmRadeonGetParam np;
+ drm_radeon_getparam_t np;
int num_pipes;
memset(&np, 0, sizeof(np));
@@ -513,14 +511,14 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
/* Stop the CP */
int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
{
- drmRadeonCPStop stop;
+ drm_radeon_cp_stop_t stop;
int ret, i;
stop.flush = 1;
stop.idle = 1;
ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drmRadeonCPStop));
+ sizeof(drm_radeon_cp_stop_t));
if (ret == 0) {
return 0;
@@ -533,7 +531,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
i = 0;
do {
ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drmRadeonCPStop));
+ sizeof(drm_radeon_cp_stop_t));
} while (ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY);
if (ret == 0) {
@@ -545,7 +543,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
stop.idle = 0;
if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP,
- &stop, sizeof(drmRadeonCPStop))) {
+ &stop, sizeof(drm_radeon_cp_stop_t))) {
return -errno;
} else {
return 0;
@@ -622,7 +620,7 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
RADEONInfoPtr info = RADEONPTR(pScrn);
drmBufPtr buffer = info->cp->indirectBuffer;
int start = info->cp->indirectStart;
- drmRadeonIndirect indirect;
+ drm_radeon_indirect_t indirect;
if (!buffer) return;
if (start == buffer->used && !discard) return;
@@ -638,7 +636,7 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
indirect.discard = discard;
drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
- &indirect, sizeof(drmRadeonIndirect));
+ &indirect, sizeof(drm_radeon_indirect_t));
if (discard) {
info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn);
@@ -659,7 +657,7 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
drmBufPtr buffer = info->cp->indirectBuffer;
int start = info->cp->indirectStart;
- drmRadeonIndirect indirect;
+ drm_radeon_indirect_t indirect;
info->cp->indirectBuffer = NULL;
info->cp->indirectStart = 0;
@@ -677,7 +675,7 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn)
indirect.discard = 1;
drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
- &indirect, sizeof(drmRadeonIndirect));
+ &indirect, sizeof(drm_radeon_indirect_t));
}
/** \brief Calculate HostDataBlit parameters from pointer and pitch
@@ -972,10 +970,10 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn)
#ifdef XF86DRI
if (info->directRenderingEnabled) {
- RADEONSAREAPrivPtr pSAREAPriv;
+ drm_radeon_sarea_t *pSAREAPriv;
pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
- pSAREAPriv->ctxOwner = DRIGetContext(pScrn->pScreen);
+ pSAREAPriv->ctx_owner = DRIGetContext(pScrn->pScreen);
RADEONInit3DEngineCP(pScrn);
} else
#endif
diff --git a/src/radeon_common.h b/src/radeon_common.h
deleted file mode 100644
index 193c1f9..0000000
--- a/src/radeon_common.h
+++ /dev/null
@@ -1,496 +0,0 @@
-/* radeon_common.h -- common header definitions for Radeon 2D/3D/DRM suite
- *
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Author:
- * Gareth Hughes <gareth at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- * Keith Whitwell <keith at tungstengraphics.com>
- *
- * Converted to common header format:
- * Jens Owen <jens at tungstengraphics.com>
- *
- */
-
-#ifndef _RADEON_COMMON_H_
-#define _RADEON_COMMON_H_
-
-#include <inttypes.h>
-#include "xf86drm.h"
-
-/* WARNING: If you change any of these defines, make sure to change
- * the kernel include file as well (radeon_drm.h)
- */
-
-/* Driver specific DRM command indices
- * NOTE: these are not OS specific, but they are driver specific
- */
-#define DRM_RADEON_CP_INIT 0x00
-#define DRM_RADEON_CP_START 0x01
-#define DRM_RADEON_CP_STOP 0x02
-#define DRM_RADEON_CP_RESET 0x03
-#define DRM_RADEON_CP_IDLE 0x04
-#define DRM_RADEON_RESET 0x05
-#define DRM_RADEON_FULLSCREEN 0x06
-#define DRM_RADEON_SWAP 0x07
-#define DRM_RADEON_CLEAR 0x08
-#define DRM_RADEON_VERTEX 0x09
-#define DRM_RADEON_INDICES 0x0a
-#define DRM_RADEON_STIPPLE 0x0c
-#define DRM_RADEON_INDIRECT 0x0d
-#define DRM_RADEON_TEXTURE 0x0e
-#define DRM_RADEON_VERTEX2 0x0f
-#define DRM_RADEON_CMDBUF 0x10
-#define DRM_RADEON_GETPARAM 0x11
-#define DRM_RADEON_FLIP 0x12
-#define DRM_RADEON_ALLOC 0x13
-#define DRM_RADEON_FREE 0x14
-#define DRM_RADEON_INIT_HEAP 0x15
-#define DRM_RADEON_IRQ_EMIT 0x16
-#define DRM_RADEON_IRQ_WAIT 0x17
-#define DRM_RADEON_CP_RESUME 0x18
-#define DRM_RADEON_SETPARAM 0x19
-#define DRM_RADEON_SURF_ALLOC 0x1a
-#define DRM_RADEON_SURF_FREE 0x1b
-#define DRM_RADEON_MAX_DRM_COMMAND_INDEX 0x39
-
-
-#define RADEON_FRONT 0x1
-#define RADEON_BACK 0x2
-#define RADEON_DEPTH 0x4
-#define RADEON_STENCIL 0x8
-
-#define RADEON_CLEAR_X1 0
-#define RADEON_CLEAR_Y1 1
-#define RADEON_CLEAR_X2 2
-#define RADEON_CLEAR_Y2 3
-#define RADEON_CLEAR_DEPTH 4
-
-
-typedef struct {
- enum {
- DRM_RADEON_INIT_CP = 0x01,
- DRM_RADEON_CLEANUP_CP = 0x02,
- DRM_RADEON_INIT_R200_CP = 0x03,
- DRM_RADEON_INIT_R300_CP = 0x04
- } func;
- unsigned long sarea_priv_offset;
- int is_pci;
- int cp_mode;
- int gart_size;
- int ring_size;
- int usec_timeout;
-
- unsigned int fb_bpp;
- unsigned int front_offset, front_pitch;
- unsigned int back_offset, back_pitch;
- unsigned int depth_bpp;
- unsigned int depth_offset, depth_pitch;
-
- unsigned long fb_offset;
- unsigned long mmio_offset;
- unsigned long ring_offset;
- unsigned long ring_rptr_offset;
- unsigned long buffers_offset;
- unsigned long gart_textures_offset;
-} drmRadeonInit;
-
-typedef struct {
- int flush;
- int idle;
-} drmRadeonCPStop;
-
-typedef struct {
- int idx;
- int start;
- int end;
- int discard;
-} drmRadeonIndirect;
-
-typedef union drmRadeonClearR {
- float f[5];
- unsigned int ui[5];
-} drmRadeonClearRect;
-
-typedef struct drmRadeonClearT {
- unsigned int flags;
- unsigned int clear_color;
- unsigned int clear_depth;
- unsigned int color_mask;
- unsigned int depth_mask; /* misnamed field: should be stencil */
- drmRadeonClearRect *depth_boxes;
-} drmRadeonClearType;
-
-typedef struct drmRadeonFullscreenT {
- enum {
- RADEON_INIT_FULLSCREEN = 0x01,
- RADEON_CLEANUP_FULLSCREEN = 0x02
- } func;
-} drmRadeonFullscreenType;
-
-typedef struct {
- unsigned int *mask;
-} drmRadeonStipple;
-
-typedef struct {
- unsigned int x;
- unsigned int y;
- unsigned int width;
- unsigned int height;
- const void *data;
-} drmRadeonTexImage;
-
-typedef struct {
- unsigned int offset;
- int pitch;
- int format;
- int width; /* Texture image coordinates */
- int height;
- drmRadeonTexImage *image;
-} drmRadeonTexture;
-
-
-#define RADEON_MAX_TEXTURE_UNITS 3
-
-/* Layout matches drm_radeon_state_t in linux drm_radeon.h.
- */
-typedef struct {
- struct {
- unsigned int pp_misc; /* 0x1c14 */
- unsigned int pp_fog_color;
- unsigned int re_solid_color;
- unsigned int rb3d_blendcntl;
- unsigned int rb3d_depthoffset;
- unsigned int rb3d_depthpitch;
- unsigned int rb3d_zstencilcntl;
- unsigned int pp_cntl; /* 0x1c38 */
- unsigned int rb3d_cntl;
- unsigned int rb3d_coloroffset;
- unsigned int re_width_height;
- unsigned int rb3d_colorpitch;
- } context;
- struct {
- unsigned int se_cntl;
- } setup1;
- struct {
- unsigned int se_coord_fmt; /* 0x1c50 */
- } vertex;
- struct {
- unsigned int re_line_pattern; /* 0x1cd0 */
- unsigned int re_line_state;
- unsigned int se_line_width; /* 0x1db8 */
- } line;
- struct {
- unsigned int pp_lum_matrix; /* 0x1d00 */
- unsigned int pp_rot_matrix_0; /* 0x1d58 */
- unsigned int pp_rot_matrix_1;
- } bumpmap;
- struct {
- unsigned int rb3d_stencilrefmask; /* 0x1d7c */
- unsigned int rb3d_ropcntl;
- unsigned int rb3d_planemask;
- } mask;
- struct {
- unsigned int se_vport_xscale; /* 0x1d98 */
- unsigned int se_vport_xoffset;
- unsigned int se_vport_yscale;
- unsigned int se_vport_yoffset;
- unsigned int se_vport_zscale;
- unsigned int se_vport_zoffset;
- } viewport;
- struct {
- unsigned int se_cntl_status; /* 0x2140 */
- } setup2;
- struct {
- unsigned int re_top_left; /*ignored*/ /* 0x26c0 */
- unsigned int re_misc;
- } misc;
- struct {
- unsigned int pp_txfilter;
- unsigned int pp_txformat;
- unsigned int pp_txoffset;
- unsigned int pp_txcblend;
- unsigned int pp_txablend;
- unsigned int pp_tfactor;
- unsigned int pp_border_color;
- } texture[RADEON_MAX_TEXTURE_UNITS];
- struct {
- unsigned int se_zbias_factor;
- unsigned int se_zbias_constant;
- } zbias;
- unsigned int dirty;
-} drmRadeonState;
-
-/* 1.1 vertex ioctl. Used in compatibility modes.
- */
-typedef struct {
- int prim;
- int idx; /* Index of vertex buffer */
- int count; /* Number of vertices in buffer */
- int discard; /* Client finished with buffer? */
-} drmRadeonVertex;
-
-typedef struct {
- unsigned int start;
- unsigned int finish;
- unsigned int prim:8;
- unsigned int stateidx:8;
- unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
- unsigned int vc_format;
-} drmRadeonPrim;
-
-typedef struct {
- int idx; /* Index of vertex buffer */
- int discard; /* Client finished with buffer? */
- int nr_states;
- drmRadeonState *state;
- int nr_prims;
- drmRadeonPrim *prim;
-} drmRadeonVertex2;
-
-#define RADEON_MAX_STATES 16
-#define RADEON_MAX_PRIMS 64
-
-/* Command buffer. Replace with true dma stream?
- */
-typedef struct {
- int bufsz;
- char *buf;
- int nbox;
- drm_clip_rect_t *boxes;
-} drmRadeonCmdBuffer;
-
-/* New style per-packet identifiers for use in cmd_buffer ioctl with
- * the RADEON_EMIT_PACKET command. Comments relate new packets to old
- * state bits and the packet size:
- */
-#define RADEON_EMIT_PP_MISC 0 /* context/7 */
-#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
-#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
-#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
-#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
-#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
-#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
-#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
-#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
-#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
-#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
-#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
-#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
-#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
-#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
-#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
-#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
-#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
-#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
-#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
-#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
-#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
-#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
-#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
-#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
-#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
-#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/6 */
-#define R200_EMIT_TFACTOR_0 30 /* tf/6 */
-#define R200_EMIT_VTX_FMT_0 31 /* vtx/4 */
-#define R200_EMIT_VAP_CTL 32 /* vap/1 */
-#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
-#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
-#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
-#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
-#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
-#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
-#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
-#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
-#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
-#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
-#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
-#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
-#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
-#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
-#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
-#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
-#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
-#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
-#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
-#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
-#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
-#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
-#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
-#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
-#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
-#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
-#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
-#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
-#define R200_EMIT_PP_CUBIC_FACES_0 61
-#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
-#define R200_EMIT_PP_CUBIC_FACES_1 63
-#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
-#define R200_EMIT_PP_CUBIC_FACES_2 65
-#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
-#define R200_EMIT_PP_CUBIC_FACES_3 67
-#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
-#define R200_EMIT_PP_CUBIC_FACES_4 69
-#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
-#define R200_EMIT_PP_CUBIC_FACES_5 71
-#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
-#define RADEON_EMIT_PP_TEX_SIZE_0 73
-#define RADEON_EMIT_PP_TEX_SIZE_1 74
-#define RADEON_EMIT_PP_TEX_SIZE_2 75
-#define R200_EMIT_RB3D_BLENDCOLOR 76
-#define RADEON_MAX_STATE_PACKETS 77
-
-
-/* Commands understood by cmd_buffer ioctl. More can be added but
- * obviously these can't be removed or changed:
- */
-#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
-#define RADEON_CMD_SCALARS 2 /* emit scalar data */
-#define RADEON_CMD_VECTORS 3 /* emit vector data */
-#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
-#define RADEON_CMD_PACKET3 5 /* emit hw packet */
-#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
-#define RADEON_CMD_SCALARS2 7 /* R200 stopgap */
-#define RADEON_CMD_WAIT 8 /* synchronization */
-
-typedef union {
- int i;
- struct {
- unsigned char cmd_type, pad0, pad1, pad2;
- } header;
- struct {
- unsigned char cmd_type, packet_id, pad0, pad1;
- } packet;
- struct {
- unsigned char cmd_type, offset, stride, count;
- } scalars;
- struct {
- unsigned char cmd_type, offset, stride, count;
- } vectors;
- struct {
- unsigned char cmd_type, buf_idx, pad0, pad1;
- } dma;
- struct {
- unsigned char cmd_type, flags, pad0, pad1;
- } wait;
-} drmRadeonCmdHeader;
-
-
-#define RADEON_WAIT_2D 0x1
-#define RADEON_WAIT_3D 0x2
-
-
-/* 1.3: An ioctl to get parameters that aren't available to the 3d
- * client any other way.
- */
-#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
-#define RADEON_PARAM_LAST_FRAME 2
-#define RADEON_PARAM_LAST_DISPATCH 3
-#define RADEON_PARAM_LAST_CLEAR 4
-/* Added with DRM version 1.6. */
-#define RADEON_PARAM_IRQ_NR 5
-#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
-/* Added with DRM version 1.8. */
-#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
-#define RADEON_PARAM_STATUS_HANDLE 8
-#define RADEON_PARAM_SAREA_HANDLE 9
-#define RADEON_PARAM_GART_TEX_HANDLE 10
-#define RADEON_PARAM_SCRATCH_OFFSET 11
-#define RADEON_PARAM_CARD_TYPE 12
-#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
-#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
-#define RADEON_PARAM_NUM_GB_PIPES 15
-
-typedef struct drm_radeon_getparam {
- int param;
- int *value;
-} drmRadeonGetParam;
-
-
-#define RADEON_MEM_REGION_GART 1
-#define RADEON_MEM_REGION_FB 2
-
-typedef struct drm_radeon_mem_alloc {
- int region;
- int alignment;
- int size;
- int *region_offset; /* offset from start of fb or GART */
-} drmRadeonMemAlloc;
-
-typedef struct drm_radeon_mem_free {
- int region;
- int region_offset;
-} drmRadeonMemFree;
-
-typedef struct drm_radeon_mem_init_heap {
- int region;
- int size;
- int start;
-} drmRadeonMemInitHeap;
-
-/* 1.6: Userspace can request & wait on irq's:
- */
-typedef struct drm_radeon_irq_emit {
- int *irq_seq;
-} drmRadeonIrqEmit;
-
-typedef struct drm_radeon_irq_wait {
- int irq_seq;
-} drmRadeonIrqWait;
-
-
-/* 1.10: Clients tell the DRM where they think the framebuffer is located in
- * the card's address space, via a new generic ioctl to set parameters
- */
-
-typedef struct drm_radeon_set_param {
- unsigned int param;
- int64_t value;
-} drmRadeonSetParam;
-
-#define RADEON_SETPARAM_FB_LOCATION 1
-#define RADEON_SETPARAM_SWITCH_TILING 2
-#define RADEON_SETPARAM_PCIGART_LOCATION 3
-#define RADEON_SETPARAM_NEW_MEMMAP 4
-#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5
-#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
-/* 1.14: Clients can allocate/free a surface
- */
-typedef struct drm_radeon_surface_alloc {
- unsigned int address;
- unsigned int size;
- unsigned int flags;
-} drmRadeonSurfaceAlloc;
-
-typedef struct drm_radeon_surface_free {
- unsigned int address;
-} drmRadeonSurfaceFree;
-
-#define DRM_RADEON_VBLANK_CRTC1 1
-#define DRM_RADEON_VBLANK_CRTC2 2
-
-#endif
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index beb63b5..dce450c 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -48,8 +48,7 @@
#ifdef XF86DRI
#define _XF86DRI_SERVER_
-#include "radeon_dri.h"
-#include "radeon_sarea.h"
+#include "radeon_drm.h"
#include "sarea.h"
#endif
@@ -841,7 +840,7 @@ RADEONSetTiling(ScrnInfoPtr pScrn)
#ifdef XF86DRI
if (info->directRenderingEnabled && (info->tilingEnabled != can_tile)) {
- RADEONSAREAPrivPtr pSAREAPriv;
+ drm_radeon_sarea_t *pSAREAPriv;
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (can_tile ? 1 : 0)) < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] failed changing tiling status\n");
diff --git a/src/radeon_dga.c b/src/radeon_dga.c
index 1d4d6ca..6b0fabe 100644
--- a/src/radeon_dga.c
+++ b/src/radeon_dga.c
@@ -47,6 +47,9 @@
/* Driver data structures */
#include "radeon.h"
#include "radeon_probe.h"
+#ifdef XF86DRI
+#include "radeon_drm.h"
+#endif
/* X and server generic header files */
#include "xf86.h"
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 1baed4b..5542d2b 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -46,6 +46,7 @@
#include "radeon_video.h"
#include "radeon_reg.h"
#include "radeon_macros.h"
+#include "radeon_drm.h"
#include "radeon_dri.h"
#include "radeon_version.h"
@@ -58,10 +59,13 @@
#define _XF86DRI_SERVER_
#include "GL/glxtokens.h"
#include "sarea.h"
-#include "radeon_sarea.h"
static size_t radeon_drm_page_size;
+#define RADEON_MAX_DRAWABLES 256
+
+extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs,
+ void **configprivs);
static void RADEONDRITransitionTo2d(ScreenPtr pScreen);
static void RADEONDRITransitionTo3d(ScreenPtr pScreen);
@@ -356,13 +360,13 @@ static void RADEONEnterServer(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONSAREAPrivPtr pSAREAPriv;
+ drm_radeon_sarea_t *pSAREAPriv;
RADEON_MARK_SYNC(info, pScrn);
pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
- if (pSAREAPriv->ctxOwner != DRIGetContext(pScrn->pScreen)) {
+ if (pSAREAPriv->ctx_owner != DRIGetContext(pScrn->pScreen)) {
info->accel_state->XInited3D = FALSE;
info->cp->needCacheFlush = (info->ChipFamily >= CHIP_FAMILY_R300);
}
@@ -1090,16 +1094,16 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
int cpp = info->CurrentLayout.pixel_bytes;
- drmRadeonInit drmInfo;
+ drm_radeon_init_t drmInfo;
- memset(&drmInfo, 0, sizeof(drmRadeonInit));
+ memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
if ( info->ChipFamily >= CHIP_FAMILY_R300 )
- drmInfo.func = DRM_RADEON_INIT_R300_CP;
+ drmInfo.func = RADEON_INIT_R300_CP;
else
if ( info->ChipFamily >= CHIP_FAMILY_R200 )
- drmInfo.func = DRM_RADEON_INIT_R200_CP;
+ drmInfo.func = RADEON_INIT_R200_CP;
else
- drmInfo.func = DRM_RADEON_INIT_CP;
+ drmInfo.func = RADEON_INIT_CP;
drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
drmInfo.is_pci = (info->cardType!=CARD_AGP);
@@ -1126,7 +1130,7 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmInfo.gart_textures_offset= info->dri->gartTexHandle;
if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
- &drmInfo, sizeof(drmRadeonInit)) < 0)
+ &drmInfo, sizeof(drm_radeon_init_t)) < 0)
return FALSE;
/* DRM_RADEON_CP_INIT does an engine reset, which resets some engine
@@ -1140,7 +1144,7 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
- drmRadeonMemInitHeap drmHeap;
+ drm_radeon_mem_init_heap_t drmHeap;
/* Start up the simple memory manager for GART space */
drmHeap.region = RADEON_MEM_REGION_GART;
@@ -1492,7 +1496,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
/* For now the mapping works by using a fixed size defined
* in the SAREA header
*/
- if (sizeof(XF86DRISAREARec)+sizeof(RADEONSAREAPriv) > SAREA_MAX) {
+ if (sizeof(XF86DRISAREARec)+sizeof(drm_radeon_sarea_t) > SAREA_MAX) {
ErrorF("Data does not fit in SAREA\n");
return FALSE;
}
@@ -1622,7 +1626,7 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONSAREAPrivPtr pSAREAPriv;
+ drm_radeon_sarea_t *pSAREAPriv;
RADEONDRIPtr pRADEONDRI;
info->dri->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT;
@@ -1660,7 +1664,7 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
RADEONDRICPInit(pScrn);
/* Initialize the SAREA private data structure */
- pSAREAPriv = (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScreen);
+ pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen);
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate;
@@ -1782,7 +1786,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- drmRadeonInit drmInfo;
+ drm_radeon_init_t drmInfo;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONDRICloseScreen\n");
@@ -1805,10 +1809,10 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
}
/* De-allocate all kernel resources */
- memset(&drmInfo, 0, sizeof(drmRadeonInit));
- drmInfo.func = DRM_RADEON_CLEANUP_CP;
+ memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
+ drmInfo.func = RADEON_CLEANUP_CP;
drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
- &drmInfo, sizeof(drmRadeonInit));
+ &drmInfo, sizeof(drm_radeon_init_t));
/* De-allocate all GART resources */
if (info->dri->gartTex) {
@@ -1890,7 +1894,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
RADEONInfoPtr info = RADEONPTR(pScrn);
int i, num;
ScreenPtr pScreen = pScrn->pScreen;
- RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
+ drm_radeon_sarea_t *pSAREAPriv = DRIGetSAREAPrivate(pScreen);
#ifdef USE_EXA
PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
#endif
@@ -1903,7 +1907,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
/* Don't want to do this when no 3d is active and pages are
* right-way-round
*/
- if (!pSAREAPriv->pfAllowPageFlip && pSAREAPriv->pfCurrentPage == 0)
+ if (!pSAREAPriv->pfState && pSAREAPriv->pfCurrentPage == 0)
return;
REGION_NULL(pScreen, ®ion);
@@ -1988,12 +1992,12 @@ static void RADEONEnablePageFlip(ScreenPtr pScreen)
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->dri->allowPageFlip) {
- RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
+ drm_radeon_sarea_t *pSAREAPriv = DRIGetSAREAPrivate(pScreen);
BoxRec box = { .x1 = 0, .y1 = 0, .x2 = pScrn->virtualX - 1,
.y2 = pScrn->virtualY - 1 };
RegionPtr pReg = REGION_CREATE(pScreen, &box, 1);
- pSAREAPriv->pfAllowPageFlip = 1;
+ pSAREAPriv->pfState = 1;
RADEONDRIRefreshArea(pScrn, pReg);
REGION_DESTROY(pScreen, pReg);
}
@@ -2006,9 +2010,9 @@ static void RADEONDisablePageFlip(ScreenPtr pScreen)
* -- Field in sarea, plus bumping the window counters.
* -- DRM needs to cope with Front-to-Back swapbuffers.
*/
- RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
+ drm_radeon_sarea_t *pSAREAPriv = DRIGetSAREAPrivate(pScreen);
- pSAREAPriv->pfAllowPageFlip = 0;
+ pSAREAPriv->pfState = 0;
}
static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen)
@@ -2114,7 +2118,7 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
+ drm_radeon_sarea_t *pSAREAPriv = DRIGetSAREAPrivate(pScreen);
/* Try flipping back to the front page if necessary */
if (pSAREAPriv->pfCurrentPage == 1)
@@ -2222,14 +2226,14 @@ int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn)
int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
{
- drmRadeonSetParam radeonsetparam;
+ drm_radeon_setparam_t radeonsetparam;
RADEONInfoPtr info = RADEONPTR(pScrn);
int ret;
- memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam));
+ memset(&radeonsetparam, 0, sizeof(drm_radeon_setparam_t));
radeonsetparam.param = param;
radeonsetparam.value = value;
ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SETPARAM,
- &radeonsetparam, sizeof(drmRadeonSetParam));
+ &radeonsetparam, sizeof(drm_radeon_setparam_t));
return ret;
}
diff --git a/src/radeon_dripriv.h b/src/radeon_dripriv.h
deleted file mode 100644
index fcde08e..0000000
--- a/src/radeon_dripriv.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- *
- */
-
-#ifndef _RADEON_DRIPRIV_H_
-#define _RADEON_DRIPRIV_H_
-
-#include "GL/glxint.h"
-#include "xf86drm.h"
-#include "radeon_common.h"
-
-#define RADEON_MAX_DRAWABLES 256
-
-extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs,
- void **configprivs);
-
-typedef struct {
- /* Nothing here yet */
- int dummy;
-} RADEONConfigPrivRec, *RADEONConfigPrivPtr;
-
-typedef struct {
-#ifdef PER_CONTEXT_SAREA
- drm_context_t ctx_id;
- drm_handle_t sarea_handle;
-#else
- /* Nothing here yet */
- int dummy;
-#endif
-} RADEONDRIContextRec, *RADEONDRIContextPtr;
-
-#endif
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 9dd420e..42b6d0c 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -79,7 +79,7 @@
#ifdef XF86DRI
#define _XF86DRI_SERVER_
#include "radeon_dri.h"
-#include "radeon_sarea.h"
+#include "radeon_drm.h"
#include "sarea.h"
#endif
@@ -3952,7 +3952,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
#ifdef USE_EXA
if (info->accelDFS)
{
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
int gart_base;
memset(&gp, 0, sizeof(gp));
@@ -4043,8 +4043,8 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
}
#ifdef XF86DRI
if (info->directRenderingInited) {
- drmRadeonSurfaceFree drmsurffree;
- drmRadeonSurfaceAlloc drmsurfalloc;
+ drm_radeon_surface_free_t drmsurffree;
+ drm_radeon_surface_alloc_t drmsurfalloc;
int retvalue;
int depthCpp = (info->dri->depthBits - 8) / 4;
int depth_width_bytes = pScrn->displayWidth * depthCpp;
@@ -4117,7 +4117,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
(!((info->ChipFamily == CHIP_FAMILY_RV100) ||
(info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200)))) {
- drmRadeonSurfaceAlloc drmsurfalloc;
+ drm_radeon_surface_alloc_t drmsurfalloc;
drmsurfalloc.size = depthBufferSize;
drmsurfalloc.address = info->dri->depthOffset;
if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
@@ -5144,7 +5144,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
#ifdef XF86DRI
if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
- RADEONSAREAPrivPtr pSAREAPriv;
+ drm_radeon_sarea_t *pSAREAPriv;
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] failed changing tiling status\n");
@@ -5254,7 +5254,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2)
unsigned char *RADEONMMIO = info->MMIO;
int Base, reg, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0;
#ifdef XF86DRI
- RADEONSAREAPrivPtr pSAREAPriv;
+ drm_radeon_sarea_t *pSAREAPriv;
XF86DRISAREAPtr pSAREA;
#endif
@@ -5517,10 +5517,10 @@ void RADEONLeaveVT(int scrnIndex, int flags)
/* Make sure 3D clients will re-upload textures to video RAM */
if (info->dri->textureSize) {
- RADEONSAREAPrivPtr pSAREAPriv =
- (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScrn->pScreen);
- drmTextureRegionPtr list = pSAREAPriv->texList[0];
- int age = ++pSAREAPriv->texAge[0];
+ drm_radeon_sarea_t *pSAREAPriv =
+ (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScrn->pScreen);
+ drmTextureRegionPtr list = pSAREAPriv->tex_list[0];
+ int age = ++pSAREAPriv->tex_age[0];
i = 0;
diff --git a/src/radeon_drm.h b/src/radeon_drm.h
new file mode 100644
index 0000000..c0d566c
--- /dev/null
+++ b/src/radeon_drm.h
@@ -0,0 +1,755 @@
+/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
+ *
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Kevin E. Martin <martin at valinux.com>
+ * Gareth Hughes <gareth at valinux.com>
+ * Keith Whitwell <keith at tungstengraphics.com>
+ */
+
+#ifndef __RADEON_DRM_H__
+#define __RADEON_DRM_H__
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the X server file (radeon_sarea.h)
+ */
+#ifndef __RADEON_SAREA_DEFINES__
+#define __RADEON_SAREA_DEFINES__
+
+/* Old style state flags, required for sarea interface (1.1 and 1.2
+ * clears) and 1.2 drm_vertex2 ioctl.
+ */
+#define RADEON_UPLOAD_CONTEXT 0x00000001
+#define RADEON_UPLOAD_VERTFMT 0x00000002
+#define RADEON_UPLOAD_LINE 0x00000004
+#define RADEON_UPLOAD_BUMPMAP 0x00000008
+#define RADEON_UPLOAD_MASKS 0x00000010
+#define RADEON_UPLOAD_VIEWPORT 0x00000020
+#define RADEON_UPLOAD_SETUP 0x00000040
+#define RADEON_UPLOAD_TCL 0x00000080
+#define RADEON_UPLOAD_MISC 0x00000100
+#define RADEON_UPLOAD_TEX0 0x00000200
+#define RADEON_UPLOAD_TEX1 0x00000400
+#define RADEON_UPLOAD_TEX2 0x00000800
+#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
+#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
+#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
+#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
+#define RADEON_REQUIRE_QUIESCENCE 0x00010000
+#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
+#define RADEON_UPLOAD_ALL 0x003effff
+#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
+
+/* New style per-packet identifiers for use in cmd_buffer ioctl with
+ * the RADEON_EMIT_PACKET command. Comments relate new packets to old
+ * state bits and the packet size:
+ */
+#define RADEON_EMIT_PP_MISC 0 /* context/7 */
+#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
+#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
+#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
+#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
+#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
+#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
+#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
+#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
+#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
+#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
+#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
+#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
+#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
+#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
+#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
+#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
+#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
+#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
+#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
+#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
+#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
+#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
+#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
+#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
+#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
+#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
+#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
+#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
+#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
+#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
+#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
+#define R200_EMIT_VAP_CTL 32 /* vap/1 */
+#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
+#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
+#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
+#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
+#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
+#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
+#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
+#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
+#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
+#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
+#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
+#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
+#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
+#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
+#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
+#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
+#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
+#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
+#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
+#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
+#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
+#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
+#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
+#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
+#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
+#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
+#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
+#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
+#define R200_EMIT_PP_CUBIC_FACES_0 61
+#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
+#define R200_EMIT_PP_CUBIC_FACES_1 63
+#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
+#define R200_EMIT_PP_CUBIC_FACES_2 65
+#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
+#define R200_EMIT_PP_CUBIC_FACES_3 67
+#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
+#define R200_EMIT_PP_CUBIC_FACES_4 69
+#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
+#define R200_EMIT_PP_CUBIC_FACES_5 71
+#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
+#define RADEON_EMIT_PP_TEX_SIZE_0 73
+#define RADEON_EMIT_PP_TEX_SIZE_1 74
+#define RADEON_EMIT_PP_TEX_SIZE_2 75
+#define R200_EMIT_RB3D_BLENDCOLOR 76
+#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
+#define RADEON_EMIT_PP_CUBIC_FACES_0 78
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
+#define RADEON_EMIT_PP_CUBIC_FACES_1 80
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
+#define RADEON_EMIT_PP_CUBIC_FACES_2 82
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
+#define R200_EMIT_PP_TRI_PERF_CNTL 84
+#define R200_EMIT_PP_AFS_0 85
+#define R200_EMIT_PP_AFS_1 86
+#define R200_EMIT_ATF_TFACTOR 87
+#define R200_EMIT_PP_TXCTLALL_0 88
+#define R200_EMIT_PP_TXCTLALL_1 89
+#define R200_EMIT_PP_TXCTLALL_2 90
+#define R200_EMIT_PP_TXCTLALL_3 91
+#define R200_EMIT_PP_TXCTLALL_4 92
+#define R200_EMIT_PP_TXCTLALL_5 93
+#define R200_EMIT_VAP_PVS_CNTL 94
+#define RADEON_MAX_STATE_PACKETS 95
+
+/* Commands understood by cmd_buffer ioctl. More can be added but
+ * obviously these can't be removed or changed:
+ */
+#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
+#define RADEON_CMD_SCALARS 2 /* emit scalar data */
+#define RADEON_CMD_VECTORS 3 /* emit vector data */
+#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
+#define RADEON_CMD_PACKET3 5 /* emit hw packet */
+#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
+#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
+#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
+ * doesn't make the cpu wait, just
+ * the graphics hardware */
+#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
+
+typedef union {
+ int i;
+ struct {
+ unsigned char cmd_type, pad0, pad1, pad2;
+ } header;
+ struct {
+ unsigned char cmd_type, packet_id, pad0, pad1;
+ } packet;
+ struct {
+ unsigned char cmd_type, offset, stride, count;
+ } scalars;
+ struct {
+ unsigned char cmd_type, offset, stride, count;
+ } vectors;
+ struct {
+ unsigned char cmd_type, addr_lo, addr_hi, count;
+ } veclinear;
+ struct {
+ unsigned char cmd_type, buf_idx, pad0, pad1;
+ } dma;
+ struct {
+ unsigned char cmd_type, flags, pad0, pad1;
+ } wait;
+} drm_radeon_cmd_header_t;
+
+#define RADEON_WAIT_2D 0x1
+#define RADEON_WAIT_3D 0x2
+
+/* Allowed parameters for R300_CMD_PACKET3
+ */
+#define R300_CMD_PACKET3_CLEAR 0
+#define R300_CMD_PACKET3_RAW 1
+
+/* Commands understood by cmd_buffer ioctl for R300.
+ * The interface has not been stabilized, so some of these may be removed
+ * and eventually reordered before stabilization.
+ */
+#define R300_CMD_PACKET0 1
+#define R300_CMD_VPU 2 /* emit vertex program upload */
+#define R300_CMD_PACKET3 3 /* emit a packet3 */
+#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
+#define R300_CMD_CP_DELAY 5
+#define R300_CMD_DMA_DISCARD 6
+#define R300_CMD_WAIT 7
+# define R300_WAIT_2D 0x1
+# define R300_WAIT_3D 0x2
+/* these two defines are DOING IT WRONG - however
+ * we have userspace which relies on using these.
+ * The wait interface is backwards compat new
+ * code should use the NEW_WAIT defines below
+ * THESE ARE NOT BIT FIELDS
+ */
+# define R300_WAIT_2D_CLEAN 0x3
+# define R300_WAIT_3D_CLEAN 0x4
+
+# define R300_NEW_WAIT_2D_3D 0x3
+# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
+# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
+# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
+
+#define R300_CMD_SCRATCH 8
+#define R300_CMD_R500FP 9
+
+typedef union {
+ unsigned int u;
+ struct {
+ unsigned char cmd_type, pad0, pad1, pad2;
+ } header;
+ struct {
+ unsigned char cmd_type, count, reglo, reghi;
+ } packet0;
+ struct {
+ unsigned char cmd_type, count, adrlo, adrhi;
+ } vpu;
+ struct {
+ unsigned char cmd_type, packet, pad0, pad1;
+ } packet3;
+ struct {
+ unsigned char cmd_type, packet;
+ unsigned short count; /* amount of packet2 to emit */
+ } delay;
+ struct {
+ unsigned char cmd_type, buf_idx, pad0, pad1;
+ } dma;
+ struct {
+ unsigned char cmd_type, flags, pad0, pad1;
+ } wait;
+ struct {
+ unsigned char cmd_type, reg, n_bufs, flags;
+ } scratch;
+ struct {
+ unsigned char cmd_type, count, adrlo, adrhi_flags;
+ } r500fp;
+} drm_r300_cmd_header_t;
+
+#define RADEON_FRONT 0x1
+#define RADEON_BACK 0x2
+#define RADEON_DEPTH 0x4
+#define RADEON_STENCIL 0x8
+#define RADEON_CLEAR_FASTZ 0x80000000
+#define RADEON_USE_HIERZ 0x40000000
+#define RADEON_USE_COMP_ZBUF 0x20000000
+
+#define R500FP_CONSTANT_TYPE (1 << 1)
+#define R500FP_CONSTANT_CLAMP (1 << 2)
+
+/* Primitive types
+ */
+#define RADEON_POINTS 0x1
+#define RADEON_LINES 0x2
+#define RADEON_LINE_STRIP 0x3
+#define RADEON_TRIANGLES 0x4
+#define RADEON_TRIANGLE_FAN 0x5
+#define RADEON_TRIANGLE_STRIP 0x6
+
+/* Vertex/indirect buffer size
+ */
+#define RADEON_BUFFER_SIZE 65536
+
+/* Byte offsets for indirect buffer data
+ */
+#define RADEON_INDEX_PRIM_OFFSET 20
+
+#define RADEON_SCRATCH_REG_OFFSET 32
+#define R600_SCRATCH_REG_OFFSET 256
+
+#define RADEON_NR_SAREA_CLIPRECTS 12
+
+/* There are 2 heaps (local/GART). Each region within a heap is a
+ * minimum of 64k, and there are at most 64 of them per heap.
+ */
+#define RADEON_LOCAL_TEX_HEAP 0
+#define RADEON_GART_TEX_HEAP 1
+#define RADEON_NR_TEX_HEAPS 2
+#define RADEON_NR_TEX_REGIONS 64
+#define RADEON_LOG_TEX_GRANULARITY 16
+
+#define RADEON_MAX_TEXTURE_LEVELS 12
+#define RADEON_MAX_TEXTURE_UNITS 3
+
+#define RADEON_MAX_SURFACES 8
+
+/* Blits have strict offset rules. All blit offset must be aligned on
+ * a 1K-byte boundary.
+ */
+#define RADEON_OFFSET_SHIFT 10
+#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
+#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
+
+#endif /* __RADEON_SAREA_DEFINES__ */
+
+typedef struct {
+ unsigned int red;
+ unsigned int green;
+ unsigned int blue;
+ unsigned int alpha;
+} radeon_color_regs_t;
+
+typedef struct {
+ /* Context state */
+ unsigned int pp_misc; /* 0x1c14 */
+ unsigned int pp_fog_color;
+ unsigned int re_solid_color;
+ unsigned int rb3d_blendcntl;
+ unsigned int rb3d_depthoffset;
+ unsigned int rb3d_depthpitch;
+ unsigned int rb3d_zstencilcntl;
+
+ unsigned int pp_cntl; /* 0x1c38 */
+ unsigned int rb3d_cntl;
+ unsigned int rb3d_coloroffset;
+ unsigned int re_width_height;
+ unsigned int rb3d_colorpitch;
+ unsigned int se_cntl;
+
+ /* Vertex format state */
+ unsigned int se_coord_fmt; /* 0x1c50 */
+
+ /* Line state */
+ unsigned int re_line_pattern; /* 0x1cd0 */
+ unsigned int re_line_state;
+
+ unsigned int se_line_width; /* 0x1db8 */
+
+ /* Bumpmap state */
+ unsigned int pp_lum_matrix; /* 0x1d00 */
+
+ unsigned int pp_rot_matrix_0; /* 0x1d58 */
+ unsigned int pp_rot_matrix_1;
+
+ /* Mask state */
+ unsigned int rb3d_stencilrefmask; /* 0x1d7c */
+ unsigned int rb3d_ropcntl;
+ unsigned int rb3d_planemask;
+
+ /* Viewport state */
+ unsigned int se_vport_xscale; /* 0x1d98 */
+ unsigned int se_vport_xoffset;
+ unsigned int se_vport_yscale;
+ unsigned int se_vport_yoffset;
+ unsigned int se_vport_zscale;
+ unsigned int se_vport_zoffset;
+
+ /* Setup state */
+ unsigned int se_cntl_status; /* 0x2140 */
+
+ /* Misc state */
+ unsigned int re_top_left; /* 0x26c0 */
+ unsigned int re_misc;
+} drm_radeon_context_regs_t;
+
+typedef struct {
+ /* Zbias state */
+ unsigned int se_zbias_factor; /* 0x1dac */
+ unsigned int se_zbias_constant;
+} drm_radeon_context2_regs_t;
+
+/* Setup registers for each texture unit
+ */
+typedef struct {
+ unsigned int pp_txfilter;
+ unsigned int pp_txformat;
+ unsigned int pp_txoffset;
+ unsigned int pp_txcblend;
+ unsigned int pp_txablend;
+ unsigned int pp_tfactor;
+ unsigned int pp_border_color;
+} drm_radeon_texture_regs_t;
+
+typedef struct {
+ unsigned int start;
+ unsigned int finish;
+ unsigned int prim:8;
+ unsigned int stateidx:8;
+ unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
+ unsigned int vc_format; /* vertex format */
+} drm_radeon_prim_t;
+
+typedef struct {
+ drm_radeon_context_regs_t context;
+ drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
+ drm_radeon_context2_regs_t context2;
+ unsigned int dirty;
+} drm_radeon_state_t;
+
+typedef struct {
+ /* The channel for communication of state information to the
+ * kernel on firing a vertex buffer with either of the
+ * obsoleted vertex/index ioctls.
+ */
+ drm_radeon_context_regs_t context_state;
+ drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
+ unsigned int dirty;
+ unsigned int vertsize;
+ unsigned int vc_format;
+
+ /* The current cliprects, or a subset thereof.
+ */
+ struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
+ unsigned int nbox;
+
+ /* Counters for client-side throttling of rendering clients.
+ */
+ unsigned int last_frame;
+ unsigned int last_dispatch;
+ unsigned int last_clear;
+
+ struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
+ 1];
+ unsigned int tex_age[RADEON_NR_TEX_HEAPS];
+ int ctx_owner;
+ int pfState; /* number of 3d windows (0,1,2ormore) */
+ int pfCurrentPage; /* which buffer is being displayed? */
+ int crtc2_base; /* CRTC2 frame offset */
+ int tiling_enabled; /* set by drm, read by 2d + 3d clients */
+} drm_radeon_sarea_t;
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the Xserver file (xf86drmRadeon.h)
+ *
+ * KW: actually it's illegal to change any of this (backwards compatibility).
+ */
+
+/* Radeon specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_RADEON_CP_INIT 0x00
+#define DRM_RADEON_CP_START 0x01
+#define DRM_RADEON_CP_STOP 0x02
+#define DRM_RADEON_CP_RESET 0x03
+#define DRM_RADEON_CP_IDLE 0x04
+#define DRM_RADEON_RESET 0x05
+#define DRM_RADEON_FULLSCREEN 0x06
+#define DRM_RADEON_SWAP 0x07
+#define DRM_RADEON_CLEAR 0x08
+#define DRM_RADEON_VERTEX 0x09
+#define DRM_RADEON_INDICES 0x0A
+#define DRM_RADEON_NOT_USED
+#define DRM_RADEON_STIPPLE 0x0C
+#define DRM_RADEON_INDIRECT 0x0D
+#define DRM_RADEON_TEXTURE 0x0E
+#define DRM_RADEON_VERTEX2 0x0F
+#define DRM_RADEON_CMDBUF 0x10
+#define DRM_RADEON_GETPARAM 0x11
+#define DRM_RADEON_FLIP 0x12
+#define DRM_RADEON_ALLOC 0x13
+#define DRM_RADEON_FREE 0x14
+#define DRM_RADEON_INIT_HEAP 0x15
+#define DRM_RADEON_IRQ_EMIT 0x16
+#define DRM_RADEON_IRQ_WAIT 0x17
+#define DRM_RADEON_CP_RESUME 0x18
+#define DRM_RADEON_SETPARAM 0x19
+#define DRM_RADEON_SURF_ALLOC 0x1a
+#define DRM_RADEON_SURF_FREE 0x1b
+
+#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
+#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
+#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
+#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
+#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
+#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
+#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
+#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
+#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
+#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
+#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
+#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
+#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
+#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
+#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
+#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
+#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
+#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
+#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
+#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
+#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
+
+typedef struct drm_radeon_init {
+ enum {
+ RADEON_INIT_CP = 0x01,
+ RADEON_CLEANUP_CP = 0x02,
+ RADEON_INIT_R200_CP = 0x03,
+ RADEON_INIT_R300_CP = 0x04,
+ RADEON_INIT_R600_CP = 0x05,
+ } func;
+ unsigned long sarea_priv_offset;
+ int is_pci; /* for overriding only */
+ int cp_mode;
+ int gart_size;
+ int ring_size;
+ int usec_timeout;
+
+ unsigned int fb_bpp;
+ unsigned int front_offset, front_pitch;
+ unsigned int back_offset, back_pitch;
+ unsigned int depth_bpp;
+ unsigned int depth_offset, depth_pitch;
+
+ unsigned long fb_offset DEPRECATED; /* deprecated, driver asks hardware */
+ unsigned long mmio_offset DEPRECATED; /* deprecated, driver asks hardware */
+ unsigned long ring_offset;
+ unsigned long ring_rptr_offset;
+ unsigned long buffers_offset;
+ unsigned long gart_textures_offset;
+} drm_radeon_init_t;
+
+typedef struct drm_radeon_cp_stop {
+ int flush;
+ int idle;
+} drm_radeon_cp_stop_t;
+
+typedef struct drm_radeon_fullscreen {
+ enum {
+ RADEON_INIT_FULLSCREEN = 0x01,
+ RADEON_CLEANUP_FULLSCREEN = 0x02
+ } func;
+} drm_radeon_fullscreen_t;
+
+#define CLEAR_X1 0
+#define CLEAR_Y1 1
+#define CLEAR_X2 2
+#define CLEAR_Y2 3
+#define CLEAR_DEPTH 4
+
+typedef union drm_radeon_clear_rect {
+ float f[5];
+ unsigned int ui[5];
+} drm_radeon_clear_rect_t;
+
+typedef struct drm_radeon_clear {
+ unsigned int flags;
+ unsigned int clear_color;
+ unsigned int clear_depth;
+ unsigned int color_mask;
+ unsigned int depth_mask; /* misnamed field: should be stencil */
+ drm_radeon_clear_rect_t __user *depth_boxes;
+} drm_radeon_clear_t;
+
+typedef struct drm_radeon_vertex {
+ int prim;
+ int idx; /* Index of vertex buffer */
+ int count; /* Number of vertices in buffer */
+ int discard; /* Client finished with buffer? */
+} drm_radeon_vertex_t;
+
+typedef struct drm_radeon_indices {
+ int prim;
+ int idx;
+ int start;
+ int end;
+ int discard; /* Client finished with buffer? */
+} drm_radeon_indices_t;
+
+/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
+ * - allows multiple primitives and state changes in a single ioctl
+ * - supports driver change to emit native primitives
+ */
+typedef struct drm_radeon_vertex2 {
+ int idx; /* Index of vertex buffer */
+ int discard; /* Client finished with buffer? */
+ int nr_states;
+ drm_radeon_state_t __user *state;
+ int nr_prims;
+ drm_radeon_prim_t __user *prim;
+} drm_radeon_vertex2_t;
+
+/* v1.3 - obsoletes drm_radeon_vertex2
+ * - allows arbitarily large cliprect list
+ * - allows updating of tcl packet, vector and scalar state
+ * - allows memory-efficient description of state updates
+ * - allows state to be emitted without a primitive
+ * (for clears, ctx switches)
+ * - allows more than one dma buffer to be referenced per ioctl
+ * - supports tcl driver
+ * - may be extended in future versions with new cmd types, packets
+ */
+typedef struct drm_radeon_cmd_buffer {
+ int bufsz;
+ char __user *buf;
+ int nbox;
+ struct drm_clip_rect __user *boxes;
+} drm_radeon_cmd_buffer_t;
+
+typedef struct drm_radeon_tex_image {
+ unsigned int x, y; /* Blit coordinates */
+ unsigned int width, height;
+ const void __user *data;
+} drm_radeon_tex_image_t;
+
+typedef struct drm_radeon_texture {
+ unsigned int offset;
+ int pitch;
+ int format;
+ int width; /* Texture image coordinates */
+ int height;
+ drm_radeon_tex_image_t __user *image;
+} drm_radeon_texture_t;
+
+typedef struct drm_radeon_stipple {
+ unsigned int __user *mask;
+} drm_radeon_stipple_t;
+
+typedef struct drm_radeon_indirect {
+ int idx;
+ int start;
+ int end;
+ int discard;
+} drm_radeon_indirect_t;
+
+#define RADEON_INDIRECT_DISCARD (1 << 0)
+#define RADEON_INDIRECT_NOFLUSH (1 << 1)
+
+/* enum for card type parameters */
+#define RADEON_CARD_PCI 0
+#define RADEON_CARD_AGP 1
+#define RADEON_CARD_PCIE 2
+
+/* 1.3: An ioctl to get parameters that aren't available to the 3d
+ * client any other way.
+ */
+#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
+#define RADEON_PARAM_LAST_FRAME 2
+#define RADEON_PARAM_LAST_DISPATCH 3
+#define RADEON_PARAM_LAST_CLEAR 4
+/* Added with DRM version 1.6. */
+#define RADEON_PARAM_IRQ_NR 5
+#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
+/* Added with DRM version 1.8. */
+#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
+#define RADEON_PARAM_STATUS_HANDLE 8
+#define RADEON_PARAM_SAREA_HANDLE 9
+#define RADEON_PARAM_GART_TEX_HANDLE 10
+#define RADEON_PARAM_SCRATCH_OFFSET 11
+#define RADEON_PARAM_CARD_TYPE 12
+#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
+#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
+#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
+
+typedef struct drm_radeon_getparam {
+ int param;
+ void __user *value;
+} drm_radeon_getparam_t;
+
+/* 1.6: Set up a memory manager for regions of shared memory:
+ */
+#define RADEON_MEM_REGION_GART 1
+#define RADEON_MEM_REGION_FB 2
+
+typedef struct drm_radeon_mem_alloc {
+ int region;
+ int alignment;
+ int size;
+ int __user *region_offset; /* offset from start of fb or GART */
+} drm_radeon_mem_alloc_t;
+
+typedef struct drm_radeon_mem_free {
+ int region;
+ int region_offset;
+} drm_radeon_mem_free_t;
+
+typedef struct drm_radeon_mem_init_heap {
+ int region;
+ int size;
+ int start;
+} drm_radeon_mem_init_heap_t;
+
+/* 1.6: Userspace can request & wait on irq's:
+ */
+typedef struct drm_radeon_irq_emit {
+ int __user *irq_seq;
+} drm_radeon_irq_emit_t;
+
+typedef struct drm_radeon_irq_wait {
+ int irq_seq;
+} drm_radeon_irq_wait_t;
+
+/* 1.10: Clients tell the DRM where they think the framebuffer is located in
+ * the card's address space, via a new generic ioctl to set parameters
+ */
+
+typedef struct drm_radeon_setparam {
+ unsigned int param;
+ int64_t value;
+} drm_radeon_setparam_t;
+
+#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
+#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
+#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
+
+#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
+#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
+#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
+/* 1.14: Clients can allocate/free a surface
+ */
+typedef struct drm_radeon_surface_alloc {
+ unsigned int address;
+ unsigned int size;
+ unsigned int flags;
+} drm_radeon_surface_alloc_t;
+
+typedef struct drm_radeon_surface_free {
+ unsigned int address;
+} drm_radeon_surface_free_t;
+
+#define DRM_RADEON_VBLANK_CRTC1 1
+#define DRM_RADEON_VBLANK_CRTC2 2
+
+#endif
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index f77235a..8beaed7 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -36,14 +36,11 @@
#include "radeon.h"
#include "radeon_reg.h"
#ifdef XF86DRI
-#include "radeon_dri.h"
+#include "radeon_drm.h"
#endif
#include "radeon_macros.h"
#include "radeon_probe.h"
#include "radeon_version.h"
-#ifdef XF86DRI
-#include "radeon_sarea.h"
-#endif
#include "xf86.h"
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 2be9a8d..62224d0 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -403,7 +403,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
uint32_t scratch_pitch_offset = scratch_pitch << 16
| (info->gartLocation + info->dri->bufStart
+ scratch->idx * scratch->total) >> 10;
- drmRadeonIndirect indirect;
+ drm_radeon_indirect_t indirect;
ACCEL_PREAMBLE();
RADEON_SWITCH_TO_2D();
@@ -474,7 +474,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
indirect.discard = 1;
drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
- &indirect, sizeof(drmRadeonIndirect));
+ &indirect, sizeof(drm_radeon_indirect_t));
info->accel_state->exaMarkerSynced = info->accel_state->exaSyncMarker;
diff --git a/src/radeon_sarea.h b/src/radeon_sarea.h
deleted file mode 100644
index 80333a4..0000000
--- a/src/radeon_sarea.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Gareth Hughes <gareth at valinux.com>
- *
- */
-
-#ifndef _RADEON_SAREA_H_
-#define _RADEON_SAREA_H_
-
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the kernel file (radeon_drm.h)
- */
-#ifndef __RADEON_SAREA_DEFINES__
-#define __RADEON_SAREA_DEFINES__
-
-/* What needs to be changed for the current vertex buffer? */
-#define RADEON_UPLOAD_CONTEXT 0x00000001
-#define RADEON_UPLOAD_VERTFMT 0x00000002
-#define RADEON_UPLOAD_LINE 0x00000004
-#define RADEON_UPLOAD_BUMPMAP 0x00000008
-#define RADEON_UPLOAD_MASKS 0x00000010
-#define RADEON_UPLOAD_VIEWPORT 0x00000020
-#define RADEON_UPLOAD_SETUP 0x00000040
-#define RADEON_UPLOAD_TCL 0x00000080
-#define RADEON_UPLOAD_MISC 0x00000100
-#define RADEON_UPLOAD_TEX0 0x00000200
-#define RADEON_UPLOAD_TEX1 0x00000400
-#define RADEON_UPLOAD_TEX2 0x00000800
-#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
-#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
-#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
-#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
-#define RADEON_REQUIRE_QUIESCENCE 0x00010000
-#define RADEON_UPLOAD_ZBIAS 0x00020000
-#define RADEON_UPLOAD_ALL 0x0002ffff
-#define RADEON_UPLOAD_CONTEXT_ALL 0x000201ff
-
-#define RADEON_FRONT 0x1
-#define RADEON_BACK 0x2
-#define RADEON_DEPTH 0x4
-#define RADEON_STENCIL 0x8
-
-/* Primitive types */
-#define RADEON_POINTS 0x1
-#define RADEON_LINES 0x2
-#define RADEON_LINE_STRIP 0x3
-#define RADEON_TRIANGLES 0x4
-#define RADEON_TRIANGLE_FAN 0x5
-#define RADEON_TRIANGLE_STRIP 0x6
-#define RADEON_3VTX_POINTS 0x9
-#define RADEON_3VTX_LINES 0xa
-
-/* Vertex/indirect buffer size */
-#define RADEON_BUFFER_SIZE 65536
-
-/* Byte offsets for indirect buffer data */
-#define RADEON_INDEX_PRIM_OFFSET 20
-#define RADEON_HOSTDATA_BLIT_OFFSET 32
-
-#define RADEON_SCRATCH_REG_OFFSET 32
-
-/* Keep these small for testing */
-#define RADEON_NR_SAREA_CLIPRECTS 12
-
-/* There are 2 heaps (local/GART). Each region within a heap is a
- * minimum of 64k, and there are at most 64 of them per heap.
- */
-#define RADEON_CARD_HEAP 0
-#define RADEON_GART_HEAP 1
-#define RADEON_NR_TEX_HEAPS 2
-#define RADEON_NR_TEX_REGIONS 64
-#define RADEON_LOG_TEX_GRANULARITY 16
-
-#define RADEON_MAX_TEXTURE_LEVELS 12
-#define RADEON_MAX_TEXTURE_UNITS 3
-
-/* Blits have strict offset rules. All blit offset must be aligned on
- * a 1K-byte boundary.
- */
-#define RADEON_OFFSET_SHIFT 10
-#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
-#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
-
-#endif /* __RADEON_SAREA_DEFINES__ */
-
-typedef struct {
- unsigned int red;
- unsigned int green;
- unsigned int blue;
- unsigned int alpha;
-} radeon_color_regs_t;
-
-typedef struct {
- /* Context state */
- unsigned int pp_misc;
- unsigned int pp_fog_color;
- unsigned int re_solid_color;
- unsigned int rb3d_blendcntl;
- unsigned int rb3d_depthoffset;
- unsigned int rb3d_depthpitch;
- unsigned int rb3d_zstencilcntl;
-
- unsigned int pp_cntl;
- unsigned int rb3d_cntl;
- unsigned int rb3d_coloroffset;
- unsigned int re_width_height;
- unsigned int rb3d_colorpitch;
- unsigned int se_cntl;
-
- /* Vertex format state */
- unsigned int se_coord_fmt;
-
- /* Line state */
- unsigned int re_line_pattern;
- unsigned int re_line_state;
-
- unsigned int se_line_width;
-
- /* Bumpmap state */
- unsigned int pp_lum_matrix;
-
- unsigned int pp_rot_matrix_0;
- unsigned int pp_rot_matrix_1;
-
- /* Mask state */
- unsigned int rb3d_stencilrefmask;
- unsigned int rb3d_ropcntl;
- unsigned int rb3d_planemask;
-
- /* Viewport state */
- unsigned int se_vport_xscale;
- unsigned int se_vport_xoffset;
- unsigned int se_vport_yscale;
- unsigned int se_vport_yoffset;
- unsigned int se_vport_zscale;
- unsigned int se_vport_zoffset;
-
- /* Setup state */
- unsigned int se_cntl_status;
-
- /* Misc state */
- unsigned int re_top_left;
- unsigned int re_misc;
-} radeon_context_regs_t;
-
-/* Setup registers for each texture unit */
-typedef struct {
- unsigned int pp_txfilter;
- unsigned int pp_txformat;
- unsigned int pp_txoffset;
- unsigned int pp_txcblend;
- unsigned int pp_txablend;
- unsigned int pp_tfactor;
- unsigned int pp_border_color;
-} radeon_texture_regs_t;
-
-typedef struct {
- /* The channel for communication of state information to the kernel
- * on firing a vertex buffer.
- */
- radeon_context_regs_t ContextState;
- radeon_texture_regs_t TexState[RADEON_MAX_TEXTURE_UNITS];
- unsigned int dirty;
- unsigned int vertsize;
- unsigned int vc_format;
-
- /* The current cliprects, or a subset thereof */
- drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
- unsigned int nbox;
-
- /* Counters for throttling of rendering clients */
- unsigned int last_frame;
- unsigned int last_dispatch;
- unsigned int last_clear;
-
- /* Maintain an LRU of contiguous regions of texture space. If you
- * think you own a region of texture memory, and it has an age
- * different to the one you set, then you are mistaken and it has
- * been stolen by another client. If global texAge hasn't changed,
- * there is no need to walk the list.
- *
- * These regions can be used as a proxy for the fine-grained texture
- * information of other clients - by maintaining them in the same
- * lru which is used to age their own textures, clients have an
- * approximate lru for the whole of global texture space, and can
- * make informed decisions as to which areas to kick out. There is
- * no need to choose whether to kick out your own texture or someone
- * else's - simply eject them all in LRU order.
- */
- /* Last elt is sentinal */
- drmTextureRegion texList[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
- /* last time texture was uploaded */
- unsigned int texAge[RADEON_NR_TEX_HEAPS];
-
- int ctxOwner; /* last context to upload state */
- int pfAllowPageFlip; /* set by the 2d driver, read by the client */
- int pfCurrentPage; /* set by kernel, read by others */
- int crtc2_base; /* for pageflipping with CloneMode */
- int tiling_enabled; /* set by drm, read by 2d + 3d clients */
- } RADEONSAREAPriv, *RADEONSAREAPrivPtr;
-
-#endif
commit a6561f2ec673b38907f7181235386f32e60c32ba
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Jul 10 22:31:13 2008 -0400
Move DRI to a separate struct
based on Matthias' similar work in rhd
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 8995679..14e4259 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -631,7 +631,7 @@ radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post)
modeset.crtc = radeon_crtc->crtc_id;
modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET;
- ioctl(info->drmFD, DRM_IOCTL_MODESET_CTL, &modeset);
+ ioctl(info->dri->drmFD, DRM_IOCTL_MODESET_CTL, &modeset);
#endif
}
@@ -761,7 +761,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
save->crtc_offset = pScrn->fbOffset;
#ifdef XF86DRI
- if (info->allowPageFlip)
+ if (info->dri && info->dri->allowPageFlip)
save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
else
#endif
@@ -854,7 +854,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
pSAREA->frame.height = pScrn->frameY1 - y + 1;
if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
+ Base += info->dri->backOffset - info->dri->frontOffset;
}
}
#endif
@@ -981,7 +981,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
*/
save->crtc2_offset = pScrn->fbOffset;
#ifdef XF86DRI
- if (info->allowPageFlip)
+ if (info->dri && info->dri->allowPageFlip)
save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
else
#endif
@@ -1068,7 +1068,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
pSAREAPriv->crtc2_base = Base;
if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
+ Base += info->dri->backOffset - info->dri->frontOffset;
}
}
#endif
@@ -1460,7 +1460,7 @@ RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn,
} else {
#ifdef XF86DRI
if (info->directRenderingEnabled)
- sclk_eff = info->sclk - (info->agpMode * 50.0 / 3.0);
+ sclk_eff = info->sclk - (info->dri->agpMode * 50.0 / 3.0);
else
#endif
sclk_eff = info->sclk;
diff --git a/src/radeon.h b/src/radeon.h
index 78733ab..06c7689 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -433,6 +433,118 @@ struct radeon_cp {
int dma_debug_lineno;
};
+
+struct radeon_dri {
+ Bool noBackBuffer;
+
+ Bool newMemoryMap;
+ drmVersionPtr pLibDRMVersion;
+ drmVersionPtr pKernelDRMVersion;
+ DRIInfoPtr pDRIInfo;
+ int drmFD;
+ int numVisualConfigs;
+ __GLXvisualConfig *pVisualConfigs;
+ RADEONConfigPrivPtr pVisualConfigsPriv;
+ Bool (*DRICloseScreen)(int, ScreenPtr);
+
+ drm_handle_t fbHandle;
+
+ drmSize registerSize;
+ drm_handle_t registerHandle;
+
+ drmSize pciSize;
+ drm_handle_t pciMemHandle;
+ unsigned char *PCI; /* Map */
+
+ Bool depthMoves; /* Enable depth moves -- slow! */
+ Bool allowPageFlip; /* Enable 3d page flipping */
+#ifdef DAMAGE
+ DamagePtr pDamage;
+ RegionRec driRegion;
+#endif
+ Bool have3DWindows; /* Are there any 3d clients? */
+
+ int pciAperSize;
+ drmSize gartSize;
+ drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */
+ unsigned long gartOffset;
+ unsigned char *AGP; /* Map */
+ int agpMode;
+
+ uint32_t pciCommand;
+
+ /* CP ring buffer data */
+ unsigned long ringStart; /* Offset into GART space */
+ drm_handle_t ringHandle; /* Handle from drmAddMap */
+ drmSize ringMapSize; /* Size of map */
+ int ringSize; /* Size of ring (in MB) */
+ drmAddress ring; /* Map */
+ int ringSizeLog2QW;
+
+ unsigned long ringReadOffset; /* Offset into GART space */
+ drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */
+ drmSize ringReadMapSize; /* Size of map */
+ drmAddress ringReadPtr; /* Map */
+
+ /* CP vertex/indirect buffer data */
+ unsigned long bufStart; /* Offset into GART space */
+ drm_handle_t bufHandle; /* Handle from drmAddMap */
+ drmSize bufMapSize; /* Size of map */
+ int bufSize; /* Size of buffers (in MB) */
+ drmAddress buf; /* Map */
+ int bufNumBufs; /* Number of buffers */
+ drmBufMapPtr buffers; /* Buffer map */
+
+ /* CP GART Texture data */
+ unsigned long gartTexStart; /* Offset into GART space */
+ drm_handle_t gartTexHandle; /* Handle from drmAddMap */
+ drmSize gartTexMapSize; /* Size of map */
+ int gartTexSize; /* Size of GART tex space (in MB) */
+ drmAddress gartTex; /* Map */
+ int log2GARTTexGran;
+
+ /* DRI screen private data */
+ int fbX;
+ int fbY;
+ int backX;
+ int backY;
+ int depthX;
+ int depthY;
+
+ int frontOffset;
+ int frontPitch;
+ int backOffset;
+ int backPitch;
+ int depthOffset;
+ int depthPitch;
+ int depthBits;
+ int textureOffset;
+ int textureSize;
+ int log2TexGran;
+
+ int pciGartSize;
+ uint32_t pciGartOffset;
+ void *pciGartBackup;
+
+ int irq;
+
+#ifdef PER_CONTEXT_SAREA
+ int perctx_sarea_size;
+#endif
+
+#ifdef USE_XAA
+ uint32_t frontPitchOffset;
+ uint32_t backPitchOffset;
+ uint32_t depthPitchOffset;
+
+ /* offscreen memory management */
+ int backLines;
+ FBAreaPtr backArea;
+ int depthTexLines;
+ FBAreaPtr depthTexArea;
+#endif
+
+};
#endif
struct radeon_accel_state {
@@ -578,17 +690,7 @@ typedef struct {
Bool PaletteSavedOnVT; /* Palette saved on last VT switch */
- struct radeon_accel_state *accel_state;
-
-#ifdef USE_EXA
-#ifdef XF86DRI
- Bool accelDFS;
-#endif
-#endif
- Bool accelOn;
xf86CursorInfoPtr cursor;
- Bool allowColorTiling;
- Bool tilingEnabled; /* mirror of sarea->tiling_enabled */
#ifdef ARGB_CURSOR
Bool cursor_argb;
#endif
@@ -607,121 +709,30 @@ typedef struct {
RADEONFBLayout CurrentLayout;
#ifdef XF86DRI
- Bool noBackBuffer;
Bool directRenderingEnabled;
Bool directRenderingInited;
- Bool newMemoryMap;
- drmVersionPtr pLibDRMVersion;
- drmVersionPtr pKernelDRMVersion;
- DRIInfoPtr pDRIInfo;
- int drmFD;
- int numVisualConfigs;
- __GLXvisualConfig *pVisualConfigs;
- RADEONConfigPrivPtr pVisualConfigsPriv;
- Bool (*DRICloseScreen)(int, ScreenPtr);
-
- drm_handle_t fbHandle;
-
- drmSize registerSize;
- drm_handle_t registerHandle;
-
RADEONCardType cardType; /* Current card is a PCI card */
- drmSize pciSize;
- drm_handle_t pciMemHandle;
- unsigned char *PCI; /* Map */
-
- Bool depthMoves; /* Enable depth moves -- slow! */
- Bool allowPageFlip; /* Enable 3d page flipping */
-#ifdef DAMAGE
- DamagePtr pDamage;
- RegionRec driRegion;
-#endif
- Bool have3DWindows; /* Are there any 3d clients? */
-
- int pciAperSize;
- drmSize gartSize;
- drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */
- unsigned long gartOffset;
- unsigned char *AGP; /* Map */
- int agpMode;
-
- uint32_t pciCommand;
-
struct radeon_cp *cp;
-
- /* CP ring buffer data */
- unsigned long ringStart; /* Offset into GART space */
- drm_handle_t ringHandle; /* Handle from drmAddMap */
- drmSize ringMapSize; /* Size of map */
- int ringSize; /* Size of ring (in MB) */
- drmAddress ring; /* Map */
- int ringSizeLog2QW;
-
- unsigned long ringReadOffset; /* Offset into GART space */
- drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */
- drmSize ringReadMapSize; /* Size of map */
- drmAddress ringReadPtr; /* Map */
-
- /* CP vertex/indirect buffer data */
- unsigned long bufStart; /* Offset into GART space */
- drm_handle_t bufHandle; /* Handle from drmAddMap */
- drmSize bufMapSize; /* Size of map */
- int bufSize; /* Size of buffers (in MB) */
- drmAddress buf; /* Map */
- int bufNumBufs; /* Number of buffers */
- drmBufMapPtr buffers; /* Buffer map */
-
- /* CP GART Texture data */
- unsigned long gartTexStart; /* Offset into GART space */
- drm_handle_t gartTexHandle; /* Handle from drmAddMap */
- drmSize gartTexMapSize; /* Size of map */
- int gartTexSize; /* Size of GART tex space (in MB) */
- drmAddress gartTex; /* Map */
- int log2GARTTexGran;
-
- /* DRI screen private data */
- int fbX;
- int fbY;
- int backX;
- int backY;
- int depthX;
- int depthY;
-
- int frontOffset;
- int frontPitch;
- int backOffset;
- int backPitch;
- int depthOffset;
- int depthPitch;
- int depthBits;
- int textureOffset;
- int textureSize;
- int log2TexGran;
-
- int pciGartSize;
- uint32_t pciGartOffset;
- void *pciGartBackup;
-#ifdef USE_XAA
- uint32_t frontPitchOffset;
- uint32_t backPitchOffset;
- uint32_t depthPitchOffset;
-
- /* offscreen memory management */
- int backLines;
- FBAreaPtr backArea;
- int depthTexLines;
- FBAreaPtr depthTexArea;
+ struct radeon_dri *dri;
+#ifdef USE_EXA
+ Bool accelDFS;
#endif
-
- int irq;
-
Bool DMAForXv;
+#endif /* XF86DRI */
-#ifdef PER_CONTEXT_SAREA
- int perctx_sarea_size;
+ /* accel */
+ Bool RenderAccel; /* Render */
+ Bool allowColorTiling;
+ Bool tilingEnabled; /* mirror of sarea->tiling_enabled */
+ struct radeon_accel_state *accel_state;
+ Bool accelOn;
+ Bool useEXA;
+#ifdef USE_EXA
+ XF86ModReqInfo exaReq;
+#endif
+#ifdef USE_XAA
+ XF86ModReqInfo xaaReq;
#endif
-
-#endif /* XF86DRI */
/* XVideo */
XF86VideoAdaptorPtr adaptor;
@@ -751,21 +762,10 @@ typedef struct {
int overlay_scaler_buffer_width;
int ecp_div;
- /* Render */
- Bool RenderAccel;
-
/* general */
Bool showCache;
OptionInfoPtr Options;
- Bool useEXA;
-#ifdef USE_EXA
- XF86ModReqInfo exaReq;
-#endif
-#ifdef USE_XAA
- XF86ModReqInfo xaaReq;
-#endif
-
DisplayModePtr currentMode, savedCurrentMode;
/* special handlings for DELL triple-head server */
@@ -1060,7 +1060,7 @@ extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
#define RADEONCP_START(pScrn, info) \
do { \
- int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_START); \
+ int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_START); \
if (_ret) { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
"%s: CP start %d\n", __FUNCTION__, _ret); \
@@ -1095,7 +1095,7 @@ do { \
#define RADEONCP_RESET(pScrn, info) \
do { \
- int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESET); \
+ int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESET); \
if (_ret) { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
"%s: CP reset %d\n", __FUNCTION__, _ret); \
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 132a2f4..79ebf84 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -380,7 +380,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
np.param = RADEON_PARAM_NUM_GB_PIPES;
np.value = &num_pipes;
- if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &np,
+ if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &np,
sizeof(np)) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Failed to determine num pipes from DRM, falling back to "
@@ -519,7 +519,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
stop.flush = 1;
stop.idle = 1;
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
+ ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP, &stop,
sizeof(drmRadeonCPStop));
if (ret == 0) {
@@ -532,7 +532,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
i = 0;
do {
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
+ ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP, &stop,
sizeof(drmRadeonCPStop));
} while (ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY);
@@ -544,7 +544,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
stop.idle = 0;
- if (drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP,
+ if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP,
&stop, sizeof(drmRadeonCPStop))) {
return -errno;
} else {
@@ -587,7 +587,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn)
while (1) {
do {
- ret = drmDMA(info->drmFD, &dma);
+ ret = drmDMA(info->dri->drmFD, &dma);
if (ret && ret != -EBUSY) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"%s: CP GetBuffer %d\n", __FUNCTION__, ret);
@@ -595,7 +595,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn)
} while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT));
if (ret == 0) {
- buf = &info->buffers->list[indx];
+ buf = &info->dri->buffers->list[indx];
buf->used = 0;
if (RADEON_VERBOSE) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -637,7 +637,7 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
indirect.end = buffer->used;
indirect.discard = discard;
- drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
+ drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
&indirect, sizeof(drmRadeonIndirect));
if (discard) {
@@ -676,7 +676,7 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn)
indirect.end = buffer->used;
indirect.discard = 1;
- drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
+ drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
&indirect, sizeof(drmRadeonIndirect));
}
@@ -992,7 +992,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
int cpp = info->CurrentLayout.pixel_bytes;
- int depthCpp = (info->depthBits - 8) / 4;
+ int depthCpp = (info->dri->depthBits - 8) / 4;
int width_bytes = pScrn->displayWidth * cpp;
int bufferSize;
int depthSize;
@@ -1002,9 +1002,9 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
BoxRec MemBox;
FBAreaPtr fbarea;
- info->frontOffset = 0;
- info->frontPitch = pScrn->displayWidth;
- info->backPitch = pScrn->displayWidth;
+ info->dri->frontOffset = 0;
+ info->dri->frontPitch = pScrn->displayWidth;
+ info->dri->backPitch = pScrn->displayWidth;
/* make sure we use 16 line alignment for tiling (8 might be enough).
* Might need that for non-XF86DRI too?
@@ -1021,18 +1021,18 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
* which is always the case if color tiling is used due to color pitch
* but not necessarily otherwise, and its height a multiple of 16 lines.
*/
- info->depthPitch = (pScrn->displayWidth + 31) & ~31;
- depthSize = ((((pScrn->virtualY + 15) & ~15) * info->depthPitch
+ info->dri->depthPitch = (pScrn->displayWidth + 31) & ~31;
+ depthSize = ((((pScrn->virtualY + 15) & ~15) * info->dri->depthPitch
* depthCpp + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB GART aperture\n", info->gartSize);
+ "Using %d MB GART aperture\n", info->dri->gartSize);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for the ring buffer\n", info->ringSize);
+ "Using %d MB for the ring buffer\n", info->dri->ringSize);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for vertex/indirect buffers\n", info->bufSize);
+ "Using %d MB for vertex/indirect buffers\n", info->dri->bufSize);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for GART textures\n", info->gartTexSize);
+ "Using %d MB for GART textures\n", info->dri->gartTexSize);
/* Try for front, back, depth, and three framebuffers worth of
* pixmap cache. Should be enough for a fullscreen background
@@ -1042,35 +1042,35 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
* otherwise probably), and never reserve more than 3 offscreen buffers as it's
* probably useless for XAA.
*/
- if (info->textureSize >= 0) {
+ if (info->dri->textureSize >= 0) {
texsizerequest = ((int)info->FbMapSize - 2 * bufferSize - depthSize
- 2 * width_bytes - 16384 - info->FbSecureSize)
/* first divide, then multiply or we'll get an overflow (been there...) */
- / 100 * info->textureSize;
+ / 100 * info->dri->textureSize;
}
else {
texsizerequest = (int)info->FbMapSize / 2;
}
- info->textureSize = info->FbMapSize - info->FbSecureSize - 5 * bufferSize - depthSize;
+ info->dri->textureSize = info->FbMapSize - info->FbSecureSize - 5 * bufferSize - depthSize;
/* If that gives us less than the requested memory, let's
* be greedy and grab some more. Sorry, I care more about 3D
* performance than playing nicely, and you'll get around a full
* framebuffer's worth of pixmap cache anyway.
*/
- if (info->textureSize < texsizerequest) {
- info->textureSize = info->FbMapSize - 4 * bufferSize - depthSize;
+ if (info->dri->textureSize < texsizerequest) {
+ info->dri->textureSize = info->FbMapSize - 4 * bufferSize - depthSize;
}
- if (info->textureSize < texsizerequest) {
- info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize;
+ if (info->dri->textureSize < texsizerequest) {
+ info->dri->textureSize = info->FbMapSize - 3 * bufferSize - depthSize;
}
/* If there's still no space for textures, try without pixmap cache, but
* never use the reserved space, the space hw cursor and PCIGART table might
* use.
*/
- if (info->textureSize < 0) {
- info->textureSize = info->FbMapSize - 2 * bufferSize - depthSize
+ if (info->dri->textureSize < 0) {
+ info->dri->textureSize = info->FbMapSize - 2 * bufferSize - depthSize
- 2 * width_bytes - 16384 - info->FbSecureSize;
}
@@ -1079,14 +1079,14 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
*/
/* FIXME: what's this good for? condition is pretty much impossible to meet */
if ((int)info->FbMapSize - 8192*width_bytes - bufferSize - depthSize
- > info->textureSize) {
- info->textureSize =
+ > info->dri->textureSize) {
+ info->dri->textureSize =
info->FbMapSize - 8192*width_bytes - bufferSize - depthSize;
}
/* If backbuffer is disabled, don't allocate memory for it */
- if (info->noBackBuffer) {
- info->textureSize += bufferSize;
+ if (info->dri->noBackBuffer) {
+ info->dri->textureSize += bufferSize;
}
/* RADEON_BUFFER_ALIGN is not sufficient for backbuffer!
@@ -1098,61 +1098,61 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
can't be used (?) due to that log_tex_granularity thing???
Could use different copyscreentoscreen function for the pageflip copies
(which would use different src and dst offsets) to avoid this. */
- if (info->allowColorTiling && !info->noBackBuffer) {
- info->textureSize = info->FbMapSize - ((info->FbMapSize - info->textureSize +
+ if (info->allowColorTiling && !info->dri->noBackBuffer) {
+ info->dri->textureSize = info->FbMapSize - ((info->FbMapSize - info->dri->textureSize +
width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes * 16);
}
- if (info->textureSize > 0) {
- l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS);
+ if (info->dri->textureSize > 0) {
+ l = RADEONMinBits((info->dri->textureSize-1) / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY)
l = RADEON_LOG_TEX_GRANULARITY;
/* Round the texture size up to the nearest whole number of
* texture regions. Again, be greedy about this, don't
* round down.
*/
- info->log2TexGran = l;
- info->textureSize = (info->textureSize >> l) << l;
+ info->dri->log2TexGran = l;
+ info->dri->textureSize = (info->dri->textureSize >> l) << l;
} else {
- info->textureSize = 0;
+ info->dri->textureSize = 0;
}
/* Set a minimum usable local texture heap size. This will fit
* two 256x256x32bpp textures.
*/
- if (info->textureSize < 512 * 1024) {
- info->textureOffset = 0;
- info->textureSize = 0;
+ if (info->dri->textureSize < 512 * 1024) {
+ info->dri->textureOffset = 0;
+ info->dri->textureSize = 0;
}
- if (info->allowColorTiling && !info->noBackBuffer) {
- info->textureOffset = ((info->FbMapSize - info->textureSize) /
- (width_bytes * 16)) * (width_bytes * 16);
+ if (info->allowColorTiling && !info->dri->noBackBuffer) {
+ info->dri->textureOffset = ((info->FbMapSize - info->dri->textureSize) /
+ (width_bytes * 16)) * (width_bytes * 16);
}
else {
/* Reserve space for textures */
- info->textureOffset = ((info->FbMapSize - info->textureSize +
- RADEON_BUFFER_ALIGN) &
- ~(uint32_t)RADEON_BUFFER_ALIGN);
+ info->dri->textureOffset = ((info->FbMapSize - info->dri->textureSize +
+ RADEON_BUFFER_ALIGN) &
+ ~(uint32_t)RADEON_BUFFER_ALIGN);
}
/* Reserve space for the shared depth
* buffer.
*/
- info->depthOffset = ((info->textureOffset - depthSize +
- RADEON_BUFFER_ALIGN) &
- ~(uint32_t)RADEON_BUFFER_ALIGN);
+ info->dri->depthOffset = ((info->dri->textureOffset - depthSize +
+ RADEON_BUFFER_ALIGN) &
+ ~(uint32_t)RADEON_BUFFER_ALIGN);
/* Reserve space for the shared back buffer */
- if (info->noBackBuffer) {
- info->backOffset = info->depthOffset;
+ if (info->dri->noBackBuffer) {
+ info->dri->backOffset = info->dri->depthOffset;
} else {
- info->backOffset = ((info->depthOffset - bufferSize +
- RADEON_BUFFER_ALIGN) &
- ~(uint32_t)RADEON_BUFFER_ALIGN);
+ info->dri->backOffset = ((info->dri->depthOffset - bufferSize +
+ RADEON_BUFFER_ALIGN) &
+ ~(uint32_t)RADEON_BUFFER_ALIGN);
}
- info->backY = info->backOffset / width_bytes;
- info->backX = (info->backOffset - (info->backY * width_bytes)) / cpp;
+ info->dri->backY = info->dri->backOffset / width_bytes;
+ info->dri->backX = (info->dri->backOffset - (info->dri->backY * width_bytes)) / cpp;
scanlines = (info->FbMapSize-info->FbSecureSize) / width_bytes;
if (scanlines > 8191)
@@ -1203,12 +1203,12 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
/* Lines in offscreen area needed for depth buffer and
* textures
*/
- info->depthTexLines = (scanlines
- - info->depthOffset / width_bytes);
- info->backLines = (scanlines
- - info->backOffset / width_bytes
- - info->depthTexLines);
- info->backArea = NULL;
+ info->dri->depthTexLines = (scanlines
+ - info->dri->depthOffset / width_bytes);
+ info->dri->backLines = (scanlines
+ - info->dri->backOffset / width_bytes
+ - info->dri->depthTexLines);
+ info->dri->backArea = NULL;
} else {
xf86DrvMsg(scrnIndex, X_ERROR,
"Unable to determine largest offscreen area "
@@ -1219,30 +1219,30 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
xf86DrvMsg(scrnIndex, X_INFO,
"Will use front buffer at offset 0x%x\n",
- info->frontOffset);
+ info->dri->frontOffset);
xf86DrvMsg(scrnIndex, X_INFO,
"Will use back buffer at offset 0x%x\n",
- info->backOffset);
+ info->dri->backOffset);
xf86DrvMsg(scrnIndex, X_INFO,
"Will use depth buffer at offset 0x%x\n",
- info->depthOffset);
+ info->dri->depthOffset);
if (info->cardType==CARD_PCIE)
xf86DrvMsg(scrnIndex, X_INFO,
"Will use %d kb for PCI GART table at offset 0x%x\n",
- info->pciGartSize/1024, (unsigned)info->pciGartOffset);
+ info->dri->pciGartSize/1024, (unsigned)info->dri->pciGartOffset);
xf86DrvMsg(scrnIndex, X_INFO,
"Will use %d kb for textures at offset 0x%x\n",
- info->textureSize/1024, info->textureOffset);
+ info->dri->textureSize/1024, info->dri->textureOffset);
- info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) |
- ((info->frontOffset + info->fbLocation) >> 10));
+ info->dri->frontPitchOffset = (((info->dri->frontPitch * cpp / 64) << 22) |
+ ((info->dri->frontOffset + info->fbLocation) >> 10));
- info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) |
- ((info->backOffset + info->fbLocation) >> 10));
+ info->dri->backPitchOffset = (((info->dri->backPitch * cpp / 64) << 22) |
+ ((info->dri->backOffset + info->fbLocation) >> 10));
- info->depthPitchOffset = (((info->depthPitch * depthCpp / 64) << 22) |
- ((info->depthOffset + info->fbLocation) >> 10));
+ info->dri->depthPitchOffset = (((info->dri->depthPitch * depthCpp / 64) << 22) |
+ ((info->dri->depthOffset + info->fbLocation) >> 10));
return TRUE;
}
#endif /* XF86DRI */
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index a70a275..dba197e 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -694,7 +694,7 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
for (;;) {
do {
- ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE);
+ ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE);
if (ret && ret != -EBUSY) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"%s: CP idle %d\n", __FUNCTION__, ret);
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 9eb9448..beb63b5 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -492,7 +492,7 @@ radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
return NULL;
}
#ifdef XF86DRI
- rotate_offset = info->frontOffset +
+ rotate_offset = info->dri->frontOffset +
radeon_crtc->rotate_mem_xaa->offset * cpp;
#endif
}
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index c10301b..1baed4b 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -92,7 +92,7 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
RADEONConfigPrivPtr *pRADEONConfigPtrs = 0;
int i, accum, stencil, db, use_db;
- use_db = !info->noBackBuffer ? 1 : 0;
+ use_db = !info->dri->noBackBuffer ? 1 : 0;
switch (info->CurrentLayout.pixel_code) {
case 8: /* 8bpp mode is not support */
@@ -166,7 +166,7 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
pConfigs[i].doubleBuffer = FALSE;
pConfigs[i].stereo = FALSE;
pConfigs[i].bufferSize = 16;
- pConfigs[i].depthSize = info->depthBits;
+ pConfigs[i].depthSize = info->dri->depthBits;
if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil)
: stencil) {
pConfigs[i].stencilSize = 8;
@@ -252,7 +252,7 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
pConfigs[i].doubleBuffer = FALSE;
pConfigs[i].stereo = FALSE;
pConfigs[i].bufferSize = 32;
- pConfigs[i].depthSize = info->depthBits;
+ pConfigs[i].depthSize = info->dri->depthBits;
if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil)
: stencil) {
pConfigs[i].stencilSize = 8;
@@ -280,9 +280,9 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
break;
}
- info->numVisualConfigs = numConfigs;
- info->pVisualConfigs = pConfigs;
- info->pVisualConfigsPriv = pRADEONConfigs;
+ info->dri->numVisualConfigs = numConfigs;
+ info->dri->pVisualConfigs = pConfigs;
+ info->dri->pVisualConfigsPriv = pRADEONConfigs;
GlxSetVisualConfigs(numConfigs, pConfigs, (void**)pRADEONConfigPtrs);
return TRUE;
}
@@ -300,8 +300,8 @@ static Bool RADEONCreateContext(ScreenPtr pScreen, VisualPtr visual,
ctx_info = (RADEONDRIContextPtr)contextStore;
if (!ctx_info) return FALSE;
- if (drmAddMap(info->drmFD, 0,
- info->perctx_sarea_size,
+ if (drmAddMap(info->dri->drmFD, 0,
+ info->dri->perctx_sarea_size,
DRM_SHM,
DRM_REMOVABLE,
&ctx_info->sarea_handle) < 0) {
@@ -311,12 +311,12 @@ static Bool RADEONCreateContext(ScreenPtr pScreen, VisualPtr visual,
return FALSE;
}
- if (drmAddContextPrivateMapping(info->drmFD, hwContext,
+ if (drmAddContextPrivateMapping(info->dri->drmFD, hwContext,
ctx_info->sarea_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[dri] could not associate private sarea to ctx id (%d)\n",
(int)hwContext);
- drmRmMap(info->drmFD, ctx_info->sarea_handle);
+ drmRmMap(info->dri->drmFD, ctx_info->sarea_handle);
return FALSE;
}
@@ -337,7 +337,7 @@ static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
ctx_info = (RADEONDRIContextPtr)contextStore;
if (!ctx_info) return;
- if (drmRmMap(info->drmFD, ctx_info->sarea_handle) < 0) {
+ if (drmRmMap(info->dri->drmFD, ctx_info->sarea_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[dri] could not remove private sarea for ctx id (%d)\n",
(int)hwContext);
@@ -368,17 +368,17 @@ static void RADEONEnterServer(ScreenPtr pScreen)
}
#ifdef DAMAGE
- if (!info->pDamage && info->allowPageFlip) {
+ if (!info->dri->pDamage && info->dri->allowPageFlip) {
PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
- info->pDamage = DamageCreate(NULL, NULL, DamageReportNone, TRUE,
- pScreen, pPix);
+ info->dri->pDamage = DamageCreate(NULL, NULL, DamageReportNone, TRUE,
+ pScreen, pPix);
- if (info->pDamage == NULL) {
+ if (info->dri->pDamage == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"No screen damage record, page flipping disabled\n");
- info->allowPageFlip = 0;
+ info->dri->allowPageFlip = 0;
} else {
- DamageRegister(&pPix->drawable, info->pDamage);
+ DamageRegister(&pPix->drawable, info->dri->pDamage);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Damage tracking initialized for page flipping\n");
@@ -401,8 +401,8 @@ static void RADEONLeaveServer(ScreenPtr pScreen)
RING_LOCALS;
#ifdef DAMAGE
- if (info->pDamage) {
- RegionPtr pDamageReg = DamageRegion(info->pDamage);
+ if (info->dri->pDamage) {
+ RegionPtr pDamageReg = DamageRegion(info->dri->pDamage);
int nrects = pDamageReg ? REGION_NUM_RECTS(pDamageReg) : 0;
if (nrects) {
@@ -451,17 +451,17 @@ static void RADEONDRISwapContext(ScreenPtr pScreen, DRISyncType syncType,
/* 16-bit depth buffer functions */
#define WRITE_DEPTH16(_x, _y, d) \
- *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d)
+ *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->dri->frontPitch)) = (d)
#define READ_DEPTH16(d, _x, _y) \
- (d) = *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch))
+ (d) = *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->dri->frontPitch))
/* 32-bit depth buffer (stencil and depth simultaneously) functions */
#define WRITE_DEPTHSTENCIL32(_x, _y, d) \
- *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d)
+ *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->dri->frontPitch)) = (d)
#define READ_DEPTHSTENCIL32(d, _x, _y) \
- (d) = *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch))
+ (d) = *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->dri->frontPitch))
/* Screen to screen copy of data in the depth buffer */
static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn,
@@ -470,7 +470,7 @@ static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn,
int w, int h)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *buf = info->FB + info->depthOffset;
+ unsigned char *buf = info->FB + info->dri->depthOffset;
int xstart, xend, xdir;
int ystart, yend, ydir;
int x, y, d;
@@ -641,7 +641,7 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
}
/* pretty much a hack. */
- info->accel_state->dst_pitch_offset = info->backPitchOffset;
+ info->accel_state->dst_pitch_offset = info->dri->backPitchOffset;
if (info->tilingEnabled)
info->accel_state->dst_pitch_offset |= RADEON_DST_TILE_MACRO;
@@ -669,7 +669,7 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
destx, desty,
w, h);
- if (info->depthMoves) {
+ if (info->dri->depthMoves) {
RADEONScreenToScreenCopyDepth(pScrn,
xa, ya,
destx, desty,
@@ -677,7 +677,7 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
}
}
- info->accel_state->dst_pitch_offset = info->frontPitchOffset;;
+ info->accel_state->dst_pitch_offset = info->dri->frontPitchOffset;;
xfree(pptNew2);
xfree(pboxNew2);
@@ -692,36 +692,36 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info)
{
int s, l;
- info->gartOffset = 0;
+ info->dri->gartOffset = 0;
/* Initialize the CP ring buffer data */
- info->ringStart = info->gartOffset;
- info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size;
- info->ringSizeLog2QW = RADEONMinBits(info->ringSize*1024*1024/8)-1;
+ info->dri->ringStart = info->dri->gartOffset;
+ info->dri->ringMapSize = info->dri->ringSize*1024*1024 + radeon_drm_page_size;
+ info->dri->ringSizeLog2QW = RADEONMinBits(info->dri->ringSize*1024*1024/8)-1;
- info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = radeon_drm_page_size;
+ info->dri->ringReadOffset = info->dri->ringStart + info->dri->ringMapSize;
+ info->dri->ringReadMapSize = radeon_drm_page_size;
/* Reserve space for vertex/indirect buffers */
- info->bufStart = info->ringReadOffset + info->ringReadMapSize;
- info->bufMapSize = info->bufSize*1024*1024;
+ info->dri->bufStart = info->dri->ringReadOffset + info->dri->ringReadMapSize;
+ info->dri->bufMapSize = info->dri->bufSize*1024*1024;
/* Reserve the rest for GART textures */
- info->gartTexStart = info->bufStart + info->bufMapSize;
- s = (info->gartSize*1024*1024 - info->gartTexStart);
+ info->dri->gartTexStart = info->dri->bufStart + info->dri->bufMapSize;
+ s = (info->dri->gartSize*1024*1024 - info->dri->gartTexStart);
l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
- info->gartTexMapSize = (s >> l) << l;
- info->log2GARTTexGran = l;
+ info->dri->gartTexMapSize = (s >> l) << l;
+ info->dri->log2GARTTexGran = l;
}
/* Set AGP transfer mode according to requests and constraints */
static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
{
unsigned char *RADEONMMIO = info->MMIO;
- unsigned long mode = drmAgpGetMode(info->drmFD); /* Default mode */
- unsigned int vendor = drmAgpVendorId(info->drmFD);
- unsigned int device = drmAgpDeviceId(info->drmFD);
+ unsigned long mode = drmAgpGetMode(info->dri->drmFD); /* Default mode */
+ unsigned int vendor = drmAgpVendorId(info->dri->drmFD);
+ unsigned int device = drmAgpDeviceId(info->dri->drmFD);
/* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
pcie-agp rialto bridge chip - use the one from bridge which must match */
uint32_t agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode;
@@ -739,26 +739,26 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
from = X_DEFAULT;
- if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->agpMode)) {
- if ((info->agpMode < (is_v3 ? 4 : 1)) ||
- (info->agpMode > (is_v3 ? 8 : 4)) ||
- (info->agpMode & (info->agpMode - 1))) {
+ if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->dri->agpMode)) {
+ if ((info->dri->agpMode < (is_v3 ? 4 : 1)) ||
+ (info->dri->agpMode > (is_v3 ? 8 : 4)) ||
+ (info->dri->agpMode & (info->dri->agpMode - 1))) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"Illegal AGP Mode: %d (valid values: %s), leaving at "
- "%dx\n", info->agpMode, is_v3 ? "4, 8" : "1, 2, 4",
+ "%dx\n", info->dri->agpMode, is_v3 ? "4, 8" : "1, 2, 4",
defaultMode);
- info->agpMode = defaultMode;
+ info->dri->agpMode = defaultMode;
} else
from = X_CONFIG;
} else
- info->agpMode = defaultMode;
+ info->dri->agpMode = defaultMode;
- xf86DrvMsg(pScreen->myNum, from, "Using AGP %dx\n", info->agpMode);
+ xf86DrvMsg(pScreen->myNum, from, "Using AGP %dx\n", info->dri->agpMode);
mode &= ~RADEON_AGP_MODE_MASK;
if (is_v3) {
/* only set one mode bit for AGPv3 */
- switch (info->agpMode) {
+ switch (info->dri->agpMode) {
case 8: mode |= RADEON_AGPv3_8X_MODE; break;
case 4: default: mode |= RADEON_AGPv3_4X_MODE;
}
@@ -766,7 +766,7 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
* currently these bits are not used in all tested cards.
*/
} else {
- switch (info->agpMode) {
+ switch (info->dri->agpMode) {
case 4: mode |= RADEON_AGP_4X_MODE;
case 2: mode |= RADEON_AGP_2X_MODE;
case 1: default: mode |= RADEON_AGP_1X_MODE;
@@ -800,9 +800,9 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
PCI_DEV_VENDOR_ID(info->PciInfo),
PCI_DEV_DEVICE_ID(info->PciInfo));
- if (drmAgpEnable(info->drmFD, mode) < 0) {
+ if (drmAgpEnable(info->dri->drmFD, mode) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n");
- drmAgpRelease(info->drmFD);
+ drmAgpRelease(info->dri->drmFD);
return FALSE;
}
@@ -829,15 +829,15 @@ static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen)
* agp_base_2 ?
*/
if (info->ChipFamily == CHIP_FAMILY_RV515)
- OUTMC(pScrn, RV515_MC_AGP_BASE, drmAgpBase(info->drmFD));
+ OUTMC(pScrn, RV515_MC_AGP_BASE, drmAgpBase(info->dri->drmFD));
else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
(info->ChipFamily <= CHIP_FAMILY_RV570))
- OUTMC(pScrn, R520_MC_AGP_BASE, drmAgpBase(info->drmFD));
+ OUTMC(pScrn, R520_MC_AGP_BASE, drmAgpBase(info->dri->drmFD));
else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740))
- OUTMC(pScrn, RS690_MC_AGP_BASE, drmAgpBase(info->drmFD));
+ OUTMC(pScrn, RS690_MC_AGP_BASE, drmAgpBase(info->dri->drmFD));
else if (info->ChipFamily < CHIP_FAMILY_RV515)
- OUTREG(RADEON_AGP_BASE, drmAgpBase(info->drmFD));
+ OUTREG(RADEON_AGP_BASE, drmAgpBase(info->dri->drmFD));
}
/* Initialize the AGP state. Request memory for use in AGP space, and
@@ -847,7 +847,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
int ret;
- if (drmAgpAcquire(info->drmFD) < 0) {
+ if (drmAgpAcquire(info->dri->drmFD) < 0) {
xf86DrvMsg(pScreen->myNum, X_WARNING, "[agp] AGP not available\n");
return FALSE;
}
@@ -857,101 +857,101 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
RADEONDRIInitGARTValues(info);
- if ((ret = drmAgpAlloc(info->drmFD, info->gartSize*1024*1024, 0, NULL,
- &info->agpMemHandle)) < 0) {
+ if ((ret = drmAgpAlloc(info->dri->drmFD, info->dri->gartSize*1024*1024, 0, NULL,
+ &info->dri->agpMemHandle)) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Out of memory (%d)\n", ret);
- drmAgpRelease(info->drmFD);
+ drmAgpRelease(info->dri->drmFD);
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] %d kB allocated with handle 0x%08x\n",
- info->gartSize*1024, info->agpMemHandle);
+ info->dri->gartSize*1024, info->dri->agpMemHandle);
- if (drmAgpBind(info->drmFD,
- info->agpMemHandle, info->gartOffset) < 0) {
+ if (drmAgpBind(info->dri->drmFD,
+ info->dri->agpMemHandle, info->dri->gartOffset) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not bind\n");
- drmAgpFree(info->drmFD, info->agpMemHandle);
- drmAgpRelease(info->drmFD);
+ drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle);
+ drmAgpRelease(info->dri->drmFD);
return FALSE;
}
- if (drmAddMap(info->drmFD, info->ringStart, info->ringMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->ringStart, info->dri->ringMapSize,
+ DRM_AGP, DRM_READ_ONLY, &info->dri->ringHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add ring mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] ring handle = 0x%08x\n", info->ringHandle);
+ "[agp] ring handle = 0x%08x\n", info->dri->ringHandle);
- if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize,
- &info->ring) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
+ &info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring mapped at 0x%08lx\n",
- (unsigned long)info->ring);
+ (unsigned long)info->dri->ring);
- if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize,
+ DRM_AGP, DRM_READ_ONLY, &info->dri->ringReadPtrHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add ring read ptr mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] ring read ptr handle = 0x%08x\n",
- info->ringReadPtrHandle);
+ info->dri->ringReadPtrHandle);
- if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
- &info->ringReadPtr) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize,
+ &info->dri->ringReadPtr) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not map ring read ptr\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring read ptr mapped at 0x%08lx\n",
- (unsigned long)info->ringReadPtr);
+ (unsigned long)info->dri->ringReadPtr);
- if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize,
- DRM_AGP, 0, &info->bufHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
+ DRM_AGP, 0, &info->dri->bufHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add vertex/indirect buffers mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] vertex/indirect buffers handle = 0x%08x\n",
- info->bufHandle);
+ info->dri->bufHandle);
- if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize,
- &info->buf) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->bufHandle, info->dri->bufMapSize,
+ &info->dri->buf) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not map vertex/indirect buffers\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Vertex/indirect buffers mapped at 0x%08lx\n",
- (unsigned long)info->buf);
+ (unsigned long)info->dri->buf);
- if (drmAddMap(info->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_AGP, 0, &info->gartTexHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->gartTexStart, info->dri->gartTexMapSize,
+ DRM_AGP, 0, &info->dri->gartTexHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add GART texture map mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] GART texture map handle = 0x%08x\n",
- info->gartTexHandle);
+ info->dri->gartTexHandle);
- if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize,
- &info->gartTex) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->gartTexHandle, info->dri->gartTexMapSize,
+ &info->dri->gartTex) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not map GART texture map\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] GART Texture map mapped at 0x%08lx\n",
- (unsigned long)info->gartTex);
+ (unsigned long)info->dri->gartTex);
RADEONSetAgpBase(info, pScreen);
@@ -966,104 +966,104 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
int ret;
int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
- ret = drmScatterGatherAlloc(info->drmFD, info->gartSize*1024*1024,
- &info->pciMemHandle);
+ ret = drmScatterGatherAlloc(info->dri->drmFD, info->dri->gartSize*1024*1024,
+ &info->dri->pciMemHandle);
if (ret < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Out of memory (%d)\n", ret);
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] %d kB allocated with handle 0x%08x\n",
- info->gartSize*1024, info->pciMemHandle);
+ info->dri->gartSize*1024, info->dri->pciMemHandle);
RADEONDRIInitGARTValues(info);
- if (drmAddMap(info->drmFD, info->ringStart, info->ringMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->ringStart, info->dri->ringMapSize,
+ DRM_SCATTER_GATHER, flags, &info->dri->ringHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not add ring mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] ring handle = 0x%08x\n", info->ringHandle);
+ "[pci] ring handle = 0x%08x\n", info->dri->ringHandle);
- if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize,
- &info->ring) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
+ &info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring mapped at 0x%08lx\n",
- (unsigned long)info->ring);
+ (unsigned long)info->dri->ring);
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->ring);
+ *(unsigned long *)(pointer)info->dri->ring);
- if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize,
+ DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not add ring read ptr mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] ring read ptr handle = 0x%08x\n",
- info->ringReadPtrHandle);
+ info->dri->ringReadPtrHandle);
- if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
- &info->ringReadPtr) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize,
+ &info->dri->ringReadPtr) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map ring read ptr\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring read ptr mapped at 0x%08lx\n",
- (unsigned long)info->ringReadPtr);
+ (unsigned long)info->dri->ringReadPtr);
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring read ptr contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->ringReadPtr);
+ *(unsigned long *)(pointer)info->dri->ringReadPtr);
- if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize,
- DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
+ DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not add vertex/indirect buffers mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] vertex/indirect buffers handle = 0x%08x\n",
- info->bufHandle);
+ info->dri->bufHandle);
- if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize,
- &info->buf) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->bufHandle, info->dri->bufMapSize,
+ &info->dri->buf) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map vertex/indirect buffers\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Vertex/indirect buffers mapped at 0x%08lx\n",
- (unsigned long)info->buf);
+ (unsigned long)info->dri->buf);
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Vertex/indirect buffers contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->buf);
+ *(unsigned long *)(pointer)info->dri->buf);
- if (drmAddMap(info->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->gartTexStart, info->dri->gartTexMapSize,
+ DRM_SCATTER_GATHER, 0, &info->dri->gartTexHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not add GART texture map mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] GART texture map handle = 0x%08x\n",
- info->gartTexHandle);
+ info->dri->gartTexHandle);
- if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize,
- &info->gartTex) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->gartTexHandle, info->dri->gartTexMapSize,
+ &info->dri->gartTex) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map GART texture map\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] GART Texture map mapped at 0x%08lx\n",
- (unsigned long)info->gartTex);
+ (unsigned long)info->dri->gartTex);
return TRUE;
}
@@ -1074,13 +1074,13 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
/* Map registers */
- info->registerSize = info->MMIOSize;
- if (drmAddMap(info->drmFD, info->MMIOAddr, info->registerSize,
- DRM_REGISTERS, DRM_READ_ONLY, &info->registerHandle) < 0) {
+ info->dri->registerSize = info->MMIOSize;
+ if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize,
+ DRM_REGISTERS, DRM_READ_ONLY, &info->dri->registerHandle) < 0) {
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] register handle = 0x%08x\n", info->registerHandle);
+ "[drm] register handle = 0x%08x\n", info->dri->registerHandle);
return TRUE;
}
@@ -1104,28 +1104,28 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
drmInfo.is_pci = (info->cardType!=CARD_AGP);
drmInfo.cp_mode = RADEON_CSQ_PRIBM_INDBM;
- drmInfo.gart_size = info->gartSize*1024*1024;
- drmInfo.ring_size = info->ringSize*1024*1024;
+ drmInfo.gart_size = info->dri->gartSize*1024*1024;
+ drmInfo.ring_size = info->dri->ringSize*1024*1024;
drmInfo.usec_timeout = info->cp->CPusecTimeout;
drmInfo.fb_bpp = info->CurrentLayout.pixel_code;
- drmInfo.depth_bpp = (info->depthBits - 8) * 2;
-
- drmInfo.front_offset = info->frontOffset;
- drmInfo.front_pitch = info->frontPitch * cpp;
- drmInfo.back_offset = info->backOffset;
- drmInfo.back_pitch = info->backPitch * cpp;
- drmInfo.depth_offset = info->depthOffset;
- drmInfo.depth_pitch = info->depthPitch * drmInfo.depth_bpp / 8;
-
- drmInfo.fb_offset = info->fbHandle;
- drmInfo.mmio_offset = info->registerHandle;
- drmInfo.ring_offset = info->ringHandle;
- drmInfo.ring_rptr_offset = info->ringReadPtrHandle;
- drmInfo.buffers_offset = info->bufHandle;
- drmInfo.gart_textures_offset= info->gartTexHandle;
-
- if (drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT,
+ drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2;
+
+ drmInfo.front_offset = info->dri->frontOffset;
+ drmInfo.front_pitch = info->dri->frontPitch * cpp;
+ drmInfo.back_offset = info->dri->backOffset;
+ drmInfo.back_pitch = info->dri->backPitch * cpp;
+ drmInfo.depth_offset = info->dri->depthOffset;
+ drmInfo.depth_pitch = info->dri->depthPitch * drmInfo.depth_bpp / 8;
+
+ drmInfo.fb_offset = info->dri->fbHandle;
+ drmInfo.mmio_offset = info->dri->registerHandle;
+ drmInfo.ring_offset = info->dri->ringHandle;
+ drmInfo.ring_rptr_offset = info->dri->ringReadPtrHandle;
+ drmInfo.buffers_offset = info->dri->bufHandle;
+ drmInfo.gart_textures_offset= info->dri->gartTexHandle;
+
+ if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
&drmInfo, sizeof(drmRadeonInit)) < 0)
return FALSE;
@@ -1145,16 +1145,16 @@ static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen)
/* Start up the simple memory manager for GART space */
drmHeap.region = RADEON_MEM_REGION_GART;
drmHeap.start = 0;
- drmHeap.size = info->gartTexMapSize;
+ drmHeap.size = info->dri->gartTexMapSize;
- if (drmCommandWrite(info->drmFD, DRM_RADEON_INIT_HEAP,
+ if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_INIT_HEAP,
&drmHeap, sizeof(drmHeap))) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[drm] Failed to initialize GART heap manager\n");
} else {
xf86DrvMsg(pScreen->myNum, X_INFO,
"[drm] Initialized kernel GART heap manager, %d\n",
- info->gartTexMapSize);
+ info->dri->gartTexMapSize);
}
}
@@ -1164,29 +1164,29 @@ static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen)
static Bool RADEONDRIBufInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
/* Initialize vertex buffers */
- info->bufNumBufs = drmAddBufs(info->drmFD,
- info->bufMapSize / RADEON_BUFFER_SIZE,
- RADEON_BUFFER_SIZE,
- (info->cardType!=CARD_AGP) ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
- info->bufStart);
+ info->dri->bufNumBufs = drmAddBufs(info->dri->drmFD,
+ info->dri->bufMapSize / RADEON_BUFFER_SIZE,
+ RADEON_BUFFER_SIZE,
+ (info->cardType!=CARD_AGP) ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
+ info->dri->bufStart);
- if (info->bufNumBufs <= 0) {
+ if (info->dri->bufNumBufs <= 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[drm] Could not create vertex/indirect buffers list\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[drm] Added %d %d byte vertex/indirect buffers\n",
- info->bufNumBufs, RADEON_BUFFER_SIZE);
+ info->dri->bufNumBufs, RADEON_BUFFER_SIZE);
- if (!(info->buffers = drmMapBufs(info->drmFD))) {
+ if (!(info->dri->buffers = drmMapBufs(info->dri->drmFD))) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[drm] Failed to map vertex/indirect buffers list\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[drm] Mapped %d vertex/indirect buffers\n",
- info->buffers->count);
+ info->dri->buffers->count);
return TRUE;
}
@@ -1195,19 +1195,19 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- if (!info->irq) {
- info->irq = drmGetInterruptFromBusID(
- info->drmFD,
+ if (!info->dri->irq) {
+ info->dri->irq = drmGetInterruptFromBusID(
+ info->dri->drmFD,
PCI_CFG_BUS(info->PciInfo),
PCI_CFG_DEV(info->PciInfo),
PCI_CFG_FUNC(info->PciInfo));
- if ((drmCtlInstHandler(info->drmFD, info->irq)) != 0) {
+ if ((drmCtlInstHandler(info->dri->drmFD, info->dri->irq)) != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[drm] failure adding irq handler, "
"there is a device already using that irq\n"
"[drm] falling back to irq-free operation\n");
- info->irq = 0;
+ info->dri->irq = 0;
} else {
unsigned char *RADEONMMIO = info->MMIO;
info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
@@ -1220,10 +1220,10 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
}
}
- if (info->irq)
+ if (info->dri->irq)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[drm] dma control initialized, using IRQ %d\n",
- info->irq);
+ info->dri->irq);
}
@@ -1239,7 +1239,7 @@ static void RADEONDRICPInit(ScrnInfoPtr pScrn)
RADEONCP_START(pScrn, info);
#ifdef USE_XAA
if (!info->useEXA)
- info->accel_state->dst_pitch_offset = info->frontPitchOffset;
+ info->accel_state->dst_pitch_offset = info->dri->frontPitchOffset;
#endif
}
@@ -1280,16 +1280,16 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
/* Check the lib version */
if (xf86LoaderCheckSymbol("drmGetLibVersion"))
- info->pLibDRMVersion = drmGetLibVersion(info->drmFD);
- if (info->pLibDRMVersion == NULL) {
+ info->dri->pLibDRMVersion = drmGetLibVersion(info->dri->drmFD);
+ if (info->dri->pLibDRMVersion == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] RADEONDRIGetVersion failed because libDRM is really "
"way to old to even get a version number out of it.\n"
"[dri] Disabling DRI.\n");
return FALSE;
}
- if (info->pLibDRMVersion->version_major != 1 ||
- info->pLibDRMVersion->version_minor < 2) {
+ if (info->dri->pLibDRMVersion->version_major != 1 ||
+ info->dri->pLibDRMVersion->version_minor < 2) {
/* incompatible drm library version */
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] RADEONDRIGetVersion failed because of a "
@@ -1297,11 +1297,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
"[dri] libdrm.a module version is %d.%d.%d but "
"version 1.2.x is needed.\n"
"[dri] Disabling DRI.\n",
- info->pLibDRMVersion->version_major,
- info->pLibDRMVersion->version_minor,
- info->pLibDRMVersion->version_patchlevel);
- drmFreeVersion(info->pLibDRMVersion);
- info->pLibDRMVersion = NULL;
+ info->dri->pLibDRMVersion->version_major,
+ info->dri->pLibDRMVersion->version_minor,
+ info->dri->pLibDRMVersion->version_patchlevel);
+ drmFreeVersion(info->dri->pLibDRMVersion);
+ info->dri->pLibDRMVersion = NULL;
return FALSE;
}
@@ -1328,9 +1328,9 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
}
/* Get DRM version & close DRM */
- info->pKernelDRMVersion = drmGetVersion(fd);
+ info->dri->pKernelDRMVersion = drmGetVersion(fd);
drmClose(fd);
- if (info->pKernelDRMVersion == NULL) {
+ if (info->dri->pKernelDRMVersion == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] RADEONDRIGetVersion failed to get the DRM version\n"
"[dri] Disabling DRI.\n");
@@ -1350,10 +1350,10 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
}
/* We don't, bummer ! */
- if (info->pKernelDRMVersion->version_major != 1 ||
- info->pKernelDRMVersion->version_minor < req_minor ||
- (info->pKernelDRMVersion->version_minor == req_minor &&
- info->pKernelDRMVersion->version_patchlevel < req_patch)) {
+ if (info->dri->pKernelDRMVersion->version_major != 1 ||
+ info->dri->pKernelDRMVersion->version_minor < req_minor ||
+ (info->dri->pKernelDRMVersion->version_minor == req_minor &&
+ info->dri->pKernelDRMVersion->version_patchlevel < req_patch)) {
/* Incompatible drm version */
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] RADEONDRIGetVersion failed because of a version "
@@ -1361,13 +1361,13 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
"[dri] radeon.o kernel module version is %d.%d.%d "
"but version 1.%d.%d or newer is needed.\n"
"[dri] Disabling DRI.\n",
- info->pKernelDRMVersion->version_major,
- info->pKernelDRMVersion->version_minor,
- info->pKernelDRMVersion->version_patchlevel,
+ info->dri->pKernelDRMVersion->version_major,
+ info->dri->pKernelDRMVersion->version_minor,
+ info->dri->pKernelDRMVersion->version_patchlevel,
req_minor,
req_patch);
- drmFreeVersion(info->pKernelDRMVersion);
- info->pKernelDRMVersion = NULL;
+ drmFreeVersion(info->dri->pKernelDRMVersion);
+ info->dri->pKernelDRMVersion = NULL;
return FALSE;
}
@@ -1383,7 +1383,7 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
if (!info->want_vblank_interrupts)
on = FALSE;
- if (info->directRenderingEnabled && info->pKernelDRMVersion->version_minor >= 28) {
+ if (info->directRenderingEnabled && info->dri->pKernelDRMVersion->version_minor >= 28) {
if (on) {
if (xf86_config->num_crtc > 1 && xf86_config->crtc[1]->enabled)
value = DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2;
@@ -1412,7 +1412,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
DRIInfoPtr pDRIInfo;
RADEONDRIPtr pRADEONDRI;
- info->DRICloseScreen = NULL;
+ info->dri->DRICloseScreen = NULL;
switch (info->CurrentLayout.pixel_code) {
case 8:
@@ -1438,7 +1438,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
*/
if (!(pDRIInfo = DRICreateInfoRec())) return FALSE;
- info->pDRIInfo = pDRIInfo;
+ info->dri->pDRIInfo = pDRIInfo;
pDRIInfo->drmDriverName = RADEON_DRIVER_NAME;
if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) {
@@ -1462,7 +1462,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4;
pDRIInfo->ddxDriverMinorVersion = 3;
pDRIInfo->ddxDriverPatchVersion = 0;
- pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->frontOffset;
+ pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->dri->frontOffset;
pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize;
pDRIInfo->frameBufferStride = (pScrn->displayWidth *
info->CurrentLayout.pixel_bytes);
@@ -1500,8 +1500,8 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
#endif
if (!(pRADEONDRI = (RADEONDRIPtr)xcalloc(sizeof(RADEONDRIRec),1))) {
- DRIDestroyInfoRec(info->pDRIInfo);
- info->pDRIInfo = NULL;
+ DRIDestroyInfoRec(info->dri->pDRIInfo);
+ info->dri->pDRIInfo = NULL;
return FALSE;
}
pDRIInfo->devPrivate = pRADEONDRI;
@@ -1543,7 +1543,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
}
#endif
- if (!DRIScreenInit(pScreen, pDRIInfo, &info->drmFD)) {
+ if (!DRIScreenInit(pScreen, pDRIInfo, &info->dri->drmFD)) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[dri] DRIScreenInit failed. Disabling DRI.\n");
xfree(pDRIInfo->devPrivate);
@@ -1586,7 +1586,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
void *scratch_ptr;
int scratch_int;
- DRIGetDeviceInfo(pScreen, &info->fbHandle,
+ DRIGetDeviceInfo(pScreen, &info->dri->fbHandle,
&scratch_int, &scratch_int,
&scratch_int, &scratch_int,
&scratch_ptr);
@@ -1610,7 +1610,7 @@ static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen)
RADEONDRICloseScreen(pScreen);
- pScreen->CloseScreen = info->DRICloseScreen;
+ pScreen->CloseScreen = info->dri->DRICloseScreen;
return (*pScreen->CloseScreen)(scrnIndex, pScreen);
}
@@ -1625,8 +1625,8 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
RADEONSAREAPrivPtr pSAREAPriv;
RADEONDRIPtr pRADEONDRI;
- info->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT;
- /* info->pDRIInfo->driverSwapMethod = DRI_SERVER_SWAP; */
+ info->dri->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT;
+ /* info->dri->pDRIInfo->driverSwapMethod = DRI_SERVER_SWAP; */
/* NOTE: DRIFinishScreenInit must be called before *DRIKernelInit
* because *DRIKernelInit requires that the hardware lock is held by
@@ -1663,7 +1663,7 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
pSAREAPriv = (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScreen);
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
- pRADEONDRI = (RADEONDRIPtr)info->pDRIInfo->devPrivate;
+ pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate;
pRADEONDRI->deviceID = info->Chipset;
pRADEONDRI->width = pScrn->virtualX;
@@ -1672,40 +1672,40 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
pRADEONDRI->bpp = pScrn->bitsPerPixel;
pRADEONDRI->IsPCI = (info->cardType!=CARD_AGP);
- pRADEONDRI->AGPMode = info->agpMode;
+ pRADEONDRI->AGPMode = info->dri->agpMode;
- pRADEONDRI->frontOffset = info->frontOffset;
- pRADEONDRI->frontPitch = info->frontPitch;
- pRADEONDRI->backOffset = info->backOffset;
- pRADEONDRI->backPitch = info->backPitch;
- pRADEONDRI->depthOffset = info->depthOffset;
- pRADEONDRI->depthPitch = info->depthPitch;
- pRADEONDRI->textureOffset = info->textureOffset;
- pRADEONDRI->textureSize = info->textureSize;
- pRADEONDRI->log2TexGran = info->log2TexGran;
+ pRADEONDRI->frontOffset = info->dri->frontOffset;
+ pRADEONDRI->frontPitch = info->dri->frontPitch;
+ pRADEONDRI->backOffset = info->dri->backOffset;
+ pRADEONDRI->backPitch = info->dri->backPitch;
+ pRADEONDRI->depthOffset = info->dri->depthOffset;
+ pRADEONDRI->depthPitch = info->dri->depthPitch;
+ pRADEONDRI->textureOffset = info->dri->textureOffset;
+ pRADEONDRI->textureSize = info->dri->textureSize;
+ pRADEONDRI->log2TexGran = info->dri->log2TexGran;
- pRADEONDRI->registerHandle = info->registerHandle;
- pRADEONDRI->registerSize = info->registerSize;
+ pRADEONDRI->registerHandle = info->dri->registerHandle;
+ pRADEONDRI->registerSize = info->dri->registerSize;
- pRADEONDRI->statusHandle = info->ringReadPtrHandle;
- pRADEONDRI->statusSize = info->ringReadMapSize;
+ pRADEONDRI->statusHandle = info->dri->ringReadPtrHandle;
+ pRADEONDRI->statusSize = info->dri->ringReadMapSize;
- pRADEONDRI->gartTexHandle = info->gartTexHandle;
- pRADEONDRI->gartTexMapSize = info->gartTexMapSize;
- pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran;
- pRADEONDRI->gartTexOffset = info->gartTexStart;
+ pRADEONDRI->gartTexHandle = info->dri->gartTexHandle;
+ pRADEONDRI->gartTexMapSize = info->dri->gartTexMapSize;
+ pRADEONDRI->log2GARTTexGran = info->dri->log2GARTTexGran;
+ pRADEONDRI->gartTexOffset = info->dri->gartTexStart;
pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
#ifdef PER_CONTEXT_SAREA
/* Set per-context SAREA size */
- pRADEONDRI->perctx_sarea_size = info->perctx_sarea_size;
+ pRADEONDRI->perctx_sarea_size = info->dri->perctx_sarea_size;
#endif
info->directRenderingInited = TRUE;
/* Wrap CloseScreen */
- info->DRICloseScreen = pScreen->CloseScreen;
+ info->dri->DRICloseScreen = pScreen->CloseScreen;
pScreen->CloseScreen = RADEONDRIDoCloseScreen;
/* disable vblank at startup */
@@ -1726,7 +1726,7 @@ void RADEONDRIResume(ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- if (info->pKernelDRMVersion->version_minor >= 9) {
+ if (info->dri->pKernelDRMVersion->version_minor >= 9) {
xf86DrvMsg(pScreen->myNum, X_INFO,
"[RESUME] Attempting to re-init Radeon hardware.\n");
} else {
@@ -1743,7 +1743,7 @@ void RADEONDRIResume(ScreenPtr pScreen)
RADEONSetAgpBase(info, pScreen);
}
- _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME);
+ _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESUME);
if (_ret) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"%s: CP resume %d\n", __FUNCTION__, _ret);
@@ -1788,80 +1788,80 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
"RADEONDRICloseScreen\n");
#ifdef DAMAGE
- REGION_UNINIT(pScreen, &info->driRegion);
+ REGION_UNINIT(pScreen, &info->dri->driRegion);
#endif
- if (info->irq) {
+ if (info->dri->irq) {
RADEONDRISetVBlankInterrupt (pScrn, FALSE);
- drmCtlUninstHandler(info->drmFD);
- info->irq = 0;
+ drmCtlUninstHandler(info->dri->drmFD);
+ info->dri->irq = 0;
info->ModeReg->gen_int_cntl = 0;
}
/* De-allocate vertex buffers */
- if (info->buffers) {
- drmUnmapBufs(info->buffers);
- info->buffers = NULL;
+ if (info->dri->buffers) {
+ drmUnmapBufs(info->dri->buffers);
+ info->dri->buffers = NULL;
}
/* De-allocate all kernel resources */
memset(&drmInfo, 0, sizeof(drmRadeonInit));
drmInfo.func = DRM_RADEON_CLEANUP_CP;
- drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT,
+ drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
&drmInfo, sizeof(drmRadeonInit));
/* De-allocate all GART resources */
- if (info->gartTex) {
- drmUnmap(info->gartTex, info->gartTexMapSize);
- info->gartTex = NULL;
+ if (info->dri->gartTex) {
+ drmUnmap(info->dri->gartTex, info->dri->gartTexMapSize);
+ info->dri->gartTex = NULL;
}
- if (info->buf) {
- drmUnmap(info->buf, info->bufMapSize);
- info->buf = NULL;
+ if (info->dri->buf) {
+ drmUnmap(info->dri->buf, info->dri->bufMapSize);
+ info->dri->buf = NULL;
}
- if (info->ringReadPtr) {
- drmUnmap(info->ringReadPtr, info->ringReadMapSize);
- info->ringReadPtr = NULL;
+ if (info->dri->ringReadPtr) {
+ drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize);
+ info->dri->ringReadPtr = NULL;
}
- if (info->ring) {
- drmUnmap(info->ring, info->ringMapSize);
- info->ring = NULL;
+ if (info->dri->ring) {
+ drmUnmap(info->dri->ring, info->dri->ringMapSize);
+ info->dri->ring = NULL;
}
- if (info->agpMemHandle != DRM_AGP_NO_HANDLE) {
- drmAgpUnbind(info->drmFD, info->agpMemHandle);
- drmAgpFree(info->drmFD, info->agpMemHandle);
- info->agpMemHandle = DRM_AGP_NO_HANDLE;
- drmAgpRelease(info->drmFD);
+ if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) {
+ drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle);
+ drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle);
+ info->dri->agpMemHandle = DRM_AGP_NO_HANDLE;
+ drmAgpRelease(info->dri->drmFD);
}
- if (info->pciMemHandle) {
- drmScatterGatherFree(info->drmFD, info->pciMemHandle);
- info->pciMemHandle = 0;
+ if (info->dri->pciMemHandle) {
+ drmScatterGatherFree(info->dri->drmFD, info->dri->pciMemHandle);
+ info->dri->pciMemHandle = 0;
}
- if (info->pciGartBackup) {
- xfree(info->pciGartBackup);
- info->pciGartBackup = NULL;
+ if (info->dri->pciGartBackup) {
+ xfree(info->dri->pciGartBackup);
+ info->dri->pciGartBackup = NULL;
}
/* De-allocate all DRI resources */
DRICloseScreen(pScreen);
/* De-allocate all DRI data structures */
- if (info->pDRIInfo) {
- if (info->pDRIInfo->devPrivate) {
- xfree(info->pDRIInfo->devPrivate);
- info->pDRIInfo->devPrivate = NULL;
+ if (info->dri->pDRIInfo) {
+ if (info->dri->pDRIInfo->devPrivate) {
+ xfree(info->dri->pDRIInfo->devPrivate);
+ info->dri->pDRIInfo->devPrivate = NULL;
}
- DRIDestroyInfoRec(info->pDRIInfo);
- info->pDRIInfo = NULL;
+ DRIDestroyInfoRec(info->dri->pDRIInfo);
+ info->dri->pDRIInfo = NULL;
}
- if (info->pVisualConfigs) {
- xfree(info->pVisualConfigs);
- info->pVisualConfigs = NULL;
+ if (info->dri->pVisualConfigs) {
+ xfree(info->dri->pVisualConfigs);
+ info->dri->pVisualConfigs = NULL;
}
- if (info->pVisualConfigsPriv) {
- xfree(info->pVisualConfigsPriv);
- info->pVisualConfigsPriv = NULL;
+ if (info->dri->pVisualConfigsPriv) {
+ xfree(info->dri->pVisualConfigsPriv);
+ info->dri->pVisualConfigsPriv = NULL;
}
}
@@ -1907,7 +1907,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
return;
REGION_NULL(pScreen, ®ion);
- REGION_SUBTRACT(pScreen, ®ion, pReg, &info->driRegion);
+ REGION_SUBTRACT(pScreen, ®ion, pReg, &info->dri->driRegion);
num = REGION_NUM_RECTS(®ion);
@@ -1924,7 +1924,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
uint32_t src_pitch_offset, dst_pitch_offset, datatype;
RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset);
- dst_pitch_offset = src_pitch_offset + (info->backOffset >> 10);
+ dst_pitch_offset = src_pitch_offset + (info->dri->backOffset >> 10);
RADEONGetDatatypeBpp(pScrn->bitsPerPixel, &datatype);
info->accel_state->xdir = info->accel_state->ydir = 1;
@@ -1961,8 +1961,8 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
#ifdef USE_XAA
if (!info->useEXA) {
(*info->accel_state->accel->SubsequentScreenToScreenCopy)(pScrn, xa, ya,
- xa + info->backX,
- ya + info->backY,
+ xa + info->dri->backX,
+ ya + info->dri->backY,
xb - xa + 1,
yb - ya + 1);
}
@@ -1976,7 +1976,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
out:
REGION_NULL(pScreen, ®ion);
- DamageEmpty(info->pDamage);
+ DamageEmpty(info->dri->pDamage);
}
#endif /* DAMAGE */
@@ -1987,7 +1987,7 @@ static void RADEONEnablePageFlip(ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- if (info->allowPageFlip) {
+ if (info->dri->allowPageFlip) {
RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
BoxRec box = { .x1 = 0, .y1 = 0, .x2 = pScrn->virtualX - 1,
.y2 = pScrn->virtualY - 1 };
@@ -2040,9 +2040,9 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
* first so we always start with all free offscreen memory, except
* maybe for Xv
*/
- if (info->backArea) {
- xf86FreeOffscreenArea(info->backArea);
- info->backArea = NULL;
+ if (info->dri->backArea) {
+ xf86FreeOffscreenArea(info->dri->backArea);
+ info->dri->backArea = NULL;
}
xf86PurgeUnlockedOffscreenAreas(pScreen);
@@ -2053,7 +2053,7 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
* FIXME: This is hideous. What about telling xv "oh btw you have no memory
* any more?" -- anholt
*/
- if (height < (info->depthTexLines + info->backLines)) {
+ if (height < (info->dri->depthTexLines + info->dri->backLines)) {
RADEONPortPrivPtr portPriv = info->adaptor->pPortPrivates[0].ptr;
xf86FreeOffscreenLinear((FBLinearPtr)portPriv->video_memory);
portPriv->video_memory = NULL;
@@ -2067,29 +2067,29 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
*/
fbarea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth,
height
- - info->depthTexLines
- - info->backLines,
+ - info->dri->depthTexLines
+ - info->dri->backLines,
pScrn->displayWidth,
NULL, NULL, NULL);
if (!fbarea)
xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve placeholder "
"offscreen area, you might experience screen corruption\n");
- info->backArea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth,
- info->backLines,
- pScrn->displayWidth,
- NULL, NULL, NULL);
- if (!info->backArea)
+ info->dri->backArea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth,
+ info->dri->backLines,
+ pScrn->displayWidth,
+ NULL, NULL, NULL);
+ if (!info->dri->backArea)
xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen "
"area for back buffer, you might experience screen "
"corruption\n");
- info->depthTexArea = xf86AllocateOffscreenArea(pScreen,
- pScrn->displayWidth,
- info->depthTexLines,
- pScrn->displayWidth,
- NULL, NULL, NULL);
- if (!info->depthTexArea)
+ info->dri->depthTexArea = xf86AllocateOffscreenArea(pScreen,
+ pScrn->displayWidth,
+ info->dri->depthTexLines,
+ pScrn->displayWidth,
+ NULL, NULL, NULL);
+ if (!info->dri->depthTexArea)
xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen "
"area for depth buffer and textures, you might "
"experience screen corruption\n");
@@ -2098,7 +2098,7 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
}
#endif /* USE_XAA */
- info->have3DWindows = 1;
+ info->dri->have3DWindows = 1;
RADEONChangeSurfaces(pScrn);
RADEONEnablePageFlip(pScreen);
@@ -2118,15 +2118,15 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen)
/* Try flipping back to the front page if necessary */
if (pSAREAPriv->pfCurrentPage == 1)
- drmCommandNone(info->drmFD, DRM_RADEON_FLIP);
+ drmCommandNone(info->dri->drmFD, DRM_RADEON_FLIP);
/* Shut down shadowing if we've made it back to the front page */
if (pSAREAPriv->pfCurrentPage == 0) {
RADEONDisablePageFlip(pScreen);
#ifdef USE_XAA
if (!info->useEXA) {
- xf86FreeOffscreenArea(info->backArea);
- info->backArea = NULL;
+ xf86FreeOffscreenArea(info->dri->backArea);
+ info->dri->backArea = NULL;
}
#endif
} else {
@@ -2137,10 +2137,10 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen)
#ifdef USE_XAA
if (!info->useEXA)
- xf86FreeOffscreenArea(info->depthTexArea);
+ xf86FreeOffscreenArea(info->dri->depthTexArea);
#endif
- info->have3DWindows = 0;
+ info->dri->have3DWindows = 0;
RADEONChangeSurfaces(pScrn);
@@ -2160,8 +2160,8 @@ RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- REGION_UNINIT(pScreen, &info->driRegion);
- REGION_NULL(pScreen, &info->driRegion);
+ REGION_UNINIT(pScreen, &info->dri->driRegion);
+ REGION_NULL(pScreen, &info->dri->driRegion);
if (num > 0) {
int i;
@@ -2170,8 +2170,8 @@ RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num)
WindowPtr pWin = ppWin[i];
if (pWin) {
- REGION_UNION(pScreen, &info->driRegion, &pWin->clipList,
- &info->driRegion);
+ REGION_UNION(pScreen, &info->dri->driRegion, &pWin->clipList,
+ &info->dri->driRegion);
}
}
}
@@ -2184,24 +2184,24 @@ void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen)
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->cardType != CARD_PCIE ||
- info->pKernelDRMVersion->version_minor < 19)
+ info->dri->pKernelDRMVersion->version_minor < 19)
return;
if (info->FbSecureSize==0)
return;
/* set the old default size of pci gart table */
- if (info->pKernelDRMVersion->version_minor < 26)
- info->pciGartSize = 32768;
+ if (info->dri->pKernelDRMVersion->version_minor < 26)
+ info->dri->pciGartSize = 32768;
- info->pciGartSize = RADEONDRIGetPciAperTableSize(pScrn);
+ info->dri->pciGartSize = RADEONDRIGetPciAperTableSize(pScrn);
/* allocate space to back up PCIEGART table */
- info->pciGartBackup = xnfcalloc(1, info->pciGartSize);
- if (info->pciGartBackup == NULL)
+ info->dri->pciGartBackup = xnfcalloc(1, info->dri->pciGartSize);
+ if (info->dri->pciGartBackup == NULL)
return;
- info->pciGartOffset = (info->FbMapSize - info->FbSecureSize);
+ info->dri->pciGartOffset = (info->FbMapSize - info->FbSecureSize);
}
@@ -2213,7 +2213,7 @@ int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn)
int ret_size;
int num_pages;
- num_pages = (info->pciAperSize * 1024 * 1024) / page_size;
+ num_pages = (info->dri->pciAperSize * 1024 * 1024) / page_size;
ret_size = num_pages * sizeof(unsigned int);
@@ -2229,7 +2229,7 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam));
radeonsetparam.param = param;
radeonsetparam.value = value;
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM,
+ ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SETPARAM,
&radeonsetparam, sizeof(drmRadeonSetParam));
return ret;
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index d485865..9dd420e 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1284,7 +1284,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
#ifdef XF86DRI
/* Apply memory map limitation if using an old DRI */
- if (info->directRenderingEnabled && !info->newMemoryMap) {
+ if (info->directRenderingEnabled && !info->dri->newMemoryMap) {
if (aper_size < mem_size)
mem_size = aper_size;
}
@@ -1299,7 +1299,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
#ifdef XF86DRI
/* Old DRI has restrictions on the memory map */
if ( info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 10 )
+ info->dri->pKernelDRMVersion->version_minor < 10 )
info->mc_fb_location = (mem_size - 1) & 0xffff0000U;
else
#endif
@@ -1487,18 +1487,18 @@ static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
* we need to limit the amount of accessible video memory
*/
if (info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 23) {
+ info->dri->pKernelDRMVersion->version_minor < 23) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[dri] limiting video memory to one aperture of %uK\n",
(unsigned)aper_size);
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[dri] detected radeon kernel module version 1.%d but"
" 1.23 or newer is required for full memory mapping.\n",
- info->pKernelDRMVersion->version_minor);
- info->newMemoryMap = FALSE;
+ info->dri->pKernelDRMVersion->version_minor);
+ info->dri->newMemoryMap = FALSE;
return aper_size;
}
- info->newMemoryMap = TRUE;
+ info->dri->newMemoryMap = TRUE;
#endif /* XF86DRI */
/* Set HDP_APER_CNTL only on cards that are known not to be broken,
@@ -2111,8 +2111,11 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->directRenderingEnabled = FALSE;
info->directRenderingInited = FALSE;
- info->pLibDRMVersion = NULL;
- info->pKernelDRMVersion = NULL;
+
+ if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
+ return FALSE;
+ }
if (!(info->cp = xcalloc(1, sizeof(struct radeon_cp)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
@@ -2163,18 +2166,26 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
return FALSE;
}
+ if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) {
+ ErrorF("Unable to allocate dri rec!\n");
+ return FALSE;
+ }
+
+ info->dri->pLibDRMVersion = NULL;
+ info->dri->pKernelDRMVersion = NULL;
+
if (!RADEONDRIGetVersion(pScrn))
return FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[dri] Found DRI library version %d.%d.%d and kernel"
" module version %d.%d.%d\n",
- info->pLibDRMVersion->version_major,
- info->pLibDRMVersion->version_minor,
- info->pLibDRMVersion->version_patchlevel,
- info->pKernelDRMVersion->version_major,
- info->pKernelDRMVersion->version_minor,
- info->pKernelDRMVersion->version_patchlevel);
+ info->dri->pLibDRMVersion->version_major,
+ info->dri->pLibDRMVersion->version_minor,
+ info->dri->pLibDRMVersion->version_patchlevel,
+ info->dri->pKernelDRMVersion->version_major,
+ info->dri->pKernelDRMVersion->version_minor,
+ info->dri->pKernelDRMVersion->version_patchlevel);
if (info->Chipset == PCI_CHIP_RS400_5A41 ||
info->Chipset == PCI_CHIP_RS400_5A42 ||
@@ -2185,7 +2196,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->Chipset == PCI_CHIP_RS482_5974 ||
info->Chipset == PCI_CHIP_RS485_5975) {
- if (info->pKernelDRMVersion->version_minor < 27) {
+ if (info->dri->pKernelDRMVersion->version_minor < 27) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n");
return FALSE;
@@ -2195,21 +2206,21 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
}
if (info->ChipFamily >= CHIP_FAMILY_R300)
- info->gartSize = R300_DEFAULT_GART_SIZE;
+ info->dri->gartSize = R300_DEFAULT_GART_SIZE;
else
- info->gartSize = RADEON_DEFAULT_GART_SIZE;
+ info->dri->gartSize = RADEON_DEFAULT_GART_SIZE;
- info->ringSize = RADEON_DEFAULT_RING_SIZE;
- info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
- info->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE;
- info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE;
+ info->dri->ringSize = RADEON_DEFAULT_RING_SIZE;
+ info->dri->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
+ info->dri->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE;
+ info->dri->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE;
info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
if ((xf86GetOptValInteger(info->Options,
- OPTION_GART_SIZE, (int *)&(info->gartSize))) ||
+ OPTION_GART_SIZE, (int *)&(info->dri->gartSize))) ||
(xf86GetOptValInteger(info->Options,
- OPTION_GART_SIZE_OLD, (int *)&(info->gartSize)))) {
- switch (info->gartSize) {
+ OPTION_GART_SIZE_OLD, (int *)&(info->dri->gartSize)))) {
+ switch (info->dri->gartSize) {
case 4:
case 8:
case 16:
@@ -2221,24 +2232,24 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal GART size: %d MB\n", info->gartSize);
+ "Illegal GART size: %d MB\n", info->dri->gartSize);
return FALSE;
}
}
if (xf86GetOptValInteger(info->Options,
- OPTION_RING_SIZE, &(info->ringSize))) {
- if (info->ringSize < 1 || info->ringSize >= (int)info->gartSize) {
+ OPTION_RING_SIZE, &(info->dri->ringSize))) {
+ if (info->dri->ringSize < 1 || info->dri->ringSize >= (int)info->dri->gartSize) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal ring buffer size: %d MB\n",
- info->ringSize);
+ info->dri->ringSize);
return FALSE;
}
}
if (xf86GetOptValInteger(info->Options,
- OPTION_PCIAPER_SIZE, &(info->pciAperSize))) {
- switch(info->pciAperSize) {
+ OPTION_PCIAPER_SIZE, &(info->dri->pciAperSize))) {
+ switch(info->dri->pciAperSize) {
case 32:
case 64:
case 128:
@@ -2247,38 +2258,38 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal pci aper size: %d MB\n",
- info->pciAperSize);
+ info->dri->pciAperSize);
return FALSE;
}
}
if (xf86GetOptValInteger(info->Options,
- OPTION_BUFFER_SIZE, &(info->bufSize))) {
- if (info->bufSize < 1 || info->bufSize >= (int)info->gartSize) {
+ OPTION_BUFFER_SIZE, &(info->dri->bufSize))) {
+ if (info->dri->bufSize < 1 || info->dri->bufSize >= (int)info->dri->gartSize) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal vertex/indirect buffers size: %d MB\n",
- info->bufSize);
+ info->dri->bufSize);
return FALSE;
}
- if (info->bufSize > 2) {
+ if (info->dri->bufSize > 2) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal vertex/indirect buffers size: %d MB\n",
- info->bufSize);
+ info->dri->bufSize);
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Clamping vertex/indirect buffers size to 2 MB\n");
- info->bufSize = 2;
+ info->dri->bufSize = 2;
}
}
- if (info->ringSize + info->bufSize + info->gartTexSize >
- (int)info->gartSize) {
+ if (info->dri->ringSize + info->dri->bufSize + info->dri->gartTexSize >
+ (int)info->dri->gartSize) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Buffers are too big for requested GART space\n");
return FALSE;
}
- info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize);
+ info->dri->gartTexSize = info->dri->gartSize - (info->dri->ringSize + info->dri->bufSize);
if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT,
&(info->cp->CPusecTimeout))) {
@@ -2288,22 +2299,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
/* Two options to try and squeeze as much texture memory as possible
* for dedicated 3d rendering boxes
*/
- info->noBackBuffer = xf86ReturnOptValBool(info->Options,
- OPTION_NO_BACKBUFFER,
- FALSE);
+ info->dri->noBackBuffer = xf86ReturnOptValBool(info->Options,
+ OPTION_NO_BACKBUFFER,
+ FALSE);
- info->allowPageFlip = 0;
+ info->dri->allowPageFlip = 0;
#ifdef DAMAGE
- if (info->noBackBuffer) {
+ if (info->dri->noBackBuffer) {
from = X_DEFAULT;
reason = " because back buffer disabled";
} else {
from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP,
- &info->allowPageFlip) ? X_CONFIG : X_DEFAULT;
+ &info->dri->allowPageFlip) ? X_CONFIG : X_DEFAULT;
if (IS_AVIVO_VARIANT) {
- info->allowPageFlip = 0;
+ info->dri->allowPageFlip = 0;
reason = " on r5xx and newer chips.\n";
} else {
reason = "";
@@ -2316,7 +2327,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
#endif
xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n",
- info->allowPageFlip ? "en" : "dis", reason);
+ info->dri->allowPageFlip ? "en" : "dis", reason);
info->DMAForXv = TRUE;
from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv)
@@ -2356,15 +2367,15 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn)
#ifdef XF86DRI
if (info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 14) {
+ info->dri->pKernelDRMVersion->version_minor < 14) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[dri] color tiling disabled because of version "
"mismatch.\n"
"[dri] radeon.o kernel module version is %d.%d.%d but "
"1.14.0 or later is required for color tiling.\n",
- info->pKernelDRMVersion->version_major,
- info->pKernelDRMVersion->version_minor,
- info->pKernelDRMVersion->version_patchlevel);
+ info->dri->pKernelDRMVersion->version_major,
+ info->dri->pKernelDRMVersion->version_minor,
+ info->dri->pKernelDRMVersion->version_patchlevel);
info->allowColorTiling = FALSE;
return;
}
@@ -3202,14 +3213,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->accel_state->accel = NULL;
#endif
#ifdef XF86DRI
- pScrn->fbOffset = info->frontOffset;
+ pScrn->fbOffset = info->dri->frontOffset;
#endif
if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024;
#ifdef XF86DRI
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONScreenInit %lx %ld %d\n",
- pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset);
+ pScrn->memPhysBase, pScrn->fbOffset, info->dri->frontOffset);
#else
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONScreenInit %lx %ld\n",
@@ -3218,8 +3229,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (!RADEONMapMem(pScrn)) return FALSE;
#ifdef XF86DRI
- info->fbX = 0;
- info->fbY = 0;
+ info->dri->fbX = 0;
+ info->dri->fbY = 0;
#endif
info->PaletteSavedOnVT = FALSE;
@@ -3273,21 +3284,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (info->directRenderingEnabled) {
MessageType from;
- info->depthBits = pScrn->depth;
+ info->dri->depthBits = pScrn->depth;
from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS,
- &info->depthBits)
+ &info->dri->depthBits)
? X_CONFIG : X_DEFAULT;
- if (info->depthBits != 16 && info->depthBits != 24) {
+ if (info->dri->depthBits != 16 && info->dri->depthBits != 24) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Value for Option \"DepthBits\" must be 16 or 24\n");
- info->depthBits = pScrn->depth;
+ info->dri->depthBits = pScrn->depth;
from = X_DEFAULT;
}
xf86DrvMsg(pScrn->scrnIndex, from,
- "Using %d bit depth buffer\n", info->depthBits);
+ "Using %d bit depth buffer\n", info->dri->depthBits);
}
@@ -3312,14 +3323,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#ifdef XF86DRI
/* Depth moves are disabled by default since they are extremely slow */
- info->depthMoves = xf86ReturnOptValBool(info->Options,
+ info->dri->depthMoves = xf86ReturnOptValBool(info->Options,
OPTION_DEPTH_MOVE, FALSE);
- if (info->depthMoves && info->allowColorTiling) {
+ if (info->dri->depthMoves && info->allowColorTiling) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n");
- } else if (info->depthMoves) {
+ } else if (info->dri->depthMoves) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Depth moves don't work without color tiling, disabled\n");
- info->depthMoves = FALSE;
+ info->dri->depthMoves = FALSE;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Depth moves disabled by default\n");
@@ -3355,15 +3366,15 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
* default, can be overridden with Option "FBTexPercent".
* Round down to a whole number of texture regions.
*/
- info->textureSize = 50;
+ info->dri->textureSize = 50;
if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
- &(info->textureSize))) {
- if (info->textureSize < 0 || info->textureSize > 100) {
+ &(info->dri->textureSize))) {
+ if (info->dri->textureSize < 0 || info->dri->textureSize > 100) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal texture memory percentage: %dx, setting to default 50%%\n",
- info->textureSize);
- info->textureSize = 50;
+ info->dri->textureSize);
+ info->dri->textureSize = 50;
}
}
}
@@ -3380,19 +3391,19 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#if defined(XF86DRI) && defined(USE_XAA)
if (!info->useEXA && hasDRI) {
- info->textureSize = -1;
+ info->dri->textureSize = -1;
if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
- &(info->textureSize))) {
- if (info->textureSize < 0 || info->textureSize > 100) {
+ &(info->dri->textureSize))) {
+ if (info->dri->textureSize < 0 || info->dri->textureSize > 100) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal texture memory percentage: %dx, using default behaviour\n",
- info->textureSize);
- info->textureSize = -1;
+ info->dri->textureSize);
+ info->dri->textureSize = -1;
}
}
if (!RADEONSetupMemXAA_DRI(scrnIndex, pScreen))
return FALSE;
- pScrn->fbOffset = info->frontOffset;
+ pScrn->fbOffset = info->dri->frontOffset;
}
#endif
@@ -3433,7 +3444,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
}
/* Tell DRI about new memory map */
- if (info->directRenderingEnabled && info->newMemoryMap) {
+ if (info->directRenderingEnabled && info->dri->newMemoryMap) {
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[drm] failed to enable new memory map\n");
@@ -3520,14 +3531,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* DRI finalisation */
#ifdef XF86DRI
if (info->directRenderingEnabled && info->cardType==CARD_PCIE &&
- info->pKernelDRMVersion->version_minor >= 19)
+ info->dri->pKernelDRMVersion->version_minor >= 19)
{
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->pciGartOffset) < 0)
+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] failed set pci gart location\n");
- if (info->pKernelDRMVersion->version_minor >= 26) {
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->pciGartSize) < 0)
+ if (info->dri->pKernelDRMVersion->version_minor >= 26) {
+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->dri->pciGartSize) < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] failed set pci gart table size\n");
}
@@ -3544,10 +3555,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
*/
RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
- if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {
- /* we need to re-calculate bandwidth because of AGPMode difference. */
- RADEONInitDispBandwidth(pScrn);
- }
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
/* we might already be in tiled mode, tell drm about it */
@@ -3952,7 +3959,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
gp.param = RADEON_PARAM_GART_BASE;
gp.value = &gart_base;
- if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &gp,
+ if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &gp,
sizeof(gp)) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to determine GART area MC location, not using "
@@ -4039,32 +4046,32 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
drmRadeonSurfaceFree drmsurffree;
drmRadeonSurfaceAlloc drmsurfalloc;
int retvalue;
- int depthCpp = (info->depthBits - 8) / 4;
+ int depthCpp = (info->dri->depthBits - 8) / 4;
int depth_width_bytes = pScrn->displayWidth * depthCpp;
int depthBufferSize = ((((pScrn->virtualY + 15) & ~15) * depth_width_bytes
+ RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
unsigned int depth_pattern;
- drmsurffree.address = info->frontOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
+ drmsurffree.address = info->dri->frontOffset;
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
if (!((info->ChipFamily == CHIP_FAMILY_RV100) ||
(info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200))) {
- drmsurffree.address = info->depthOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
+ drmsurffree.address = info->dri->depthOffset;
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
}
- if (!info->noBackBuffer) {
- drmsurffree.address = info->backOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
+ if (!info->dri->noBackBuffer) {
+ drmsurffree.address = info->dri->backOffset;
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
}
drmsurfalloc.size = bufferSize;
- drmsurfalloc.address = info->frontOffset;
+ drmsurfalloc.address = info->dri->frontOffset;
drmsurfalloc.flags = swap_pattern;
if (info->tilingEnabled) {
@@ -4073,15 +4080,15 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
else
drmsurfalloc.flags |= (width_bytes / 16) | color_pattern;
}
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC,
&drmsurfalloc, sizeof(drmsurfalloc));
if (retvalue < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"drm: could not allocate surface for front buffer!\n");
- if ((info->have3DWindows) && (!info->noBackBuffer)) {
- drmsurfalloc.address = info->backOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
+ if ((info->dri->have3DWindows) && (!info->dri->noBackBuffer)) {
+ drmsurfalloc.address = info->dri->backOffset;
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC,
&drmsurfalloc, sizeof(drmsurfalloc));
if (retvalue < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -4106,18 +4113,18 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
}
/* rv100 and probably the derivative igps don't have depth tiling on all the time? */
- if (info->have3DWindows &&
+ if (info->dri->have3DWindows &&
(!((info->ChipFamily == CHIP_FAMILY_RV100) ||
(info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200)))) {
drmRadeonSurfaceAlloc drmsurfalloc;
drmsurfalloc.size = depthBufferSize;
- drmsurfalloc.address = info->depthOffset;
+ drmsurfalloc.address = info->dri->depthOffset;
if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern;
else
drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC,
&drmsurfalloc, sizeof(drmsurfalloc));
if (retvalue < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -5286,7 +5293,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2)
#if 0
/* try to get rid of flickering when scrolling at least for 2d */
#ifdef XF86DRI
- if (!info->have3DWindows)
+ if (!info->dri->have3DWindows)
#endif
crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
#endif
@@ -5343,7 +5350,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2)
}
if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
+ Base += info->dri->backOffset - info->dri->frontOffset;
}
}
#endif
@@ -5451,10 +5458,10 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
#ifdef XF86DRI
if (info->directRenderingEnabled) {
if (info->cardType == CARD_PCIE &&
- info->pKernelDRMVersion->version_minor >= 19 &&
+ info->dri->pKernelDRMVersion->version_minor >= 19 &&
info->FbSecureSize) {
/* we need to backup the PCIE GART TABLE from fb memory */
- memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize);
+ memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize);
}
/* get the DRI back into shape after resume */
@@ -5502,14 +5509,14 @@ void RADEONLeaveVT(int scrnIndex, int flags)
RADEONCP_STOP(pScrn, info);
if (info->cardType == CARD_PCIE &&
- info->pKernelDRMVersion->version_minor >= 19 &&
+ info->dri->pKernelDRMVersion->version_minor >= 19 &&
info->FbSecureSize) {
/* we need to backup the PCIE GART TABLE from fb memory */
- memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize);
+ memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize);
}
/* Make sure 3D clients will re-upload textures to video RAM */
- if (info->textureSize) {
+ if (info->dri->textureSize) {
RADEONSAREAPrivPtr pSAREAPriv =
(RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScrn->pScreen);
drmTextureRegionPtr list = pSAREAPriv->texList[0];
@@ -5570,12 +5577,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
#ifdef XF86DRI
#ifdef DAMAGE
- if (info->pDamage) {
+ if (info->dri && info->dri->pDamage) {
PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
- DamageUnregister(&pPix->drawable, info->pDamage);
- DamageDestroy(info->pDamage);
- info->pDamage = NULL;
+ DamageUnregister(&pPix->drawable, info->dri->pDamage);
+ DamageDestroy(info->dri->pDamage);
+ info->dri->pDamage = NULL;
}
#endif
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index d8dcbac..f77235a 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -244,7 +244,7 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index)
drmsurfalloc.size = size;
drmsurfalloc.flags = flags | 1; /* bogus pitch to please DRM */
- rc = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
+ rc = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC,
&drmsurfalloc, sizeof(drmsurfalloc));
if (rc < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -283,7 +283,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index)
drmRadeonSurfaceFree drmsurffree;
drmsurffree.address = offset;
- drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
+ drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
swapper_surfaces[index] = 0;
return;
@@ -444,21 +444,21 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
#if defined(XF86DRI)
if (info->directRenderingEnabled) {
- int depthCpp = (info->depthBits - 8) / 4, l, next, depth_size;
+ int depthCpp = (info->dri->depthBits - 8) / 4, l, next, depth_size;
- info->frontOffset = 0;
- info->frontPitch = pScrn->displayWidth;
+ info->dri->frontOffset = 0;
+ info->dri->frontPitch = pScrn->displayWidth;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for front buffer at offset 0x%08x\n",
- screen_size / 1024, info->frontOffset);
+ screen_size / 1024, info->dri->frontOffset);
RADEONDRIAllocatePCIGARTTable(pScreen);
if (info->cardType==CARD_PCIE)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for PCI GART at offset 0x%08x\n",
- info->pciGartSize / 1024,
- (int)info->pciGartOffset);
+ info->dri->pciGartSize / 1024,
+ (int)info->dri->pciGartOffset);
/* Reserve a static area for the back buffer the same size as the
* visible screen. XXX: This would be better initialized in ati_dri.c
@@ -466,49 +466,49 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
* don't last through VT switches, while the kernel's understanding of
* offscreen locations does.
*/
- info->backPitch = pScrn->displayWidth;
+ info->dri->backPitch = pScrn->displayWidth;
next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_BUFFER_ALIGN);
- if (!info->noBackBuffer &&
+ if (!info->dri->noBackBuffer &&
next + screen_size <= info->accel_state->exa->memorySize)
{
- info->backOffset = next;
+ info->dri->backOffset = next;
info->accel_state->exa->offScreenBase = next + screen_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for back buffer at offset 0x%08x\n",
- screen_size / 1024, info->backOffset);
+ screen_size / 1024, info->dri->backOffset);
}
/* Reserve the static depth buffer, and adjust pitch and height to
* handle tiling.
*/
- info->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32);
- depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->depthPitch * depthCpp;
+ info->dri->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32);
+ depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->dri->depthPitch * depthCpp;
next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_BUFFER_ALIGN);
if (next + depth_size <= info->accel_state->exa->memorySize)
{
- info->depthOffset = next;
+ info->dri->depthOffset = next;
info->accel_state->exa->offScreenBase = next + depth_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for depth buffer at offset 0x%08x\n",
- depth_size / 1024, info->depthOffset);
+ depth_size / 1024, info->dri->depthOffset);
}
- info->textureSize *= (info->accel_state->exa->memorySize -
- info->accel_state->exa->offScreenBase) / 100;
+ info->dri->textureSize *= (info->accel_state->exa->memorySize -
+ info->accel_state->exa->offScreenBase) / 100;
- l = RADEONLog2(info->textureSize / RADEON_NR_TEX_REGIONS);
+ l = RADEONLog2(info->dri->textureSize / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY)
l = RADEON_LOG_TEX_GRANULARITY;
- info->textureSize = (info->textureSize >> l) << l;
- if (info->textureSize >= 512 * 1024) {
- info->textureOffset = info->accel_state->exa->offScreenBase;
- info->accel_state->exa->offScreenBase += info->textureSize;
+ info->dri->textureSize = (info->dri->textureSize >> l) << l;
+ if (info->dri->textureSize >= 512 * 1024) {
+ info->dri->textureOffset = info->accel_state->exa->offScreenBase;
+ info->accel_state->exa->offScreenBase += info->dri->textureSize;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for textures at offset 0x%08x\n",
- info->textureSize / 1024, info->textureOffset);
+ info->dri->textureSize / 1024, info->dri->textureOffset);
} else {
/* Minimum texture size is for 2 256x256x32bpp textures */
- info->textureSize = 0;
+ info->dri->textureSize = 0;
}
} else
#endif /* XF86DRI */
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 783e83d..2be9a8d 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -401,7 +401,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8;
int hpass = min(h, scratch->total/2 / scratch_pitch);
uint32_t scratch_pitch_offset = scratch_pitch << 16
- | (info->gartLocation + info->bufStart
+ | (info->gartLocation + info->dri->bufStart
+ scratch->idx * scratch->total) >> 10;
drmRadeonIndirect indirect;
ACCEL_PREAMBLE();
@@ -450,7 +450,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
* we'd really need is a way to reliably wait for the host interface
* to be done with pushing the data to the host.
*/
- while ((drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE) == -EBUSY)
+ while ((drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE) == -EBUSY)
&& (i++ < RADEON_TIMEOUT))
;
@@ -473,7 +473,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
indirect.start = indirect.end = 0;
indirect.discard = 1;
- drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
+ drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
&indirect, sizeof(drmRadeonIndirect));
info->accel_state->exaMarkerSynced = info->accel_state->exaSyncMarker;
commit 75ef8dc214715d3c5c50996b293933842903ba65
Author: Egbert Eich <eich at freedesktop.org>
Date: Thu Jul 10 21:49:55 2008 -0400
Cleanups from rhd port
- remove unused vars
- remove static exa render vars
diff --git a/src/radeon.h b/src/radeon.h
index e2ba360..78733ab 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -439,8 +439,6 @@ struct radeon_accel_state {
/* common accel data */
int fifo_slots; /* Free slots in the FIFO (64 max) */
/* Computed values for Radeon */
- int pitch;
- int datatype;
uint32_t dp_gui_master_cntl;
uint32_t dp_gui_master_cntl_clip;
uint32_t trans_color;
@@ -465,6 +463,16 @@ struct radeon_accel_state {
#define EXA_ENGINEMODE_UNKNOWN 0
#define EXA_ENGINEMODE_2D 1
#define EXA_ENGINEMODE_3D 2
+
+ Bool is_transform[2];
+ PictTransform *transform[2];
+ Bool has_mask;
+ /* Whether we are tiling horizontally and vertically */
+ Bool need_src_tile_x;
+ Bool need_src_tile_y;
+ /* Size of tiles ... set to 65536x65536 if not tiling in that direction */
+ Bool src_tile_width;
+ Bool src_tile_height;
#endif
#ifdef USE_XAA
@@ -501,18 +509,6 @@ struct radeon_accel_state {
*/
Bool XAAForceTransBlit;
#endif
-#ifdef XF86DRI
- /* Saved scissor values */
- uint32_t sc_left;
- uint32_t sc_right;
- uint32_t sc_top;
- uint32_t sc_bottom;
-
- uint32_t re_top_left;
- uint32_t re_width_height;
-
- uint32_t aux_sc_cntl;
-#endif
};
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 6c19b70..132a2f4 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -364,6 +364,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
+ int datatype = 0;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"EngineInit (%d/%d)\n",
@@ -446,11 +447,11 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
RADEONEngineReset(pScrn);
switch (info->CurrentLayout.pixel_code) {
- case 8: info->accel_state->datatype = 2; break;
- case 15: info->accel_state->datatype = 3; break;
- case 16: info->accel_state->datatype = 4; break;
- case 24: info->accel_state->datatype = 5; break;
- case 32: info->accel_state->datatype = 6; break;
+ case 8: datatype = 2; break;
+ case 15: datatype = 3; break;
+ case 16: datatype = 4; break;
+ case 24: datatype = 5; break;
+ case 32: datatype = 6; break;
default:
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Unknown depth/bpp = %d/%d (code = %d)\n",
@@ -458,14 +459,9 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
info->CurrentLayout.bitsPerPixel,
info->CurrentLayout.pixel_code);
}
- info->accel_state->pitch = ((info->CurrentLayout.displayWidth / 8) *
- (info->CurrentLayout.pixel_bytes == 3 ? 3 : 1));
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Pitch for acceleration = %d\n", info->accel_state->pitch);
info->accel_state->dp_gui_master_cntl =
- ((info->accel_state->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
+ ((datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
| RADEON_GMC_CLR_CMP_CNTL_DIS
| RADEON_GMC_DST_PITCH_OFFSET_CNTL);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index ddb28be..97199ae 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -56,15 +56,6 @@
/* Only include the following (generic) bits once. */
#ifdef ONLY_ONCE
-static Bool is_transform[2];
-static PictTransform *transform[2];
-static Bool has_mask;
-/* Whether we are tiling horizontally and vertically */
-static Bool need_src_tile_x;
-static Bool need_src_tile_y;
-/* Size of tiles ... set to 65536x65536 if not tiling in that direction */
-static Bool src_tile_width;
-static Bool src_tile_height;
struct blendinfo {
Bool dst_alpha;
@@ -287,8 +278,10 @@ static Bool RADEONSetupSourceTile(PicturePtr pPict,
Bool canTile1d,
Bool needMatchingPitch)
{
- need_src_tile_x = need_src_tile_y = FALSE;
- src_tile_width = src_tile_height = 65536; /* "infinite" */
+ RINFO_FROM_SCREEN(pPix->drawable.pScreen);
+
+ info->accel_state->need_src_tile_x = info->accel_state->need_src_tile_y = FALSE;
+ info->accel_state->src_tile_width = info->accel_state->src_tile_height = 65536; /* "infinite" */
if (pPict->repeat) {
Bool badPitch = needMatchingPitch && !RADEONPitchMatches(pPix);
@@ -301,17 +294,19 @@ static Bool RADEONSetupSourceTile(PicturePtr pPict,
RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
w, (unsigned)exaGetPixmapPitch(pPix)));
} else {
- need_src_tile_x = (w & (w - 1)) != 0 || badPitch;
- need_src_tile_y = (h & (h - 1)) != 0;
+ info->accel_state->need_src_tile_x = (w & (w - 1)) != 0 || badPitch;
+ info->accel_state->need_src_tile_y = (h & (h - 1)) != 0;
if (!canTile1d)
- need_src_tile_x = need_src_tile_y = need_src_tile_x || need_src_tile_y;
+ info->accel_state->need_src_tile_x =
+ info->accel_state->need_src_tile_y =
+ info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y;
}
- if (need_src_tile_x)
- src_tile_width = w;
- if (need_src_tile_y)
- src_tile_height = h;
+ if (info->accel_state->need_src_tile_x)
+ info->accel_state->src_tile_width = w;
+ if (info->accel_state->need_src_tile_y)
+ info->accel_state->src_tile_height = h;
}
return TRUE;
@@ -357,7 +352,8 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
uint32_t txfilter, txformat, txoffset, txpitch;
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
- Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y));
+ Bool repeat = pPict->repeat &&
+ !(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y));
int i;
ACCEL_PREAMBLE();
@@ -427,10 +423,10 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
FINISH_ACCEL();
if (pPict->transform != 0) {
- is_transform[unit] = TRUE;
- transform[unit] = pPict->transform;
+ info->accel_state->is_transform[unit] = TRUE;
+ info->accel_state->transform[unit] = pPict->transform;
} else {
- is_transform[unit] = FALSE;
+ info->accel_state->is_transform[unit] = FALSE;
}
return TRUE;
@@ -538,9 +534,9 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
return FALSE;
if (pMask)
- has_mask = TRUE;
+ info->accel_state->has_mask = TRUE;
else
- has_mask = FALSE;
+ info->accel_state->has_mask = FALSE;
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
@@ -569,7 +565,7 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
return FALSE;
pp_cntl |= RADEON_TEX_1_ENABLE;
} else {
- is_transform[1] = FALSE;
+ info->accel_state->is_transform[1] = FALSE;
}
RADEON_SWITCH_TO_3D();
@@ -670,7 +666,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
uint32_t txfilter, txformat, txoffset, txpitch;
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
- Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y));
+ Bool repeat = pPict->repeat &&
+ !(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y));
int i;
ACCEL_PREAMBLE();
@@ -742,10 +739,10 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
FINISH_ACCEL();
if (pPict->transform != 0) {
- is_transform[unit] = TRUE;
- transform[unit] = pPict->transform;
+ info->accel_state->is_transform[unit] = TRUE;
+ info->accel_state->transform[unit] = pPict->transform;
} else {
- is_transform[unit] = FALSE;
+ info->accel_state->is_transform[unit] = FALSE;
}
return TRUE;
@@ -837,9 +834,9 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
return FALSE;
if (pMask)
- has_mask = TRUE;
+ info->accel_state->has_mask = TRUE;
else
- has_mask = FALSE;
+ info->accel_state->has_mask = FALSE;
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
@@ -866,7 +863,7 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
return FALSE;
pp_cntl |= RADEON_TEX_1_ENABLE;
} else {
- is_transform[1] = FALSE;
+ info->accel_state->is_transform[1] = FALSE;
}
RADEON_SWITCH_TO_3D();
@@ -1048,12 +1045,12 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
info->accel_state->texW[unit] = w;
info->accel_state->texH[unit] = h;
- if (pPict->repeat && !(unit == 0 && need_src_tile_x))
+ if (pPict->repeat && !(unit == 0 && info->accel_state->need_src_tile_x))
txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
else
txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL);
- if (pPict->repeat && !(unit == 0 && need_src_tile_y))
+ if (pPict->repeat && !(unit == 0 && info->accel_state->need_src_tile_y))
txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP);
else
txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
@@ -1083,10 +1080,10 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
FINISH_ACCEL();
if (pPict->transform != 0) {
- is_transform[unit] = TRUE;
- transform[unit] = pPict->transform;
+ info->accel_state->is_transform[unit] = TRUE;
+ info->accel_state->transform[unit] = pPict->transform;
} else {
- is_transform[unit] = FALSE;
+ info->accel_state->is_transform[unit] = FALSE;
}
return TRUE;
@@ -1198,9 +1195,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
return FALSE;
if (pMask)
- has_mask = TRUE;
+ info->accel_state->has_mask = TRUE;
else
- has_mask = FALSE;
+ info->accel_state->has_mask = FALSE;
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
@@ -1230,7 +1227,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
return FALSE;
txenable |= R300_TEX_1_ENABLE;
} else {
- is_transform[1] = FALSE;
+ info->accel_state->is_transform[1] = FALSE;
}
RADEON_SWITCH_TO_3D();
@@ -1938,20 +1935,20 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
maskBottomRight.x = IntToxFixed(maskX + w);
maskBottomRight.y = IntToxFixed(maskY + h);
- if (is_transform[0]) {
- transformPoint(transform[0], &srcTopLeft);
- transformPoint(transform[0], &srcTopRight);
- transformPoint(transform[0], &srcBottomLeft);
- transformPoint(transform[0], &srcBottomRight);
+ if (info->accel_state->is_transform[0]) {
+ transformPoint(info->accel_state->transform[0], &srcTopLeft);
+ transformPoint(info->accel_state->transform[0], &srcTopRight);
+ transformPoint(info->accel_state->transform[0], &srcBottomLeft);
+ transformPoint(info->accel_state->transform[0], &srcBottomRight);
}
- if (is_transform[1]) {
- transformPoint(transform[1], &maskTopLeft);
- transformPoint(transform[1], &maskTopRight);
- transformPoint(transform[1], &maskBottomLeft);
- transformPoint(transform[1], &maskBottomRight);
+ if (info->accel_state->is_transform[1]) {
+ transformPoint(info->accel_state->transform[1], &maskTopLeft);
+ transformPoint(info->accel_state->transform[1], &maskTopRight);
+ transformPoint(info->accel_state->transform[1], &maskBottomLeft);
+ transformPoint(info->accel_state->transform[1], &maskBottomRight);
}
- if (has_mask)
+ if (info->accel_state->has_mask)
vtx_count = VTX_COUNT_MASK;
else
vtx_count = VTX_COUNT;
@@ -1967,7 +1964,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
BEGIN_RING(3 * vtx_count + 3);
OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD,
3 * vtx_count + 1));
- if (has_mask)
+ if (info->accel_state->has_mask)
OUT_RING(RADEON_CP_VC_FRMT_XY |
RADEON_CP_VC_FRMT_ST0 |
RADEON_CP_VC_FRMT_ST1);
@@ -2012,7 +2009,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
#endif
- if (has_mask) {
+ if (info->accel_state->has_mask) {
if (info->ChipFamily >= CHIP_FAMILY_R200) {
VTX_OUT_MASK((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0],
@@ -2063,8 +2060,9 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
{
int tileSrcY, tileMaskY, tileDstY;
int remainingHeight;
-
- if (!need_src_tile_x && !need_src_tile_y) {
+ RINFO_FROM_SCREEN(pDst->drawable.pScreen);
+
+ if (!info->accel_state->need_src_tile_x && !info->accel_state->need_src_tile_y) {
FUNC_NAME(RadeonCompositeTile)(pDst,
srcX, srcY,
maskX, maskY,
@@ -2075,7 +2073,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
/* Tiling logic borrowed from exaFillRegionTiled */
- modulus(srcY, src_tile_height, tileSrcY);
+ modulus(srcY, info->accel_state->src_tile_height, tileSrcY);
tileMaskY = maskY;
tileDstY = dstY;
@@ -2083,18 +2081,18 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
while (remainingHeight > 0) {
int remainingWidth = width;
int tileSrcX, tileMaskX, tileDstX;
- int h = src_tile_height - tileSrcY;
+ int h = info->accel_state->src_tile_height - tileSrcY;
if (h > remainingHeight)
h = remainingHeight;
remainingHeight -= h;
- modulus(srcX, src_tile_width, tileSrcX);
+ modulus(srcX, info->accel_state->src_tile_width, tileSrcX);
tileMaskX = maskX;
tileDstX = dstX;
while (remainingWidth > 0) {
- int w = src_tile_width - tileSrcX;
+ int w = info->accel_state->src_tile_width - tileSrcX;
if (w > remainingWidth)
w = remainingWidth;
remainingWidth -= w;
commit 71ad140fa11f3a504c38d6bddf40e3a3c0a20e60
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Jul 10 21:24:16 2008 -0400
Move accel state to a separate struct
diff --git a/src/radeon.h b/src/radeon.h
index 626b492..e2ba360 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -435,6 +435,87 @@ struct radeon_cp {
};
#endif
+struct radeon_accel_state {
+ /* common accel data */
+ int fifo_slots; /* Free slots in the FIFO (64 max) */
+ /* Computed values for Radeon */
+ int pitch;
+ int datatype;
+ uint32_t dp_gui_master_cntl;
+ uint32_t dp_gui_master_cntl_clip;
+ uint32_t trans_color;
+ /* Saved values for ScreenToScreenCopy */
+ int xdir;
+ int ydir;
+ uint32_t dst_pitch_offset;
+
+ /* render accel */
+ unsigned short texW[2];
+ unsigned short texH[2];
+ Bool XInited3D; /* X itself has the 3D context */
+ int num_gb_pipes;
+ Bool has_tcl;
+
+#ifdef USE_EXA
+ /* EXA */
+ ExaDriverPtr exa;
+ int exaSyncMarker;
+ int exaMarkerSynced;
+ int engineMode;
+#define EXA_ENGINEMODE_UNKNOWN 0
+#define EXA_ENGINEMODE_2D 1
+#define EXA_ENGINEMODE_3D 2
+#endif
+
+#ifdef USE_XAA
+ /* XAA */
+ XAAInfoRecPtr accel;
+ /* ScanlineScreenToScreenColorExpand support */
+ unsigned char *scratch_buffer[1];
+ unsigned char *scratch_save;
+ int scanline_x;
+ int scanline_y;
+ int scanline_w;
+ int scanline_h;
+ int scanline_h_w;
+ int scanline_words;
+ int scanline_direct;
+ int scanline_bpp; /* Only used for ImageWrite */
+ int scanline_fg;
+ int scanline_bg;
+ int scanline_hpass;
+ int scanline_x1clip;
+ int scanline_x2clip;
+ /* Saved values for DashedTwoPointLine */
+ int dashLen;
+ uint32_t dashPattern;
+ int dash_fg;
+ int dash_bg;
+
+ FBLinearPtr RenderTex;
+ void (*RenderCallback)(ScrnInfoPtr);
+ Time RenderTimeout;
+ /*
+ * XAAForceTransBlit is used to change the behavior of the XAA
+ * SetupForScreenToScreenCopy function, to make it DGA-friendly.
+ */
+ Bool XAAForceTransBlit;
+#endif
+#ifdef XF86DRI
+ /* Saved scissor values */
+ uint32_t sc_left;
+ uint32_t sc_right;
+ uint32_t sc_top;
+ uint32_t sc_bottom;
+
+ uint32_t re_top_left;
+ uint32_t re_width_height;
+
+ uint32_t aux_sc_cntl;
+#endif
+
+};
+
typedef struct {
EntityInfoPtr pEnt;
pciVideoPtr PciInfo;
@@ -501,21 +582,13 @@ typedef struct {
Bool PaletteSavedOnVT; /* Palette saved on last VT switch */
+ struct radeon_accel_state *accel_state;
+
#ifdef USE_EXA
- ExaDriverPtr exa;
- int exaSyncMarker;
- int exaMarkerSynced;
- int engineMode;
-#define EXA_ENGINEMODE_UNKNOWN 0
-#define EXA_ENGINEMODE_2D 1
-#define EXA_ENGINEMODE_3D 2
#ifdef XF86DRI
Bool accelDFS;
#endif
#endif
-#ifdef USE_XAA
- XAAInfoRecPtr accel;
-#endif
Bool accelOn;
xf86CursorInfoPtr cursor;
Bool allowColorTiling;
@@ -526,53 +599,9 @@ typedef struct {
int cursor_fg;
int cursor_bg;
-#ifdef USE_XAA
- /*
- * XAAForceTransBlit is used to change the behavior of the XAA
- * SetupForScreenToScreenCopy function, to make it DGA-friendly.
- */
- Bool XAAForceTransBlit;
-#endif
-
- int fifo_slots; /* Free slots in the FIFO (64 max) */
int pix24bpp; /* Depth of pixmap for 24bpp fb */
Bool dac6bits; /* Use 6 bit DAC? */
- /* Computed values for Radeon */
- int pitch;
- int datatype;
- uint32_t dp_gui_master_cntl;
- uint32_t dp_gui_master_cntl_clip;
- uint32_t trans_color;
-
- /* Saved values for ScreenToScreenCopy */
- int xdir;
- int ydir;
-
-#ifdef USE_XAA
- /* ScanlineScreenToScreenColorExpand support */
- unsigned char *scratch_buffer[1];
- unsigned char *scratch_save;
- int scanline_x;
- int scanline_y;
- int scanline_w;
- int scanline_h;
- int scanline_h_w;
- int scanline_words;
- int scanline_direct;
- int scanline_bpp; /* Only used for ImageWrite */
- int scanline_fg;
- int scanline_bg;
- int scanline_hpass;
- int scanline_x1clip;
- int scanline_x2clip;
-#endif
- /* Saved values for DashedTwoPointLine */
- int dashLen;
- uint32_t dashPattern;
- int dash_fg;
- int dash_bg;
-
DGAModePtr DGAModes;
int numDGAModes;
Bool DGAactive;
@@ -580,7 +609,7 @@ typedef struct {
DGAFunctionRec DGAFuncs;
RADEONFBLayout CurrentLayout;
- uint32_t dst_pitch_offset;
+
#ifdef XF86DRI
Bool noBackBuffer;
Bool directRenderingEnabled;
@@ -728,13 +757,6 @@ typedef struct {
/* Render */
Bool RenderAccel;
- unsigned short texW[2];
- unsigned short texH[2];
-#ifdef USE_XAA
- FBLinearPtr RenderTex;
- void (*RenderCallback)(ScrnInfoPtr);
- Time RenderTimeout;
-#endif
/* general */
Bool showCache;
@@ -748,9 +770,6 @@ typedef struct {
XF86ModReqInfo xaaReq;
#endif
- /* X itself has the 3D context */
- Bool XInited3D;
-
DisplayModePtr currentMode, savedCurrentMode;
/* special handlings for DELL triple-head server */
@@ -805,15 +824,13 @@ typedef struct {
Bool r600_shadow_fb;
void *fb_shadow;
- int num_gb_pipes;
- Bool has_tcl;
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
do { \
- if (info->fifo_slots < entries) \
+ if (info->accel_state->fifo_slots < entries) \
RADEONWaitForFifoFunction(pScrn, entries); \
- info->fifo_slots -= entries; \
+ info->accel_state->fifo_slots -= entries; \
} while (0)
/* legacy_crtc.c */
@@ -1258,7 +1275,7 @@ static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
#endif
#ifdef USE_XAA
if (!info->useEXA)
- SET_SYNC_FLAG(info->accel);
+ SET_SYNC_FLAG(info->accel_state->accel);
#endif
}
@@ -1269,8 +1286,8 @@ static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
exaWaitSync(pScrn->pScreen);
#endif
#ifdef USE_XAA
- if (!info->useEXA && info->accel)
- info->accel->Sync(pScrn);
+ if (!info->useEXA && info->accel_state->accel)
+ info->accel_state->accel->Sync(pScrn);
#endif
}
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 72866d1..6c19b70 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -130,9 +130,9 @@ void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries)
for (;;) {
for (i = 0; i < RADEON_TIMEOUT; i++) {
- info->fifo_slots =
+ info->accel_state->fifo_slots =
INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
- if (info->fifo_slots >= entries) return;
+ if (info->accel_state->fifo_slots >= entries) return;
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"FIFO timed out: %u entries, stat=0x%08x\n",
@@ -324,8 +324,8 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn)
* in the wrong place (happened).
*/
RADEONWaitForFifo(pScrn, 2);
- OUTREG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset);
- OUTREG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset);
+ OUTREG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset);
+ OUTREG(RADEON_SRC_PITCH_OFFSET, info->accel_state->dst_pitch_offset);
RADEONWaitForFifo(pScrn, 1);
#if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -343,7 +343,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn)
OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
| RADEON_DEFAULT_SC_BOTTOM_MAX));
RADEONWaitForFifo(pScrn, 1);
- OUTREG(RADEON_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
+ OUTREG(RADEON_DP_GUI_MASTER_CNTL, (info->accel_state->dp_gui_master_cntl
| RADEON_GMC_BRUSH_SOLID_COLOR
| RADEON_GMC_SRC_DATATYPE_COLOR));
@@ -356,7 +356,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn)
RADEONWaitForIdleMMIO(pScrn);
- info->XInited3D = FALSE;
+ info->accel_state->XInited3D = FALSE;
}
/* Initialize the acceleration hardware */
@@ -384,9 +384,9 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Failed to determine num pipes from DRM, falling back to "
"manual look-up!\n");
- info->num_gb_pipes = 0;
+ info->accel_state->num_gb_pipes = 0;
} else {
- info->num_gb_pipes = num_pipes;
+ info->accel_state->num_gb_pipes = num_pipes;
}
}
#endif
@@ -399,34 +399,34 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
(info->ChipFamily == CHIP_FAMILY_RS400) ||
(info->ChipFamily == CHIP_FAMILY_RS480) ||
IS_R500_3D) {
- if (info->num_gb_pipes == 0) {
+ if (info->accel_state->num_gb_pipes == 0) {
uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
- info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
+ info->accel_state->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
if (IS_R500_3D)
OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
}
} else {
- if (info->num_gb_pipes == 0) {
+ if (info->accel_state->num_gb_pipes == 0) {
if ((info->ChipFamily == CHIP_FAMILY_R300) ||
(info->ChipFamily == CHIP_FAMILY_R350)) {
/* R3xx chips */
- info->num_gb_pipes = 2;
+ info->accel_state->num_gb_pipes = 2;
} else {
/* RV3xx chips */
- info->num_gb_pipes = 1;
+ info->accel_state->num_gb_pipes = 1;
}
}
}
if (IS_R300_3D || IS_R500_3D)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "num pipes is %d\n", info->num_gb_pipes);
+ "num quad-pipes is %d\n", info->accel_state->num_gb_pipes);
if (IS_R300_3D || IS_R500_3D) {
uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
- switch(info->num_gb_pipes) {
+ switch(info->accel_state->num_gb_pipes) {
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
@@ -446,11 +446,11 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
RADEONEngineReset(pScrn);
switch (info->CurrentLayout.pixel_code) {
- case 8: info->datatype = 2; break;
- case 15: info->datatype = 3; break;
- case 16: info->datatype = 4; break;
- case 24: info->datatype = 5; break;
- case 32: info->datatype = 6; break;
+ case 8: info->accel_state->datatype = 2; break;
+ case 15: info->accel_state->datatype = 3; break;
+ case 16: info->accel_state->datatype = 4; break;
+ case 24: info->accel_state->datatype = 5; break;
+ case 32: info->accel_state->datatype = 6; break;
default:
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Unknown depth/bpp = %d/%d (code = %d)\n",
@@ -458,14 +458,14 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
info->CurrentLayout.bitsPerPixel,
info->CurrentLayout.pixel_code);
}
- info->pitch = ((info->CurrentLayout.displayWidth / 8) *
- (info->CurrentLayout.pixel_bytes == 3 ? 3 : 1));
+ info->accel_state->pitch = ((info->CurrentLayout.displayWidth / 8) *
+ (info->CurrentLayout.pixel_bytes == 3 ? 3 : 1));
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Pitch for acceleration = %d\n", info->pitch);
+ "Pitch for acceleration = %d\n", info->accel_state->pitch);
- info->dp_gui_master_cntl =
- ((info->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
+ info->accel_state->dp_gui_master_cntl =
+ ((info->accel_state->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
| RADEON_GMC_CLR_CMP_CNTL_DIS
| RADEON_GMC_DST_PITCH_OFFSET_CNTL);
@@ -947,7 +947,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
if (!info->useEXA) {
XAAInfoRecPtr a;
- if (!(a = info->accel = XAACreateInfoRec())) {
+ if (!(a = info->accel_state->accel = XAACreateInfoRec())) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "XAACreateInfoRec Error\n");
return FALSE;
}
@@ -985,7 +985,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn)
#endif
RADEONInit3DEngineMMIO(pScrn);
- info->XInited3D = TRUE;
+ info->accel_state->XInited3D = TRUE;
}
#ifdef USE_XAA
diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c
index f83579f..45eb6d5 100644
--- a/src/radeon_accelfuncs.c
+++ b/src/radeon_accelfuncs.c
@@ -137,14 +137,14 @@ FUNC_NAME(RADEONSetupForSolidFill)(ScrnInfoPtr pScrn,
ACCEL_PREAMBLE();
/* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].pattern);
+ info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl
+ | RADEON_GMC_BRUSH_SOLID_COLOR
+ | RADEON_GMC_SRC_DATATYPE_COLOR
+ | RADEON_ROP[rop].pattern);
BEGIN_ACCEL(4);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, color);
OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT
@@ -172,7 +172,7 @@ FUNC_NAME(RADEONSubsequentSolidFillRect)(ScrnInfoPtr pScrn,
BEGIN_ACCEL(3);
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);
@@ -191,10 +191,10 @@ FUNC_NAME(RADEONSetupForSolidLine)(ScrnInfoPtr pScrn,
ACCEL_PREAMBLE();
/* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].pattern);
+ info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl
+ | RADEON_GMC_BRUSH_SOLID_COLOR
+ | RADEON_GMC_SRC_DATATYPE_COLOR
+ | RADEON_ROP[rop].pattern);
if (info->ChipFamily >= CHIP_FAMILY_RV200) {
BEGIN_ACCEL(1);
@@ -205,7 +205,7 @@ FUNC_NAME(RADEONSetupForSolidLine)(ScrnInfoPtr pScrn,
BEGIN_ACCEL(3);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, color);
OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
@@ -236,7 +236,7 @@ FUNC_NAME(RADEONSubsequentSolidHorVertLine)(ScrnInfoPtr pScrn,
OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT
| RADEON_DST_Y_TOP_TO_BOTTOM));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);
@@ -269,7 +269,7 @@ FUNC_NAME(RADEONSubsequentSolidTwoPointLine)(ScrnInfoPtr pScrn,
BEGIN_ACCEL(3);
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_DST_LINE_START, (ya << 16) | xa);
OUT_ACCEL_REG(RADEON_DST_LINE_END, (yb << 16) | xb);
@@ -298,8 +298,8 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn,
ACCEL_PREAMBLE();
/* Save for determining whether or not to draw last pixel */
- info->dashLen = length;
- info->dashPattern = pat;
+ info->accel_state->dashLen = length;
+ info->accel_state->dashPattern = pat;
#if X_BYTE_ORDER == X_BIG_ENDIAN
# define PAT_SHIFT(pat, shift) (pat >> shift)
@@ -315,18 +315,18 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn,
}
/* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | (bg == -1
- ? RADEON_GMC_BRUSH_32x1_MONO_FG_LA
- : RADEON_GMC_BRUSH_32x1_MONO_FG_BG)
- | RADEON_ROP[rop].pattern
- | RADEON_GMC_BYTE_LSB_TO_MSB);
- info->dash_fg = fg;
- info->dash_bg = bg;
+ info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl
+ | (bg == -1
+ ? RADEON_GMC_BRUSH_32x1_MONO_FG_LA
+ : RADEON_GMC_BRUSH_32x1_MONO_FG_BG)
+ | RADEON_ROP[rop].pattern
+ | RADEON_GMC_BYTE_LSB_TO_MSB);
+ info->accel_state->dash_fg = fg;
+ info->accel_state->dash_bg = bg;
BEGIN_ACCEL((bg == -1) ? 4 : 5);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg);
if (bg != -1)
@@ -348,7 +348,7 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn,
int fg)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- uint32_t dp_gui_master_cntl = info->dp_gui_master_cntl_clip;
+ uint32_t dp_gui_master_cntl = info->accel_state->dp_gui_master_cntl_clip;
ACCEL_PREAMBLE();
dp_gui_master_cntl &= ~RADEON_GMC_BRUSH_DATATYPE_MASK;
@@ -362,15 +362,15 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn,
OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, dp_gui_master_cntl);
OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT
| RADEON_DST_Y_TOP_TO_BOTTOM));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg);
OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (1 << 16) | 1);
/* Restore old values */
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->dash_fg);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->accel_state->dash_fg);
FINISH_ACCEL();
BEGIN_ACCEL(2);
@@ -402,17 +402,17 @@ FUNC_NAME(RADEONSubsequentDashedTwoPointLine)(ScrnInfoPtr pScrn,
else shift = deltay;
shift += phase;
- shift %= info->dashLen;
+ shift %= info->accel_state->dashLen;
- if ((info->dashPattern >> shift) & 1)
- FUNC_NAME(RADEONDashedLastPel)(pScrn, xb, yb, info->dash_fg);
- else if (info->dash_bg != -1)
- FUNC_NAME(RADEONDashedLastPel)(pScrn, xb, yb, info->dash_bg);
+ if ((info->accel_state->dashPattern >> shift) & 1)
+ FUNC_NAME(RADEONDashedLastPel)(pScrn, xb, yb, info->accel_state->dash_fg);
+ else if (info->accel_state->dash_bg != -1)
+ FUNC_NAME(RADEONDashedLastPel)(pScrn, xb, yb, info->accel_state->dash_bg);
}
BEGIN_ACCEL(4);
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_DST_LINE_START, (ya << 16) | xa);
OUT_ACCEL_REG(RADEON_DST_LINE_PATCOUNT, phase);
@@ -433,7 +433,7 @@ FUNC_NAME(RADEONSetTransparency)(ScrnInfoPtr pScrn,
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- if ((trans_color != -1) || (info->XAAForceTransBlit == TRUE)) {
+ if ((trans_color != -1) || (info->accel_state->XAAForceTransBlit == TRUE)) {
ACCEL_PREAMBLE();
BEGIN_ACCEL(3);
@@ -461,20 +461,20 @@ FUNC_NAME(RADEONSetupForScreenToScreenCopy)(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
ACCEL_PREAMBLE();
- info->xdir = xdir;
- info->ydir = ydir;
+ info->accel_state->xdir = xdir;
+ info->accel_state->ydir = ydir;
/* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_BRUSH_NONE
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].rop
- | RADEON_DP_SRC_SOURCE_MEMORY
- | RADEON_GMC_SRC_PITCH_OFFSET_CNTL);
+ info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl
+ | RADEON_GMC_BRUSH_NONE
+ | RADEON_GMC_SRC_DATATYPE_COLOR
+ | RADEON_ROP[rop].rop
+ | RADEON_DP_SRC_SOURCE_MEMORY
+ | RADEON_GMC_SRC_PITCH_OFFSET_CNTL);
BEGIN_ACCEL(3);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
OUT_ACCEL_REG(RADEON_DP_CNTL,
((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
@@ -487,7 +487,7 @@ FUNC_NAME(RADEONSetupForScreenToScreenCopy)(ScrnInfoPtr pScrn,
RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
FINISH_ACCEL();
- info->trans_color = trans_color;
+ info->accel_state->trans_color = trans_color;
FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color);
}
@@ -501,14 +501,14 @@ FUNC_NAME(RADEONSubsequentScreenToScreenCopy)(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
ACCEL_PREAMBLE();
- if (info->xdir < 0) xa += w - 1, xb += w - 1;
- if (info->ydir < 0) ya += h - 1, yb += h - 1;
+ if (info->accel_state->xdir < 0) xa += w - 1, xb += w - 1;
+ if (info->accel_state->ydir < 0) ya += h - 1, yb += h - 1;
BEGIN_ACCEL(5);
- OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (yb <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_SRC_Y_X, (ya << 16) | xa);
OUT_ACCEL_REG(RADEON_DST_Y_X, (yb << 16) | xb);
@@ -552,19 +552,19 @@ FUNC_NAME(RADEONSetupForMono8x8PatternFill)(ScrnInfoPtr pScrn,
#endif
/* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | (bg == -1
- ? RADEON_GMC_BRUSH_8X8_MONO_FG_LA
- : RADEON_GMC_BRUSH_8X8_MONO_FG_BG)
- | RADEON_ROP[rop].pattern
+ info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl
+ | (bg == -1
+ ? RADEON_GMC_BRUSH_8X8_MONO_FG_LA
+ : RADEON_GMC_BRUSH_8X8_MONO_FG_BG)
+ | RADEON_ROP[rop].pattern
#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- | RADEON_GMC_BYTE_MSB_TO_LSB
+ | RADEON_GMC_BYTE_MSB_TO_LSB
#endif
- );
+ );
BEGIN_ACCEL((bg == -1) ? 5 : 6);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg);
if (bg != -1)
@@ -600,7 +600,7 @@ FUNC_NAME(RADEONSubsequentMono8x8PatternFillRect)(ScrnInfoPtr pScrn,
BEGIN_ACCEL(4);
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_BRUSH_Y_X, (patterny << 8) | patternx);
OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
@@ -625,21 +625,21 @@ FUNC_NAME(RADEONSetupForColor8x8PatternFill)(ScrnInfoPtr pScrn,
ACCEL_PREAMBLE();
/* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_BRUSH_8x8_COLOR
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].pattern
- | RADEON_DP_SRC_SOURCE_MEMORY);
+ info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl
+ | RADEON_GMC_BRUSH_8x8_COLOR
+ | RADEON_GMC_SRC_DATATYPE_COLOR
+ | RADEON_ROP[rop].pattern
+ | RADEON_DP_SRC_SOURCE_MEMORY);
BEGIN_ACCEL(3);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
OUT_ACCEL_REG(RADEON_SRC_Y_X, (paty << 16) | patx);
FINISH_ACCEL();
- info->trans_color = trans_color;
+ info->accel_state->trans_color = trans_color;
FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color);
}
@@ -655,7 +655,7 @@ FUNC_NAME(RADEONSubsequentColor8x8PatternFillRect)(ScrnInfoPtr pScrn,
BEGIN_ACCEL(4);
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_BRUSH_Y_X, (paty << 16) | patx);
OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
@@ -675,41 +675,41 @@ static void
RADEONCPScanlinePacket(ScrnInfoPtr pScrn, int bufno)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- int chunk_words = info->scanline_hpass * info->scanline_words;
+ int chunk_words = info->accel_state->scanline_hpass * info->accel_state->scanline_words;
ACCEL_PREAMBLE();
if (RADEON_VERBOSE) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"CPScanline Packet h=%d hpass=%d chunkwords=%d\n",
- info->scanline_h, info->scanline_hpass, chunk_words);
+ info->accel_state->scanline_h, info->accel_state->scanline_hpass, chunk_words);
}
BEGIN_RING(chunk_words+10);
OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT,chunk_words+10-2));
- OUT_RING(info->dp_gui_master_cntl_clip);
- OUT_RING(info->dst_pitch_offset |
- ((info->tilingEnabled && (info->scanline_y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_RING((info->scanline_y << 16) |
- (info->scanline_x1clip & 0xffff));
- OUT_RING(((info->scanline_y+info->scanline_hpass) << 16) |
- (info->scanline_x2clip & 0xffff));
- OUT_RING(info->scanline_fg);
- OUT_RING(info->scanline_bg);
- OUT_RING((info->scanline_y << 16) |
- (info->scanline_x & 0xffff));
- OUT_RING((info->scanline_hpass << 16) |
- (info->scanline_w & 0xffff));
+ OUT_RING(info->accel_state->dp_gui_master_cntl_clip);
+ OUT_RING(info->accel_state->dst_pitch_offset |
+ ((info->tilingEnabled && (info->accel_state->scanline_y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
+ OUT_RING((info->accel_state->scanline_y << 16) |
+ (info->accel_state->scanline_x1clip & 0xffff));
+ OUT_RING(((info->accel_state->scanline_y+info->accel_state->scanline_hpass) << 16) |
+ (info->accel_state->scanline_x2clip & 0xffff));
+ OUT_RING(info->accel_state->scanline_fg);
+ OUT_RING(info->accel_state->scanline_bg);
+ OUT_RING((info->accel_state->scanline_y << 16) |
+ (info->accel_state->scanline_x & 0xffff));
+ OUT_RING((info->accel_state->scanline_hpass << 16) |
+ (info->accel_state->scanline_w & 0xffff));
OUT_RING(chunk_words);
- info->scratch_buffer[bufno] = (unsigned char *)&__head[__count];
+ info->accel_state->scratch_buffer[bufno] = (unsigned char *)&__head[__count];
__count += chunk_words;
/* The ring can only be advanced after the __head and __count have
been adjusted above */
FINISH_ACCEL();
- info->scanline_y += info->scanline_hpass;
- info->scanline_h -= info->scanline_hpass;
+ info->accel_state->scanline_y += info->accel_state->scanline_hpass;
+ info->accel_state->scanline_h -= info->accel_state->scanline_hpass;
}
#endif
@@ -729,22 +729,22 @@ FUNC_NAME(RADEONSetupForScanlineCPUToScreenColorExpandFill)(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
ACCEL_PREAMBLE();
- info->scanline_bpp = 0;
+ info->accel_state->scanline_bpp = 0;
/* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_DST_CLIPPING
- | RADEON_GMC_BRUSH_NONE
- | (bg == -1
- ? RADEON_GMC_SRC_DATATYPE_MONO_FG_LA
- : RADEON_GMC_SRC_DATATYPE_MONO_FG_BG)
- | RADEON_ROP[rop].rop
+ info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl
+ | RADEON_GMC_DST_CLIPPING
+ | RADEON_GMC_BRUSH_NONE
+ | (bg == -1
+ ? RADEON_GMC_SRC_DATATYPE_MONO_FG_LA
+ : RADEON_GMC_SRC_DATATYPE_MONO_FG_BG)
+ | RADEON_ROP[rop].rop
#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- | RADEON_GMC_BYTE_LSB_TO_MSB
+ | RADEON_GMC_BYTE_LSB_TO_MSB
#else
- | RADEON_GMC_BYTE_MSB_TO_LSB
+ | RADEON_GMC_BYTE_MSB_TO_LSB
#endif
- | RADEON_DP_SRC_SOURCE_HOST_DATA);
+ | RADEON_DP_SRC_SOURCE_HOST_DATA);
#ifdef ACCEL_MMIO
@@ -755,15 +755,15 @@ FUNC_NAME(RADEONSetupForScanlineCPUToScreenColorExpandFill)(ScrnInfoPtr pScrn,
OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE);
#endif
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
OUT_ACCEL_REG(RADEON_DP_SRC_FRGD_CLR, fg);
OUT_ACCEL_REG(RADEON_DP_SRC_BKGD_CLR, bg);
#else /* ACCEL_CP */
- info->scanline_fg = fg;
- info->scanline_bg = bg;
+ info->accel_state->scanline_fg = fg;
+ info->accel_state->scanline_bg = bg;
#if X_BYTE_ORDER == X_LITTLE_ENDIAN
BEGIN_ACCEL(1);
@@ -796,31 +796,31 @@ FUNC_NAME(RADEONSubsequentScanlineCPUToScreenColorExpandFill)(ScrnInfoPtr
#ifdef ACCEL_MMIO
ACCEL_PREAMBLE();
- info->scanline_h = h;
- info->scanline_words = (w + 31) >> 5;
+ info->accel_state->scanline_h = h;
+ info->accel_state->scanline_words = (w + 31) >> 5;
#ifdef __alpha__
/* Always use indirect for Alpha */
if (0)
#else
- if ((info->scanline_words * h) <= 9)
+ if ((info->accel_state->scanline_words * h) <= 9)
#endif
{
/* Turn on direct for less than 9 dword colour expansion */
- info->scratch_buffer[0] =
+ info->accel_state->scratch_buffer[0] =
(unsigned char *)(ADDRREG(RADEON_HOST_DATA_LAST)
- - (info->scanline_words - 1));
- info->scanline_direct = 1;
+ - (info->accel_state->scanline_words - 1));
+ info->accel_state->scanline_direct = 1;
} else {
/* Use indirect for anything else */
- info->scratch_buffer[0] = info->scratch_save;
- info->scanline_direct = 0;
+ info->accel_state->scratch_buffer[0] = info->accel_state->scratch_save;
+ info->accel_state->scanline_direct = 0;
}
- BEGIN_ACCEL(5 + (info->scanline_direct ?
- (info->scanline_words * h) : 0));
+ BEGIN_ACCEL(5 + (info->accel_state->scanline_direct ?
+ (info->accel_state->scanline_words * h) : 0));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft)
& 0xffff));
@@ -833,17 +833,17 @@ FUNC_NAME(RADEONSubsequentScanlineCPUToScreenColorExpandFill)(ScrnInfoPtr
#else /* ACCEL_CP */
- info->scanline_x = x;
- info->scanline_y = y;
+ info->accel_state->scanline_x = x;
+ info->accel_state->scanline_y = y;
/* Have to pad the width here and use clipping engine */
- info->scanline_w = (w + 31) & ~31;
- info->scanline_h = h;
+ info->accel_state->scanline_w = (w + 31) & ~31;
+ info->accel_state->scanline_h = h;
- info->scanline_x1clip = x + skipleft;
- info->scanline_x2clip = x + w;
+ info->accel_state->scanline_x1clip = x + skipleft;
+ info->accel_state->scanline_x2clip = x + w;
- info->scanline_words = info->scanline_w / 32;
- info->scanline_hpass = min(h,(CP_BUFSIZE/info->scanline_words));
+ info->accel_state->scanline_words = info->accel_state->scanline_w / 32;
+ info->accel_state->scanline_hpass = min(h,(CP_BUFSIZE/info->accel_state->scanline_words));
RADEONCPScanlinePacket(pScrn, 0);
@@ -859,21 +859,21 @@ FUNC_NAME(RADEONSubsequentScanline)(ScrnInfoPtr pScrn,
{
RADEONInfoPtr info = RADEONPTR(pScrn);
#ifdef ACCEL_MMIO
- uint32_t *p = (pointer)info->scratch_buffer[bufno];
+ uint32_t *p = (pointer)info->accel_state->scratch_buffer[bufno];
int i;
- int left = info->scanline_words;
+ int left = info->accel_state->scanline_words;
volatile uint32_t *d;
ACCEL_PREAMBLE();
- if (info->scanline_direct) return;
+ if (info->accel_state->scanline_direct) return;
- --info->scanline_h;
+ --info->accel_state->scanline_h;
while (left) {
write_mem_barrier();
if (left <= 8) {
/* Last scanline - finish write to DATA_LAST */
- if (info->scanline_h == 0) {
+ if (info->accel_state->scanline_h == 0) {
BEGIN_ACCEL(left);
/* Unrolling doesn't improve performance */
for (d = ADDRREG(RADEON_HOST_DATA_LAST) - (left - 1); left; --left)
@@ -900,25 +900,25 @@ FUNC_NAME(RADEONSubsequentScanline)(ScrnInfoPtr pScrn,
#if X_BYTE_ORDER == X_BIG_ENDIAN
if (info->ChipFamily >= CHIP_FAMILY_R300) {
- if (info->scanline_bpp == 16) {
- RADEONCopySwap(info->scratch_buffer[bufno],
- info->scratch_buffer[bufno],
- info->scanline_words << 2,
+ if (info->accel_state->scanline_bpp == 16) {
+ RADEONCopySwap(info->accel_state->scratch_buffer[bufno],
+ info->accel_state->scratch_buffer[bufno],
+ info->accel_state->scanline_words << 2,
RADEON_HOST_DATA_SWAP_HDW);
- } else if (info->scanline_bpp < 15) {
- RADEONCopySwap(info->scratch_buffer[bufno],
- info->scratch_buffer[bufno],
- info->scanline_words << 2,
+ } else if (info->accel_state->scanline_bpp < 15) {
+ RADEONCopySwap(info->accel_state->scratch_buffer[bufno],
+ info->accel_state->scratch_buffer[bufno],
+ info->accel_state->scanline_words << 2,
RADEON_HOST_DATA_SWAP_32BIT);
}
}
#endif
- if (--info->scanline_hpass) {
- info->scratch_buffer[bufno] += 4 * info->scanline_words;
- } else if (info->scanline_h) {
- info->scanline_hpass =
- min(info->scanline_h,(CP_BUFSIZE/info->scanline_words));
+ if (--info->accel_state->scanline_hpass) {
+ info->accel_state->scratch_buffer[bufno] += 4 * info->accel_state->scanline_words;
+ } else if (info->accel_state->scanline_h) {
+ info->accel_state->scanline_hpass =
+ min(info->accel_state->scanline_h,(CP_BUFSIZE/info->accel_state->scanline_words));
RADEONCPScanlinePacket(pScrn, bufno);
}
@@ -937,16 +937,16 @@ FUNC_NAME(RADEONSetupForScanlineImageWrite)(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
ACCEL_PREAMBLE();
- info->scanline_bpp = bpp;
+ info->accel_state->scanline_bpp = bpp;
/* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_DST_CLIPPING
- | RADEON_GMC_BRUSH_NONE
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].rop
- | RADEON_GMC_BYTE_MSB_TO_LSB
- | RADEON_DP_SRC_SOURCE_HOST_DATA);
+ info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl
+ | RADEON_GMC_DST_CLIPPING
+ | RADEON_GMC_BRUSH_NONE
+ | RADEON_GMC_SRC_DATATYPE_COLOR
+ | RADEON_ROP[rop].rop
+ | RADEON_GMC_BYTE_MSB_TO_LSB
+ | RADEON_DP_SRC_SOURCE_HOST_DATA);
#ifdef ACCEL_MMIO
@@ -962,7 +962,7 @@ FUNC_NAME(RADEONSetupForScanlineImageWrite)(ScrnInfoPtr pScrn,
else
OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE);
#endif
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
#else /* ACCEL_CP */
@@ -984,7 +984,7 @@ FUNC_NAME(RADEONSetupForScanlineImageWrite)(ScrnInfoPtr pScrn,
FINISH_ACCEL();
- info->trans_color = trans_color;
+ info->accel_state->trans_color = trans_color;
FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color);
}
@@ -1007,31 +1007,31 @@ FUNC_NAME(RADEONSubsequentScanlineImageWriteRect)(ScrnInfoPtr pScrn,
if (pScrn->bitsPerPixel == 8) shift = 3;
else if (pScrn->bitsPerPixel == 16) shift = 1;
- info->scanline_h = h;
- info->scanline_words = (w * info->scanline_bpp + 31) >> 5;
+ info->accel_state->scanline_h = h;
+ info->accel_state->scanline_words = (w * info->accel_state->scanline_bpp + 31) >> 5;
#ifdef __alpha__
/* Always use indirect for Alpha */
if (0)
#else
- if ((info->scanline_words * h) <= 9)
+ if ((info->accel_state->scanline_words * h) <= 9)
#endif
{
/* Turn on direct for less than 9 dword colour expansion */
- info->scratch_buffer[0]
+ info->accel_state->scratch_buffer[0]
= (unsigned char *)(ADDRREG(RADEON_HOST_DATA_LAST)
- - (info->scanline_words - 1));
- info->scanline_direct = 1;
+ - (info->accel_state->scanline_words - 1));
+ info->accel_state->scanline_direct = 1;
} else {
/* Use indirect for anything else */
- info->scratch_buffer[0] = info->scratch_save;
- info->scanline_direct = 0;
+ info->accel_state->scratch_buffer[0] = info->accel_state->scratch_save;
+ info->accel_state->scanline_direct = 0;
}
- BEGIN_ACCEL(5 + (info->scanline_direct ?
- (info->scanline_words * h) : 0));
+ BEGIN_ACCEL(5 + (info->accel_state->scanline_direct ?
+ (info->accel_state->scanline_words * h) : 0));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
+ OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft)
& 0xffff));
@@ -1050,17 +1050,17 @@ FUNC_NAME(RADEONSubsequentScanlineImageWriteRect)(ScrnInfoPtr pScrn,
if (pScrn->bitsPerPixel == 8) pad = 3;
else if (pScrn->bitsPerPixel == 16) pad = 1;
- info->scanline_x = x;
- info->scanline_y = y;
+ info->accel_state->scanline_x = x;
+ info->accel_state->scanline_y = y;
/* Have to pad the width here and use clipping engine */
- info->scanline_w = (w + pad) & ~pad;
- info->scanline_h = h;
+ info->accel_state->scanline_w = (w + pad) & ~pad;
+ info->accel_state->scanline_h = h;
- info->scanline_x1clip = x + skipleft;
- info->scanline_x2clip = x + w;
+ info->accel_state->scanline_x1clip = x + skipleft;
+ info->accel_state->scanline_x2clip = x + w;
- info->scanline_words = (w * info->scanline_bpp + 31) / 32;
- info->scanline_hpass = min(h,(CP_BUFSIZE/info->scanline_words));
+ info->accel_state->scanline_words = (w * info->accel_state->scanline_bpp + 31) / 32;
+ info->accel_state->scanline_hpass = min(h,(CP_BUFSIZE/info->accel_state->scanline_words));
RADEONCPScanlinePacket(pScrn, 0);
@@ -1110,7 +1110,7 @@ FUNC_NAME(RADEONSetClippingRectangle)(ScrnInfoPtr pScrn,
BEGIN_ACCEL(3);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl_clip
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, (info->accel_state->dp_gui_master_cntl_clip
| RADEON_GMC_DST_CLIPPING));
OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, tmp1);
OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, tmp2);
@@ -1122,7 +1122,7 @@ FUNC_NAME(RADEONSetClippingRectangle)(ScrnInfoPtr pScrn,
RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
FINISH_ACCEL();
- FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color);
+ FUNC_NAME(RADEONSetTransparency)(pScrn, info->accel_state->trans_color);
}
/* Disable the clipping rectangle */
@@ -1134,7 +1134,7 @@ FUNC_NAME(RADEONDisableClipping)(ScrnInfoPtr pScrn)
BEGIN_ACCEL(3);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
+ OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, 0);
OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX |
RADEON_DEFAULT_SC_BOTTOM_MAX));
@@ -1146,7 +1146,7 @@ FUNC_NAME(RADEONDisableClipping)(ScrnInfoPtr pScrn)
RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
FINISH_ACCEL();
- FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color);
+ FUNC_NAME(RADEONSetTransparency)(pScrn, info->accel_state->trans_color);
}
void
@@ -1203,12 +1203,12 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
| ROP_NEEDS_SOURCE
| LEFT_EDGE_CLIPPING_NEGATIVE_X);
a->NumScanlineColorExpandBuffers = 1;
- a->ScanlineColorExpandBuffers = info->scratch_buffer;
- if (!info->scratch_save)
- info->scratch_save
+ a->ScanlineColorExpandBuffers = info->accel_state->scratch_buffer;
+ if (!info->accel_state->scratch_save)
+ info->accel_state->scratch_save
= xalloc(((pScrn->virtualX+31)/32*4)
+ (pScrn->virtualX * info->CurrentLayout.pixel_bytes));
- info->scratch_buffer[0] = info->scratch_save;
+ info->accel_state->scratch_buffer[0] = info->accel_state->scratch_save;
a->SetupForScanlineCPUToScreenColorExpandFill
= FUNC_NAME(RADEONSetupForScanlineCPUToScreenColorExpandFill);
a->SubsequentScanlineCPUToScreenColorExpandFill
@@ -1299,7 +1299,7 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
/* ImageWrite */
a->NumScanlineImageWriteBuffers = 1;
- a->ScanlineImageWriteBuffers = info->scratch_buffer;
+ a->ScanlineImageWriteBuffers = info->accel_state->scratch_buffer;
a->SetupForScanlineImageWrite
= FUNC_NAME(RADEONSetupForScanlineImageWrite);
a->SubsequentScanlineImageWriteRect
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 00def66..a70a275 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -58,7 +58,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
uint32_t gb_tile_config, su_reg_dest, vap_cntl;
ACCEL_PREAMBLE();
- info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
+ info->accel_state->texW[0] = info->accel_state->texH[0] =
+ info->accel_state->texW[1] = info->accel_state->texH[1] = 1;
if (IS_R300_3D || IS_R500_3D) {
@@ -70,7 +71,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
- switch(info->num_gb_pipes) {
+ switch(info->accel_state->num_gb_pipes) {
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
@@ -87,7 +88,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
FINISH_ACCEL();
if (IS_R500_3D) {
- su_reg_dest = ((1 << info->num_gb_pipes) - 1);
+ su_reg_dest = ((1 << info->accel_state->num_gb_pipes) - 1);
BEGIN_ACCEL(2);
OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0);
@@ -146,7 +147,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
FINISH_ACCEL();
/* setup the VAP */
- if (info->has_tcl)
+ if (info->accel_state->has_tcl)
vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) |
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
(9 << R300_VF_MAX_VTX_NUM_SHIFT));
@@ -170,14 +171,14 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
else
vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
- if (info->has_tcl)
+ if (info->accel_state->has_tcl)
BEGIN_ACCEL(15);
else
BEGIN_ACCEL(9);
OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0);
OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- if (info->has_tcl)
+ if (info->accel_state->has_tcl)
OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
else
OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
@@ -207,7 +208,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_2_SHIFT)));
- if (info->has_tcl) {
+ if (info->accel_state->has_tcl) {
OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
@@ -218,7 +219,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
FINISH_ACCEL();
/* pre-load the vertex shaders */
- if (info->has_tcl) {
+ if (info->accel_state->has_tcl) {
/* exa mask/Xv bicubic shader program */
BEGIN_ACCEL(13);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
diff --git a/src/radeon_dga.c b/src/radeon_dga.c
index d623fe4..1d4d6ca 100644
--- a/src/radeon_dga.c
+++ b/src/radeon_dga.c
@@ -126,12 +126,12 @@ SECOND_PASS:
}
#endif /* USE_EXA */
#ifdef USE_XAA
- if (!info->useEXA && info->accel) {
- if (info->accel->SetupForSolidFill &&
- info->accel->SubsequentSolidFillRect)
+ if (!info->useEXA && info->accel_state->accel) {
+ if (info->accel_state->accel->SetupForSolidFill &&
+ info->accel_state->accel->SubsequentSolidFillRect)
currentMode->flags |= DGA_FILL_RECT;
- if (info->accel->SetupForScreenToScreenCopy &&
- info->accel->SubsequentScreenToScreenCopy)
+ if (info->accel_state->accel->SetupForScreenToScreenCopy &&
+ info->accel_state->accel->SubsequentScreenToScreenCopy)
currentMode->flags |= DGA_BLIT_RECT | DGA_BLIT_RECT_TRANS;
if (currentMode->flags &
(DGA_PIXMAP_AVAILABLE | DGA_FILL_RECT |
@@ -265,13 +265,13 @@ Bool RADEONDGAInit(ScreenPtr pScreen)
}
#endif /* USE_EXA */
#ifdef USE_XAA
- if (!info->useEXA && info->accel) {
- info->DGAFuncs.Sync = info->accel->Sync;
- if (info->accel->SetupForSolidFill &&
- info->accel->SubsequentSolidFillRect)
+ if (!info->useEXA && info->accel_state->accel) {
+ info->DGAFuncs.Sync = info->accel_state->accel->Sync;
+ if (info->accel_state->accel->SetupForSolidFill &&
+ info->accel_state->accel->SubsequentSolidFillRect)
info->DGAFuncs.FillRect = RADEON_FillRect;
- if (info->accel->SetupForScreenToScreenCopy &&
- info->accel->SubsequentScreenToScreenCopy) {
+ if (info->accel_state->accel->SetupForScreenToScreenCopy &&
+ info->accel_state->accel->SubsequentScreenToScreenCopy) {
info->DGAFuncs.BlitRect = RADEON_BlitRect;
info->DGAFuncs.BlitTransRect = RADEON_BlitTransRect;
}
@@ -383,8 +383,8 @@ static void RADEON_FillRect(ScrnInfoPtr pScrn,
#endif /* USE_EXA */
#ifdef USE_XAA
if (!info->useEXA) {
- (*info->accel->SetupForSolidFill)(pScrn, color, GXcopy, (uint32_t)(~0));
- (*info->accel->SubsequentSolidFillRect)(pScrn, x, y, w, h);
+ (*info->accel_state->accel->SetupForSolidFill)(pScrn, color, GXcopy, (uint32_t)(~0));
+ (*info->accel_state->accel->SubsequentSolidFillRect)(pScrn, x, y, w, h);
if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel)
RADEON_MARK_SYNC(info, pScrn);
}
@@ -413,10 +413,10 @@ static void RADEON_BlitRect(ScrnInfoPtr pScrn,
#endif /* USE_EXA */
#ifdef USE_XAA
if (!info->useEXA) {
- (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir,
- GXcopy, (uint32_t)(~0), -1);
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn, srcx, srcy,
- dstx, dsty, w, h);
+ (*info->accel_state->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir,
+ GXcopy, (uint32_t)(~0), -1);
+ (*info->accel_state->accel->SubsequentScreenToScreenCopy)(pScrn, srcx, srcy,
+ dstx, dsty, w, h);
if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel)
RADEON_MARK_SYNC(info, pScrn);
}
@@ -431,14 +431,14 @@ static void RADEON_BlitTransRect(ScrnInfoPtr pScrn,
int xdir = ((srcx < dstx) && (srcy == dsty)) ? -1 : 1;
int ydir = (srcy < dsty) ? -1 : 1;
- info->XAAForceTransBlit = TRUE;
- (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir,
- GXcopy, (uint32_t)(~0), color);
+ info->accel_state->XAAForceTransBlit = TRUE;
+ (*info->accel_state->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir,
+ GXcopy, (uint32_t)(~0), color);
- info->XAAForceTransBlit = FALSE;
+ info->accel_state->XAAForceTransBlit = FALSE;
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn, srcx, srcy,
- dstx, dsty, w, h);
+ (*info->accel_state->accel->SubsequentScreenToScreenCopy)(pScrn, srcx, srcy,
+ dstx, dsty, w, h);
if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel)
RADEON_MARK_SYNC(info, pScrn);
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index c0b809c..c10301b 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -363,7 +363,7 @@ static void RADEONEnterServer(ScreenPtr pScreen)
pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
if (pSAREAPriv->ctxOwner != DRIGetContext(pScrn->pScreen)) {
- info->XInited3D = FALSE;
+ info->accel_state->XInited3D = FALSE;
info->cp->needCacheFlush = (info->ChipFamily >= CHIP_FAMILY_R300);
}
@@ -417,7 +417,7 @@ static void RADEONLeaveServer(ScreenPtr pScreen)
RADEONCP_RELEASE(pScrn, info);
#ifdef USE_EXA
- info->engineMode = EXA_ENGINEMODE_UNKNOWN;
+ info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
#endif
}
@@ -641,12 +641,12 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
}
/* pretty much a hack. */
- info->dst_pitch_offset = info->backPitchOffset;
+ info->accel_state->dst_pitch_offset = info->backPitchOffset;
if (info->tilingEnabled)
- info->dst_pitch_offset |= RADEON_DST_TILE_MACRO;
+ info->accel_state->dst_pitch_offset |= RADEON_DST_TILE_MACRO;
- (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, GXcopy,
- (uint32_t)(-1), -1);
+ (*info->accel_state->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, GXcopy,
+ (uint32_t)(-1), -1);
for (; nbox-- ; pbox++) {
int xa = pbox->x1;
@@ -664,10 +664,10 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
if (w <= 0) continue;
if (h <= 0) continue;
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn,
- xa, ya,
- destx, desty,
- w, h);
+ (*info->accel_state->accel->SubsequentScreenToScreenCopy)(pScrn,
+ xa, ya,
+ destx, desty,
+ w, h);
if (info->depthMoves) {
RADEONScreenToScreenCopyDepth(pScrn,
@@ -677,14 +677,14 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
}
}
- info->dst_pitch_offset = info->frontPitchOffset;;
+ info->accel_state->dst_pitch_offset = info->frontPitchOffset;;
xfree(pptNew2);
xfree(pboxNew2);
xfree(pptNew1);
xfree(pboxNew1);
- info->accel->NeedToSync = TRUE;
+ info->accel_state->accel->NeedToSync = TRUE;
#endif /* USE_XAA */
}
@@ -1239,7 +1239,7 @@ static void RADEONDRICPInit(ScrnInfoPtr pScrn)
RADEONCP_START(pScrn, info);
#ifdef USE_XAA
if (!info->useEXA)
- info->dst_pitch_offset = info->frontPitchOffset;
+ info->accel_state->dst_pitch_offset = info->frontPitchOffset;
#endif
}
@@ -1926,7 +1926,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset);
dst_pitch_offset = src_pitch_offset + (info->backOffset >> 10);
RADEONGetDatatypeBpp(pScrn->bitsPerPixel, &datatype);
- info->xdir = info->ydir = 1;
+ info->accel_state->xdir = info->accel_state->ydir = 1;
RADEONDoPrepareCopyCP(pScrn, src_pitch_offset, dst_pitch_offset, datatype,
GXcopy, ~0);
@@ -1936,13 +1936,14 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
#ifdef USE_XAA
if (!info->useEXA) {
/* Make sure accel has been properly inited */
- if (info->accel == NULL || info->accel->SetupForScreenToScreenCopy == NULL)
+ if (info->accel_state->accel == NULL ||
+ info->accel_state->accel->SetupForScreenToScreenCopy == NULL)
goto out;
if (info->tilingEnabled)
- info->dst_pitch_offset |= RADEON_DST_TILE_MACRO;
- (*info->accel->SetupForScreenToScreenCopy)(pScrn,
- 1, 1, GXcopy,
- (uint32_t)(-1), -1);
+ info->accel_state->dst_pitch_offset |= RADEON_DST_TILE_MACRO;
+ (*info->accel_state->accel->SetupForScreenToScreenCopy)(pScrn,
+ 1, 1, GXcopy,
+ (uint32_t)(-1), -1);
}
#endif
@@ -1959,18 +1960,18 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
#ifdef USE_XAA
if (!info->useEXA) {
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn, xa, ya,
- xa + info->backX,
- ya + info->backY,
- xb - xa + 1,
- yb - ya + 1);
+ (*info->accel_state->accel->SubsequentScreenToScreenCopy)(pScrn, xa, ya,
+ xa + info->backX,
+ ya + info->backY,
+ xb - xa + 1,
+ yb - ya + 1);
}
#endif
}
}
#ifdef USE_XAA
- info->dst_pitch_offset &= ~RADEON_DST_TILE_MACRO;
+ info->accel_state->dst_pitch_offset &= ~RADEON_DST_TILE_MACRO;
#endif
out:
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 3e3d0b5..d485865 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1174,7 +1174,6 @@ static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn)
xf86PrintDepthBpp(pScrn);
- info->fifo_slots = 0;
info->pix24bpp = xf86GetBppFromDepth(pScrn,
pScrn->depth);
info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel;
@@ -1907,20 +1906,6 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
return FALSE;
}
-
- if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200) ||
- (info->ChipFamily == CHIP_FAMILY_RS300) ||
- (info->ChipFamily == CHIP_FAMILY_RS400) ||
- (info->ChipFamily == CHIP_FAMILY_RS480) ||
- (info->ChipFamily == CHIP_FAMILY_RS600) ||
- (info->ChipFamily == CHIP_FAMILY_RS690) ||
- (info->ChipFamily == CHIP_FAMILY_RS740))
- info->has_tcl = FALSE;
- else {
- info->has_tcl = TRUE;
- }
-
return TRUE;
}
@@ -1974,6 +1959,25 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
char *optstr;
#endif
+ if (!(info->accel_state = xcalloc(1, sizeof(struct radeon_accel_state)))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n");
+ return FALSE;
+ }
+ info->accel_state->fifo_slots = 0;
+
+ if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS200) ||
+ (info->ChipFamily == CHIP_FAMILY_RS300) ||
+ (info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480) ||
+ (info->ChipFamily == CHIP_FAMILY_RS600) ||
+ (info->ChipFamily == CHIP_FAMILY_RS690) ||
+ (info->ChipFamily == CHIP_FAMILY_RS740))
+ info->accel_state->has_tcl = FALSE;
+ else {
+ info->accel_state->has_tcl = TRUE;
+ }
+
info->useEXA = FALSE;
if (info->ChipFamily >= CHIP_FAMILY_R600) {
@@ -3097,12 +3101,12 @@ static void RADEONBlockHandler(int i, pointer blockData,
(*info->VideoTimerCallback)(pScrn, currentTime.milliseconds);
#if defined(RENDER) && defined(USE_XAA)
- if(info->RenderCallback)
- (*info->RenderCallback)(pScrn);
+ if(info->accel_state->RenderCallback)
+ (*info->accel_state->RenderCallback)(pScrn);
#endif
#ifdef USE_EXA
- info->engineMode = EXA_ENGINEMODE_UNKNOWN;
+ info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
#endif
}
@@ -3195,7 +3199,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->accelOn = FALSE;
#ifdef USE_XAA
- info->accel = NULL;
+ info->accel_state->accel = NULL;
#endif
#ifdef XF86DRI
pScrn->fbOffset = info->frontOffset;
@@ -3397,8 +3401,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
return FALSE;
#endif
- info->dst_pitch_offset = (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
- << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
+ info->accel_state->dst_pitch_offset =
+ (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
+ << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
/* Setup DRI after visuals have been established, but before fbScreenInit is
* called. fbScreenInit will eventually call the driver's InitGLXVisuals
@@ -3930,7 +3935,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
else
info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
- info->dst_pitch_offset =
+ info->accel_state->dst_pitch_offset =
(((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
<< 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
RADEONInitMemMapRegisters(pScrn, save, info);
@@ -5578,9 +5583,9 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
#endif
#ifdef USE_XAA
- if(!info->useEXA && info->RenderTex) {
- xf86FreeOffscreenLinear(info->RenderTex);
- info->RenderTex = NULL;
+ if(!info->useEXA && info->accel_state->RenderTex) {
+ xf86FreeOffscreenLinear(info->accel_state->RenderTex);
+ info->accel_state->RenderTex = NULL;
}
#endif /* USE_XAA */
@@ -5591,21 +5596,21 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Disposing accel...\n");
#ifdef USE_EXA
- if (info->exa) {
+ if (info->accel_state->exa) {
exaDriverFini(pScreen);
- xfree(info->exa);
- info->exa = NULL;
+ xfree(info->accel_state->exa);
+ info->accel_state->exa = NULL;
}
#endif /* USE_EXA */
#ifdef USE_XAA
if (!info->useEXA) {
- if (info->accel)
- XAADestroyInfoRec(info->accel);
- info->accel = NULL;
+ if (info->accel_state->accel)
+ XAADestroyInfoRec(info->accel_state->accel);
+ info->accel_state->accel = NULL;
- if (info->scratch_save)
- xfree(info->scratch_save);
- info->scratch_save = NULL;
+ if (info->accel_state->scratch_save)
+ xfree(info->accel_state->scratch_save);
+ info->accel_state->scratch_save = NULL;
}
#endif /* USE_XAA */
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 96d8ea4..d8dcbac 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -164,10 +164,10 @@ static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, uint32_t *pitch_offset
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
- if (pitch > 16320 || pitch % info->exa->pixmapPitchAlign != 0)
+ if (pitch > 16320 || pitch % info->accel_state->exa->pixmapPitchAlign != 0)
RADEON_FALLBACK(("Bad pitch 0x%08x\n", pitch));
- if (offset % info->exa->pixmapOffsetAlign != 0)
+ if (offset % info->accel_state->exa->pixmapOffsetAlign != 0)
RADEON_FALLBACK(("Bad offset 0x%08x\n", offset));
pitch = pitch >> 6;
@@ -302,7 +302,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index)
do { \
uint32_t wait_until = 0; \
BEGIN_ACCEL(1); \
- switch (info->engineMode) { \
+ switch (info->accel_state->engineMode) { \
case EXA_ENGINEMODE_UNKNOWN: \
wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN; \
case EXA_ENGINEMODE_3D: \
@@ -312,14 +312,14 @@ do { \
} \
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \
FINISH_ACCEL(); \
- info->engineMode = EXA_ENGINEMODE_2D; \
+ info->accel_state->engineMode = EXA_ENGINEMODE_2D; \
} while (0);
#define RADEON_SWITCH_TO_3D() \
do { \
uint32_t wait_until = 0; \
BEGIN_ACCEL(1); \
- switch (info->engineMode) { \
+ switch (info->accel_state->engineMode) { \
case EXA_ENGINEMODE_UNKNOWN: \
wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \
case EXA_ENGINEMODE_2D: \
@@ -329,7 +329,7 @@ do { \
} \
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \
FINISH_ACCEL(); \
- info->engineMode = EXA_ENGINEMODE_3D; \
+ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \
} while (0);
#define ENTER_DRAW(x) TRACE
@@ -394,12 +394,12 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
int screen_size;
int byteStride = pScrn->displayWidth * cpp;
- if (info->exa != NULL) {
+ if (info->accel_state->exa != NULL) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
return FALSE;
}
- info->exa = exaDriverAlloc();
- if (info->exa == NULL)
+ info->accel_state->exa = exaDriverAlloc();
+ if (info->accel_state->exa == NULL)
return FALSE;
/* Need to adjust screen size for 16 line tiles, and then make it align to.
@@ -410,12 +410,12 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
else
screen_size = pScrn->virtualY * byteStride;
- info->exa->memoryBase = info->FB;
- info->exa->memorySize = info->FbMapSize - info->FbSecureSize;
- info->exa->offScreenBase = screen_size;
+ info->accel_state->exa->memoryBase = info->FB;
+ info->accel_state->exa->memorySize = info->FbMapSize - info->FbSecureSize;
+ info->accel_state->exa->offScreenBase = screen_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Allocating from a screen of %ld kb\n",
- info->exa->memorySize / 1024);
+ info->accel_state->exa->memorySize / 1024);
/* Reserve static area for hardware cursor */
@@ -429,8 +429,8 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
radeon_crtc->cursor_offset =
- RADEON_ALIGN(info->exa->offScreenBase, align);
- info->exa->offScreenBase = radeon_crtc->cursor_offset + cursor_size;
+ RADEON_ALIGN(info->accel_state->exa->offScreenBase, align);
+ info->accel_state->exa->offScreenBase = radeon_crtc->cursor_offset + cursor_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for hardware cursor %d at offset 0x%08x\n",
@@ -467,12 +467,12 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
* offscreen locations does.
*/
info->backPitch = pScrn->displayWidth;
- next = RADEON_ALIGN(info->exa->offScreenBase, RADEON_BUFFER_ALIGN);
+ next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_BUFFER_ALIGN);
if (!info->noBackBuffer &&
- next + screen_size <= info->exa->memorySize)
+ next + screen_size <= info->accel_state->exa->memorySize)
{
info->backOffset = next;
- info->exa->offScreenBase = next + screen_size;
+ info->accel_state->exa->offScreenBase = next + screen_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for back buffer at offset 0x%08x\n",
screen_size / 1024, info->backOffset);
@@ -483,26 +483,26 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
*/
info->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32);
depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->depthPitch * depthCpp;
- next = RADEON_ALIGN(info->exa->offScreenBase, RADEON_BUFFER_ALIGN);
- if (next + depth_size <= info->exa->memorySize)
+ next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_BUFFER_ALIGN);
+ if (next + depth_size <= info->accel_state->exa->memorySize)
{
info->depthOffset = next;
- info->exa->offScreenBase = next + depth_size;
+ info->accel_state->exa->offScreenBase = next + depth_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for depth buffer at offset 0x%08x\n",
depth_size / 1024, info->depthOffset);
}
- info->textureSize *= (info->exa->memorySize -
- info->exa->offScreenBase) / 100;
+ info->textureSize *= (info->accel_state->exa->memorySize -
+ info->accel_state->exa->offScreenBase) / 100;
l = RADEONLog2(info->textureSize / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY)
l = RADEON_LOG_TEX_GRANULARITY;
info->textureSize = (info->textureSize >> l) << l;
if (info->textureSize >= 512 * 1024) {
- info->textureOffset = info->exa->offScreenBase;
- info->exa->offScreenBase += info->textureSize;
+ info->textureOffset = info->accel_state->exa->offScreenBase;
+ info->accel_state->exa->offScreenBase += info->textureSize;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for textures at offset 0x%08x\n",
info->textureSize / 1024, info->textureOffset);
@@ -518,8 +518,8 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %ld kb for X Server offscreen at offset 0x%08lx\n",
- (info->exa->memorySize - info->exa->offScreenBase) /
- 1024, info->exa->offScreenBase);
+ (info->accel_state->exa->memorySize - info->accel_state->exa->offScreenBase) /
+ 1024, info->accel_state->exa->offScreenBase);
return TRUE;
}
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 56de23e..783e83d 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -65,7 +65,7 @@ FUNC_NAME(RADEONMarkSync)(ScreenPtr pScreen)
TRACE;
- return ++info->exaSyncMarker;
+ return ++info->accel_state->exaSyncMarker;
}
static void
@@ -76,12 +76,12 @@ FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker)
TRACE;
- if (info->exaMarkerSynced != marker) {
+ if (info->accel_state->exaMarkerSynced != marker) {
FUNC_NAME(RADEONWaitForIdle)(pScrn);
- info->exaMarkerSynced = marker;
+ info->accel_state->exaMarkerSynced = marker;
}
- RADEONPTR(pScrn)->engineMode = EXA_ENGINEMODE_UNKNOWN;
+ RADEONPTR(pScrn)->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
}
static Bool
@@ -172,8 +172,8 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset,
RADEON_GMC_CLR_CMP_CNTL_DIS);
OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
OUT_ACCEL_REG(RADEON_DP_CNTL,
- ((info->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
- (info->ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0)));
+ ((info->accel_state->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
+ (info->accel_state->ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0)));
OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset);
OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, src_pitch_offset);
FINISH_ACCEL();
@@ -190,8 +190,8 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst,
TRACE;
- info->xdir = xdir;
- info->ydir = ydir;
+ info->accel_state->xdir = xdir;
+ info->accel_state->ydir = ydir;
if (pDst->drawable.bitsPerPixel == 24)
RADEON_FALLBACK(("24bpp unsupported"));
@@ -219,11 +219,11 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
TRACE;
- if (info->xdir < 0) {
+ if (info->accel_state->xdir < 0) {
srcX += w - 1;
dstX += w - 1;
}
- if (info->ydir < 0) {
+ if (info->accel_state->ydir < 0) {
srcY += h - 1;
dstY += h - 1;
}
@@ -476,7 +476,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
&indirect, sizeof(drmRadeonIndirect));
- info->exaMarkerSynced = info->exaSyncMarker;
+ info->accel_state->exaMarkerSynced = info->accel_state->exaSyncMarker;
return TRUE;
}
@@ -522,35 +522,35 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
{
RINFO_FROM_SCREEN(pScreen);
- if (info->exa == NULL) {
+ if (info->accel_state->exa == NULL) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n");
return FALSE;
}
- info->exa->exa_major = EXA_VERSION_MAJOR;
- info->exa->exa_minor = EXA_VERSION_MINOR;
+ info->accel_state->exa->exa_major = EXA_VERSION_MAJOR;
+ info->accel_state->exa->exa_minor = EXA_VERSION_MINOR;
- info->exa->PrepareSolid = FUNC_NAME(RADEONPrepareSolid);
- info->exa->Solid = FUNC_NAME(RADEONSolid);
- info->exa->DoneSolid = FUNC_NAME(RADEONDoneSolid);
+ info->accel_state->exa->PrepareSolid = FUNC_NAME(RADEONPrepareSolid);
+ info->accel_state->exa->Solid = FUNC_NAME(RADEONSolid);
+ info->accel_state->exa->DoneSolid = FUNC_NAME(RADEONDoneSolid);
- info->exa->PrepareCopy = FUNC_NAME(RADEONPrepareCopy);
- info->exa->Copy = FUNC_NAME(RADEONCopy);
- info->exa->DoneCopy = FUNC_NAME(RADEONDoneCopy);
+ info->accel_state->exa->PrepareCopy = FUNC_NAME(RADEONPrepareCopy);
+ info->accel_state->exa->Copy = FUNC_NAME(RADEONCopy);
+ info->accel_state->exa->DoneCopy = FUNC_NAME(RADEONDoneCopy);
- info->exa->MarkSync = FUNC_NAME(RADEONMarkSync);
- info->exa->WaitMarker = FUNC_NAME(RADEONSync);
- info->exa->UploadToScreen = FUNC_NAME(RADEONUploadToScreen);
- info->exa->DownloadFromScreen = FUNC_NAME(RADEONDownloadFromScreen);
+ info->accel_state->exa->MarkSync = FUNC_NAME(RADEONMarkSync);
+ info->accel_state->exa->WaitMarker = FUNC_NAME(RADEONSync);
+ info->accel_state->exa->UploadToScreen = FUNC_NAME(RADEONUploadToScreen);
+ info->accel_state->exa->DownloadFromScreen = FUNC_NAME(RADEONDownloadFromScreen);
#if X_BYTE_ORDER == X_BIG_ENDIAN
- info->exa->PrepareAccess = RADEONPrepareAccess;
- info->exa->FinishAccess = RADEONFinishAccess;
+ info->accel_state->exa->PrepareAccess = RADEONPrepareAccess;
+ info->accel_state->exa->FinishAccess = RADEONFinishAccess;
#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */
- info->exa->flags = EXA_OFFSCREEN_PIXMAPS;
- info->exa->pixmapOffsetAlign = RADEON_BUFFER_ALIGN + 1;
- info->exa->pixmapPitchAlign = 64;
+ info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS;
+ info->accel_state->exa->pixmapOffsetAlign = RADEON_BUFFER_ALIGN + 1;
+ info->accel_state->exa->pixmapPitchAlign = 64;
#ifdef RENDER
if (info->RenderAccel) {
@@ -565,11 +565,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
"enabled for R300/R400/R500 type cards.\n");
- info->exa->CheckComposite = R300CheckComposite;
- info->exa->PrepareComposite =
+ info->accel_state->exa->CheckComposite = R300CheckComposite;
+ info->accel_state->exa->PrepareComposite =
FUNC_NAME(R300PrepareComposite);
- info->exa->Composite = FUNC_NAME(RadeonComposite);
- info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
+ info->accel_state->exa->Composite = FUNC_NAME(RadeonComposite);
+ info->accel_state->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
} else
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA Composite requires CP on R5xx/IGP\n");
} else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
@@ -578,19 +578,19 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
(info->ChipFamily == CHIP_FAMILY_R200)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
"enabled for R200 type cards.\n");
- info->exa->CheckComposite = R200CheckComposite;
- info->exa->PrepareComposite =
+ info->accel_state->exa->CheckComposite = R200CheckComposite;
+ info->accel_state->exa->PrepareComposite =
FUNC_NAME(R200PrepareComposite);
- info->exa->Composite = FUNC_NAME(RadeonComposite);
- info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
+ info->accel_state->exa->Composite = FUNC_NAME(RadeonComposite);
+ info->accel_state->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
"enabled for R100 type cards.\n");
- info->exa->CheckComposite = R100CheckComposite;
- info->exa->PrepareComposite =
+ info->accel_state->exa->CheckComposite = R100CheckComposite;
+ info->accel_state->exa->PrepareComposite =
FUNC_NAME(R100PrepareComposite);
- info->exa->Composite = FUNC_NAME(RadeonComposite);
- info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
+ info->accel_state->exa->Composite = FUNC_NAME(RadeonComposite);
+ info->accel_state->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
}
}
#endif
@@ -598,17 +598,17 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
#if EXA_VERSION_MAJOR > 2 || (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 3)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n");
- info->exa->maxPitchBytes = 16320;
- info->exa->maxX = 8192;
+ info->accel_state->exa->maxPitchBytes = 16320;
+ info->accel_state->exa->maxX = 8192;
#else
- info->exa->maxX = 16320 / 4;
+ info->accel_state->exa->maxX = 16320 / 4;
#endif
- info->exa->maxY = 8192;
+ info->accel_state->exa->maxY = 8192;
RADEONEngineInit(pScrn);
- if (!exaDriverInit(pScreen, info->exa)) {
- xfree(info->exa);
+ if (!exaDriverInit(pScreen, info->accel_state->exa)) {
+ xfree(info->accel_state->exa);
return FALSE;
}
exaMarkSync(pScreen);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 043b0d4..ddb28be 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -389,8 +389,8 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txformat |= RADEON_TXFORMAT_NON_POWER2;
txformat |= unit << 24; /* RADEON_TXFORMAT_ST_ROUTE_STQX */
- info->texW[unit] = 1;
- info->texH[unit] = 1;
+ info->accel_state->texW[unit] = 1;
+ info->accel_state->texH[unit] = 1;
switch (pPict->filter) {
case PictFilterNearest:
@@ -531,7 +531,7 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
TRACE;
- if (!info->XInited3D)
+ if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
if (!RADEONGetDestFormat(pDstPicture, &dst_format))
@@ -702,8 +702,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txformat |= R200_TXFORMAT_NON_POWER2;
txformat |= unit << R200_TXFORMAT_ST_ROUTE_SHIFT;
- info->texW[unit] = w;
- info->texH[unit] = h;
+ info->accel_state->texW[unit] = w;
+ info->accel_state->texH[unit] = h;
switch (pPict->filter) {
case PictFilterNearest:
@@ -830,7 +830,7 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
TRACE;
- if (!info->XInited3D)
+ if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
if (!RADEONGetDestFormat(pDstPicture, &dst_format))
@@ -1045,8 +1045,8 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
*/
txformat0 |= R300_TXPITCH_EN;
- info->texW[unit] = w;
- info->texH[unit] = h;
+ info->accel_state->texW[unit] = w;
+ info->accel_state->texH[unit] = h;
if (pPict->repeat && !(unit == 0 && need_src_tile_x))
txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
@@ -1191,7 +1191,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
TRACE;
- if (!info->XInited3D)
+ if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
if (!R300GetDestFormat(pDstPicture, &dst_format))
@@ -1236,7 +1236,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
RADEON_SWITCH_TO_3D();
/* setup the VAP */
- if (info->has_tcl) {
+ if (info->accel_state->has_tcl) {
if (pMask)
BEGIN_ACCEL(8);
else
@@ -1296,7 +1296,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
* - Xv
* Here we select the offset of the vertex program we want to use
*/
- if (info->has_tcl) {
+ if (info->accel_state->has_tcl) {
if (pMask) {
OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
((0 << R300_PVS_FIRST_INST_SHIFT) |
@@ -2000,44 +2000,44 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
else
BEGIN_ACCEL(1 + vtx_count * 4);
- if (info->ChipFamily < CHIP_FAMILY_R200) {
+ if (info->ChipFamily < CHIP_FAMILY_R200)
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
RADEON_VF_RADEON_MODE |
(3 << RADEON_VF_NUM_VERTICES_SHIFT)));
- } else {
+ else
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
RADEON_VF_PRIM_WALK_DATA |
(4 << RADEON_VF_NUM_VERTICES_SHIFT)));
- }
+
#endif
if (has_mask) {
if (info->ChipFamily >= CHIP_FAMILY_R200) {
VTX_OUT_MASK((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
- xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]);
+ xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0],
+ xFixedToFloat(maskTopLeft.x) / info->accel_state->texW[1], xFixedToFloat(maskTopLeft.y) / info->accel_state->texH[1]);
}
VTX_OUT_MASK((float)dstX, (float)(dstY + h),
- xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0],
- xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]);
+ xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0],
+ xFixedToFloat(maskBottomLeft.x) / info->accel_state->texW[1], xFixedToFloat(maskBottomLeft.y) / info->accel_state->texH[1]);
VTX_OUT_MASK((float)(dstX + w), (float)(dstY + h),
- xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0],
- xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]);
+ xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0],
+ xFixedToFloat(maskBottomRight.x) / info->accel_state->texW[1], xFixedToFloat(maskBottomRight.y) / info->accel_state->texH[1]);
VTX_OUT_MASK((float)(dstX + w), (float)dstY,
- xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0],
- xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]);
+ xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0],
+ xFixedToFloat(maskTopRight.x) / info->accel_state->texW[1], xFixedToFloat(maskTopRight.y) / info->accel_state->texH[1]);
} else {
if (info->ChipFamily >= CHIP_FAMILY_R200) {
VTX_OUT((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+ xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]);
}
VTX_OUT((float)dstX, (float)(dstY + h),
- xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]);
+ xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0]);
VTX_OUT((float)(dstX + w), (float)(dstY + h),
- xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0]);
+ xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0]);
VTX_OUT((float)(dstX + w), (float)dstY,
- xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]);
+ xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]);
}
if (IS_R300_3D || IS_R500_3D)
diff --git a/src/radeon_render.c b/src/radeon_render.c
index dbd5b79..6668fe0 100644
--- a/src/radeon_render.c
+++ b/src/radeon_render.c
@@ -268,7 +268,7 @@ RemoveLinear (FBLinearPtr linear)
{
RADEONInfoPtr info = (RADEONInfoPtr)(linear->devPrivate.ptr);
- info->RenderTex = NULL;
+ info->accel_state->RenderTex = NULL;
}
static void
@@ -276,13 +276,14 @@ RenderCallback (ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- if ((currentTime.milliseconds > info->RenderTimeout) && info->RenderTex) {
- xf86FreeOffscreenLinear(info->RenderTex);
- info->RenderTex = NULL;
+ if ((currentTime.milliseconds > info->accel_state->RenderTimeout) &&
+ info->accel_state->RenderTex) {
+ xf86FreeOffscreenLinear(info->accel_state->RenderTex);
+ info->accel_state->RenderTex = NULL;
}
- if (!info->RenderTex)
- info->RenderCallback = NULL;
+ if (!info->accel_state->RenderTex)
+ info->accel_state->RenderCallback = NULL;
}
static Bool
@@ -293,30 +294,30 @@ AllocateLinear (
RADEONInfoPtr info = RADEONPTR(pScrn);
int cpp = info->CurrentLayout.bitsPerPixel / 8;
- info->RenderTimeout = currentTime.milliseconds + 30000;
- info->RenderCallback = RenderCallback;
+ info->accel_state->RenderTimeout = currentTime.milliseconds + 30000;
+ info->accel_state->RenderCallback = RenderCallback;
/* XAA allocates in units of pixels at the screen bpp, so adjust size
* appropriately.
*/
sizeNeeded = (sizeNeeded + cpp - 1) / cpp;
- if (info->RenderTex) {
- if (info->RenderTex->size >= sizeNeeded)
+ if (info->accel_state->RenderTex) {
+ if (info->accel_state->RenderTex->size >= sizeNeeded)
return TRUE;
else {
- if (xf86ResizeOffscreenLinear(info->RenderTex, sizeNeeded))
+ if (xf86ResizeOffscreenLinear(info->accel_state->RenderTex, sizeNeeded))
return TRUE;
- xf86FreeOffscreenLinear(info->RenderTex);
- info->RenderTex = NULL;
+ xf86FreeOffscreenLinear(info->accel_state->RenderTex);
+ info->accel_state->RenderTex = NULL;
}
}
- info->RenderTex = xf86AllocateOffscreenLinear(pScrn->pScreen, sizeNeeded, 32,
- NULL, RemoveLinear, info);
+ info->accel_state->RenderTex = xf86AllocateOffscreenLinear(pScrn->pScreen, sizeNeeded, 32,
+ NULL, RemoveLinear, info);
- return (info->RenderTex != NULL);
+ return (info->accel_state->RenderTex != NULL);
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -435,7 +436,7 @@ static Bool FUNC_NAME(R100SetupTexture)(
txformat |= RADEON_TXFORMAT_NON_POWER2;
}
- offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8;
+ offset = info->accel_state->RenderTex->offset * pScrn->bitsPerPixel / 8;
dst = (uint8_t*)(info->FB + offset);
/* Upload texture to card. */
@@ -459,8 +460,8 @@ static Bool FUNC_NAME(R100SetupTexture)(
#else
- if (info->accel->NeedToSync)
- info->accel->Sync(pScrn);
+ if (info->accel_state->accel->NeedToSync)
+ info->accel_state->accel->Sync(pScrn);
while (height--) {
memcpy(dst, src, width * tex_bytepp);
@@ -514,7 +515,7 @@ FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) (
if (blend_cntl == 0)
return FALSE;
- if (!info->XInited3D)
+ if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
if (!FUNC_NAME(R100SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch,
@@ -565,7 +566,7 @@ FUNC_NAME(R100SetupForCPUToScreenTexture) (
if (blend_cntl == 0)
return FALSE;
- if (!info->XInited3D)
+ if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
if (!FUNC_NAME(R100SetupTexture)(pScrn, srcFormat, texPtr, texPitch, width,
@@ -772,10 +773,10 @@ static Bool FUNC_NAME(R200SetupTexture)(
txformat |= RADEON_TXFORMAT_NON_POWER2;
}
- info->texW[0] = width;
- info->texH[0] = height;
+ info->accel_state->texW[0] = width;
+ info->accel_state->texH[0] = height;
- offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8;
+ offset = info->accel_state->RenderTex->offset * pScrn->bitsPerPixel / 8;
dst = (uint8_t*)(info->FB + offset);
/* Upload texture to card. */
@@ -799,8 +800,8 @@ static Bool FUNC_NAME(R200SetupTexture)(
#else
- if (info->accel->NeedToSync)
- info->accel->Sync(pScrn);
+ if (info->accel_state->accel->NeedToSync)
+ info->accel_state->accel->Sync(pScrn);
while (height--) {
memcpy(dst, src, width * tex_bytepp);
@@ -855,7 +856,7 @@ FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) (
if (blend_cntl == 0)
return FALSE;
- if (!info->XInited3D)
+ if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
if (!FUNC_NAME(R200SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch,
@@ -907,7 +908,7 @@ FUNC_NAME(R200SetupForCPUToScreenTexture) (
if (blend_cntl == 0)
return FALSE;
- if (!info->XInited3D)
+ if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
if (!FUNC_NAME(R200SetupTexture)(pScrn, srcFormat, texPtr, texPitch, width,
@@ -974,10 +975,10 @@ FUNC_NAME(R200SubsequentCPUToScreenTexture) (
r = width + l;
b = height + t;
- fl = (float)srcx / info->texW[0];
- fr = (float)(srcx + width) / info->texW[0];
- ft = (float)srcy / info->texH[0];
- fb = (float)(srcy + height) / info->texH[0];
+ fl = (float)srcx / info->accel_state->texW[0];
+ fr = (float)(srcx + width) / info->accel_state->texW[0];
+ ft = (float)srcy / info->accel_state->texH[0];
+ fb = (float)(srcy + height) / info->accel_state->texH[0];
#ifdef ACCEL_CP
BEGIN_RING(24);
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 09e2811..c5ad0e1 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -127,7 +127,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
dstyoff = 0;
#endif
- if (!info->XInited3D)
+ if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
/* we can probably improve this */
@@ -189,8 +189,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) |
R300_TXPITCH_EN);
- info->texW[0] = pPriv->w;
- info->texH[0] = pPriv->h;
+ info->accel_state->texW[0] = pPriv->w;
+ info->accel_state->texH[0] = pPriv->h;
txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) |
@@ -251,7 +251,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
}
/* setup the VAP */
- if (info->has_tcl) {
+ if (info->accel_state->has_tcl) {
if (pPriv->bicubic_enabled)
BEGIN_ACCEL(7);
else
@@ -312,7 +312,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
* - Xv
* Here we select the offset of the vertex program we want to use
*/
- if (info->has_tcl) {
+ if (info->accel_state->has_tcl) {
if (pPriv->bicubic_enabled) {
OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
((0 << R300_PVS_FIRST_INST_SHIFT) |
@@ -1044,8 +1044,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(info->ChipFamily == CHIP_FAMILY_RS300) ||
(info->ChipFamily == CHIP_FAMILY_R200)) {
- info->texW[0] = pPriv->w;
- info->texH[0] = pPriv->h;
+ info->accel_state->texW[0] = pPriv->w;
+ info->accel_state->texH[0] = pPriv->h;
BEGIN_ACCEL(12);
@@ -1085,8 +1085,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_ACCEL();
} else {
- info->texW[0] = 1;
- info->texH[0] = 1;
+ info->accel_state->texW[0] = 1;
+ info->accel_state->texH[0] = 1;
BEGIN_ACCEL(8);
@@ -1199,28 +1199,28 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
#endif
if (pPriv->bicubic_enabled) {
VTX_OUT_FILTER((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
+ xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0],
xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5);
VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth),
- xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0],
+ xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0],
xFixedToFloat(srcBottomLeft.x) + 0.5, xFixedToFloat(srcBottomLeft.y) + 0.5);
VTX_OUT_FILTER((float)(dstX + dstw), (float)(dstY + dsth),
- xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0],
+ xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0],
xFixedToFloat(srcBottomRight.x) + 0.5, xFixedToFloat(srcBottomRight.y) + 0.5);
VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY,
- xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0],
+ xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0],
xFixedToFloat(srcTopRight.x) + 0.5, xFixedToFloat(srcTopRight.y) + 0.5);
} else {
if (info->ChipFamily >= CHIP_FAMILY_R200) {
VTX_OUT((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+ xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]);
}
VTX_OUT((float)dstX, (float)(dstY + dsth),
- xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]);
+ xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0]);
VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth),
- xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0]);
+ xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0]);
VTX_OUT((float)(dstX + dstw), (float)dstY,
- xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]);
+ xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]);
}
if (IS_R300_3D || IS_R500_3D)
commit 5b2e095c31b88d8495a4f86e6cb46b49fa4acd65
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Jul 10 20:07:44 2008 -0400
Move CP into a separate struct
diff --git a/src/radeon.h b/src/radeon.h
index 2348e7c..626b492 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -413,6 +413,28 @@ typedef struct {
int singledac;
} RADEONCardInfo;
+#ifdef XF86DRI
+struct radeon_cp {
+ Bool CPRuns; /* CP is running */
+ Bool CPInUse; /* CP has been used by X server */
+ Bool CPStarted; /* CP has started */
+ int CPMode; /* CP mode that server/clients use */
+ int CPFifoSize; /* Size of the CP command FIFO */
+ int CPusecTimeout; /* CP timeout in usecs */
+ Bool needCacheFlush;
+
+ /* CP accleration */
+ drmBufPtr indirectBuffer;
+ int indirectStart;
+
+ /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */
+ int dma_begin_count;
+ char *dma_debug_func;
+ int dma_debug_lineno;
+
+ };
+#endif
+
typedef struct {
EntityInfoPtr pEnt;
pciVideoPtr PciInfo;
@@ -600,12 +622,7 @@ typedef struct {
uint32_t pciCommand;
- Bool CPRuns; /* CP is running */
- Bool CPInUse; /* CP has been used by X server */
- Bool CPStarted; /* CP has started */
- int CPFifoSize; /* Size of the CP command FIFO */
- int CPusecTimeout; /* CP timeout in usecs */
- Bool needCacheFlush;
+ struct radeon_cp *cp;
/* CP ring buffer data */
unsigned long ringStart; /* Offset into GART space */
@@ -637,10 +654,6 @@ typedef struct {
drmAddress gartTex; /* Map */
int log2GARTTexGran;
- /* CP accleration */
- drmBufPtr indirectBuffer;
- int indirectStart;
-
/* DRI screen private data */
int fbX;
int fbY;
@@ -683,10 +696,6 @@ typedef struct {
int perctx_sarea_size;
#endif
- /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */
- int dma_begin_count;
- char *dma_debug_func;
- int dma_debug_lineno;
#endif /* XF86DRI */
/* XVideo */
@@ -1043,32 +1052,32 @@ do { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
"%s: CP start %d\n", __FUNCTION__, _ret); \
} \
- info->CPStarted = TRUE; \
+ info->cp->CPStarted = TRUE; \
} while (0)
#define RADEONCP_RELEASE(pScrn, info) \
do { \
- if (info->CPInUse) { \
+ if (info->cp->CPInUse) { \
RADEON_PURGE_CACHE(); \
RADEON_WAIT_UNTIL_IDLE(); \
RADEONCPReleaseIndirect(pScrn); \
- info->CPInUse = FALSE; \
+ info->cp->CPInUse = FALSE; \
} \
} while (0)
#define RADEONCP_STOP(pScrn, info) \
do { \
int _ret; \
- if (info->CPStarted) { \
+ if (info->cp->CPStarted) { \
_ret = RADEONCPStop(pScrn, info); \
if (_ret) { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
"%s: CP stop %d\n", __FUNCTION__, _ret); \
} \
- info->CPStarted = FALSE; \
+ info->cp->CPStarted = FALSE; \
} \
RADEONEngineRestore(pScrn); \
- info->CPRuns = FALSE; \
+ info->cp->CPRuns = FALSE; \
} while (0)
#define RADEONCP_RESET(pScrn, info) \
@@ -1082,14 +1091,14 @@ do { \
#define RADEONCP_REFRESH(pScrn, info) \
do { \
- if (!info->CPInUse) { \
- if (info->needCacheFlush) { \
+ if (!info->cp->CPInUse) { \
+ if (info->cp->needCacheFlush) { \
RADEON_PURGE_CACHE(); \
RADEON_PURGE_ZCACHE(); \
- info->needCacheFlush = FALSE; \
+ info->cp->needCacheFlush = FALSE; \
} \
RADEON_WAIT_UNTIL_IDLE(); \
- info->CPInUse = TRUE; \
+ info->cp->CPInUse = TRUE; \
} \
} while (0)
@@ -1113,33 +1122,33 @@ do { \
xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
"BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\
} \
- if (++info->dma_begin_count != 1) { \
+ if (++info->cp->dma_begin_count != 1) { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
"BEGIN_RING without end at %s:%d\n", \
- info->dma_debug_func, info->dma_debug_lineno); \
- info->dma_begin_count = 1; \
+ info->cp->dma_debug_func, info->cp->dma_debug_lineno); \
+ info->cp->dma_begin_count = 1; \
} \
- info->dma_debug_func = __FILE__; \
- info->dma_debug_lineno = __LINE__; \
- if (!info->indirectBuffer) { \
- info->indirectBuffer = RADEONCPGetBuffer(pScrn); \
- info->indirectStart = 0; \
- } else if (info->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \
- info->indirectBuffer->total) { \
+ info->cp->dma_debug_func = __FILE__; \
+ info->cp->dma_debug_lineno = __LINE__; \
+ if (!info->cp->indirectBuffer) { \
+ info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \
+ info->cp->indirectStart = 0; \
+ } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \
+ info->cp->indirectBuffer->total) { \
RADEONCPFlushIndirect(pScrn, 1); \
} \
__expected = n; \
- __head = (pointer)((char *)info->indirectBuffer->address + \
- info->indirectBuffer->used); \
+ __head = (pointer)((char *)info->cp->indirectBuffer->address + \
+ info->cp->indirectBuffer->used); \
__count = 0; \
} while (0)
#define ADVANCE_RING() do { \
- if (info->dma_begin_count-- != 1) { \
+ if (info->cp->dma_begin_count-- != 1) { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
"ADVANCE_RING without begin at %s:%d\n", \
__FILE__, __LINE__); \
- info->dma_begin_count = 0; \
+ info->cp->dma_begin_count = 0; \
} \
if (__count != __expected) { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
@@ -1149,11 +1158,11 @@ do { \
if (RADEON_VERBOSE) { \
xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
"ADVANCE_RING() start: %d used: %d count: %d\n", \
- info->indirectStart, \
- info->indirectBuffer->used, \
+ info->cp->indirectStart, \
+ info->cp->indirectBuffer->used, \
__count * (int)sizeof(uint32_t)); \
} \
- info->indirectBuffer->used += __count * (int)sizeof(uint32_t); \
+ info->cp->indirectBuffer->used += __count * (int)sizeof(uint32_t); \
} while (0)
#define OUT_RING(x) do { \
@@ -1175,7 +1184,7 @@ do { \
if (RADEON_VERBOSE) \
xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
"FLUSH_RING in %s\n", __FUNCTION__); \
- if (info->indirectBuffer) { \
+ if (info->cp->indirectBuffer) { \
RADEONCPFlushIndirect(pScrn, 0); \
} \
} while (0)
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index e617fd5..72866d1 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -624,8 +624,8 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn)
void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- drmBufPtr buffer = info->indirectBuffer;
- int start = info->indirectStart;
+ drmBufPtr buffer = info->cp->indirectBuffer;
+ int start = info->cp->indirectStart;
drmRadeonIndirect indirect;
if (!buffer) return;
@@ -645,14 +645,14 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
&indirect, sizeof(drmRadeonIndirect));
if (discard) {
- info->indirectBuffer = RADEONCPGetBuffer(pScrn);
- info->indirectStart = 0;
+ info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn);
+ info->cp->indirectStart = 0;
} else {
/* Start on a double word boundary */
- info->indirectStart = buffer->used = (buffer->used + 7) & ~7;
+ info->cp->indirectStart = buffer->used = (buffer->used + 7) & ~7;
if (RADEON_VERBOSE) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, " Starting at %d\n",
- info->indirectStart);
+ info->cp->indirectStart);
}
}
}
@@ -661,12 +661,12 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- drmBufPtr buffer = info->indirectBuffer;
- int start = info->indirectStart;
+ drmBufPtr buffer = info->cp->indirectBuffer;
+ int start = info->cp->indirectStart;
drmRadeonIndirect indirect;
- info->indirectBuffer = NULL;
- info->indirectStart = 0;
+ info->cp->indirectBuffer = NULL;
+ info->cp->indirectStart = 0;
if (!buffer) return;
diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c
index 56793cd..f83579f 100644
--- a/src/radeon_accelfuncs.c
+++ b/src/radeon_accelfuncs.c
@@ -666,7 +666,7 @@ FUNC_NAME(RADEONSubsequentColor8x8PatternFillRect)(ScrnInfoPtr pScrn,
#endif
#ifdef ACCEL_CP
-#define CP_BUFSIZE (info->indirectBuffer->total/4-10)
+#define CP_BUFSIZE (info->cp->indirectBuffer->total/4-10)
/* Helper function to write out a HOSTDATA_BLT packet into the indirect
* buffer and set the XAA scratch buffer address appropriately.
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 1de6bf8..00def66 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -686,7 +686,7 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
#ifdef ACCEL_CP
/* Make sure the CP is idle first */
- if (info->CPStarted) {
+ if (info->cp->CPStarted) {
int ret;
FLUSH_RING();
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 5ab00c1..9eb9448 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -367,7 +367,7 @@ radeon_crtc_lock(xf86CrtcPtr crtc)
RADEONInfoPtr info = RADEONPTR(pScrn);
#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) {
+ if (info->cp->CPStarted && pScrn->pScreen) {
DRILock(pScrn->pScreen, 0);
if (info->accelOn)
RADEON_SYNC(info, pScrn);
@@ -388,7 +388,7 @@ radeon_crtc_unlock(xf86CrtcPtr crtc)
RADEONInfoPtr info = RADEONPTR(pScrn);
#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
+ if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
#endif
if (info->accelOn)
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index a192811..c0b809c 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -364,7 +364,7 @@ static void RADEONEnterServer(ScreenPtr pScreen)
pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
if (pSAREAPriv->ctxOwner != DRIGetContext(pScrn->pScreen)) {
info->XInited3D = FALSE;
- info->needCacheFlush = (info->ChipFamily >= CHIP_FAMILY_R300);
+ info->cp->needCacheFlush = (info->ChipFamily >= CHIP_FAMILY_R300);
}
#ifdef DAMAGE
@@ -1106,7 +1106,7 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmInfo.cp_mode = RADEON_CSQ_PRIBM_INDBM;
drmInfo.gart_size = info->gartSize*1024*1024;
drmInfo.ring_size = info->ringSize*1024*1024;
- drmInfo.usec_timeout = info->CPusecTimeout;
+ drmInfo.usec_timeout = info->cp->CPusecTimeout;
drmInfo.fb_bpp = info->CurrentLayout.pixel_code;
drmInfo.depth_bpp = (info->depthBits - 8) * 2;
@@ -1897,7 +1897,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
RegionRec region;
BoxPtr pbox;
- if (!info->directRenderingInited || !info->CPStarted)
+ if (!info->directRenderingInited || !info->cp->CPStarted)
return;
/* Don't want to do this when no 3d is active and pages are
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 45d2c2f..3e3d0b5 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2107,11 +2107,17 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->directRenderingEnabled = FALSE;
info->directRenderingInited = FALSE;
- info->CPInUse = FALSE;
- info->CPStarted = FALSE;
info->pLibDRMVersion = NULL;
info->pKernelDRMVersion = NULL;
+ if (!(info->cp = xcalloc(1, sizeof(struct radeon_cp)))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
+ return FALSE;
+ }
+ info->cp->CPInUse = FALSE;
+ info->cp->CPStarted = FALSE;
+ info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
+
if (xf86IsEntityShared(info->pEnt->index)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Direct Rendering Disabled -- "
@@ -2193,7 +2199,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
info->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE;
info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE;
- info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
+ info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
if ((xf86GetOptValInteger(info->Options,
OPTION_GART_SIZE, (int *)&(info->gartSize))) ||
@@ -2271,7 +2277,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize);
if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT,
- &(info->CPusecTimeout))) {
+ &(info->cp->CPusecTimeout))) {
/* This option checked by the RADEON DRM kernel module */
}
@@ -3008,7 +3014,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
int c;
#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
+ if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
#endif
if (info->accelOn && pScrn->pScreen)
@@ -3072,7 +3078,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
}
#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
+ if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
#endif
}
@@ -5111,7 +5117,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
Bool tilingOld = info->tilingEnabled;
Bool ret;
#ifdef XF86DRI
- Bool CPStarted = info->CPStarted;
+ Bool CPStarted = info->cp->CPStarted;
if (CPStarted) {
DRILock(pScrn->pScreen, 0);
@@ -5356,7 +5362,7 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
xf86CrtcPtr crtc = output->crtc;
#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
+ if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
#endif
if (info->accelOn)
@@ -5373,7 +5379,7 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
+ if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
#endif
}
commit 2145309230e36aee7758bd244deb1e72ada0c065
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Aug 25 08:47:59 2008 -0400
match textured video macro names with other accel code
OUT_VIDEO_REG() -> OUT_ACCEL_REG()
etc.
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 02fd4fc..96d8ea4 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -352,6 +352,7 @@ do { \
#undef ACCEL_PREAMBLE
#undef BEGIN_ACCEL
#undef OUT_ACCEL_REG
+#undef OUT_ACCEL_REG_F
#undef FINISH_ACCEL
#ifdef XF86DRI
@@ -371,6 +372,13 @@ do { \
#endif
#include "radeon_exa_funcs.c"
+#undef ACCEL_CP
+#undef ACCEL_PREAMBLE
+#undef BEGIN_ACCEL
+#undef OUT_ACCEL_REG
+#undef FINISH_ACCEL
+#undef OUT_RING_F
+
#endif /* XF86DRI */
/*
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index da1d60f..9e6b37a 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -81,35 +81,43 @@ static __inline__ uint32_t F_TO_DW(float val)
}
#define ACCEL_MMIO
-#define VIDEO_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO
-#define BEGIN_VIDEO(n) RADEONWaitForFifo(pScrn, (n))
-#define OUT_VIDEO_REG(reg, val) OUTREG(reg, val)
-#define OUT_VIDEO_REG_F(reg, val) OUTREG(reg, F_TO_DW(val))
-#define FINISH_VIDEO()
+#define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO
+#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n))
+#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
+#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val))
+#define FINISH_ACCEL()
#include "radeon_textured_videofuncs.c"
#undef ACCEL_MMIO
-#undef VIDEO_PREAMBLE
-#undef BEGIN_VIDEO
-#undef OUT_VIDEO_REG
-#undef OUT_VIDEO_REG_F
-#undef FINISH_VIDEO
+#undef ACCEL_PREAMBLE
+#undef BEGIN_ACCEL
+#undef OUT_ACCEL_REG
+#undef OUT_ACCEL_REG_F
+#undef FINISH_ACCEL
#ifdef XF86DRI
#define ACCEL_CP
-#define VIDEO_PREAMBLE() \
+#define ACCEL_PREAMBLE() \
RING_LOCALS; \
RADEONCP_REFRESH(pScrn, info)
-#define BEGIN_VIDEO(n) BEGIN_RING(2*(n))
-#define OUT_VIDEO_REG(reg, val) OUT_RING_REG(reg, val)
-#define OUT_VIDEO_REG_F(reg, val) OUT_VIDEO_REG(reg, F_TO_DW(val))
-#define FINISH_VIDEO() ADVANCE_RING()
-#define OUT_VIDEO_RING_F(x) OUT_RING(F_TO_DW(x))
+#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
+#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
+#define OUT_ACCEL_REG_F(reg, val) OUT_ACCEL_REG(reg, F_TO_DW(val))
+#define FINISH_ACCEL() ADVANCE_RING()
+#define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
#include "radeon_textured_videofuncs.c"
+#undef ACCEL_CP
+#undef ACCEL_PREAMBLE
+#undef BEGIN_ACCEL
+#undef OUT_ACCEL_REG
+#undef OUT_ACCEL_REG_F
+#undef FINISH_ACCEL
+#undef OUT_RING_F
+
#endif /* XF86DRI */
static int
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index b53e114..09e2811 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -52,40 +52,40 @@
#define VTX_OUT_FILTER(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
do { \
- OUT_VIDEO_RING_F(_dstX); \
- OUT_VIDEO_RING_F(_dstY); \
- OUT_VIDEO_RING_F(_srcX); \
- OUT_VIDEO_RING_F(_srcY); \
- OUT_VIDEO_RING_F(_maskX); \
- OUT_VIDEO_RING_F(_maskY); \
+ OUT_RING_F(_dstX); \
+ OUT_RING_F(_dstY); \
+ OUT_RING_F(_srcX); \
+ OUT_RING_F(_srcY); \
+ OUT_RING_F(_maskX); \
+ OUT_RING_F(_maskY); \
} while (0)
#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
do { \
- OUT_VIDEO_RING_F(_dstX); \
- OUT_VIDEO_RING_F(_dstY); \
- OUT_VIDEO_RING_F(_srcX); \
- OUT_VIDEO_RING_F(_srcY); \
+ OUT_RING_F(_dstX); \
+ OUT_RING_F(_dstY); \
+ OUT_RING_F(_srcX); \
+ OUT_RING_F(_srcY); \
} while (0)
#else /* ACCEL_CP */
#define VTX_OUT_FILTER(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
do { \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _maskX); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _maskY); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskX); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \
} while (0)
#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
do { \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
} while (0)
#endif /* !ACCEL_CP */
@@ -103,7 +103,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
int dstxoff, dstyoff, pixel_shift, vtx_count;
BoxPtr pBox = REGION_RECTS(&pPriv->clip);
int nBox = REGION_NUM_RECTS(&pPriv->clip);
- VIDEO_PREAMBLE();
+ ACCEL_PREAMBLE();
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -131,18 +131,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEONInit3DEngine(pScrn);
/* we can probably improve this */
- BEGIN_VIDEO(2);
+ BEGIN_ACCEL(2);
if (IS_R300_3D || IS_R500_3D)
- OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
else
- OUT_VIDEO_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
+ OUT_ACCEL_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
/* We must wait for 3d to idle, in case source was just written as a dest. */
- OUT_VIDEO_REG(RADEON_WAIT_UNTIL,
+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN |
RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN |
RADEON_WAIT_DMA_GUI_IDLE);
- FINISH_VIDEO();
+ FINISH_ACCEL();
if (pPriv->bicubic_enabled)
vtx_count = VTX_DWORD_COUNT_FILTER;
@@ -210,14 +210,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txoffset = pPriv->src_offset;
- BEGIN_VIDEO(6);
- OUT_VIDEO_REG(R300_TX_FILTER0_0, txfilter);
- OUT_VIDEO_REG(R300_TX_FILTER1_0, 0);
- OUT_VIDEO_REG(R300_TX_FORMAT0_0, txformat0);
- OUT_VIDEO_REG(R300_TX_FORMAT1_0, txformat1);
- OUT_VIDEO_REG(R300_TX_FORMAT2_0, txpitch);
- OUT_VIDEO_REG(R300_TX_OFFSET_0, txoffset);
- FINISH_VIDEO();
+ BEGIN_ACCEL(6);
+ OUT_ACCEL_REG(R300_TX_FILTER0_0, txfilter);
+ OUT_ACCEL_REG(R300_TX_FILTER1_0, 0);
+ OUT_ACCEL_REG(R300_TX_FORMAT0_0, txformat0);
+ OUT_ACCEL_REG(R300_TX_FORMAT1_0, txformat1);
+ OUT_ACCEL_REG(R300_TX_FORMAT2_0, txpitch);
+ OUT_ACCEL_REG(R300_TX_OFFSET_0, txoffset);
+ FINISH_ACCEL();
txenable = R300_TEX_0_ENABLE;
@@ -237,14 +237,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_TX_MAG_FILTER_NEAREST |
(1 << R300_TX_ID_SHIFT));
- BEGIN_VIDEO(6);
- OUT_VIDEO_REG(R300_TX_FILTER0_1, txfilter);
- OUT_VIDEO_REG(R300_TX_FILTER1_1, 0);
- OUT_VIDEO_REG(R300_TX_FORMAT0_1, txformat0);
- OUT_VIDEO_REG(R300_TX_FORMAT1_1, txformat1);
- OUT_VIDEO_REG(R300_TX_FORMAT2_1, txpitch);
- OUT_VIDEO_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset);
- FINISH_VIDEO();
+ BEGIN_ACCEL(6);
+ OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter);
+ OUT_ACCEL_REG(R300_TX_FILTER1_1, 0);
+ OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0);
+ OUT_ACCEL_REG(R300_TX_FORMAT1_1, txformat1);
+ OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch);
+ OUT_ACCEL_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset);
+ FINISH_ACCEL();
/* Enable tex 1 */
txenable |= R300_TEX_1_ENABLE;
@@ -253,14 +253,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* setup the VAP */
if (info->has_tcl) {
if (pPriv->bicubic_enabled)
- BEGIN_VIDEO(7);
+ BEGIN_ACCEL(7);
else
- BEGIN_VIDEO(6);
+ BEGIN_ACCEL(6);
} else {
if (pPriv->bicubic_enabled)
- BEGIN_VIDEO(5);
+ BEGIN_ACCEL(5);
else
- BEGIN_VIDEO(4);
+ BEGIN_ACCEL(4);
}
/* These registers define the number, type, and location of data submitted
@@ -277,7 +277,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
* Fog
*/
if (pPriv->bicubic_enabled) {
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
(0 << R300_SKIP_DWORDS_0_SHIFT) |
(0 << R300_DST_VEC_LOC_0_SHIFT) |
@@ -286,14 +286,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(0 << R300_SKIP_DWORDS_1_SHIFT) |
(6 << R300_DST_VEC_LOC_1_SHIFT) |
R300_SIGNED_1));
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_1,
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
(0 << R300_SKIP_DWORDS_2_SHIFT) |
(7 << R300_DST_VEC_LOC_2_SHIFT) |
R300_LAST_VEC_2 |
R300_SIGNED_2));
} else {
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
(0 << R300_SKIP_DWORDS_0_SHIFT) |
(0 << R300_DST_VEC_LOC_0_SHIFT) |
@@ -314,52 +314,52 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
*/
if (info->has_tcl) {
if (pPriv->bicubic_enabled) {
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
((0 << R300_PVS_FIRST_INST_SHIFT) |
(2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
(2 << R300_PVS_LAST_INST_SHIFT)));
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
(2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
} else {
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
((5 << R300_PVS_FIRST_INST_SHIFT) |
(6 << R300_PVS_XYZW_VALID_INST_SHIFT) |
(6 << R300_PVS_LAST_INST_SHIFT)));
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
(6 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
}
}
/* Position and one set of 2 texture coordinates */
- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
+ OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
if (pPriv->bicubic_enabled)
- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
+ OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
(2 << R300_TEX_1_COMP_CNT_SHIFT)));
else
- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
+ OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
- OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt);
- FINISH_VIDEO();
+ OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
+ FINISH_ACCEL();
/* setup pixel shader */
if (IS_R300_3D) {
- BEGIN_VIDEO(9);
+ BEGIN_ACCEL(9);
/* 2 components: 2 for tex0 */
- OUT_VIDEO_REG(R300_RS_COUNT,
+ OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
- OUT_VIDEO_REG(R300_US_PIXSIZE, 0); /* highest temp used */
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
- OUT_VIDEO_REG(R300_US_CODE_OFFSET,
+ OUT_ACCEL_REG(R300_US_CODE_OFFSET,
(R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(1) |
R300_TEX_CODE_OFFSET(0) |
R300_TEX_CODE_SIZE(1)));
- OUT_VIDEO_REG(R300_US_CODE_ADDR_3,
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
(R300_ALU_START(0) |
R300_ALU_SIZE(0) |
R300_TEX_START(0) |
@@ -370,7 +370,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* ALU inst */
/* RGB */
- OUT_VIDEO_REG(R300_US_ALU_RGB_ADDR_0,
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
(R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(0) |
R300_ALU_RGB_ADDR2(0) |
@@ -379,7 +379,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_RGB_MASK_G |
R300_ALU_RGB_MASK_B)) |
R300_ALU_RGB_TARGET_A));
- OUT_VIDEO_REG(R300_US_ALU_RGB_INST_0,
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
(R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
@@ -390,7 +390,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
R300_ALU_RGB_CLAMP));
/* Alpha */
- OUT_VIDEO_REG(R300_US_ALU_ALPHA_ADDR_0,
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
(R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(0) |
R300_ALU_ALPHA_ADDR2(0) |
@@ -398,7 +398,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
R300_ALU_ALPHA_TARGET_A |
R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
- OUT_VIDEO_REG(R300_US_ALU_ALPHA_INST_0,
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
(R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) |
R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) |
@@ -408,34 +408,34 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
R300_ALU_ALPHA_CLAMP));
- FINISH_VIDEO();
+ FINISH_ACCEL();
} else {
if (pPriv->bicubic_enabled) {
- BEGIN_VIDEO(7);
+ BEGIN_ACCEL(7);
/* 4 components: 2 for tex0 and 2 for tex1 */
- OUT_VIDEO_REG(R300_RS_COUNT,
+ OUT_ACCEL_REG(R300_RS_COUNT,
((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
/* Pixel stack frame size. */
- OUT_VIDEO_REG(R300_US_PIXSIZE, 5);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 5);
/* FP length. */
- OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(13)));
- OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
R500_US_CODE_RANGE_SIZE(13)));
/* Prepare for FP emission. */
- OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
- FINISH_VIDEO();
+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
+ FINISH_ACCEL();
- BEGIN_VIDEO(89);
+ BEGIN_ACCEL(89);
/* Pixel shader.
* I've gone ahead and annotated each instruction, since this
* thing is MASSIVE. :3
@@ -443,14 +443,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
* inputs, all temps are offset by 2. temp0 -> register2. */
/* TEX temp2, input1.xxxx, tex1, 1D */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_R |
R500_TEX_SRC_R_SWIZ_R |
@@ -460,21 +460,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* TEX temp5, input1.yyyy, tex1, 1D */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
R500_TEX_SRC_S_SWIZ_G |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_G |
@@ -484,24 +484,24 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* MUL temp4, const0.x0x0, temp2.yyxx */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(2)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(2)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_0 |
R500_ALU_RGB_B_SWIZ_A_R |
@@ -509,13 +509,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_0 |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
@@ -523,20 +523,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_A_SWIZ_0));
/* MAD temp3, const0.0y0y, temp5.xxxx, temp4 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(5) |
R500_RGB_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(5) |
R500_ALPHA_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_0 |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_0 |
@@ -544,13 +544,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_G |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -559,28 +559,28 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_A_SWIZ_A));
/* ADD temp3, temp3, input0.xyxy */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(3) |
R500_RGB_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(3) |
R500_ALPHA_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
R500_ALU_RGB_G_SWIZ_A_1 |
R500_ALU_RGB_B_SWIZ_A_1 |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -589,15 +589,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_A_SWIZ_G));
/* TEX temp1, temp3.zwxy, tex0, 1D */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
R500_TEX_SRC_S_SWIZ_B |
R500_TEX_SRC_T_SWIZ_A |
R500_TEX_SRC_R_SWIZ_R |
@@ -607,22 +607,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* TEX temp3, temp3.xyzw, tex0, 1D */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_B |
@@ -632,25 +632,25 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* MAD temp4, const1.0y0y, temp5.yyyy, temp4 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(5) |
R500_RGB_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(5) |
R500_ALPHA_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_0 |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_0 |
@@ -658,13 +658,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_G |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -673,28 +673,28 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_A_SWIZ_A));
/* ADD temp0, temp4, input0.xyxy */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
R500_RGB_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
R500_ALPHA_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
R500_ALU_RGB_G_SWIZ_A_1 |
R500_ALU_RGB_B_SWIZ_A_1 |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -703,16 +703,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_A_SWIZ_G));
/* TEX temp4, temp0.zwzw, tex0, 1D */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_B |
R500_TEX_SRC_T_SWIZ_A |
R500_TEX_SRC_R_SWIZ_B |
@@ -722,22 +722,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* TEX temp0, temp0.xyzw, tex0, 1D */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_B |
@@ -747,27 +747,27 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* LRP temp3, temp2.zzzz, temp1, temp3 ->
* - PRESUB temps, temp1 - temp3
* - MAD temp2.zzzz, temps, temp3 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(2)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR2(2)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -775,13 +775,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -792,21 +792,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* LRP temp0, temp2.zzzz, temp4, temp0 ->
* - PRESUB temps, temp4 - temp1
* - MAD temp2.zzzz, temps, temp0 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(4) |
R500_RGB_ADDR2(2)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(4) |
R500_ALPHA_ADDR2(2)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -814,13 +814,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -831,7 +831,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* LRP output, temp5.zzzz, temp3, temp0 ->
* - PRESUB temps, temp3 - temp0
* - MAD temp5.zzzz, temps, temp0 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_LAST |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -842,15 +842,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
R500_INST_ALPHA_OMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(3) |
R500_RGB_ADDR2(5)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(3) |
R500_ALPHA_ADDR2(5)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -858,13 +858,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -873,41 +873,41 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_A_SWIZ_A));
/* Shader constants. */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0));
/* const0 = {1 / texture[0].width, 0, 0, 0} */
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w));
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->h));
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w));
+ OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->h));
+ OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
- FINISH_VIDEO();
+ FINISH_ACCEL();
} else {
- BEGIN_VIDEO(19);
+ BEGIN_ACCEL(19);
/* 2 components: 2 for tex0 */
- OUT_VIDEO_REG(R300_RS_COUNT,
+ OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
/* Pixel stack frame size. */
- OUT_VIDEO_REG(R300_US_PIXSIZE, 0); /* highest temp used */
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
/* FP length. */
- OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(1)));
- OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
R500_US_CODE_RANGE_SIZE(1)));
/* Prepare for FP emission. */
- OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
/* tex inst */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -915,11 +915,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_DST_ADDR(0) |
@@ -927,7 +927,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
R500_DX_S_SWIZ_R |
R500_DX_T_SWIZ_R |
R500_DX_R_SWIZ_R |
@@ -937,11 +937,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
R500_DY_Q_SWIZ_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* ALU inst */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
R500_INST_RGB_OMASK_R |
@@ -950,17 +950,17 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_OMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR1(0) |
R500_RGB_ADDR1_CONST |
R500_RGB_ADDR2(0) |
R500_RGB_ADDR2_CONST));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR1_CONST |
R500_ALPHA_ADDR2(0) |
R500_ALPHA_ADDR2_CONST));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -968,31 +968,31 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1 |
R500_ALU_RGB_G_SWIZ_B_1));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_A |
R500_ALPHA_SWIZ_B_1));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0));
- FINISH_VIDEO();
+ FINISH_ACCEL();
}
}
- BEGIN_VIDEO(6);
- OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
- OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
+ BEGIN_ACCEL(6);
+ OUT_ACCEL_REG(R300_TX_INVALTAGS, 0);
+ OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
- OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset);
- OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch);
+ OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
+ OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
/* no need to enable blending */
- OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl);
+ OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl);
- OUT_VIDEO_REG(R300_VAP_VTX_SIZE, vtx_count);
- FINISH_VIDEO();
+ OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
+ FINISH_ACCEL();
} else {
@@ -1023,20 +1023,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (RADEONTilingEnabled(pScrn, pPixmap))
colorpitch |= RADEON_COLOR_TILE_ENABLE;
- BEGIN_VIDEO(5);
+ BEGIN_ACCEL(5);
- OUT_VIDEO_REG(RADEON_PP_CNTL,
+ OUT_ACCEL_REG(RADEON_PP_CNTL,
RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
- OUT_VIDEO_REG(RADEON_RB3D_CNTL,
+ OUT_ACCEL_REG(RADEON_RB3D_CNTL,
dst_format | RADEON_ALPHA_BLEND_ENABLE);
- OUT_VIDEO_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
+ OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
- OUT_VIDEO_REG(RADEON_RB3D_COLORPITCH, colorpitch);
+ OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch);
- OUT_VIDEO_REG(RADEON_RB3D_BLENDCNTL,
+ OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
- FINISH_VIDEO();
+ FINISH_ACCEL();
if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
@@ -1047,79 +1047,79 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
info->texW[0] = pPriv->w;
info->texH[0] = pPriv->h;
- BEGIN_VIDEO(12);
+ BEGIN_ACCEL(12);
- OUT_VIDEO_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
- OUT_VIDEO_REG(R200_SE_VTX_FMT_1,
+ OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
+ OUT_ACCEL_REG(R200_SE_VTX_FMT_1,
(2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
- OUT_VIDEO_REG(R200_PP_TXFILTER_0,
+ OUT_ACCEL_REG(R200_PP_TXFILTER_0,
R200_MAG_FILTER_LINEAR |
R200_MIN_FILTER_LINEAR |
R200_CLAMP_S_CLAMP_LAST |
R200_CLAMP_T_CLAMP_LAST |
R200_YUV_TO_RGB);
- OUT_VIDEO_REG(R200_PP_TXFORMAT_0, txformat);
- OUT_VIDEO_REG(R200_PP_TXFORMAT_X_0, 0);
- OUT_VIDEO_REG(R200_PP_TXSIZE_0,
+ OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
+ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
+ OUT_ACCEL_REG(R200_PP_TXSIZE_0,
(pPriv->w - 1) |
((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_VIDEO_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
+ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
- OUT_VIDEO_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
+ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
- OUT_VIDEO_REG(R200_PP_TXCBLEND_0,
+ OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
R200_TXC_ARG_A_ZERO |
R200_TXC_ARG_B_ZERO |
R200_TXC_ARG_C_R0_COLOR |
R200_TXC_OP_MADD);
- OUT_VIDEO_REG(R200_PP_TXCBLEND2_0,
+ OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
- OUT_VIDEO_REG(R200_PP_TXABLEND_0,
+ OUT_ACCEL_REG(R200_PP_TXABLEND_0,
R200_TXA_ARG_A_ZERO |
R200_TXA_ARG_B_ZERO |
R200_TXA_ARG_C_R0_ALPHA |
R200_TXA_OP_MADD);
- OUT_VIDEO_REG(R200_PP_TXABLEND2_0,
+ OUT_ACCEL_REG(R200_PP_TXABLEND2_0,
R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
- FINISH_VIDEO();
+ FINISH_ACCEL();
} else {
info->texW[0] = 1;
info->texH[0] = 1;
- BEGIN_VIDEO(8);
+ BEGIN_ACCEL(8);
- OUT_VIDEO_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
+ OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
RADEON_SE_VTX_FMT_ST0));
- OUT_VIDEO_REG(RADEON_PP_TXFILTER_0,
+ OUT_ACCEL_REG(RADEON_PP_TXFILTER_0,
RADEON_MAG_FILTER_LINEAR |
RADEON_MIN_FILTER_LINEAR |
RADEON_CLAMP_S_CLAMP_LAST |
RADEON_CLAMP_T_CLAMP_LAST |
RADEON_YUV_TO_RGB);
- OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat);
- OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset);
- OUT_VIDEO_REG(RADEON_PP_TXCBLEND_0,
+ OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat);
+ OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset);
+ OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
RADEON_COLOR_ARG_C_T0_COLOR |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_VIDEO_REG(RADEON_PP_TXABLEND_0,
+ OUT_ACCEL_REG(RADEON_PP_TXABLEND_0,
RADEON_ALPHA_ARG_A_ZERO |
RADEON_ALPHA_ARG_B_ZERO |
RADEON_ALPHA_ARG_C_T0_ALPHA |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_VIDEO_REG(RADEON_PP_TEX_SIZE_0,
+ OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0,
(pPriv->w - 1) |
((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_VIDEO_REG(RADEON_PP_TEX_PITCH_0,
+ OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0,
pPriv->src_pitch - 32);
- FINISH_VIDEO();
+ FINISH_ACCEL();
}
}
@@ -1180,19 +1180,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
}
#else /* ACCEL_CP */
if (IS_R300_3D || IS_R500_3D)
- BEGIN_VIDEO(2 + vtx_count * 4);
+ BEGIN_ACCEL(2 + vtx_count * 4);
else if (info->ChipFamily < CHIP_FAMILY_R200)
- BEGIN_VIDEO(1 + vtx_count * 3);
+ BEGIN_ACCEL(1 + vtx_count * 3);
else
- BEGIN_VIDEO(1 + vtx_count * 4);
+ BEGIN_ACCEL(1 + vtx_count * 4);
if (info->ChipFamily < CHIP_FAMILY_R200)
- OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
+ OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
RADEON_VF_RADEON_MODE |
(3 << RADEON_VF_NUM_VERTICES_SHIFT)));
else
- OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
+ OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
RADEON_VF_PRIM_WALK_DATA |
(4 << RADEON_VF_NUM_VERTICES_SHIFT)));
@@ -1225,24 +1225,24 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (IS_R300_3D || IS_R500_3D)
/* flushing is pipelined, free/finish is not */
- OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
#ifdef ACCEL_CP
ADVANCE_RING();
#else
- FINISH_VIDEO();
+ FINISH_ACCEL();
#endif /* !ACCEL_CP */
pBox++;
}
if (IS_R300_3D || IS_R500_3D) {
- BEGIN_VIDEO(2);
- OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL);
+ BEGIN_ACCEL(2);
+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL);
} else
- BEGIN_VIDEO(1);
- OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
- FINISH_VIDEO();
+ BEGIN_ACCEL(1);
+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+ FINISH_ACCEL();
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
}
commit 01daef0f095fbbaee701d5fe97f3dd7838b5f915
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Aug 25 08:26:16 2008 -0400
Additional cleanups and re-arragement following bicubic merge
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index d0c5229..1de6bf8 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -219,7 +219,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
/* pre-load the vertex shaders */
if (info->has_tcl) {
- /* exa mask shader program */
+ /* exa mask/Xv bicubic shader program */
BEGIN_ACCEL(13);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
/* PVS inst 0 */
@@ -499,14 +499,14 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
if (IS_R300_3D) {
BEGIN_ACCEL(2);
/* tex inst for src texture */
- OUT_ACCEL_REG(R300_US_TEX_INST_0,
+ OUT_ACCEL_REG(R300_US_TEX_INST(0),
(R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(0) |
R300_TEX_ID(0) |
R300_TEX_INST(R300_TEX_INST_LD)));
/* tex inst for mask texture */
- OUT_ACCEL_REG(R300_US_TEX_INST_1,
+ OUT_ACCEL_REG(R300_US_TEX_INST(1),
(R300_TEX_SRC_ADDR(1) |
R300_TEX_DST_ADDR(1) |
R300_TEX_ID(1) |
@@ -515,9 +515,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
}
if (IS_R300_3D) {
- BEGIN_ACCEL(9);
+ BEGIN_ACCEL(8);
OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
(R300_ALU_START(0) |
R300_ALU_SIZE(0) |
@@ -534,9 +533,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
R300_TEX_START(0) |
R300_TEX_SIZE(0)));
} else {
- BEGIN_ACCEL(7);
+ BEGIN_ACCEL(6);
OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
}
OUT_ACCEL_REG(R300_US_W_FMT, 0);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 5d28d80..043b0d4 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1419,7 +1419,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
/* setup the rasterizer, load FS */
- BEGIN_ACCEL(9);
+ BEGIN_ACCEL(10);
if (pMask) {
/* 4 components: 2 for tex0, 2 for tex1 */
OUT_ACCEL_REG(R300_RS_COUNT,
@@ -1461,6 +1461,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_RGBA_OUT));
}
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
/* shader output swizzling */
OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
@@ -1474,7 +1475,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
* R300_ALU_RGB_OMASK - output components to write
* R300_ALU_RGB_TARGET_A - render target
*/
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0),
(R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(1) |
R300_ALU_RGB_ADDR2(0) |
@@ -1486,7 +1487,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
/* RGB inst
* ALU operation
*/
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0),
(R300_ALU_RGB_SEL_A(src_color) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(mask_color) |
@@ -1503,7 +1504,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
* R300_ALU_ALPHA_OMASK - output components to write
* R300_ALU_ALPHA_TARGET_A - render target
*/
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0),
(R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(1) |
R300_ALU_ALPHA_ADDR2(0) |
@@ -1514,7 +1515,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
/* Alpha inst
* ALU operation
*/
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0),
(R300_ALU_ALPHA_SEL_A(src_alpha) |
R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
R300_ALU_ALPHA_SEL_B(mask_alpha) |
@@ -1633,7 +1634,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
break;
}
- BEGIN_ACCEL(6);
+ BEGIN_ACCEL(7);
if (pMask) {
/* 4 components: 2 for tex0, 2 for tex1 */
OUT_ACCEL_REG(R300_RS_COUNT,
@@ -1662,12 +1663,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
}
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
FINISH_ACCEL();
if (pMask) {
BEGIN_ACCEL(19);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
/* tex inst for src texture */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_RGB_WMASK_R |
@@ -1739,7 +1741,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
} else {
BEGIN_ACCEL(13);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
/* tex inst for src texture */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 97cb4b6..19f9869 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4258,7 +4258,7 @@
#define R300_PVS_SRC_ADDR_SEL(x) (x << 29)
#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31)
-#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
+#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc
#define R300_VAP_OUT_VTX_FMT_0 0x2090
# define R300_VTX_POS_PRESENT (1 << 0)
# define R300_VTX_COLOR_0_PRESENT (1 << 1)
@@ -4806,10 +4806,11 @@
/* R500 US has to be loaded through an index/data pair */
#define R500_GA_US_VECTOR_INDEX 0x4250
-# define R500_US_VECTOR_INDEX(x) (x << 0)
# define R500_US_VECTOR_TYPE_INST (0 << 16)
# define R500_US_VECTOR_TYPE_CONST (1 << 16)
# define R500_US_VECTOR_CLAMP (1 << 17)
+# define R500_US_VECTOR_INST_INDEX(x) ((x) | R500_US_VECTOR_TYPE_INST)
+# define R500_US_VECTOR_CONST_INDEX(x) ((x) | R500_US_VECTOR_TYPE_CONST)
#define R500_GA_US_VECTOR_DATA 0x4254
/*
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 8162281..da1d60f 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -342,7 +342,7 @@ static XF86VideoFormatRec Formats[NUM_FORMATS] =
static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] =
{
- {XvSettable | XvGettable, -1, 1, "XV_BICUBIC"},
+ {XvSettable | XvGettable, 0, 1, "XV_BICUBIC"},
{0, 0, 0, NULL}
};
@@ -389,9 +389,7 @@ RADEONSetTexPortAttribute(ScrnInfoPtr pScrn,
RADEON_SYNC(info, pScrn);
if (attribute == xvBicubic)
- /* -1 -> set default */
- pPriv->bicubic_enabled = (value == -1) ?
- (info->ChipFamily >= CHIP_FAMILY_RV515) : value;
+ pPriv->bicubic_enabled = ClipValue (value, 0, 1);
else
return BadMatch;
@@ -431,8 +429,13 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
pPortPriv =
(RADEONPortPrivPtr)(&adapt->pPortPrivates[num_texture_ports]);
- adapt->nAttributes = NUM_ATTRIBUTES;
- adapt->pAttributes = Attributes;
+ if (IS_R500_3D) {
+ adapt->nAttributes = NUM_ATTRIBUTES;
+ adapt->pAttributes = Attributes;
+ } else {
+ adapt->nAttributes = 0;
+ adapt->pAttributes = NULL;
+ }
adapt->pImages = Images;
adapt->nImages = NUM_IMAGES;
adapt->PutVideo = NULL;
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index ce60b05..b53e114 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -100,7 +100,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
uint32_t dst_offset, dst_pitch, dst_format;
uint32_t txenable, colorpitch;
uint32_t blendcntl;
- int dstxoff, dstyoff, pixel_shift;
+ int dstxoff, dstyoff, pixel_shift, vtx_count;
BoxPtr pBox = REGION_RECTS(&pPriv->clip);
int nBox = REGION_NUM_RECTS(&pPriv->clip);
VIDEO_PREAMBLE();
@@ -144,6 +144,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_WAIT_DMA_GUI_IDLE);
FINISH_VIDEO();
+ if (pPriv->bicubic_enabled)
+ vtx_count = VTX_DWORD_COUNT_FILTER;
+ else
+ vtx_count = VTX_DWORD_COUNT;
+
if (IS_R300_3D || IS_R500_3D) {
uint32_t output_fmt;
@@ -181,16 +186,17 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP;
txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
- (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
-
- txformat0 |= R300_TXPITCH_EN;
+ (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) |
+ R300_TXPITCH_EN);
info->texW[0] = pPriv->w;
info->texH[0] = pPriv->h;
txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) |
- R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
+ R300_TX_MAG_FILTER_LINEAR |
+ R300_TX_MIN_FILTER_LINEAR |
+ (0 << R300_TX_ID_SHIFT));
/* pitch is in pixels */
txpitch = pPriv->src_pitch / 2;
@@ -217,19 +223,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (pPriv->bicubic_enabled) {
/* Size is 128x1 */
- txformat0 = (0x7f << R300_TXWIDTH_SHIFT) |
- (0x0 << R300_TXHEIGHT_SHIFT) |
- R300_TXPITCH_EN;
+ txformat0 = ((0x7f << R300_TXWIDTH_SHIFT) |
+ (0x0 << R300_TXHEIGHT_SHIFT) |
+ R300_TXPITCH_EN);
/* Format is 32-bit floats, 4bpp */
txformat1 = R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16);
/* Pitch is 127 (128-1) */
txpitch = 0x7f;
/* Tex filter */
- txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP) |
- R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP) |
- R300_TX_MIN_FILTER_NEAREST |
- R300_TX_MAG_FILTER_NEAREST |
- (1 << R300_TX_ID_SHIFT);
+ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP) |
+ R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP) |
+ R300_TX_MIN_FILTER_NEAREST |
+ R300_TX_MAG_FILTER_NEAREST |
+ (1 << R300_TX_ID_SHIFT));
BEGIN_VIDEO(6);
OUT_VIDEO_REG(R300_TX_FILTER0_1, txfilter);
@@ -272,64 +278,64 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
*/
if (pPriv->bicubic_enabled) {
OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (6 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_SIGNED_1));
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (6 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_SIGNED_1));
OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_1,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
- (0 << R300_SKIP_DWORDS_2_SHIFT) |
- (7 << R300_DST_VEC_LOC_2_SHIFT) |
- R300_LAST_VEC_2 |
- R300_SIGNED_2));
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
+ (0 << R300_SKIP_DWORDS_2_SHIFT) |
+ (7 << R300_DST_VEC_LOC_2_SHIFT) |
+ R300_LAST_VEC_2 |
+ R300_SIGNED_2));
} else {
OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (6 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_LAST_VEC_1 |
- R300_SIGNED_1));
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (6 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_LAST_VEC_1 |
+ R300_SIGNED_1));
}
/* load the vertex shader
* We pre-load vertex programs in RADEONInit3DEngine():
- * - exa no mask/Xv bicubic
- * - exa mask
+ * - exa mask/Xv bicubic
+ * - exa no mask
* - Xv
* Here we select the offset of the vertex program we want to use
*/
if (info->has_tcl) {
if (pPriv->bicubic_enabled) {
OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
- ((0 << R300_PVS_FIRST_INST_SHIFT) |
- (2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (2 << R300_PVS_LAST_INST_SHIFT)));
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (2 << R300_PVS_LAST_INST_SHIFT)));
OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
- (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
} else {
OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
- ((5 << R300_PVS_FIRST_INST_SHIFT) |
- (6 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (6 << R300_PVS_LAST_INST_SHIFT)));
+ ((5 << R300_PVS_FIRST_INST_SHIFT) |
+ (6 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (6 << R300_PVS_LAST_INST_SHIFT)));
OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
- (6 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ (6 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
}
}
/* Position and one set of 2 texture coordinates */
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
- if (pPriv->bicubic_enabled) {
+ if (pPriv->bicubic_enabled)
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
(2 << R300_TEX_1_COMP_CNT_SHIFT)));
- } else
+ else
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt);
@@ -337,7 +343,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* setup pixel shader */
if (IS_R300_3D) {
- BEGIN_VIDEO(8);
+ BEGIN_VIDEO(9);
/* 2 components: 2 for tex0 */
OUT_VIDEO_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -345,6 +351,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* R300_INST_COUNT_RS - highest RS instruction used */
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+ OUT_VIDEO_REG(R300_US_PIXSIZE, 0); /* highest temp used */
+
OUT_VIDEO_REG(R300_US_CODE_OFFSET,
(R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(1) |
@@ -414,7 +422,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
/* Pixel stack frame size. */
- OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(5));
+ OUT_VIDEO_REG(R300_US_PIXSIZE, 5);
/* FP length. */
OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
@@ -424,7 +432,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* Prepare for FP emission. */
OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
FINISH_VIDEO();
BEGIN_VIDEO(89);
@@ -865,7 +873,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_A_SWIZ_A));
/* Shader constants. */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, (1 << 16));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0));
/* const0 = {1 / texture[0].width, 0, 0, 0} */
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w));
@@ -879,14 +887,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
BEGIN_VIDEO(19);
/* 2 components: 2 for tex0 */
OUT_VIDEO_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
/* Pixel stack frame size. */
- OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(2));
+ OUT_VIDEO_REG(R300_US_PIXSIZE, 0); /* highest temp used */
/* FP length. */
OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
@@ -896,7 +904,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* Prepare for FP emission. */
OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
/* tex inst */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
@@ -972,7 +980,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
}
}
- BEGIN_VIDEO(5);
+ BEGIN_VIDEO(6);
OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
@@ -982,13 +990,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
/* no need to enable blending */
OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl);
- FINISH_VIDEO();
- BEGIN_VIDEO(1);
- if (pPriv->bicubic_enabled)
- OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT_FILTER);
- else
- OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT);
+ OUT_VIDEO_REG(R300_VAP_VTX_SIZE, vtx_count);
FINISH_VIDEO();
} else {
@@ -1023,15 +1026,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
BEGIN_VIDEO(5);
OUT_VIDEO_REG(RADEON_PP_CNTL,
- RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
+ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
OUT_VIDEO_REG(RADEON_RB3D_CNTL,
- dst_format | RADEON_ALPHA_BLEND_ENABLE);
+ dst_format | RADEON_ALPHA_BLEND_ENABLE);
OUT_VIDEO_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
OUT_VIDEO_REG(RADEON_RB3D_COLORPITCH, colorpitch);
OUT_VIDEO_REG(RADEON_RB3D_BLENDCNTL,
- RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
+ RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
FINISH_VIDEO();
@@ -1048,37 +1051,37 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
OUT_VIDEO_REG(R200_SE_VTX_FMT_1,
- (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
+ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
OUT_VIDEO_REG(R200_PP_TXFILTER_0,
- R200_MAG_FILTER_LINEAR |
- R200_MIN_FILTER_LINEAR |
- R200_CLAMP_S_CLAMP_LAST |
- R200_CLAMP_T_CLAMP_LAST |
- R200_YUV_TO_RGB);
+ R200_MAG_FILTER_LINEAR |
+ R200_MIN_FILTER_LINEAR |
+ R200_CLAMP_S_CLAMP_LAST |
+ R200_CLAMP_T_CLAMP_LAST |
+ R200_YUV_TO_RGB);
OUT_VIDEO_REG(R200_PP_TXFORMAT_0, txformat);
OUT_VIDEO_REG(R200_PP_TXFORMAT_X_0, 0);
OUT_VIDEO_REG(R200_PP_TXSIZE_0,
- (pPriv->w - 1) |
- ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
+ (pPriv->w - 1) |
+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
OUT_VIDEO_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
OUT_VIDEO_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
OUT_VIDEO_REG(R200_PP_TXCBLEND_0,
- R200_TXC_ARG_A_ZERO |
- R200_TXC_ARG_B_ZERO |
- R200_TXC_ARG_C_R0_COLOR |
- R200_TXC_OP_MADD);
+ R200_TXC_ARG_A_ZERO |
+ R200_TXC_ARG_B_ZERO |
+ R200_TXC_ARG_C_R0_COLOR |
+ R200_TXC_OP_MADD);
OUT_VIDEO_REG(R200_PP_TXCBLEND2_0,
- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
+ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
OUT_VIDEO_REG(R200_PP_TXABLEND_0,
- R200_TXA_ARG_A_ZERO |
- R200_TXA_ARG_B_ZERO |
- R200_TXA_ARG_C_R0_ALPHA |
- R200_TXA_OP_MADD);
+ R200_TXA_ARG_A_ZERO |
+ R200_TXA_ARG_B_ZERO |
+ R200_TXA_ARG_C_R0_ALPHA |
+ R200_TXA_OP_MADD);
OUT_VIDEO_REG(R200_PP_TXABLEND2_0,
- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
+ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
FINISH_VIDEO();
} else {
@@ -1087,35 +1090,35 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
BEGIN_VIDEO(8);
- OUT_VIDEO_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
- RADEON_SE_VTX_FMT_ST0);
+ OUT_VIDEO_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
+ RADEON_SE_VTX_FMT_ST0));
OUT_VIDEO_REG(RADEON_PP_TXFILTER_0,
- RADEON_MAG_FILTER_LINEAR |
- RADEON_MIN_FILTER_LINEAR |
- RADEON_CLAMP_S_CLAMP_LAST |
- RADEON_CLAMP_T_CLAMP_LAST |
- RADEON_YUV_TO_RGB);
+ RADEON_MAG_FILTER_LINEAR |
+ RADEON_MIN_FILTER_LINEAR |
+ RADEON_CLAMP_S_CLAMP_LAST |
+ RADEON_CLAMP_T_CLAMP_LAST |
+ RADEON_YUV_TO_RGB);
OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat);
OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset);
OUT_VIDEO_REG(RADEON_PP_TXCBLEND_0,
- RADEON_COLOR_ARG_A_ZERO |
- RADEON_COLOR_ARG_B_ZERO |
- RADEON_COLOR_ARG_C_T0_COLOR |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
+ RADEON_COLOR_ARG_A_ZERO |
+ RADEON_COLOR_ARG_B_ZERO |
+ RADEON_COLOR_ARG_C_T0_COLOR |
+ RADEON_BLEND_CTL_ADD |
+ RADEON_CLAMP_TX);
OUT_VIDEO_REG(RADEON_PP_TXABLEND_0,
- RADEON_ALPHA_ARG_A_ZERO |
- RADEON_ALPHA_ARG_B_ZERO |
- RADEON_ALPHA_ARG_C_T0_ALPHA |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
+ RADEON_ALPHA_ARG_A_ZERO |
+ RADEON_ALPHA_ARG_B_ZERO |
+ RADEON_ALPHA_ARG_C_T0_ALPHA |
+ RADEON_BLEND_CTL_ADD |
+ RADEON_CLAMP_TX);
OUT_VIDEO_REG(RADEON_PP_TEX_SIZE_0,
- (pPriv->w - 1) |
- ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
+ (pPriv->w - 1) |
+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
OUT_VIDEO_REG(RADEON_PP_TEX_PITCH_0,
- pPriv->src_pitch - 32);
+ pPriv->src_pitch - 32);
FINISH_VIDEO();
}
}
@@ -1154,9 +1157,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
#ifdef ACCEL_CP
if (info->ChipFamily < CHIP_FAMILY_R200) {
- BEGIN_RING(3 * VTX_DWORD_COUNT + 3);
+ BEGIN_RING(3 * vtx_count + 3);
OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD,
- 3 * VTX_DWORD_COUNT + 1));
+ 3 * vtx_count + 1));
OUT_RING(RADEON_CP_VC_FRMT_XY |
RADEON_CP_VC_FRMT_ST0);
OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
@@ -1165,43 +1168,34 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
(3 << RADEON_CP_VC_CNTL_NUM_SHIFT));
} else {
- if (IS_R300_3D || IS_R500_3D) {
- if (pPriv->bicubic_enabled)
- BEGIN_RING(4 * VTX_DWORD_COUNT_FILTER + 4);
- else
- BEGIN_RING(4 * VTX_DWORD_COUNT + 4);
- } else
- BEGIN_RING(4 * VTX_DWORD_COUNT + 2);
- if (pPriv->bicubic_enabled)
- OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
- 4 * VTX_DWORD_COUNT_FILTER));
+ if (IS_R300_3D || IS_R500_3D)
+ BEGIN_RING(4 * vtx_count + 4);
else
- OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
- 4 * VTX_DWORD_COUNT));
+ BEGIN_RING(4 * vtx_count + 2);
+ OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
+ 4 * vtx_count));
OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST |
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
}
#else /* ACCEL_CP */
- if (pPriv->bicubic_enabled)
- BEGIN_VIDEO(2 + VTX_DWORD_COUNT_FILTER * 4);
- else if (IS_R300_3D || IS_R500_3D)
- BEGIN_VIDEO(2 + VTX_DWORD_COUNT * 4);
+ if (IS_R300_3D || IS_R500_3D)
+ BEGIN_VIDEO(2 + vtx_count * 4);
else if (info->ChipFamily < CHIP_FAMILY_R200)
- BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 3);
+ BEGIN_VIDEO(1 + vtx_count * 3);
else
- BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4);
+ BEGIN_VIDEO(1 + vtx_count * 4);
- if (info->ChipFamily < CHIP_FAMILY_R200) {
+ if (info->ChipFamily < CHIP_FAMILY_R200)
OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
RADEON_VF_RADEON_MODE |
(3 << RADEON_VF_NUM_VERTICES_SHIFT)));
- } else {
+ else
OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
RADEON_VF_PRIM_WALK_DATA |
(4 << RADEON_VF_NUM_VERTICES_SHIFT)));
- }
+
#endif
if (pPriv->bicubic_enabled) {
VTX_OUT_FILTER((float)dstX, (float)dstY,
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 46a2e55..e71f0f8 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -89,10 +89,6 @@ static void RADEON_MSP_SetEncoding(RADEONPortPrivPtr pPriv);
static void RADEON_TDA9885_SetEncoding(RADEONPortPrivPtr pPriv);
static void RADEON_FI1236_SetEncoding(RADEONPortPrivPtr pPriv);
-
-
-#define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v))
-
static Atom xvBrightness, xvColorKey, xvSaturation, xvDoubleBuffer;
static Atom xvRedIntensity, xvGreenIntensity, xvBlueIntensity;
static Atom xvContrast, xvHue, xvColor, xvAutopaintColorkey, xvSetDefaults;
diff --git a/src/radeon_video.h b/src/radeon_video.h
index abf8d98..b9d900d 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -15,6 +15,8 @@
#include "bicubic_table.h"
+#define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v))
+
/* Xvideo port struct */
typedef struct {
uint32_t transform_index;
commit 0a51d08c24af040fe48690662b1a912acad51700
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Aug 25 06:43:14 2008 -0400
Whitespace cleanup from bucubic merge
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index ab08fec..97cb4b6 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4530,7 +4530,7 @@
#define R300_US_TEX_INST_0 0x4620
#define R300_US_TEX_INST_1 0x4624
#define R300_US_TEX_INST_2 0x4628
-# define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4)
+#define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4)
# define R300_TEX_SRC_ADDR(x) (x << 0)
# define R300_TEX_DST_ADDR(x) (x << 6)
# define R300_TEX_ID(x) (x << 11)
@@ -4543,7 +4543,7 @@
#define R300_US_ALU_RGB_ADDR_0 0x46c0
#define R300_US_ALU_RGB_ADDR_1 0x46c4
#define R300_US_ALU_RGB_ADDR_2 0x46c8
-# define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4)
+#define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_RGB_ADDR0(x) (x << 0)
@@ -4567,7 +4567,7 @@
#define R300_US_ALU_RGB_INST_0 0x48c0
#define R300_US_ALU_RGB_INST_1 0x48c4
#define R300_US_ALU_RGB_INST_2 0x48c8
-# define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4)
+#define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4)
# define R300_ALU_RGB_SEL_A(x) (x << 0)
# define R300_ALU_RGB_SRC0_RGB 0
# define R300_ALU_RGB_SRC0_RRR 1
@@ -4639,7 +4639,7 @@
#define R300_US_ALU_ALPHA_ADDR_0 0x47c0
#define R300_US_ALU_ALPHA_ADDR_1 0x47c4
#define R300_US_ALU_ALPHA_ADDR_2 0x47c8
-# define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4)
+#define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_ALPHA_ADDR0(x) (x << 0)
@@ -4661,7 +4661,7 @@
#define R300_US_ALU_ALPHA_INST_0 0x49c0
#define R300_US_ALU_ALPHA_INST_1 0x49c4
#define R300_US_ALU_ALPHA_INST_2 0x49c8
-# define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4)
+#define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4)
# define R300_ALU_ALPHA_SEL_A(x) (x << 0)
# define R300_ALU_ALPHA_SRC0_R 0
# define R300_ALU_ALPHA_SRC0_G 1
@@ -4719,13 +4719,13 @@
# define R300_ALU_ALPHA_CLAMP (1 << 30)
#define R300_US_ALU_CONST_R_0 0x4c00
-# define R300_US_ALU_CONST_R(x) (R300_US_ALU_CONST_R_0 + (x)*16)
+#define R300_US_ALU_CONST_R(x) (R300_US_ALU_CONST_R_0 + (x)*16)
#define R300_US_ALU_CONST_G_0 0x4c04
-# define R300_US_ALU_CONST_G(x) (R300_US_ALU_CONST_G_0 + (x)*16)
+#define R300_US_ALU_CONST_G(x) (R300_US_ALU_CONST_G_0 + (x)*16)
#define R300_US_ALU_CONST_B_0 0x4c08
-# define R300_US_ALU_CONST_B(x) (R300_US_ALU_CONST_B_0 + (x)*16)
+#define R300_US_ALU_CONST_B(x) (R300_US_ALU_CONST_B_0 + (x)*16)
#define R300_US_ALU_CONST_A_0 0x4c0c
-# define R300_US_ALU_CONST_A(x) (R300_US_ALU_CONST_A_0 + (x)*16)
+#define R300_US_ALU_CONST_A(x) (R300_US_ALU_CONST_A_0 + (x)*16)
#define R300_FG_DEPTH_SRC 0x4bd8
#define R300_FG_FOG_BLEND 0x4bc0
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 314a71d..ce60b05 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -327,11 +327,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* Position and one set of 2 texture coordinates */
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
if (pPriv->bicubic_enabled) {
- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT) |
- (2 << R300_TEX_1_COMP_CNT_SHIFT));
- } else {
+ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
+ (2 << R300_TEX_1_COMP_CNT_SHIFT)));
+ } else
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
- }
+
OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt);
FINISH_VIDEO();
@@ -407,8 +407,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* 4 components: 2 for tex0 and 2 for tex1 */
OUT_VIDEO_REG(R300_RS_COUNT,
- ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
@@ -418,9 +418,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* FP length. */
OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(13)));
+ R500_US_CODE_END_ADDR(13)));
OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(13)));
+ R500_US_CODE_RANGE_SIZE(13)));
/* Prepare for FP emission. */
OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
@@ -436,309 +436,309 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* TEX temp2, input1.xxxx, tex1, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B));
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
- R500_TEX_INST_LD |
- R500_TEX_IGNORE_UNCOVERED));
+ R500_TEX_INST_LD |
+ R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_R |
- R500_TEX_SRC_R_SWIZ_R |
- R500_TEX_SRC_Q_SWIZ_R |
- R500_TEX_DST_ADDR(2) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_R |
+ R500_TEX_SRC_R_SWIZ_R |
+ R500_TEX_SRC_Q_SWIZ_R |
+ R500_TEX_DST_ADDR(2) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* TEX temp5, input1.yyyy, tex1, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B));
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
- R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
- R500_TEX_IGNORE_UNCOVERED));
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
- R500_TEX_SRC_S_SWIZ_G |
- R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_SRC_R_SWIZ_G |
- R500_TEX_SRC_Q_SWIZ_G |
- R500_TEX_DST_ADDR(5) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
+ R500_TEX_SRC_S_SWIZ_G |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_SRC_R_SWIZ_G |
+ R500_TEX_SRC_Q_SWIZ_G |
+ R500_TEX_DST_ADDR(5) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* MUL temp4, const0.x0x0, temp2.yyxx */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(2)));
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(2)));
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_0 |
- R500_ALU_RGB_B_SWIZ_A_R |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_G |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_R));
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_0 |
+ R500_ALU_RGB_B_SWIZ_A_R |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_G |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_0 |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_R));
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
+ R500_ALPHA_SWIZ_A_0 |
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 |
- R500_ALU_RGBA_G_SWIZ_0 |
- R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));
/* MAD temp3, const0.0y0y, temp5.xxxx, temp4 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(5) |
- R500_RGB_ADDR2(4)));
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(5) |
+ R500_RGB_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(5) |
- R500_ALPHA_ADDR2(4)));
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(5) |
+ R500_ALPHA_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_0 |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_0 |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_R |
- R500_ALU_RGB_B_SWIZ_B_R));
+ R500_ALU_RGB_R_SWIZ_A_0 |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_0 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_R |
+ R500_ALU_RGB_B_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_G |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_R));
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
+ R500_ALPHA_SWIZ_A_G |
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
/* ADD temp3, temp3, input0.xyxy */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(3) |
- R500_RGB_ADDR2(0)));
+ R500_RGB_ADDR2(0)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(3) |
- R500_ALPHA_ADDR2(0)));
+ R500_ALPHA_ADDR2(0)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
- R500_ALU_RGB_G_SWIZ_A_1 |
- R500_ALU_RGB_B_SWIZ_A_1 |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_1 |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A));
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_R |
- R500_ALU_RGBA_A_SWIZ_G));
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_R |
+ R500_ALU_RGBA_A_SWIZ_G));
/* TEX temp1, temp3.zwxy, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
- R500_TEX_INST_LD |
- R500_TEX_IGNORE_UNCOVERED));
+ R500_TEX_INST_LD |
+ R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
- R500_TEX_SRC_S_SWIZ_B |
- R500_TEX_SRC_T_SWIZ_A |
- R500_TEX_SRC_R_SWIZ_R |
- R500_TEX_SRC_Q_SWIZ_G |
- R500_TEX_DST_ADDR(1) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
+ R500_TEX_SRC_S_SWIZ_B |
+ R500_TEX_SRC_T_SWIZ_A |
+ R500_TEX_SRC_R_SWIZ_R |
+ R500_TEX_SRC_Q_SWIZ_G |
+ R500_TEX_DST_ADDR(1) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* TEX temp3, temp3.xyzw, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
- R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
- R500_TEX_IGNORE_UNCOVERED));
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_SRC_R_SWIZ_B |
- R500_TEX_SRC_Q_SWIZ_A |
- R500_TEX_DST_ADDR(3) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_SRC_R_SWIZ_B |
+ R500_TEX_SRC_Q_SWIZ_A |
+ R500_TEX_DST_ADDR(3) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* MAD temp4, const1.0y0y, temp5.yyyy, temp4 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(5) |
- R500_RGB_ADDR2(4)));
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(5) |
+ R500_RGB_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(5) |
- R500_ALPHA_ADDR2(4)));
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(5) |
+ R500_ALPHA_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_0 |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_0 |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_G |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_G));
+ R500_ALU_RGB_R_SWIZ_A_0 |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_0 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_G |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_G));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_G |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_G));
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
+ R500_ALPHA_SWIZ_A_G |
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_G));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
/* ADD temp0, temp4, input0.xyxy */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
- R500_RGB_ADDR2(0)));
+ R500_RGB_ADDR2(0)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
- R500_ALPHA_ADDR2(0)));
+ R500_ALPHA_ADDR2(0)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
- R500_ALU_RGB_G_SWIZ_A_1 |
- R500_ALU_RGB_B_SWIZ_A_1 |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_1 |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A));
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_R |
- R500_ALU_RGBA_A_SWIZ_G));
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_R |
+ R500_ALU_RGBA_A_SWIZ_G));
/* TEX temp4, temp0.zwzw, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
- R500_TEX_INST_LD |
- R500_TEX_IGNORE_UNCOVERED));
+ R500_TEX_INST_LD |
+ R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
- R500_TEX_SRC_S_SWIZ_B |
- R500_TEX_SRC_T_SWIZ_A |
- R500_TEX_SRC_R_SWIZ_B |
- R500_TEX_SRC_Q_SWIZ_A |
- R500_TEX_DST_ADDR(4) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
+ R500_TEX_SRC_S_SWIZ_B |
+ R500_TEX_SRC_T_SWIZ_A |
+ R500_TEX_SRC_R_SWIZ_B |
+ R500_TEX_SRC_Q_SWIZ_A |
+ R500_TEX_DST_ADDR(4) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* TEX temp0, temp0.xyzw, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
- R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
- R500_TEX_IGNORE_UNCOVERED));
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_SRC_R_SWIZ_B |
- R500_TEX_SRC_Q_SWIZ_A |
- R500_TEX_DST_ADDR(0) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_SRC_R_SWIZ_B |
+ R500_TEX_SRC_Q_SWIZ_A |
+ R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
@@ -747,122 +747,122 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
* - PRESUB temps, temp1 - temp3
* - MAD temp2.zzzz, temps, temp3 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
- R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
- R500_RGB_ADDR1(1) |
- R500_RGB_ADDR2(2)));
+ R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
+ R500_RGB_ADDR1(1) |
+ R500_RGB_ADDR2(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
- R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
- R500_ALPHA_ADDR1(1) |
- R500_ALPHA_ADDR2(2)));
+ R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
+ R500_ALPHA_ADDR1(1) |
+ R500_ALPHA_ADDR2(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
- R500_ALU_RGB_R_SWIZ_A_B |
- R500_ALU_RGB_G_SWIZ_A_B |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRCP |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
+ R500_ALU_RGB_R_SWIZ_A_B |
+ R500_ALU_RGB_G_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRCP |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC2 |
- R500_ALPHA_SWIZ_A_B |
- R500_ALPHA_SEL_B_SRCP |
- R500_ALPHA_SWIZ_B_A));
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC2 |
+ R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SEL_B_SRCP |
+ R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC0 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC0 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
/* LRP temp0, temp2.zzzz, temp4, temp0 ->
* - PRESUB temps, temp4 - temp1
* - MAD temp2.zzzz, temps, temp0 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
- R500_RGB_ADDR1(4) |
- R500_RGB_ADDR2(2)));
+ R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
+ R500_RGB_ADDR1(4) |
+ R500_RGB_ADDR2(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
- R500_ALPHA_ADDR1(4) |
- R500_ALPHA_ADDR2(2)));
+ R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
+ R500_ALPHA_ADDR1(4) |
+ R500_ALPHA_ADDR2(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
- R500_ALU_RGB_R_SWIZ_A_B |
- R500_ALU_RGB_G_SWIZ_A_B |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRCP |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
+ R500_ALU_RGB_R_SWIZ_A_B |
+ R500_ALU_RGB_G_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRCP |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC2 |
- R500_ALPHA_SWIZ_A_B |
- R500_ALPHA_SEL_B_SRCP |
- R500_ALPHA_SWIZ_B_A));
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC2 |
+ R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SEL_B_SRCP |
+ R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC0 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC0 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
/* LRP output, temp5.zzzz, temp3, temp0 ->
* - PRESUB temps, temp3 - temp0
* - MAD temp5.zzzz, temps, temp0 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
- R500_INST_LAST |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK |
- R500_INST_RGB_OMASK_R |
- R500_INST_RGB_OMASK_G |
- R500_INST_RGB_OMASK_B |
- R500_INST_ALPHA_OMASK));
+ R500_INST_LAST |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_OMASK_R |
+ R500_INST_RGB_OMASK_G |
+ R500_INST_RGB_OMASK_B |
+ R500_INST_ALPHA_OMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
- R500_RGB_ADDR1(3) |
- R500_RGB_ADDR2(5)));
+ R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
+ R500_RGB_ADDR1(3) |
+ R500_RGB_ADDR2(5)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
- R500_ALPHA_ADDR1(3) |
- R500_ALPHA_ADDR2(5)));
+ R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
+ R500_ALPHA_ADDR1(3) |
+ R500_ALPHA_ADDR2(5)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
- R500_ALU_RGB_R_SWIZ_A_B |
- R500_ALU_RGB_G_SWIZ_A_B |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRCP |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
+ R500_ALU_RGB_R_SWIZ_A_B |
+ R500_ALU_RGB_G_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRCP |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC2 |
- R500_ALPHA_SWIZ_A_B |
- R500_ALPHA_SEL_B_SRCP |
- R500_ALPHA_SWIZ_B_A));
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC2 |
+ R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SEL_B_SRCP |
+ R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC0 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC0 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
/* Shader constants. */
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, (1 << 16));
@@ -890,9 +890,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* FP length. */
OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(1)));
+ R500_US_CODE_END_ADDR(1)));
OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(1)));
+ R500_US_CODE_RANGE_SIZE(1)));
/* Prepare for FP emission. */
OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
@@ -900,74 +900,74 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* tex inst */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK |
- R500_INST_RGB_CLAMP |
- R500_INST_ALPHA_CLAMP));
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
- R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
- R500_TEX_IGNORE_UNCOVERED));
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_DST_ADDR(0) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
- R500_DX_S_SWIZ_R |
- R500_DX_T_SWIZ_R |
- R500_DX_R_SWIZ_R |
- R500_DX_Q_SWIZ_R |
- R500_DY_ADDR(0) |
- R500_DY_S_SWIZ_R |
- R500_DY_T_SWIZ_R |
- R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R));
+ R500_DX_S_SWIZ_R |
+ R500_DX_T_SWIZ_R |
+ R500_DX_R_SWIZ_R |
+ R500_DX_Q_SWIZ_R |
+ R500_DY_ADDR(0) |
+ R500_DY_S_SWIZ_R |
+ R500_DY_T_SWIZ_R |
+ R500_DY_R_SWIZ_R |
+ R500_DY_Q_SWIZ_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* ALU inst */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_LAST |
- R500_INST_RGB_OMASK_R |
- R500_INST_RGB_OMASK_G |
- R500_INST_RGB_OMASK_B |
- R500_INST_ALPHA_OMASK |
- R500_INST_RGB_CLAMP |
- R500_INST_ALPHA_CLAMP));
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_LAST |
+ R500_INST_RGB_OMASK_R |
+ R500_INST_RGB_OMASK_G |
+ R500_INST_RGB_OMASK_B |
+ R500_INST_ALPHA_OMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR1(0) |
- R500_RGB_ADDR1_CONST |
- R500_RGB_ADDR2(0) |
- R500_RGB_ADDR2_CONST));
+ R500_RGB_ADDR1(0) |
+ R500_RGB_ADDR1_CONST |
+ R500_RGB_ADDR2(0) |
+ R500_RGB_ADDR2_CONST));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR1(0) |
- R500_ALPHA_ADDR1_CONST |
- R500_ALPHA_ADDR2(0) |
- R500_ALPHA_ADDR2_CONST));
+ R500_ALPHA_ADDR1(0) |
+ R500_ALPHA_ADDR1_CONST |
+ R500_ALPHA_ADDR2(0) |
+ R500_ALPHA_ADDR2_CONST));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC0 |
- R500_ALU_RGB_R_SWIZ_B_1 |
- R500_ALU_RGB_B_SWIZ_B_1 |
- R500_ALU_RGB_G_SWIZ_B_1));
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC0 |
+ R500_ALU_RGB_R_SWIZ_B_1 |
+ R500_ALU_RGB_B_SWIZ_B_1 |
+ R500_ALU_RGB_G_SWIZ_B_1));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SWIZ_B_1));
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_1));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 |
- R500_ALU_RGBA_G_SWIZ_0 |
- R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));
FINISH_VIDEO();
}
}
commit c0170fef510b53a6ca2c6ea7a99119235229c929
Author: Maciej Cencora <m.cencora at gmail.com>
Date: Thu Aug 7 06:53:39 2008 -0700
Add needed FP registers, etc. for r3xx bicubic Xv.
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 8b47dba..ab08fec 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4530,6 +4530,7 @@
#define R300_US_TEX_INST_0 0x4620
#define R300_US_TEX_INST_1 0x4624
#define R300_US_TEX_INST_2 0x4628
+# define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4)
# define R300_TEX_SRC_ADDR(x) (x << 0)
# define R300_TEX_DST_ADDR(x) (x << 6)
# define R300_TEX_ID(x) (x << 11)
@@ -4542,11 +4543,13 @@
#define R300_US_ALU_RGB_ADDR_0 0x46c0
#define R300_US_ALU_RGB_ADDR_1 0x46c4
#define R300_US_ALU_RGB_ADDR_2 0x46c8
+# define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_RGB_ADDR0(x) (x << 0)
# define R300_ALU_RGB_ADDR1(x) (x << 6)
# define R300_ALU_RGB_ADDR2(x) (x << 12)
+# define R300_ALU_RGB_CONST(x) ((x) | (1 << 5))
/* ADDRD - where on the pixel stack the result of this instruction
will be written */
# define R300_ALU_RGB_ADDRD(x) (x << 18)
@@ -4556,6 +4559,7 @@
# define R300_ALU_RGB_MASK_R 1
# define R300_ALU_RGB_MASK_G 2
# define R300_ALU_RGB_MASK_B 4
+# define R300_ALU_RGB_MASK_RGB 7
# define R300_ALU_RGB_TARGET_A (0 << 29)
# define R300_ALU_RGB_TARGET_B (1 << 29)
# define R300_ALU_RGB_TARGET_C (2 << 29)
@@ -4563,6 +4567,7 @@
#define R300_US_ALU_RGB_INST_0 0x48c0
#define R300_US_ALU_RGB_INST_1 0x48c4
#define R300_US_ALU_RGB_INST_2 0x48c8
+# define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4)
# define R300_ALU_RGB_SEL_A(x) (x << 0)
# define R300_ALU_RGB_SRC0_RGB 0
# define R300_ALU_RGB_SRC0_RRR 1
@@ -4634,11 +4639,13 @@
#define R300_US_ALU_ALPHA_ADDR_0 0x47c0
#define R300_US_ALU_ALPHA_ADDR_1 0x47c4
#define R300_US_ALU_ALPHA_ADDR_2 0x47c8
+# define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_ALPHA_ADDR0(x) (x << 0)
# define R300_ALU_ALPHA_ADDR1(x) (x << 6)
# define R300_ALU_ALPHA_ADDR2(x) (x << 12)
+# define R300_ALU_ALPHA_CONST(x) ((x) | (1 << 5))
/* ADDRD - where on the pixel stack the result of this instruction
will be written */
# define R300_ALU_ALPHA_ADDRD(x) (x << 18)
@@ -4654,6 +4661,7 @@
#define R300_US_ALU_ALPHA_INST_0 0x49c0
#define R300_US_ALU_ALPHA_INST_1 0x49c4
#define R300_US_ALU_ALPHA_INST_2 0x49c8
+# define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4)
# define R300_ALU_ALPHA_SEL_A(x) (x << 0)
# define R300_ALU_ALPHA_SRC0_R 0
# define R300_ALU_ALPHA_SRC0_G 1
@@ -4710,6 +4718,15 @@
# define R300_ALU_ALPHA_OMOD_DIV_8 6
# define R300_ALU_ALPHA_CLAMP (1 << 30)
+#define R300_US_ALU_CONST_R_0 0x4c00
+# define R300_US_ALU_CONST_R(x) (R300_US_ALU_CONST_R_0 + (x)*16)
+#define R300_US_ALU_CONST_G_0 0x4c04
+# define R300_US_ALU_CONST_G(x) (R300_US_ALU_CONST_G_0 + (x)*16)
+#define R300_US_ALU_CONST_B_0 0x4c08
+# define R300_US_ALU_CONST_B(x) (R300_US_ALU_CONST_B_0 + (x)*16)
+#define R300_US_ALU_CONST_A_0 0x4c0c
+# define R300_US_ALU_CONST_A(x) (R300_US_ALU_CONST_A_0 + (x)*16)
+
#define R300_FG_DEPTH_SRC 0x4bd8
#define R300_FG_FOG_BLEND 0x4bc0
#define R300_FG_ALPHA_FUNC 0x4bd4
commit d9c38326cf70f57ab777ffdf9520b8cdea9d9cb6
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Tue Aug 5 18:45:38 2008 +0200
Fix typos.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 0ee9b64..314a71d 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -664,7 +664,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* ADD temp4, temp4, input0.xyxy */
+ /* ADD temp0, temp4, input0.xyxy */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -758,7 +758,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(1) |
- R500_ALPHA_ADDR1(2)));
+ R500_ALPHA_ADDR2(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
commit d38ceba62aa5cee76baa342ce7719a983a79f09e
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Tue Aug 5 16:21:57 2008 +0200
Fix bicubic fp calculation.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index df1d178..0ee9b64 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -550,15 +550,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* ADD temp3, temp4, input0.xyxy */
+ /* ADD temp3, temp3, input0.xyxy */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(3) |
R500_RGB_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(3) |
R500_ALPHA_ADDR2(0)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
R500_ALU_RGB_G_SWIZ_A_1 |
commit 6f9c7fde75edc0399559f975db9a6c4dc22714ae
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Tue Aug 5 15:38:42 2008 +0200
Fixed bicubic fragment program comments.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index dbcd353..df1d178 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -434,7 +434,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
* Note: In order to avoid buggies with temps and multiple
* inputs, all temps are offset by 2. temp0 -> register2. */
- /* TEX temp0, input1.xxxx, tex1, 1D */
+ /* TEX temp2, input1.xxxx, tex1, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -456,7 +456,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp1, input1.yyyy, tex1, 1D */
+ /* TEX temp5, input1.yyyy, tex1, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -480,7 +480,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* MUL temp2, const0, temp0.yyyy */
+ /* MUL temp4, const0.x0x0, temp2.yyxx */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -514,7 +514,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0));
- /* MAD temp2, const1, temp1.xxxx, temp2 */
+ /* MAD temp3, const0.0y0y, temp5.xxxx, temp4 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -550,7 +550,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* ADD temp2, temp2, input0 */
+ /* ADD temp3, temp4, input0.xyxy */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -580,7 +580,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_R |
R500_ALU_RGBA_A_SWIZ_G));
- /* TEX temp3, temp3, tex0, 1D */
+ /* TEX temp1, temp3.zwxy, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -603,7 +603,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp2, temp2, tex0, 1D */
+ /* TEX temp3, temp3.xyzw, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -628,7 +628,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* MAD temp4, const1, temp1.yyyy, temp2 */
+ /* MAD temp4, const1.0y0y, temp5.yyyy, temp4 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -664,7 +664,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* ADD temp4, temp4, input0 */
+ /* ADD temp4, temp4, input0.xyxy */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -694,7 +694,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_R |
R500_ALU_RGBA_A_SWIZ_G));
- /* TEX temp5, temp5, tex0, 1D */
+ /* TEX temp4, temp0.zwzw, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -718,7 +718,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp4, temp4, tex0, 1D */
+ /* TEX temp0, temp0.xyzw, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -743,9 +743,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* LRP temp3, temp1.zzzz, temp3, temp5 ->
- * - PRESUB temps, temp3 - temp5
- * - MAD temp1.zzzz, temps, temp5 */
+ /* LRP temp3, temp2.zzzz, temp1, temp3 ->
+ * - PRESUB temps, temp1 - temp3
+ * - MAD temp2.zzzz, temps, temp3 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -781,9 +781,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* LRP temp2, temp1.zzzz, temp2, temp4 ->
- * - PRESUB temps, temp2 - temp4
- * - MAD temp1.zzzz, temps, temp4 */
+ /* LRP temp0, temp2.zzzz, temp4, temp0 ->
+ * - PRESUB temps, temp4 - temp1
+ * - MAD temp2.zzzz, temps, temp0 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -820,9 +820,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* LRP output, temp0.zzzz, temp3, temp2 ->
- * - PRESUB temps, temp3 - temp2
- * - MAD temp0.zzzz, temps, temp2 */
+ /* LRP output, temp5.zzzz, temp3, temp0 ->
+ * - PRESUB temps, temp3 - temp0
+ * - MAD temp5.zzzz, temps, temp0 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_LAST |
R500_INST_TEX_SEM_WAIT |
commit 48b09ca40ccb28b5584069316fd38786a78c1dd3
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Sat Aug 2 02:36:21 2008 -0700
Switch from 32-bit floats to 16-bit half-floats.
Massive bandwidth savings, or so I'm told. Yay?
diff --git a/src/bicubic_table.h b/src/bicubic_table.h
index 3b728fa..765cfff 100644
--- a/src/bicubic_table.h
+++ b/src/bicubic_table.h
@@ -1,646 +1,646 @@
-static const uint32_t bicubic_tex_512[] = {
- 0xbe4ccccd, 0x3f800000, 0x3f555555, 0x3e2aaaab,
- 0xbe50fca2, 0x3f7e0008, 0x3f545358, 0x3e2eb2a0,
- 0xbe553a10, 0x3f7c003d, 0x3f534d6b, 0x3e32ca55,
- 0xbe5984de, 0x3f7a00ca, 0x3f52439d, 0x3e36f18b,
- 0xbe5ddcd4, 0x3f7801d3, 0x3f513600, 0x3e3b2800,
- 0xbe6241bc, 0x3f76037c, 0x3f5024a3, 0x3e3f6d75,
- 0xbe66b361, 0x3f7405e3, 0x3f4f0f95, 0x3e43c1ab,
- 0xbe6b3191, 0x3f720924, 0x3f4df6e8, 0x3e482460,
- 0xbe6fbc1a, 0x3f700d59, 0x3f4cdaab, 0x3e4c9555,
- 0xbe7452cb, 0x3f6e1299, 0x3f4bbaed, 0x3e51144b,
- 0xbe78f574, 0x3f6c18f7, 0x3f4a97c0, 0x3e55a100,
- 0xbe7da3e9, 0x3f6a2087, 0x3f497133, 0x3e5a3b35,
- 0xbe812efe, 0x3f682959, 0x3f484755, 0x3e5ee2ab,
- 0xbe8391c0, 0x3f66337c, 0x3f471a38, 0x3e639720,
- 0xbe85fa27, 0x3f643efd, 0x3f45e9eb, 0x3e685855,
- 0xbe88681d, 0x3f624be7, 0x3f44b67d, 0x3e6d260b,
- 0xbe8adb8e, 0x3f605a45, 0x3f438000, 0x3e720000,
- 0xbe8d5466, 0x3f5e6a21, 0x3f424683, 0x3e76e5f5,
- 0xbe8fd293, 0x3f5c7b81, 0x3f410a15, 0x3e7bd7ab,
- 0xbe925602, 0x3f5a8e6f, 0x3f3fcac8, 0x3e806a70,
- 0xbe94dea1, 0x3f58a2ef, 0x3f3e88ab, 0x3e82eeab,
- 0xbe976c5f, 0x3f56b908, 0x3f3d43cd, 0x3e857865,
- 0xbe99ff29, 0x3f54d0bd, 0x3f3bfc40, 0x3e880780,
- 0xbe9c96f0, 0x3f52ea14, 0x3f3ab213, 0x3e8a9bdb,
- 0xbe9f33a3, 0x3f510510, 0x3f396555, 0x3e8d3555,
- 0xbea1d533, 0x3f4f21b3, 0x3f381618, 0x3e8fd3d0,
- 0xbea47b90, 0x3f4d4001, 0x3f36c46b, 0x3e92772b,
- 0xbea726ab, 0x3f4b5ffb, 0x3f35705d, 0x3e951f45,
- 0xbea9d676, 0x3f4981a3, 0x3f341a00, 0x3e97cc00,
- 0xbeac8ae3, 0x3f47a4fc, 0x3f32c163, 0x3e9a7d3b,
- 0xbeaf43e3, 0x3f45ca05, 0x3f316695, 0x3e9d32d5,
- 0xbeb2016a, 0x3f43f0c0, 0x3f3009a8, 0x3e9fecb0,
- 0xbeb4c36b, 0x3f42192e, 0x3f2eaaab, 0x3ea2aaab,
- 0xbeb789da, 0x3f40434f, 0x3f2d49ad, 0x3ea56ca5,
- 0xbeba54a9, 0x3f3e6f24, 0x3f2be6c0, 0x3ea83280,
- 0xbebd23cd, 0x3f3c9cad, 0x3f2a81f3, 0x3eaafc1b,
- 0xbebff73b, 0x3f3acbea, 0x3f291b55, 0x3eadc955,
- 0xbec2cee8, 0x3f38fcdb, 0x3f27b2f8, 0x3eb09a10,
- 0xbec5aac9, 0x3f372f80, 0x3f2648eb, 0x3eb36e2b,
- 0xbec88ad2, 0x3f3563d9, 0x3f24dd3d, 0x3eb64585,
- 0xbecb6efb, 0x3f3399e6, 0x3f237000, 0x3eb92000,
- 0xbece573a, 0x3f31d1a7, 0x3f220143, 0x3ebbfd7b,
- 0xbed14384, 0x3f300b1c, 0x3f209115, 0x3ebeddd5,
- 0xbed433d1, 0x3f2e4645, 0x3f1f1f88, 0x3ec1c0f0,
- 0xbed72818, 0x3f2c8321, 0x3f1dacab, 0x3ec4a6ab,
- 0xbeda2051, 0x3f2ac1b1, 0x3f1c388d, 0x3ec78ee5,
- 0xbedd1c72, 0x3f2901f4, 0x3f1ac340, 0x3eca7980,
- 0xbee01c75, 0x3f2743ea, 0x3f194cd3, 0x3ecd665b,
- 0xbee32051, 0x3f258794, 0x3f17d555, 0x3ed05555,
- 0xbee627ff, 0x3f23ccf1, 0x3f165cd8, 0x3ed34650,
- 0xbee93378, 0x3f221402, 0x3f14e36b, 0x3ed6392b,
- 0xbeec42b6, 0x3f205cc7, 0x3f13691d, 0x3ed92dc5,
- 0xbeef55b1, 0x3f1ea740, 0x3f11ee00, 0x3edc2400,
- 0xbef26c63, 0x3f1cf36e, 0x3f107223, 0x3edf1bbb,
- 0xbef586c7, 0x3f1b4150, 0x3f0ef595, 0x3ee214d5,
- 0xbef8a4d6, 0x3f1990e8, 0x3f0d7868, 0x3ee50f30,
- 0xbefbc68b, 0x3f17e236, 0x3f0bfaab, 0x3ee80aab,
- 0xbefeebe2, 0x3f16353b, 0x3f0a7c6d, 0x3eeb0725,
- 0xbf010a6a, 0x3f1489f8, 0x3f08fdc0, 0x3eee0480,
- 0xbf02a0af, 0x3f12e06d, 0x3f077eb3, 0x3ef1029b,
- 0xbf0438bd, 0x3f11389b, 0x3f05ff55, 0x3ef40155,
- 0xbf05d292, 0x3f0f9284, 0x3f047fb8, 0x3ef70090,
- 0xbf076e2d, 0x3f0dee29, 0x3f02ffeb, 0x3efa002b,
- 0xbf090b8b, 0x3f0c4b8a, 0x3f017ffd, 0x3efd0005,
- 0xbf0aaaab, 0x3f0aaaab, 0x3f000000, 0x3f000000,
- 0xbf0c4b8a, 0x3f090b8b, 0x3efd0005, 0x3f017ffd,
- 0xbf0dee29, 0x3f076e2d, 0x3efa002b, 0x3f02ffeb,
- 0xbf0f9284, 0x3f05d292, 0x3ef70090, 0x3f047fb8,
- 0xbf11389b, 0x3f0438bd, 0x3ef40155, 0x3f05ff55,
- 0xbf12e06d, 0x3f02a0af, 0x3ef1029b, 0x3f077eb3,
- 0xbf1489f8, 0x3f010a6a, 0x3eee0480, 0x3f08fdc0,
- 0xbf16353b, 0x3efeebe2, 0x3eeb0725, 0x3f0a7c6d,
- 0xbf17e236, 0x3efbc68b, 0x3ee80aab, 0x3f0bfaab,
- 0xbf1990e8, 0x3ef8a4d6, 0x3ee50f30, 0x3f0d7868,
- 0xbf1b4150, 0x3ef586c7, 0x3ee214d5, 0x3f0ef595,
- 0xbf1cf36e, 0x3ef26c63, 0x3edf1bbb, 0x3f107223,
- 0xbf1ea740, 0x3eef55b1, 0x3edc2400, 0x3f11ee00,
- 0xbf205cc7, 0x3eec42b6, 0x3ed92dc5, 0x3f13691d,
- 0xbf221402, 0x3ee93378, 0x3ed6392b, 0x3f14e36b,
- 0xbf23ccf1, 0x3ee627ff, 0x3ed34650, 0x3f165cd8,
- 0xbf258794, 0x3ee32051, 0x3ed05555, 0x3f17d555,
- 0xbf2743ea, 0x3ee01c75, 0x3ecd665b, 0x3f194cd3,
- 0xbf2901f4, 0x3edd1c72, 0x3eca7980, 0x3f1ac340,
- 0xbf2ac1b1, 0x3eda2051, 0x3ec78ee5, 0x3f1c388d,
- 0xbf2c8321, 0x3ed72818, 0x3ec4a6ab, 0x3f1dacab,
- 0xbf2e4645, 0x3ed433d1, 0x3ec1c0f0, 0x3f1f1f88,
- 0xbf300b1c, 0x3ed14384, 0x3ebeddd5, 0x3f209115,
- 0xbf31d1a7, 0x3ece573a, 0x3ebbfd7b, 0x3f220143,
- 0xbf3399e6, 0x3ecb6efb, 0x3eb92000, 0x3f237000,
- 0xbf3563d9, 0x3ec88ad2, 0x3eb64585, 0x3f24dd3d,
- 0xbf372f80, 0x3ec5aac9, 0x3eb36e2b, 0x3f2648eb,
- 0xbf38fcdb, 0x3ec2cee8, 0x3eb09a10, 0x3f27b2f8,
- 0xbf3acbea, 0x3ebff73b, 0x3eadc955, 0x3f291b55,
- 0xbf3c9cad, 0x3ebd23cd, 0x3eaafc1b, 0x3f2a81f3,
- 0xbf3e6f24, 0x3eba54a9, 0x3ea83280, 0x3f2be6c0,
- 0xbf40434f, 0x3eb789da, 0x3ea56ca5, 0x3f2d49ad,
- 0xbf42192e, 0x3eb4c36b, 0x3ea2aaab, 0x3f2eaaab,
- 0xbf43f0c0, 0x3eb2016a, 0x3e9fecb0, 0x3f3009a8,
- 0xbf45ca05, 0x3eaf43e3, 0x3e9d32d5, 0x3f316695,
- 0xbf47a4fc, 0x3eac8ae3, 0x3e9a7d3b, 0x3f32c163,
- 0xbf4981a3, 0x3ea9d676, 0x3e97cc00, 0x3f341a00,
- 0xbf4b5ffb, 0x3ea726ab, 0x3e951f45, 0x3f35705d,
- 0xbf4d4001, 0x3ea47b90, 0x3e92772b, 0x3f36c46b,
- 0xbf4f21b3, 0x3ea1d533, 0x3e8fd3d0, 0x3f381618,
- 0xbf510510, 0x3e9f33a3, 0x3e8d3555, 0x3f396555,
- 0xbf52ea14, 0x3e9c96f0, 0x3e8a9bdb, 0x3f3ab213,
- 0xbf54d0bd, 0x3e99ff29, 0x3e880780, 0x3f3bfc40,
- 0xbf56b908, 0x3e976c5f, 0x3e857865, 0x3f3d43cd,
- 0xbf58a2ef, 0x3e94dea1, 0x3e82eeab, 0x3f3e88ab,
- 0xbf5a8e6f, 0x3e925602, 0x3e806a70, 0x3f3fcac8,
- 0xbf5c7b81, 0x3e8fd293, 0x3e7bd7ab, 0x3f410a15,
- 0xbf5e6a21, 0x3e8d5466, 0x3e76e5f5, 0x3f424683,
- 0xbf605a45, 0x3e8adb8e, 0x3e720000, 0x3f438000,
- 0xbf624be7, 0x3e88681d, 0x3e6d260b, 0x3f44b67d,
- 0xbf643efd, 0x3e85fa27, 0x3e685855, 0x3f45e9eb,
- 0xbf66337c, 0x3e8391c0, 0x3e639720, 0x3f471a38,
- 0xbf682959, 0x3e812efe, 0x3e5ee2ab, 0x3f484755,
- 0xbf6a2087, 0x3e7da3e9, 0x3e5a3b35, 0x3f497133,
- 0xbf6c18f7, 0x3e78f574, 0x3e55a100, 0x3f4a97c0,
- 0xbf6e1299, 0x3e7452cb, 0x3e51144b, 0x3f4bbaed,
- 0xbf700d59, 0x3e6fbc1a, 0x3e4c9555, 0x3f4cdaab,
- 0xbf720924, 0x3e6b3191, 0x3e482460, 0x3f4df6e8,
- 0xbf7405e3, 0x3e66b361, 0x3e43c1ab, 0x3f4f0f95,
- 0xbf76037c, 0x3e6241bc, 0x3e3f6d75, 0x3f5024a3,
- 0xbf7801d3, 0x3e5ddcd4, 0x3e3b2800, 0x3f513600,
- 0xbf7a00ca, 0x3e5984de, 0x3e36f18b, 0x3f52439d,
- 0xbf7c003d, 0x3e553a10, 0x3e32ca55, 0x3f534d6b,
- 0xbf7e0008, 0x3e50fca2, 0x3e2eb2a0, 0x3f545358,
+static const uint16_t bicubic_tex_512[] = {
+ 0xb266, 0x3c00, 0x3aaa, 0x3155,
+ 0xb287, 0x3bf0, 0x3aa2, 0x3175,
+ 0xb2a9, 0x3be0, 0x3a9a, 0x3196,
+ 0xb2cc, 0x3bd0, 0x3a92, 0x31b7,
+ 0xb2ee, 0x3bc0, 0x3a89, 0x31d9,
+ 0xb312, 0x3bb0, 0x3a81, 0x31fb,
+ 0xb335, 0x3ba0, 0x3a78, 0x321e,
+ 0xb359, 0x3b90, 0x3a6f, 0x3241,
+ 0xb37d, 0x3b80, 0x3a66, 0x3264,
+ 0xb3a2, 0x3b70, 0x3a5d, 0x3288,
+ 0xb3c7, 0x3b60, 0x3a54, 0x32ad,
+ 0xb3ed, 0x3b51, 0x3a4b, 0x32d1,
+ 0xb409, 0x3b41, 0x3a42, 0x32f7,
+ 0xb41c, 0x3b31, 0x3a38, 0x331c,
+ 0xb42f, 0x3b21, 0x3a2f, 0x3342,
+ 0xb443, 0x3b12, 0x3a25, 0x3369,
+ 0xb456, 0x3b02, 0x3a1c, 0x3390,
+ 0xb46a, 0x3af3, 0x3a12, 0x33b7,
+ 0xb47e, 0x3ae3, 0x3a08, 0x33de,
+ 0xb492, 0x3ad4, 0x39fe, 0x3403,
+ 0xb4a6, 0x3ac5, 0x39f4, 0x3417,
+ 0xb4bb, 0x3ab5, 0x39ea, 0x342b,
+ 0xb4cf, 0x3aa6, 0x39df, 0x3440,
+ 0xb4e4, 0x3a97, 0x39d5, 0x3454,
+ 0xb4f9, 0x3a88, 0x39cb, 0x3469,
+ 0xb50e, 0x3a79, 0x39c0, 0x347e,
+ 0xb523, 0x3a6a, 0x39b6, 0x3493,
+ 0xb539, 0x3a5a, 0x39ab, 0x34a8,
+ 0xb54e, 0x3a4c, 0x39a0, 0x34be,
+ 0xb564, 0x3a3d, 0x3996, 0x34d3,
+ 0xb57a, 0x3a2e, 0x398b, 0x34e9,
+ 0xb590, 0x3a1f, 0x3980, 0x34ff,
+ 0xb5a6, 0x3a10, 0x3975, 0x3515,
+ 0xb5bc, 0x3a02, 0x396a, 0x352b,
+ 0xb5d2, 0x39f3, 0x395f, 0x3541,
+ 0xb5e9, 0x39e4, 0x3954, 0x3557,
+ 0xb5ff, 0x39d6, 0x3948, 0x356e,
+ 0xb616, 0x39c7, 0x393d, 0x3584,
+ 0xb62d, 0x39b9, 0x3932, 0x359b,
+ 0xb644, 0x39ab, 0x3926, 0x35b2,
+ 0xb65b, 0x399c, 0x391b, 0x35c9,
+ 0xb672, 0x398e, 0x3910, 0x35df,
+ 0xb68a, 0x3980, 0x3904, 0x35f6,
+ 0xb6a1, 0x3972, 0x38f8, 0x360e,
+ 0xb6b9, 0x3964, 0x38ed, 0x3625,
+ 0xb6d1, 0x3956, 0x38e1, 0x363c,
+ 0xb6e8, 0x3948, 0x38d6, 0x3653,
+ 0xb700, 0x393a, 0x38ca, 0x366b,
+ 0xb719, 0x392c, 0x38be, 0x3682,
+ 0xb731, 0x391e, 0x38b2, 0x369a,
+ 0xb749, 0x3910, 0x38a7, 0x36b1,
+ 0xb762, 0x3902, 0x389b, 0x36c9,
+ 0xb77a, 0x38f5, 0x388f, 0x36e1,
+ 0xb793, 0x38e7, 0x3883, 0x36f8,
+ 0xb7ac, 0x38da, 0x3877, 0x3710,
+ 0xb7c5, 0x38cc, 0x386b, 0x3728,
+ 0xb7de, 0x38bf, 0x385f, 0x3740,
+ 0xb7f7, 0x38b1, 0x3853, 0x3758,
+ 0xb808, 0x38a4, 0x3847, 0x3770,
+ 0xb815, 0x3897, 0x383b, 0x3788,
+ 0xb821, 0x3889, 0x382f, 0x37a0,
+ 0xb82e, 0x387c, 0x3823, 0x37b8,
+ 0xb83b, 0x386f, 0x3817, 0x37d0,
+ 0xb848, 0x3862, 0x380b, 0x37e8,
+ 0xb855, 0x3855, 0x3800, 0x3800,
+ 0xb862, 0x3848, 0x37e8, 0x380b,
+ 0xb86f, 0x383b, 0x37d0, 0x3817,
+ 0xb87c, 0x382e, 0x37b8, 0x3823,
+ 0xb889, 0x3821, 0x37a0, 0x382f,
+ 0xb897, 0x3815, 0x3788, 0x383b,
+ 0xb8a4, 0x3808, 0x3770, 0x3847,
+ 0xb8b1, 0x37f7, 0x3758, 0x3853,
+ 0xb8bf, 0x37de, 0x3740, 0x385f,
+ 0xb8cc, 0x37c5, 0x3728, 0x386b,
+ 0xb8da, 0x37ac, 0x3710, 0x3877,
+ 0xb8e7, 0x3793, 0x36f8, 0x3883,
+ 0xb8f5, 0x377a, 0x36e1, 0x388f,
+ 0xb902, 0x3762, 0x36c9, 0x389b,
+ 0xb910, 0x3749, 0x36b1, 0x38a7,
+ 0xb91e, 0x3731, 0x369a, 0x38b2,
+ 0xb92c, 0x3719, 0x3682, 0x38be,
+ 0xb93a, 0x3700, 0x366b, 0x38ca,
+ 0xb948, 0x36e8, 0x3653, 0x38d6,
+ 0xb956, 0x36d1, 0x363c, 0x38e1,
+ 0xb964, 0x36b9, 0x3625, 0x38ed,
+ 0xb972, 0x36a1, 0x360e, 0x38f8,
+ 0xb980, 0x368a, 0x35f6, 0x3904,
+ 0xb98e, 0x3672, 0x35df, 0x3910,
+ 0xb99c, 0x365b, 0x35c9, 0x391b,
+ 0xb9ab, 0x3644, 0x35b2, 0x3926,
+ 0xb9b9, 0x362d, 0x359b, 0x3932,
+ 0xb9c7, 0x3616, 0x3584, 0x393d,
+ 0xb9d6, 0x35ff, 0x356e, 0x3948,
+ 0xb9e4, 0x35e9, 0x3557, 0x3954,
+ 0xb9f3, 0x35d2, 0x3541, 0x395f,
+ 0xba02, 0x35bc, 0x352b, 0x396a,
+ 0xba10, 0x35a6, 0x3515, 0x3975,
+ 0xba1f, 0x3590, 0x34ff, 0x3980,
+ 0xba2e, 0x357a, 0x34e9, 0x398b,
+ 0xba3d, 0x3564, 0x34d3, 0x3996,
+ 0xba4c, 0x354e, 0x34be, 0x39a0,
+ 0xba5a, 0x3539, 0x34a8, 0x39ab,
+ 0xba6a, 0x3523, 0x3493, 0x39b6,
+ 0xba79, 0x350e, 0x347e, 0x39c0,
+ 0xba88, 0x34f9, 0x3469, 0x39cb,
+ 0xba97, 0x34e4, 0x3454, 0x39d5,
+ 0xbaa6, 0x34cf, 0x3440, 0x39df,
+ 0xbab5, 0x34bb, 0x342b, 0x39ea,
+ 0xbac5, 0x34a6, 0x3417, 0x39f4,
+ 0xbad4, 0x3492, 0x3403, 0x39fe,
+ 0xbae3, 0x347e, 0x33de, 0x3a08,
+ 0xbaf3, 0x346a, 0x33b7, 0x3a12,
+ 0xbb02, 0x3456, 0x3390, 0x3a1c,
+ 0xbb12, 0x3443, 0x3369, 0x3a25,
+ 0xbb21, 0x342f, 0x3342, 0x3a2f,
+ 0xbb31, 0x341c, 0x331c, 0x3a38,
+ 0xbb41, 0x3409, 0x32f7, 0x3a42,
+ 0xbb51, 0x33ed, 0x32d1, 0x3a4b,
+ 0xbb60, 0x33c7, 0x32ad, 0x3a54,
+ 0xbb70, 0x33a2, 0x3288, 0x3a5d,
+ 0xbb80, 0x337d, 0x3264, 0x3a66,
+ 0xbb90, 0x3359, 0x3241, 0x3a6f,
+ 0xbba0, 0x3335, 0x321e, 0x3a78,
+ 0xbbb0, 0x3312, 0x31fb, 0x3a81,
+ 0xbbc0, 0x32ee, 0x31d9, 0x3a89,
+ 0xbbd0, 0x32cc, 0x31b7, 0x3a92,
+ 0xbbe0, 0x32a9, 0x3196, 0x3a9a,
+ 0xbbf0, 0x3287, 0x3175, 0x3aa2,
0 };
-static const uint32_t bicubic_tex_2048[] = {
- 0xbe4ccccd, 0x3f800000, 0x3f555555, 0x3e2aaaab,
- 0xbe4dd779, 0x3f7f8000, 0x3f551535, 0x3e2bab2a,
- 0xbe4ee301, 0x3f7f0001, 0x3f54d4d6, 0x3e2caca9,
- 0xbe4fef64, 0x3f7e8003, 0x3f549436, 0x3e2daf26,
- 0xbe50fca2, 0x3f7e0008, 0x3f545358, 0x3e2eb2a0,
- 0xbe520aba, 0x3f7d800f, 0x3f54123b, 0x3e2fb716,
- 0xbe5319aa, 0x3f7d001a, 0x3f53d0de, 0x3e30bc87,
- 0xbe542972, 0x3f7c8029, 0x3f538f44, 0x3e31c2f2,
- 0xbe553a10, 0x3f7c003d, 0x3f534d6b, 0x3e32ca55,
- 0xbe564b85, 0x3f7b8056, 0x3f530b54, 0x3e33d2b1,
- 0xbe575dcf, 0x3f7b0076, 0x3f52c8ff, 0x3e34dc04,
- 0xbe5870ed, 0x3f7a809c, 0x3f52866d, 0x3e35e64d,
- 0xbe5984de, 0x3f7a00ca, 0x3f52439d, 0x3e36f18b,
- 0xbe5a99a2, 0x3f7980ff, 0x3f520091, 0x3e37fdbc,
- 0xbe5baf37, 0x3f79013c, 0x3f51bd48, 0x3e390ae1,
- 0xbe5cc59d, 0x3f788183, 0x3f5179c2, 0x3e3a18f8,
- 0xbe5ddcd4, 0x3f7801d3, 0x3f513600, 0x3e3b2800,
- 0xbe5ef4d9, 0x3f77822d, 0x3f50f202, 0x3e3c37f8,
- 0xbe600dad, 0x3f770291, 0x3f50adc8, 0x3e3d48df,
- 0xbe61274e, 0x3f768301, 0x3f506953, 0x3e3e5ab4,
- 0xbe6241bc, 0x3f76037c, 0x3f5024a3, 0x3e3f6d75,
- 0xbe635cf5, 0x3f758402, 0x3f4fdfb7, 0x3e408123,
- 0xbe6478fa, 0x3f750495, 0x3f4f9a91, 0x3e4195bc,
- 0xbe6595c9, 0x3f748535, 0x3f4f5530, 0x3e42ab3f,
- 0xbe66b361, 0x3f7405e3, 0x3f4f0f95, 0x3e43c1ab,
- 0xbe67d1c2, 0x3f73869d, 0x3f4ec9c0, 0x3e44d8fe,
- 0xbe68f0eb, 0x3f730766, 0x3f4e83b2, 0x3e45f139,
- 0xbe6a10db, 0x3f72883e, 0x3f4e3d69, 0x3e470a5a,
- 0xbe6b3191, 0x3f720924, 0x3f4df6e8, 0x3e482460,
- 0xbe6c530d, 0x3f718a19, 0x3f4db02e, 0x3e493f4a,
- 0xbe6d754e, 0x3f710b1e, 0x3f4d693a, 0x3e4a5b17,
- 0xbe6e9852, 0x3f708c34, 0x3f4d220f, 0x3e4b77c6,
- 0xbe6fbc1a, 0x3f700d59, 0x3f4cdaab, 0x3e4c9555,
- 0xbe70e0a4, 0x3f6f8e8f, 0x3f4c930f, 0x3e4db3c5,
- 0xbe7205f0, 0x3f6f0fd6, 0x3f4c4b3b, 0x3e4ed314,
- 0xbe732bfd, 0x3f6e912e, 0x3f4c0330, 0x3e4ff341,
- 0xbe7452cb, 0x3f6e1299, 0x3f4bbaed, 0x3e51144b,
- 0xbe757a58, 0x3f6d9415, 0x3f4b7274, 0x3e523630,
- 0xbe76a2a3, 0x3f6d15a3, 0x3f4b29c4, 0x3e5358f1,
- 0xbe77cbad, 0x3f6c9744, 0x3f4ae0dd, 0x3e547c8c,
- 0xbe78f574, 0x3f6c18f7, 0x3f4a97c0, 0x3e55a100,
- 0xbe7a1ff8, 0x3f6b9abe, 0x3f4a4e6d, 0x3e56c64c,
- 0xbe7b4b38, 0x3f6b1c98, 0x3f4a04e4, 0x3e57ec6f,
- 0xbe7c7733, 0x3f6a9e86, 0x3f49bb26, 0x3e591368,
- 0xbe7da3e9, 0x3f6a2087, 0x3f497133, 0x3e5a3b35,
- 0xbe7ed158, 0x3f69a29d, 0x3f49270a, 0x3e5b63d7,
- 0xbe7fff81, 0x3f6924c7, 0x3f48dcad, 0x3e5c8d4c,
- 0xbe809731, 0x3f68a706, 0x3f48921b, 0x3e5db793,
- 0xbe812efe, 0x3f682959, 0x3f484755, 0x3e5ee2ab,
- 0xbe81c726, 0x3f67abc2, 0x3f47fc5b, 0x3e600e92,
- 0xbe825fa9, 0x3f672e40, 0x3f47b12e, 0x3e613b49,
- 0xbe82f887, 0x3f66b0d3, 0x3f4765cc, 0x3e6268ce,
- 0xbe8391c0, 0x3f66337c, 0x3f471a38, 0x3e639720,
- 0xbe842b53, 0x3f65b63b, 0x3f46ce71, 0x3e64c63e,
- 0xbe84c540, 0x3f653910, 0x3f468276, 0x3e65f627,
- 0xbe855f87, 0x3f64bbfb, 0x3f46364a, 0x3e6726da,
- 0xbe85fa27, 0x3f643efd, 0x3f45e9eb, 0x3e685855,
- 0xbe869520, 0x3f63c215, 0x3f459d5a, 0x3e698a99,
- 0xbe873071, 0x3f634544, 0x3f455097, 0x3e6abda4,
- 0xbe87cc1b, 0x3f62c88a, 0x3f4503a3, 0x3e6bf175,
- 0xbe88681d, 0x3f624be7, 0x3f44b67d, 0x3e6d260b,
- 0xbe890476, 0x3f61cf5b, 0x3f446927, 0x3e6e5b64,
- 0xbe89a127, 0x3f6152e7, 0x3f441ba0, 0x3e6f9181,
- 0xbe8a3e2f, 0x3f60d68a, 0x3f43cde8, 0x3e70c860,
- 0xbe8adb8e, 0x3f605a45, 0x3f438000, 0x3e720000,
- 0xbe8b7943, 0x3f5fde18, 0x3f4331e8, 0x3e733860,
- 0xbe8c174e, 0x3f5f6203, 0x3f42e3a0, 0x3e74717f,
- 0xbe8cb5af, 0x3f5ee606, 0x3f429529, 0x3e75ab5c,
- 0xbe8d5466, 0x3f5e6a21, 0x3f424683, 0x3e76e5f5,
- 0xbe8df372, 0x3f5dee54, 0x3f41f7ad, 0x3e78214b,
- 0xbe8e92d3, 0x3f5d72a0, 0x3f41a8a9, 0x3e795d5c,
- 0xbe8f3289, 0x3f5cf704, 0x3f415976, 0x3e7a9a27,
- 0xbe8fd293, 0x3f5c7b81, 0x3f410a15, 0x3e7bd7ab,
- 0xbe9072f2, 0x3f5c0017, 0x3f40ba86, 0x3e7d15e6,
- 0xbe9113a4, 0x3f5b84c6, 0x3f406aca, 0x3e7e54d9,
- 0xbe91b4aa, 0x3f5b098e, 0x3f401adf, 0x3e7f9482,
- 0xbe925602, 0x3f5a8e6f, 0x3f3fcac8, 0x3e806a70,
- 0xbe92f7ae, 0x3f5a1369, 0x3f3f7a84, 0x3e810af9,
- 0xbe9399ad, 0x3f59987c, 0x3f3f2a12, 0x3e81abdb,
- 0xbe943bfe, 0x3f591da9, 0x3f3ed975, 0x3e824d17,
- 0xbe94dea1, 0x3f58a2ef, 0x3f3e88ab, 0x3e82eeab,
- 0xbe958197, 0x3f58284f, 0x3f3e37b5, 0x3e839097,
- 0xbe9624dd, 0x3f57adc8, 0x3f3de693, 0x3e8432da,
- 0xbe96c875, 0x3f57335b, 0x3f3d9546, 0x3e84d574,
- 0xbe976c5f, 0x3f56b908, 0x3f3d43cd, 0x3e857865,
- 0xbe981099, 0x3f563ece, 0x3f3cf22a, 0x3e861bac,
- 0xbe98b523, 0x3f55c4af, 0x3f3ca05c, 0x3e86bf49,
- 0xbe9959fe, 0x3f554aa9, 0x3f3c4e63, 0x3e87633a,
- 0xbe99ff29, 0x3f54d0bd, 0x3f3bfc40, 0x3e880780,
- 0xbe9aa4a4, 0x3f5456ec, 0x3f3ba9f3, 0x3e88ac1a,
- 0xbe9b4a6e, 0x3f53dd34, 0x3f3b577c, 0x3e895107,
- 0xbe9bf087, 0x3f536397, 0x3f3b04dc, 0x3e89f648,
- 0xbe9c96f0, 0x3f52ea14, 0x3f3ab213, 0x3e8a9bdb,
- 0xbe9d3da7, 0x3f5270ab, 0x3f3a5f20, 0x3e8b41c0,
- 0xbe9de4ad, 0x3f51f75d, 0x3f3a0c05, 0x3e8be7f6,
- 0xbe9e8c01, 0x3f517e29, 0x3f39b8c1, 0x3e8c8e7d,
- 0xbe9f33a3, 0x3f510510, 0x3f396555, 0x3e8d3555,
- 0xbe9fdb93, 0x3f508c11, 0x3f3911c1, 0x3e8ddc7d,
- 0xbea083d0, 0x3f50132c, 0x3f38be06, 0x3e8e83f5,
- 0xbea12c5b, 0x3f4f9a62, 0x3f386a22, 0x3e8f2bbb,
- 0xbea1d533, 0x3f4f21b3, 0x3f381618, 0x3e8fd3d0,
- 0xbea27e57, 0x3f4ea91e, 0x3f37c1e7, 0x3e907c33,
- 0xbea327c9, 0x3f4e30a4, 0x3f376d8e, 0x3e9124e3,
- 0xbea3d186, 0x3f4db845, 0x3f371910, 0x3e91cde1,
- 0xbea47b90, 0x3f4d4001, 0x3f36c46b, 0x3e92772b,
- 0xbea525e5, 0x3f4cc7d7, 0x3f366fa0, 0x3e9320c1,
- 0xbea5d086, 0x3f4c4fc8, 0x3f361aaf, 0x3e93caa2,
- 0xbea67b73, 0x3f4bd7d4, 0x3f35c599, 0x3e9474ce,
- 0xbea726ab, 0x3f4b5ffb, 0x3f35705d, 0x3e951f45,
- 0xbea7d22e, 0x3f4ae83d, 0x3f351afd, 0x3e95ca06,
- 0xbea87dfb, 0x3f4a7099, 0x3f34c578, 0x3e967511,
- 0xbea92a13, 0x3f49f911, 0x3f346fce, 0x3e972064,
- 0xbea9d676, 0x3f4981a3, 0x3f341a00, 0x3e97cc00,
- 0xbeaa8322, 0x3f490a51, 0x3f33c40e, 0x3e9877e4,
- 0xbeab3019, 0x3f489319, 0x3f336df8, 0x3e99240f,
- 0xbeabdd59, 0x3f481bfd, 0x3f3317bf, 0x3e99d082,
- 0xbeac8ae3, 0x3f47a4fc, 0x3f32c163, 0x3e9a7d3b,
- 0xbead38b5, 0x3f472e15, 0x3f326ae3, 0x3e9b2a3a,
- 0xbeade6d1, 0x3f46b74a, 0x3f321441, 0x3e9bd77e,
- 0xbeae9536, 0x3f46409a, 0x3f31bd7c, 0x3e9c8507,
- 0xbeaf43e3, 0x3f45ca05, 0x3f316695, 0x3e9d32d5,
- 0xbeaff2d9, 0x3f45538b, 0x3f310f8c, 0x3e9de0e7,
- 0xbeb0a217, 0x3f44dd2c, 0x3f30b862, 0x3e9e8f3d,
- 0xbeb1519d, 0x3f4466e9, 0x3f306115, 0x3e9f3dd5,
- 0xbeb2016a, 0x3f43f0c0, 0x3f3009a8, 0x3e9fecb0,
- 0xbeb2b180, 0x3f437ab3, 0x3f2fb21a, 0x3ea09bcd,
- 0xbeb361dd, 0x3f4304c1, 0x3f2f5a6a, 0x3ea14b2b,
- 0xbeb41280, 0x3f428eea, 0x3f2f029b, 0x3ea1facb,
- 0xbeb4c36b, 0x3f42192e, 0x3f2eaaab, 0x3ea2aaab,
- 0xbeb5749d, 0x3f41a38e, 0x3f2e529b, 0x3ea35acb,
- 0xbeb62616, 0x3f412e08, 0x3f2dfa6b, 0x3ea40b2a,
- 0xbeb6d7d5, 0x3f40b89e, 0x3f2da21c, 0x3ea4bbc8,
- 0xbeb789da, 0x3f40434f, 0x3f2d49ad, 0x3ea56ca5,
- 0xbeb83c25, 0x3f3fce1c, 0x3f2cf120, 0x3ea61dc0,
- 0xbeb8eeb6, 0x3f3f5903, 0x3f2c9874, 0x3ea6cf19,
- 0xbeb9a18d, 0x3f3ee406, 0x3f2c3fa9, 0x3ea780ae,
- 0xbeba54a9, 0x3f3e6f24, 0x3f2be6c0, 0x3ea83280,
- 0xbebb080b, 0x3f3dfa5d, 0x3f2b8db9, 0x3ea8e48e,
- 0xbebbbbb1, 0x3f3d85b2, 0x3f2b3494, 0x3ea996d7,
- 0xbebc6f9d, 0x3f3d1122, 0x3f2adb52, 0x3eaa495c,
- 0xbebd23cd, 0x3f3c9cad, 0x3f2a81f3, 0x3eaafc1b,
- 0xbebdd842, 0x3f3c2853, 0x3f2a2876, 0x3eabaf14,
- 0xbebe8cfc, 0x3f3bb415, 0x3f29cedd, 0x3eac6246,
- 0xbebf41fa, 0x3f3b3ff2, 0x3f297527, 0x3ead15b1,
- 0xbebff73b, 0x3f3acbea, 0x3f291b55, 0x3eadc955,
- 0xbec0acc1, 0x3f3a57fd, 0x3f28c167, 0x3eae7d31,
- 0xbec1628b, 0x3f39e42c, 0x3f28675e, 0x3eaf3145,
- 0xbec21898, 0x3f397076, 0x3f280d38, 0x3eafe58f,
- 0xbec2cee8, 0x3f38fcdb, 0x3f27b2f8, 0x3eb09a10,
- 0xbec3857c, 0x3f38895b, 0x3f27589d, 0x3eb14ec7,
- 0xbec43c53, 0x3f3815f7, 0x3f26fe26, 0x3eb203b3,
- 0xbec4f36c, 0x3f37a2ae, 0x3f26a396, 0x3eb2b8d5,
- 0xbec5aac9, 0x3f372f80, 0x3f2648eb, 0x3eb36e2b,
- 0xbec66268, 0x3f36bc6d, 0x3f25ee26, 0x3eb423b5,
- 0xbec71a49, 0x3f364976, 0x3f259347, 0x3eb4d972,
- 0xbec7d26d, 0x3f35d69a, 0x3f25384f, 0x3eb58f62,
- 0xbec88ad2, 0x3f3563d9, 0x3f24dd3d, 0x3eb64585,
- 0xbec9437a, 0x3f34f134, 0x3f248213, 0x3eb6fbda,
- 0xbec9fc64, 0x3f347ea9, 0x3f2426d0, 0x3eb7b261,
- 0xbecab58f, 0x3f340c3a, 0x3f23cb74, 0x3eb86918,
- 0xbecb6efb, 0x3f3399e6, 0x3f237000, 0x3eb92000,
- 0xbecc28a9, 0x3f3327ae, 0x3f231474, 0x3eb9d718,
- 0xbecce299, 0x3f32b590, 0x3f22b8d0, 0x3eba8e5f,
- 0xbecd9cc9, 0x3f32438e, 0x3f225d15, 0x3ebb45d6,
- 0xbece573a, 0x3f31d1a7, 0x3f220143, 0x3ebbfd7b,
- 0xbecf11ec, 0x3f315fdc, 0x3f21a559, 0x3ebcb54e,
- 0xbecfccde, 0x3f30ee2b, 0x3f214959, 0x3ebd6d4e,
- 0xbed08811, 0x3f307c96, 0x3f20ed42, 0x3ebe257b,
- 0xbed14384, 0x3f300b1c, 0x3f209115, 0x3ebeddd5,
- 0xbed1ff38, 0x3f2f99be, 0x3f2034d2, 0x3ebf965b,
- 0xbed2bb2b, 0x3f2f287a, 0x3f1fd87a, 0x3ec04f0d,
- 0xbed3775e, 0x3f2eb752, 0x3f1f7c0b, 0x3ec107e9,
- 0xbed433d1, 0x3f2e4645, 0x3f1f1f88, 0x3ec1c0f0,
- 0xbed4f084, 0x3f2dd553, 0x3f1ec2f0, 0x3ec27a21,
- 0xbed5ad76, 0x3f2d647d, 0x3f1e6642, 0x3ec3337b,
- 0xbed66aa8, 0x3f2cf3c1, 0x3f1e0981, 0x3ec3ecff,
- 0xbed72818, 0x3f2c8321, 0x3f1dacab, 0x3ec4a6ab,
- 0xbed7e5c8, 0x3f2c129c, 0x3f1d4fc1, 0x3ec5607f,
- 0xbed8a3b7, 0x3f2ba232, 0x3f1cf2c3, 0x3ec61a7a,
- 0xbed961e4, 0x3f2b31e4, 0x3f1c95b2, 0x3ec6d49c,
- 0xbeda2051, 0x3f2ac1b1, 0x3f1c388d, 0x3ec78ee5,
- 0xbedadefc, 0x3f2a5199, 0x3f1bdb56, 0x3ec84954,
- 0xbedb9de5, 0x3f29e19c, 0x3f1b7e0c, 0x3ec903e9,
- 0xbedc5d0c, 0x3f2971ba, 0x3f1b20af, 0x3ec9bea2,
- 0xbedd1c72, 0x3f2901f4, 0x3f1ac340, 0x3eca7980,
- 0xbedddc16, 0x3f289248, 0x3f1a65bf, 0x3ecb3482,
- 0xbede9bf8, 0x3f2822b8, 0x3f1a082c, 0x3ecbefa7,
- 0xbedf5c18, 0x3f27b344, 0x3f19aa88, 0x3eccaaf0,
- 0xbee01c75, 0x3f2743ea, 0x3f194cd3, 0x3ecd665b,
- 0xbee0dd10, 0x3f26d4ac, 0x3f18ef0c, 0x3ece21e8,
- 0xbee19de8, 0x3f266589, 0x3f189135, 0x3ecedd96,
- 0xbee25efe, 0x3f25f681, 0x3f18334d, 0x3ecf9965,
- 0xbee32051, 0x3f258794, 0x3f17d555, 0x3ed05555,
- 0xbee3e1e1, 0x3f2518c2, 0x3f17774d, 0x3ed11165,
- 0xbee4a3ae, 0x3f24aa0c, 0x3f171936, 0x3ed1cd95,
- 0xbee565b8, 0x3f243b71, 0x3f16bb0e, 0x3ed289e3,
- 0xbee627ff, 0x3f23ccf1, 0x3f165cd8, 0x3ed34650,
- 0xbee6ea83, 0x3f235e8d, 0x3f15fe93, 0x3ed402db,
- 0xbee7ad43, 0x3f22f043, 0x3f15a03e, 0x3ed4bf83,
- 0xbee8703f, 0x3f228215, 0x3f1541dc, 0x3ed57c49,
- 0xbee93378, 0x3f221402, 0x3f14e36b, 0x3ed6392b,
- 0xbee9f6ed, 0x3f21a60b, 0x3f1484ec, 0x3ed6f629,
- 0xbeeaba9f, 0x3f21382e, 0x3f14265f, 0x3ed7b342,
- 0xbeeb7e8c, 0x3f20ca6d, 0x3f13c7c5, 0x3ed87076,
- 0xbeec42b6, 0x3f205cc7, 0x3f13691d, 0x3ed92dc5,
- 0xbeed071b, 0x3f1fef3c, 0x3f130a69, 0x3ed9eb2e,
- 0xbeedcbbc, 0x3f1f81cd, 0x3f12aba8, 0x3edaa8b1,
- 0xbeee9098, 0x3f1f1479, 0x3f124cda, 0x3edb664c,
- 0xbeef55b1, 0x3f1ea740, 0x3f11ee00, 0x3edc2400,
- 0xbef01b04, 0x3f1e3a23, 0x3f118f1a, 0x3edce1cc,
- 0xbef0e093, 0x3f1dcd20, 0x3f113028, 0x3edd9faf,
- 0xbef1a65d, 0x3f1d6039, 0x3f10d12b, 0x3ede5daa,
- 0xbef26c63, 0x3f1cf36e, 0x3f107223, 0x3edf1bbb,
- 0xbef332a3, 0x3f1c86bd, 0x3f10130f, 0x3edfd9e2,
- 0xbef3f91f, 0x3f1c1a28, 0x3f0fb3f1, 0x3ee0981e,
- 0xbef4bfd5, 0x3f1badaf, 0x3f0f54c8, 0x3ee1566f,
- 0xbef586c7, 0x3f1b4150, 0x3f0ef595, 0x3ee214d5,
- 0xbef64df2, 0x3f1ad50d, 0x3f0e9658, 0x3ee2d34f,
- 0xbef71559, 0x3f1a68e6, 0x3f0e3712, 0x3ee391dd,
- 0xbef7dcfa, 0x3f19fcd9, 0x3f0dd7c1, 0x3ee4507d,
- 0xbef8a4d6, 0x3f1990e8, 0x3f0d7868, 0x3ee50f30,
- 0xbef96cec, 0x3f192513, 0x3f0d1906, 0x3ee5cdf5,
- 0xbefa353c, 0x3f18b958, 0x3f0cb99a, 0x3ee68ccb,
- 0xbefafdc7, 0x3f184dba, 0x3f0c5a27, 0x3ee74bb3,
- 0xbefbc68b, 0x3f17e236, 0x3f0bfaab, 0x3ee80aab,
- 0xbefc8f8a, 0x3f1776ce, 0x3f0b9b27, 0x3ee8c9b3,
- 0xbefd58c3, 0x3f170b82, 0x3f0b3b9b, 0x3ee988ca,
- 0xbefe2235, 0x3f16a051, 0x3f0adc08, 0x3eea47f0,
- 0xbefeebe2, 0x3f16353b, 0x3f0a7c6d, 0x3eeb0725,
- 0xbeffb5c8, 0x3f15ca41, 0x3f0a1ccc, 0x3eebc668,
- 0xbf003ff4, 0x3f155f62, 0x3f09bd24, 0x3eec85b9,
- 0xbf00a520, 0x3f14f49f, 0x3f095d75, 0x3eed4516,
- 0xbf010a6a, 0x3f1489f8, 0x3f08fdc0, 0x3eee0480,
- 0xbf016fd0, 0x3f141f6c, 0x3f089e05, 0x3eeec3f6,
- 0xbf01d553, 0x3f13b4fb, 0x3f083e44, 0x3eef8377,
- 0xbf023af2, 0x3f134aa6, 0x3f07de7e, 0x3ef04304,
- 0xbf02a0af, 0x3f12e06d, 0x3f077eb3, 0x3ef1029b,
- 0xbf030687, 0x3f12764f, 0x3f071ee2, 0x3ef1c23c,
- 0xbf036c7d, 0x3f120c4d, 0x3f06bf0d, 0x3ef281e6,
- 0xbf03d28e, 0x3f11a266, 0x3f065f33, 0x3ef34199,
- 0xbf0438bd, 0x3f11389b, 0x3f05ff55, 0x3ef40155,
- 0xbf049f08, 0x3f10ceec, 0x3f059f73, 0x3ef4c119,
- 0xbf05056f, 0x3f106558, 0x3f053f8e, 0x3ef580e5,
- 0xbf056bf2, 0x3f0ffbe0, 0x3f04dfa4, 0x3ef640b7,
- 0xbf05d292, 0x3f0f9284, 0x3f047fb8, 0x3ef70090,
- 0xbf06394e, 0x3f0f2943, 0x3f041fc9, 0x3ef7c06f,
- 0xbf06a027, 0x3f0ec01f, 0x3f03bfd6, 0x3ef88053,
- 0xbf07071c, 0x3f0e5716, 0x3f035fe2, 0x3ef9403d,
- 0xbf076e2d, 0x3f0dee29, 0x3f02ffeb, 0x3efa002b,
- 0xbf07d55a, 0x3f0d8557, 0x3f029ff2, 0x3efac01d,
- 0xbf083ca4, 0x3f0d1ca2, 0x3f023ff7, 0x3efb8012,
- 0xbf08a409, 0x3f0cb408, 0x3f01dffb, 0x3efc400a,
- 0xbf090b8b, 0x3f0c4b8a, 0x3f017ffd, 0x3efd0005,
- 0xbf097329, 0x3f0be329, 0x3f011fff, 0x3efdc002,
- 0xbf09dae3, 0x3f0b7ae3, 0x3f00c000, 0x3efe8001,
- 0xbf0a42b9, 0x3f0b12b9, 0x3f006000, 0x3eff4000,
- 0xbf0aaaab, 0x3f0aaaab, 0x3f000000, 0x3f000000,
- 0xbf0b12b9, 0x3f0a42b9, 0x3eff4000, 0x3f006000,
- 0xbf0b7ae3, 0x3f09dae3, 0x3efe8001, 0x3f00c000,
- 0xbf0be329, 0x3f097329, 0x3efdc002, 0x3f011fff,
- 0xbf0c4b8a, 0x3f090b8b, 0x3efd0005, 0x3f017ffd,
- 0xbf0cb408, 0x3f08a409, 0x3efc400a, 0x3f01dffb,
- 0xbf0d1ca2, 0x3f083ca4, 0x3efb8012, 0x3f023ff7,
- 0xbf0d8557, 0x3f07d55a, 0x3efac01d, 0x3f029ff2,
- 0xbf0dee29, 0x3f076e2d, 0x3efa002b, 0x3f02ffeb,
- 0xbf0e5716, 0x3f07071c, 0x3ef9403d, 0x3f035fe2,
- 0xbf0ec01f, 0x3f06a027, 0x3ef88053, 0x3f03bfd6,
- 0xbf0f2943, 0x3f06394e, 0x3ef7c06f, 0x3f041fc9,
- 0xbf0f9284, 0x3f05d292, 0x3ef70090, 0x3f047fb8,
- 0xbf0ffbe0, 0x3f056bf2, 0x3ef640b7, 0x3f04dfa4,
- 0xbf106558, 0x3f05056f, 0x3ef580e5, 0x3f053f8e,
- 0xbf10ceec, 0x3f049f08, 0x3ef4c119, 0x3f059f73,
- 0xbf11389b, 0x3f0438bd, 0x3ef40155, 0x3f05ff55,
- 0xbf11a266, 0x3f03d28e, 0x3ef34199, 0x3f065f33,
- 0xbf120c4d, 0x3f036c7d, 0x3ef281e6, 0x3f06bf0d,
- 0xbf12764f, 0x3f030687, 0x3ef1c23c, 0x3f071ee2,
- 0xbf12e06d, 0x3f02a0af, 0x3ef1029b, 0x3f077eb3,
- 0xbf134aa6, 0x3f023af2, 0x3ef04304, 0x3f07de7e,
- 0xbf13b4fb, 0x3f01d553, 0x3eef8377, 0x3f083e44,
- 0xbf141f6c, 0x3f016fd0, 0x3eeec3f6, 0x3f089e05,
- 0xbf1489f8, 0x3f010a6a, 0x3eee0480, 0x3f08fdc0,
- 0xbf14f49f, 0x3f00a520, 0x3eed4516, 0x3f095d75,
- 0xbf155f62, 0x3f003ff4, 0x3eec85b9, 0x3f09bd24,
- 0xbf15ca41, 0x3effb5c8, 0x3eebc668, 0x3f0a1ccc,
- 0xbf16353b, 0x3efeebe2, 0x3eeb0725, 0x3f0a7c6d,
- 0xbf16a051, 0x3efe2235, 0x3eea47f0, 0x3f0adc08,
- 0xbf170b82, 0x3efd58c3, 0x3ee988ca, 0x3f0b3b9b,
- 0xbf1776ce, 0x3efc8f8a, 0x3ee8c9b3, 0x3f0b9b27,
- 0xbf17e236, 0x3efbc68b, 0x3ee80aab, 0x3f0bfaab,
- 0xbf184dba, 0x3efafdc7, 0x3ee74bb3, 0x3f0c5a27,
- 0xbf18b958, 0x3efa353c, 0x3ee68ccb, 0x3f0cb99a,
- 0xbf192513, 0x3ef96cec, 0x3ee5cdf5, 0x3f0d1906,
- 0xbf1990e8, 0x3ef8a4d6, 0x3ee50f30, 0x3f0d7868,
- 0xbf19fcd9, 0x3ef7dcfa, 0x3ee4507d, 0x3f0dd7c1,
- 0xbf1a68e6, 0x3ef71559, 0x3ee391dd, 0x3f0e3712,
- 0xbf1ad50d, 0x3ef64df2, 0x3ee2d34f, 0x3f0e9658,
- 0xbf1b4150, 0x3ef586c7, 0x3ee214d5, 0x3f0ef595,
- 0xbf1badaf, 0x3ef4bfd5, 0x3ee1566f, 0x3f0f54c8,
- 0xbf1c1a28, 0x3ef3f91f, 0x3ee0981e, 0x3f0fb3f1,
- 0xbf1c86bd, 0x3ef332a3, 0x3edfd9e2, 0x3f10130f,
- 0xbf1cf36e, 0x3ef26c63, 0x3edf1bbb, 0x3f107223,
- 0xbf1d6039, 0x3ef1a65d, 0x3ede5daa, 0x3f10d12b,
- 0xbf1dcd20, 0x3ef0e093, 0x3edd9faf, 0x3f113028,
- 0xbf1e3a23, 0x3ef01b04, 0x3edce1cc, 0x3f118f1a,
- 0xbf1ea740, 0x3eef55b1, 0x3edc2400, 0x3f11ee00,
- 0xbf1f1479, 0x3eee9098, 0x3edb664c, 0x3f124cda,
- 0xbf1f81cd, 0x3eedcbbc, 0x3edaa8b1, 0x3f12aba8,
- 0xbf1fef3c, 0x3eed071b, 0x3ed9eb2e, 0x3f130a69,
- 0xbf205cc7, 0x3eec42b6, 0x3ed92dc5, 0x3f13691d,
- 0xbf20ca6d, 0x3eeb7e8c, 0x3ed87076, 0x3f13c7c5,
- 0xbf21382e, 0x3eeaba9f, 0x3ed7b342, 0x3f14265f,
- 0xbf21a60b, 0x3ee9f6ed, 0x3ed6f629, 0x3f1484ec,
- 0xbf221402, 0x3ee93378, 0x3ed6392b, 0x3f14e36b,
- 0xbf228215, 0x3ee8703f, 0x3ed57c49, 0x3f1541dc,
- 0xbf22f043, 0x3ee7ad43, 0x3ed4bf83, 0x3f15a03e,
- 0xbf235e8d, 0x3ee6ea83, 0x3ed402db, 0x3f15fe93,
- 0xbf23ccf1, 0x3ee627ff, 0x3ed34650, 0x3f165cd8,
- 0xbf243b71, 0x3ee565b8, 0x3ed289e3, 0x3f16bb0e,
- 0xbf24aa0c, 0x3ee4a3ae, 0x3ed1cd95, 0x3f171936,
- 0xbf2518c2, 0x3ee3e1e1, 0x3ed11165, 0x3f17774d,
- 0xbf258794, 0x3ee32051, 0x3ed05555, 0x3f17d555,
- 0xbf25f681, 0x3ee25efe, 0x3ecf9965, 0x3f18334d,
- 0xbf266589, 0x3ee19de8, 0x3ecedd96, 0x3f189135,
- 0xbf26d4ac, 0x3ee0dd10, 0x3ece21e8, 0x3f18ef0c,
- 0xbf2743ea, 0x3ee01c75, 0x3ecd665b, 0x3f194cd3,
- 0xbf27b344, 0x3edf5c18, 0x3eccaaf0, 0x3f19aa88,
- 0xbf2822b8, 0x3ede9bf8, 0x3ecbefa7, 0x3f1a082c,
- 0xbf289248, 0x3edddc16, 0x3ecb3482, 0x3f1a65bf,
- 0xbf2901f4, 0x3edd1c72, 0x3eca7980, 0x3f1ac340,
- 0xbf2971ba, 0x3edc5d0c, 0x3ec9bea2, 0x3f1b20af,
- 0xbf29e19c, 0x3edb9de5, 0x3ec903e9, 0x3f1b7e0c,
- 0xbf2a5199, 0x3edadefc, 0x3ec84954, 0x3f1bdb56,
- 0xbf2ac1b1, 0x3eda2051, 0x3ec78ee5, 0x3f1c388d,
- 0xbf2b31e4, 0x3ed961e4, 0x3ec6d49c, 0x3f1c95b2,
- 0xbf2ba232, 0x3ed8a3b7, 0x3ec61a7a, 0x3f1cf2c3,
- 0xbf2c129c, 0x3ed7e5c8, 0x3ec5607f, 0x3f1d4fc1,
- 0xbf2c8321, 0x3ed72818, 0x3ec4a6ab, 0x3f1dacab,
- 0xbf2cf3c1, 0x3ed66aa8, 0x3ec3ecff, 0x3f1e0981,
- 0xbf2d647d, 0x3ed5ad76, 0x3ec3337b, 0x3f1e6642,
- 0xbf2dd553, 0x3ed4f084, 0x3ec27a21, 0x3f1ec2f0,
- 0xbf2e4645, 0x3ed433d1, 0x3ec1c0f0, 0x3f1f1f88,
- 0xbf2eb752, 0x3ed3775e, 0x3ec107e9, 0x3f1f7c0b,
- 0xbf2f287a, 0x3ed2bb2b, 0x3ec04f0d, 0x3f1fd87a,
- 0xbf2f99be, 0x3ed1ff38, 0x3ebf965b, 0x3f2034d2,
- 0xbf300b1c, 0x3ed14384, 0x3ebeddd5, 0x3f209115,
- 0xbf307c96, 0x3ed08811, 0x3ebe257b, 0x3f20ed42,
- 0xbf30ee2b, 0x3ecfccde, 0x3ebd6d4e, 0x3f214959,
- 0xbf315fdc, 0x3ecf11ec, 0x3ebcb54e, 0x3f21a559,
- 0xbf31d1a7, 0x3ece573a, 0x3ebbfd7b, 0x3f220143,
- 0xbf32438e, 0x3ecd9cc9, 0x3ebb45d6, 0x3f225d15,
- 0xbf32b590, 0x3ecce299, 0x3eba8e5f, 0x3f22b8d0,
- 0xbf3327ae, 0x3ecc28a9, 0x3eb9d718, 0x3f231474,
- 0xbf3399e6, 0x3ecb6efb, 0x3eb92000, 0x3f237000,
- 0xbf340c3a, 0x3ecab58f, 0x3eb86918, 0x3f23cb74,
- 0xbf347ea9, 0x3ec9fc64, 0x3eb7b261, 0x3f2426d0,
- 0xbf34f134, 0x3ec9437a, 0x3eb6fbda, 0x3f248213,
- 0xbf3563d9, 0x3ec88ad2, 0x3eb64585, 0x3f24dd3d,
- 0xbf35d69a, 0x3ec7d26d, 0x3eb58f62, 0x3f25384f,
- 0xbf364976, 0x3ec71a49, 0x3eb4d972, 0x3f259347,
- 0xbf36bc6d, 0x3ec66268, 0x3eb423b5, 0x3f25ee26,
- 0xbf372f80, 0x3ec5aac9, 0x3eb36e2b, 0x3f2648eb,
- 0xbf37a2ae, 0x3ec4f36c, 0x3eb2b8d5, 0x3f26a396,
- 0xbf3815f7, 0x3ec43c53, 0x3eb203b3, 0x3f26fe26,
- 0xbf38895b, 0x3ec3857c, 0x3eb14ec7, 0x3f27589d,
- 0xbf38fcdb, 0x3ec2cee8, 0x3eb09a10, 0x3f27b2f8,
- 0xbf397076, 0x3ec21898, 0x3eafe58f, 0x3f280d38,
- 0xbf39e42c, 0x3ec1628b, 0x3eaf3145, 0x3f28675e,
- 0xbf3a57fd, 0x3ec0acc1, 0x3eae7d31, 0x3f28c167,
- 0xbf3acbea, 0x3ebff73b, 0x3eadc955, 0x3f291b55,
- 0xbf3b3ff2, 0x3ebf41fa, 0x3ead15b1, 0x3f297527,
- 0xbf3bb415, 0x3ebe8cfc, 0x3eac6246, 0x3f29cedd,
- 0xbf3c2853, 0x3ebdd842, 0x3eabaf14, 0x3f2a2876,
- 0xbf3c9cad, 0x3ebd23cd, 0x3eaafc1b, 0x3f2a81f3,
- 0xbf3d1122, 0x3ebc6f9d, 0x3eaa495c, 0x3f2adb52,
- 0xbf3d85b2, 0x3ebbbbb1, 0x3ea996d7, 0x3f2b3494,
- 0xbf3dfa5d, 0x3ebb080b, 0x3ea8e48e, 0x3f2b8db9,
- 0xbf3e6f24, 0x3eba54a9, 0x3ea83280, 0x3f2be6c0,
- 0xbf3ee406, 0x3eb9a18d, 0x3ea780ae, 0x3f2c3fa9,
- 0xbf3f5903, 0x3eb8eeb6, 0x3ea6cf19, 0x3f2c9874,
- 0xbf3fce1c, 0x3eb83c25, 0x3ea61dc0, 0x3f2cf120,
- 0xbf40434f, 0x3eb789da, 0x3ea56ca5, 0x3f2d49ad,
- 0xbf40b89e, 0x3eb6d7d5, 0x3ea4bbc8, 0x3f2da21c,
- 0xbf412e08, 0x3eb62616, 0x3ea40b2a, 0x3f2dfa6b,
- 0xbf41a38e, 0x3eb5749d, 0x3ea35acb, 0x3f2e529b,
- 0xbf42192e, 0x3eb4c36b, 0x3ea2aaab, 0x3f2eaaab,
- 0xbf428eea, 0x3eb41280, 0x3ea1facb, 0x3f2f029b,
- 0xbf4304c1, 0x3eb361dd, 0x3ea14b2b, 0x3f2f5a6a,
- 0xbf437ab3, 0x3eb2b180, 0x3ea09bcd, 0x3f2fb21a,
- 0xbf43f0c0, 0x3eb2016a, 0x3e9fecb0, 0x3f3009a8,
- 0xbf4466e9, 0x3eb1519d, 0x3e9f3dd5, 0x3f306115,
- 0xbf44dd2c, 0x3eb0a217, 0x3e9e8f3d, 0x3f30b862,
- 0xbf45538b, 0x3eaff2d9, 0x3e9de0e7, 0x3f310f8c,
- 0xbf45ca05, 0x3eaf43e3, 0x3e9d32d5, 0x3f316695,
- 0xbf46409a, 0x3eae9536, 0x3e9c8507, 0x3f31bd7c,
- 0xbf46b74a, 0x3eade6d1, 0x3e9bd77e, 0x3f321441,
- 0xbf472e15, 0x3ead38b5, 0x3e9b2a3a, 0x3f326ae3,
- 0xbf47a4fc, 0x3eac8ae3, 0x3e9a7d3b, 0x3f32c163,
- 0xbf481bfd, 0x3eabdd59, 0x3e99d082, 0x3f3317bf,
- 0xbf489319, 0x3eab3019, 0x3e99240f, 0x3f336df8,
- 0xbf490a51, 0x3eaa8322, 0x3e9877e4, 0x3f33c40e,
- 0xbf4981a3, 0x3ea9d676, 0x3e97cc00, 0x3f341a00,
- 0xbf49f911, 0x3ea92a13, 0x3e972064, 0x3f346fce,
- 0xbf4a7099, 0x3ea87dfb, 0x3e967511, 0x3f34c578,
- 0xbf4ae83d, 0x3ea7d22e, 0x3e95ca06, 0x3f351afd,
- 0xbf4b5ffb, 0x3ea726ab, 0x3e951f45, 0x3f35705d,
- 0xbf4bd7d4, 0x3ea67b73, 0x3e9474ce, 0x3f35c599,
- 0xbf4c4fc8, 0x3ea5d086, 0x3e93caa2, 0x3f361aaf,
- 0xbf4cc7d7, 0x3ea525e5, 0x3e9320c1, 0x3f366fa0,
- 0xbf4d4001, 0x3ea47b90, 0x3e92772b, 0x3f36c46b,
- 0xbf4db845, 0x3ea3d186, 0x3e91cde1, 0x3f371910,
- 0xbf4e30a4, 0x3ea327c9, 0x3e9124e3, 0x3f376d8e,
- 0xbf4ea91e, 0x3ea27e57, 0x3e907c33, 0x3f37c1e7,
- 0xbf4f21b3, 0x3ea1d533, 0x3e8fd3d0, 0x3f381618,
- 0xbf4f9a62, 0x3ea12c5b, 0x3e8f2bbb, 0x3f386a22,
- 0xbf50132c, 0x3ea083d0, 0x3e8e83f5, 0x3f38be06,
- 0xbf508c11, 0x3e9fdb93, 0x3e8ddc7d, 0x3f3911c1,
- 0xbf510510, 0x3e9f33a3, 0x3e8d3555, 0x3f396555,
- 0xbf517e29, 0x3e9e8c01, 0x3e8c8e7d, 0x3f39b8c1,
- 0xbf51f75d, 0x3e9de4ad, 0x3e8be7f6, 0x3f3a0c05,
- 0xbf5270ab, 0x3e9d3da7, 0x3e8b41c0, 0x3f3a5f20,
- 0xbf52ea14, 0x3e9c96f0, 0x3e8a9bdb, 0x3f3ab213,
- 0xbf536397, 0x3e9bf087, 0x3e89f648, 0x3f3b04dc,
- 0xbf53dd34, 0x3e9b4a6e, 0x3e895107, 0x3f3b577c,
- 0xbf5456ec, 0x3e9aa4a4, 0x3e88ac1a, 0x3f3ba9f3,
- 0xbf54d0bd, 0x3e99ff29, 0x3e880780, 0x3f3bfc40,
- 0xbf554aa9, 0x3e9959fe, 0x3e87633a, 0x3f3c4e63,
- 0xbf55c4af, 0x3e98b523, 0x3e86bf49, 0x3f3ca05c,
- 0xbf563ece, 0x3e981099, 0x3e861bac, 0x3f3cf22a,
- 0xbf56b908, 0x3e976c5f, 0x3e857865, 0x3f3d43cd,
- 0xbf57335b, 0x3e96c875, 0x3e84d574, 0x3f3d9546,
- 0xbf57adc8, 0x3e9624dd, 0x3e8432da, 0x3f3de693,
- 0xbf58284f, 0x3e958197, 0x3e839097, 0x3f3e37b5,
- 0xbf58a2ef, 0x3e94dea1, 0x3e82eeab, 0x3f3e88ab,
- 0xbf591da9, 0x3e943bfe, 0x3e824d17, 0x3f3ed975,
- 0xbf59987c, 0x3e9399ad, 0x3e81abdb, 0x3f3f2a12,
- 0xbf5a1369, 0x3e92f7ae, 0x3e810af9, 0x3f3f7a84,
- 0xbf5a8e6f, 0x3e925602, 0x3e806a70, 0x3f3fcac8,
- 0xbf5b098e, 0x3e91b4aa, 0x3e7f9482, 0x3f401adf,
- 0xbf5b84c6, 0x3e9113a4, 0x3e7e54d9, 0x3f406aca,
- 0xbf5c0017, 0x3e9072f2, 0x3e7d15e6, 0x3f40ba86,
- 0xbf5c7b81, 0x3e8fd293, 0x3e7bd7ab, 0x3f410a15,
- 0xbf5cf704, 0x3e8f3289, 0x3e7a9a27, 0x3f415976,
- 0xbf5d72a0, 0x3e8e92d3, 0x3e795d5c, 0x3f41a8a9,
- 0xbf5dee54, 0x3e8df372, 0x3e78214b, 0x3f41f7ad,
- 0xbf5e6a21, 0x3e8d5466, 0x3e76e5f5, 0x3f424683,
- 0xbf5ee606, 0x3e8cb5af, 0x3e75ab5c, 0x3f429529,
- 0xbf5f6203, 0x3e8c174e, 0x3e74717f, 0x3f42e3a0,
- 0xbf5fde18, 0x3e8b7943, 0x3e733860, 0x3f4331e8,
- 0xbf605a45, 0x3e8adb8e, 0x3e720000, 0x3f438000,
- 0xbf60d68a, 0x3e8a3e2f, 0x3e70c860, 0x3f43cde8,
- 0xbf6152e7, 0x3e89a127, 0x3e6f9181, 0x3f441ba0,
- 0xbf61cf5b, 0x3e890476, 0x3e6e5b64, 0x3f446927,
- 0xbf624be7, 0x3e88681d, 0x3e6d260b, 0x3f44b67d,
- 0xbf62c88a, 0x3e87cc1b, 0x3e6bf175, 0x3f4503a3,
- 0xbf634544, 0x3e873071, 0x3e6abda4, 0x3f455097,
- 0xbf63c215, 0x3e869520, 0x3e698a99, 0x3f459d5a,
- 0xbf643efd, 0x3e85fa27, 0x3e685855, 0x3f45e9eb,
- 0xbf64bbfb, 0x3e855f87, 0x3e6726da, 0x3f46364a,
- 0xbf653910, 0x3e84c540, 0x3e65f627, 0x3f468276,
- 0xbf65b63b, 0x3e842b53, 0x3e64c63e, 0x3f46ce71,
- 0xbf66337c, 0x3e8391c0, 0x3e639720, 0x3f471a38,
- 0xbf66b0d3, 0x3e82f887, 0x3e6268ce, 0x3f4765cc,
- 0xbf672e40, 0x3e825fa9, 0x3e613b49, 0x3f47b12e,
- 0xbf67abc2, 0x3e81c726, 0x3e600e92, 0x3f47fc5b,
- 0xbf682959, 0x3e812efe, 0x3e5ee2ab, 0x3f484755,
- 0xbf68a706, 0x3e809731, 0x3e5db793, 0x3f48921b,
- 0xbf6924c7, 0x3e7fff81, 0x3e5c8d4c, 0x3f48dcad,
- 0xbf69a29d, 0x3e7ed158, 0x3e5b63d7, 0x3f49270a,
- 0xbf6a2087, 0x3e7da3e9, 0x3e5a3b35, 0x3f497133,
- 0xbf6a9e86, 0x3e7c7733, 0x3e591368, 0x3f49bb26,
- 0xbf6b1c98, 0x3e7b4b38, 0x3e57ec6f, 0x3f4a04e4,
- 0xbf6b9abe, 0x3e7a1ff8, 0x3e56c64c, 0x3f4a4e6d,
- 0xbf6c18f7, 0x3e78f574, 0x3e55a100, 0x3f4a97c0,
- 0xbf6c9744, 0x3e77cbad, 0x3e547c8c, 0x3f4ae0dd,
- 0xbf6d15a3, 0x3e76a2a3, 0x3e5358f1, 0x3f4b29c4,
- 0xbf6d9415, 0x3e757a58, 0x3e523630, 0x3f4b7274,
- 0xbf6e1299, 0x3e7452cb, 0x3e51144b, 0x3f4bbaed,
- 0xbf6e912e, 0x3e732bfd, 0x3e4ff341, 0x3f4c0330,
- 0xbf6f0fd6, 0x3e7205f0, 0x3e4ed314, 0x3f4c4b3b,
- 0xbf6f8e8f, 0x3e70e0a4, 0x3e4db3c5, 0x3f4c930f,
- 0xbf700d59, 0x3e6fbc1a, 0x3e4c9555, 0x3f4cdaab,
- 0xbf708c34, 0x3e6e9852, 0x3e4b77c6, 0x3f4d220f,
- 0xbf710b1e, 0x3e6d754e, 0x3e4a5b17, 0x3f4d693a,
- 0xbf718a19, 0x3e6c530d, 0x3e493f4a, 0x3f4db02e,
- 0xbf720924, 0x3e6b3191, 0x3e482460, 0x3f4df6e8,
- 0xbf72883e, 0x3e6a10db, 0x3e470a5a, 0x3f4e3d69,
- 0xbf730766, 0x3e68f0eb, 0x3e45f139, 0x3f4e83b2,
- 0xbf73869d, 0x3e67d1c2, 0x3e44d8fe, 0x3f4ec9c0,
- 0xbf7405e3, 0x3e66b361, 0x3e43c1ab, 0x3f4f0f95,
- 0xbf748535, 0x3e6595c9, 0x3e42ab3f, 0x3f4f5530,
- 0xbf750495, 0x3e6478fa, 0x3e4195bc, 0x3f4f9a91,
- 0xbf758402, 0x3e635cf5, 0x3e408123, 0x3f4fdfb7,
- 0xbf76037c, 0x3e6241bc, 0x3e3f6d75, 0x3f5024a3,
- 0xbf768301, 0x3e61274e, 0x3e3e5ab4, 0x3f506953,
- 0xbf770291, 0x3e600dad, 0x3e3d48df, 0x3f50adc8,
- 0xbf77822d, 0x3e5ef4d9, 0x3e3c37f8, 0x3f50f202,
- 0xbf7801d3, 0x3e5ddcd4, 0x3e3b2800, 0x3f513600,
- 0xbf788183, 0x3e5cc59d, 0x3e3a18f8, 0x3f5179c2,
- 0xbf79013c, 0x3e5baf37, 0x3e390ae1, 0x3f51bd48,
- 0xbf7980ff, 0x3e5a99a2, 0x3e37fdbc, 0x3f520091,
- 0xbf7a00ca, 0x3e5984de, 0x3e36f18b, 0x3f52439d,
- 0xbf7a809c, 0x3e5870ed, 0x3e35e64d, 0x3f52866d,
- 0xbf7b0076, 0x3e575dcf, 0x3e34dc04, 0x3f52c8ff,
- 0xbf7b8056, 0x3e564b85, 0x3e33d2b1, 0x3f530b54,
- 0xbf7c003d, 0x3e553a10, 0x3e32ca55, 0x3f534d6b,
- 0xbf7c8029, 0x3e542972, 0x3e31c2f2, 0x3f538f44,
- 0xbf7d001a, 0x3e5319aa, 0x3e30bc87, 0x3f53d0de,
- 0xbf7d800f, 0x3e520aba, 0x3e2fb716, 0x3f54123b,
- 0xbf7e0008, 0x3e50fca2, 0x3e2eb2a0, 0x3f545358,
- 0xbf7e8003, 0x3e4fef64, 0x3e2daf26, 0x3f549436,
- 0xbf7f0001, 0x3e4ee301, 0x3e2caca9, 0x3f54d4d6,
- 0xbf7f8000, 0x3e4dd779, 0x3e2bab2a, 0x3f551535,
+static const uint16_t bicubic_tex_2048[] = {
+ 0xb266, 0x3c00, 0x3aaa, 0x3155,
+ 0xb26e, 0x3bfc, 0x3aa8, 0x315d,
+ 0xb277, 0x3bf8, 0x3aa6, 0x3165,
+ 0xb27f, 0x3bf4, 0x3aa4, 0x316d,
+ 0xb287, 0x3bf0, 0x3aa2, 0x3175,
+ 0xb290, 0x3bec, 0x3aa0, 0x317d,
+ 0xb298, 0x3be8, 0x3a9e, 0x3185,
+ 0xb2a1, 0x3be4, 0x3a9c, 0x318e,
+ 0xb2a9, 0x3be0, 0x3a9a, 0x3196,
+ 0xb2b2, 0x3bdc, 0x3a98, 0x319e,
+ 0xb2ba, 0x3bd8, 0x3a96, 0x31a6,
+ 0xb2c3, 0x3bd4, 0x3a94, 0x31af,
+ 0xb2cc, 0x3bd0, 0x3a92, 0x31b7,
+ 0xb2d4, 0x3bcc, 0x3a90, 0x31bf,
+ 0xb2dd, 0x3bc8, 0x3a8d, 0x31c8,
+ 0xb2e6, 0x3bc4, 0x3a8b, 0x31d0,
+ 0xb2ee, 0x3bc0, 0x3a89, 0x31d9,
+ 0xb2f7, 0x3bbc, 0x3a87, 0x31e1,
+ 0xb300, 0x3bb8, 0x3a85, 0x31ea,
+ 0xb309, 0x3bb4, 0x3a83, 0x31f2,
+ 0xb312, 0x3bb0, 0x3a81, 0x31fb,
+ 0xb31a, 0x3bac, 0x3a7e, 0x3204,
+ 0xb323, 0x3ba8, 0x3a7c, 0x320c,
+ 0xb32c, 0x3ba4, 0x3a7a, 0x3215,
+ 0xb335, 0x3ba0, 0x3a78, 0x321e,
+ 0xb33e, 0x3b9c, 0x3a76, 0x3226,
+ 0xb347, 0x3b98, 0x3a74, 0x322f,
+ 0xb350, 0x3b94, 0x3a71, 0x3238,
+ 0xb359, 0x3b90, 0x3a6f, 0x3241,
+ 0xb362, 0x3b8c, 0x3a6d, 0x3249,
+ 0xb36b, 0x3b88, 0x3a6b, 0x3252,
+ 0xb374, 0x3b84, 0x3a69, 0x325b,
+ 0xb37d, 0x3b80, 0x3a66, 0x3264,
+ 0xb387, 0x3b7c, 0x3a64, 0x326d,
+ 0xb390, 0x3b78, 0x3a62, 0x3276,
+ 0xb399, 0x3b74, 0x3a60, 0x327f,
+ 0xb3a2, 0x3b70, 0x3a5d, 0x3288,
+ 0xb3ab, 0x3b6c, 0x3a5b, 0x3291,
+ 0xb3b5, 0x3b68, 0x3a59, 0x329a,
+ 0xb3be, 0x3b64, 0x3a57, 0x32a3,
+ 0xb3c7, 0x3b60, 0x3a54, 0x32ad,
+ 0xb3d0, 0x3b5c, 0x3a52, 0x32b6,
+ 0xb3da, 0x3b58, 0x3a50, 0x32bf,
+ 0xb3e3, 0x3b54, 0x3a4d, 0x32c8,
+ 0xb3ed, 0x3b51, 0x3a4b, 0x32d1,
+ 0xb3f6, 0x3b4d, 0x3a49, 0x32db,
+ 0xb3ff, 0x3b49, 0x3a46, 0x32e4,
+ 0xb404, 0x3b45, 0x3a44, 0x32ed,
+ 0xb409, 0x3b41, 0x3a42, 0x32f7,
+ 0xb40e, 0x3b3d, 0x3a3f, 0x3300,
+ 0xb412, 0x3b39, 0x3a3d, 0x3309,
+ 0xb417, 0x3b35, 0x3a3b, 0x3313,
+ 0xb41c, 0x3b31, 0x3a38, 0x331c,
+ 0xb421, 0x3b2d, 0x3a36, 0x3326,
+ 0xb426, 0x3b29, 0x3a34, 0x332f,
+ 0xb42a, 0x3b25, 0x3a31, 0x3339,
+ 0xb42f, 0x3b21, 0x3a2f, 0x3342,
+ 0xb434, 0x3b1e, 0x3a2c, 0x334c,
+ 0xb439, 0x3b1a, 0x3a2a, 0x3355,
+ 0xb43e, 0x3b16, 0x3a28, 0x335f,
+ 0xb443, 0x3b12, 0x3a25, 0x3369,
+ 0xb448, 0x3b0e, 0x3a23, 0x3372,
+ 0xb44d, 0x3b0a, 0x3a20, 0x337c,
+ 0xb451, 0x3b06, 0x3a1e, 0x3386,
+ 0xb456, 0x3b02, 0x3a1c, 0x3390,
+ 0xb45b, 0x3afe, 0x3a19, 0x3399,
+ 0xb460, 0x3afb, 0x3a17, 0x33a3,
+ 0xb465, 0x3af7, 0x3a14, 0x33ad,
+ 0xb46a, 0x3af3, 0x3a12, 0x33b7,
+ 0xb46f, 0x3aef, 0x3a0f, 0x33c1,
+ 0xb474, 0x3aeb, 0x3a0d, 0x33ca,
+ 0xb479, 0x3ae7, 0x3a0a, 0x33d4,
+ 0xb47e, 0x3ae3, 0x3a08, 0x33de,
+ 0xb483, 0x3ae0, 0x3a05, 0x33e8,
+ 0xb488, 0x3adc, 0x3a03, 0x33f2,
+ 0xb48d, 0x3ad8, 0x3a00, 0x33fc,
+ 0xb492, 0x3ad4, 0x39fe, 0x3403,
+ 0xb497, 0x3ad0, 0x39fb, 0x3408,
+ 0xb49c, 0x3acc, 0x39f9, 0x340d,
+ 0xb4a1, 0x3ac8, 0x39f6, 0x3412,
+ 0xb4a6, 0x3ac5, 0x39f4, 0x3417,
+ 0xb4ac, 0x3ac1, 0x39f1, 0x341c,
+ 0xb4b1, 0x3abd, 0x39ef, 0x3421,
+ 0xb4b6, 0x3ab9, 0x39ec, 0x3426,
+ 0xb4bb, 0x3ab5, 0x39ea, 0x342b,
+ 0xb4c0, 0x3ab1, 0x39e7, 0x3430,
+ 0xb4c5, 0x3aae, 0x39e5, 0x3435,
+ 0xb4ca, 0x3aaa, 0x39e2, 0x343b,
+ 0xb4cf, 0x3aa6, 0x39df, 0x3440,
+ 0xb4d5, 0x3aa2, 0x39dd, 0x3445,
+ 0xb4da, 0x3a9e, 0x39da, 0x344a,
+ 0xb4df, 0x3a9b, 0x39d8, 0x344f,
+ 0xb4e4, 0x3a97, 0x39d5, 0x3454,
+ 0xb4e9, 0x3a93, 0x39d2, 0x345a,
+ 0xb4ef, 0x3a8f, 0x39d0, 0x345f,
+ 0xb4f4, 0x3a8b, 0x39cd, 0x3464,
+ 0xb4f9, 0x3a88, 0x39cb, 0x3469,
+ 0xb4fe, 0x3a84, 0x39c8, 0x346e,
+ 0xb504, 0x3a80, 0x39c5, 0x3474,
+ 0xb509, 0x3a7c, 0x39c3, 0x3479,
+ 0xb50e, 0x3a79, 0x39c0, 0x347e,
+ 0xb513, 0x3a75, 0x39be, 0x3483,
+ 0xb519, 0x3a71, 0x39bb, 0x3489,
+ 0xb51e, 0x3a6d, 0x39b8, 0x348e,
+ 0xb523, 0x3a6a, 0x39b6, 0x3493,
+ 0xb529, 0x3a66, 0x39b3, 0x3499,
+ 0xb52e, 0x3a62, 0x39b0, 0x349e,
+ 0xb533, 0x3a5e, 0x39ae, 0x34a3,
+ 0xb539, 0x3a5a, 0x39ab, 0x34a8,
+ 0xb53e, 0x3a57, 0x39a8, 0x34ae,
+ 0xb543, 0x3a53, 0x39a6, 0x34b3,
+ 0xb549, 0x3a4f, 0x39a3, 0x34b9,
+ 0xb54e, 0x3a4c, 0x39a0, 0x34be,
+ 0xb554, 0x3a48, 0x399e, 0x34c3,
+ 0xb559, 0x3a44, 0x399b, 0x34c9,
+ 0xb55e, 0x3a40, 0x3998, 0x34ce,
+ 0xb564, 0x3a3d, 0x3996, 0x34d3,
+ 0xb569, 0x3a39, 0x3993, 0x34d9,
+ 0xb56f, 0x3a35, 0x3990, 0x34de,
+ 0xb574, 0x3a32, 0x398d, 0x34e4,
+ 0xb57a, 0x3a2e, 0x398b, 0x34e9,
+ 0xb57f, 0x3a2a, 0x3988, 0x34ef,
+ 0xb585, 0x3a26, 0x3985, 0x34f4,
+ 0xb58a, 0x3a23, 0x3983, 0x34f9,
+ 0xb590, 0x3a1f, 0x3980, 0x34ff,
+ 0xb595, 0x3a1b, 0x397d, 0x3504,
+ 0xb59b, 0x3a18, 0x397a, 0x350a,
+ 0xb5a0, 0x3a14, 0x3978, 0x350f,
+ 0xb5a6, 0x3a10, 0x3975, 0x3515,
+ 0xb5ab, 0x3a0d, 0x3972, 0x351a,
+ 0xb5b1, 0x3a09, 0x396f, 0x3520,
+ 0xb5b6, 0x3a05, 0x396d, 0x3525,
+ 0xb5bc, 0x3a02, 0x396a, 0x352b,
+ 0xb5c1, 0x39fe, 0x3967, 0x3530,
+ 0xb5c7, 0x39fa, 0x3964, 0x3536,
+ 0xb5cd, 0x39f7, 0x3961, 0x353c,
+ 0xb5d2, 0x39f3, 0x395f, 0x3541,
+ 0xb5d8, 0x39ef, 0x395c, 0x3547,
+ 0xb5dd, 0x39ec, 0x3959, 0x354c,
+ 0xb5e3, 0x39e8, 0x3956, 0x3552,
+ 0xb5e9, 0x39e4, 0x3954, 0x3557,
+ 0xb5ee, 0x39e1, 0x3951, 0x355d,
+ 0xb5f4, 0x39dd, 0x394e, 0x3563,
+ 0xb5fa, 0x39d9, 0x394b, 0x3568,
+ 0xb5ff, 0x39d6, 0x3948, 0x356e,
+ 0xb605, 0x39d2, 0x3946, 0x3573,
+ 0xb60b, 0x39cf, 0x3943, 0x3579,
+ 0xb610, 0x39cb, 0x3940, 0x357f,
+ 0xb616, 0x39c7, 0x393d, 0x3584,
+ 0xb61c, 0x39c4, 0x393a, 0x358a,
+ 0xb621, 0x39c0, 0x3937, 0x3590,
+ 0xb627, 0x39bd, 0x3935, 0x3595,
+ 0xb62d, 0x39b9, 0x3932, 0x359b,
+ 0xb633, 0x39b5, 0x392f, 0x35a1,
+ 0xb638, 0x39b2, 0x392c, 0x35a6,
+ 0xb63e, 0x39ae, 0x3929, 0x35ac,
+ 0xb644, 0x39ab, 0x3926, 0x35b2,
+ 0xb64a, 0x39a7, 0x3924, 0x35b7,
+ 0xb64f, 0x39a3, 0x3921, 0x35bd,
+ 0xb655, 0x39a0, 0x391e, 0x35c3,
+ 0xb65b, 0x399c, 0x391b, 0x35c9,
+ 0xb661, 0x3999, 0x3918, 0x35ce,
+ 0xb667, 0x3995, 0x3915, 0x35d4,
+ 0xb66c, 0x3992, 0x3912, 0x35da,
+ 0xb672, 0x398e, 0x3910, 0x35df,
+ 0xb678, 0x398a, 0x390d, 0x35e5,
+ 0xb67e, 0x3987, 0x390a, 0x35eb,
+ 0xb684, 0x3983, 0x3907, 0x35f1,
+ 0xb68a, 0x3980, 0x3904, 0x35f6,
+ 0xb68f, 0x397c, 0x3901, 0x35fc,
+ 0xb695, 0x3979, 0x38fe, 0x3602,
+ 0xb69b, 0x3975, 0x38fb, 0x3608,
+ 0xb6a1, 0x3972, 0x38f8, 0x360e,
+ 0xb6a7, 0x396e, 0x38f6, 0x3613,
+ 0xb6ad, 0x396b, 0x38f3, 0x3619,
+ 0xb6b3, 0x3967, 0x38f0, 0x361f,
+ 0xb6b9, 0x3964, 0x38ed, 0x3625,
+ 0xb6bf, 0x3960, 0x38ea, 0x362b,
+ 0xb6c5, 0x395d, 0x38e7, 0x3630,
+ 0xb6cb, 0x3959, 0x38e4, 0x3636,
+ 0xb6d1, 0x3956, 0x38e1, 0x363c,
+ 0xb6d6, 0x3952, 0x38de, 0x3642,
+ 0xb6dc, 0x394f, 0x38db, 0x3648,
+ 0xb6e2, 0x394b, 0x38d9, 0x364d,
+ 0xb6e8, 0x3948, 0x38d6, 0x3653,
+ 0xb6ee, 0x3944, 0x38d3, 0x3659,
+ 0xb6f4, 0x3941, 0x38d0, 0x365f,
+ 0xb6fa, 0x393d, 0x38cd, 0x3665,
+ 0xb700, 0x393a, 0x38ca, 0x366b,
+ 0xb706, 0x3936, 0x38c7, 0x3671,
+ 0xb70c, 0x3933, 0x38c4, 0x3676,
+ 0xb712, 0x392f, 0x38c1, 0x367c,
+ 0xb719, 0x392c, 0x38be, 0x3682,
+ 0xb71f, 0x3928, 0x38bb, 0x3688,
+ 0xb725, 0x3925, 0x38b8, 0x368e,
+ 0xb72b, 0x3921, 0x38b5, 0x3694,
+ 0xb731, 0x391e, 0x38b2, 0x369a,
+ 0xb737, 0x391a, 0x38af, 0x36a0,
+ 0xb73d, 0x3917, 0x38ad, 0x36a5,
+ 0xb743, 0x3914, 0x38aa, 0x36ab,
+ 0xb749, 0x3910, 0x38a7, 0x36b1,
+ 0xb74f, 0x390d, 0x38a4, 0x36b7,
+ 0xb755, 0x3909, 0x38a1, 0x36bd,
+ 0xb75b, 0x3906, 0x389e, 0x36c3,
+ 0xb762, 0x3902, 0x389b, 0x36c9,
+ 0xb768, 0x38ff, 0x3898, 0x36cf,
+ 0xb76e, 0x38fc, 0x3895, 0x36d5,
+ 0xb774, 0x38f8, 0x3892, 0x36db,
+ 0xb77a, 0x38f5, 0x388f, 0x36e1,
+ 0xb780, 0x38f1, 0x388c, 0x36e7,
+ 0xb787, 0x38ee, 0x3889, 0x36ec,
+ 0xb78d, 0x38eb, 0x3886, 0x36f2,
+ 0xb793, 0x38e7, 0x3883, 0x36f8,
+ 0xb799, 0x38e4, 0x3880, 0x36fe,
+ 0xb79f, 0x38e0, 0x387d, 0x3704,
+ 0xb7a5, 0x38dd, 0x387a, 0x370a,
+ 0xb7ac, 0x38da, 0x3877, 0x3710,
+ 0xb7b2, 0x38d6, 0x3874, 0x3716,
+ 0xb7b8, 0x38d3, 0x3871, 0x371c,
+ 0xb7be, 0x38cf, 0x386e, 0x3722,
+ 0xb7c5, 0x38cc, 0x386b, 0x3728,
+ 0xb7cb, 0x38c9, 0x3868, 0x372e,
+ 0xb7d1, 0x38c5, 0x3865, 0x3734,
+ 0xb7d7, 0x38c2, 0x3862, 0x373a,
+ 0xb7de, 0x38bf, 0x385f, 0x3740,
+ 0xb7e4, 0x38bb, 0x385c, 0x3746,
+ 0xb7ea, 0x38b8, 0x3859, 0x374c,
+ 0xb7f1, 0x38b5, 0x3856, 0x3752,
+ 0xb7f7, 0x38b1, 0x3853, 0x3758,
+ 0xb7fd, 0x38ae, 0x3850, 0x375e,
+ 0xb801, 0x38aa, 0x384d, 0x3764,
+ 0xb805, 0x38a7, 0x384a, 0x376a,
+ 0xb808, 0x38a4, 0x3847, 0x3770,
+ 0xb80b, 0x38a0, 0x3844, 0x3776,
+ 0xb80e, 0x389d, 0x3841, 0x377c,
+ 0xb811, 0x389a, 0x383e, 0x3782,
+ 0xb815, 0x3897, 0x383b, 0x3788,
+ 0xb818, 0x3893, 0x3838, 0x378e,
+ 0xb81b, 0x3890, 0x3835, 0x3794,
+ 0xb81e, 0x388d, 0x3832, 0x379a,
+ 0xb821, 0x3889, 0x382f, 0x37a0,
+ 0xb824, 0x3886, 0x382c, 0x37a6,
+ 0xb828, 0x3883, 0x3829, 0x37ac,
+ 0xb82b, 0x387f, 0x3826, 0x37b2,
+ 0xb82e, 0x387c, 0x3823, 0x37b8,
+ 0xb831, 0x3879, 0x3820, 0x37be,
+ 0xb835, 0x3876, 0x381d, 0x37c4,
+ 0xb838, 0x3872, 0x381a, 0x37ca,
+ 0xb83b, 0x386f, 0x3817, 0x37d0,
+ 0xb83e, 0x386c, 0x3814, 0x37d6,
+ 0xb841, 0x3868, 0x3811, 0x37dc,
+ 0xb845, 0x3865, 0x380e, 0x37e2,
+ 0xb848, 0x3862, 0x380b, 0x37e8,
+ 0xb84b, 0x385f, 0x3808, 0x37ee,
+ 0xb84e, 0x385b, 0x3806, 0x37f4,
+ 0xb852, 0x3858, 0x3803, 0x37fa,
+ 0xb855, 0x3855, 0x3800, 0x3800,
+ 0xb858, 0x3852, 0x37fa, 0x3803,
+ 0xb85b, 0x384e, 0x37f4, 0x3806,
+ 0xb85f, 0x384b, 0x37ee, 0x3808,
+ 0xb862, 0x3848, 0x37e8, 0x380b,
+ 0xb865, 0x3845, 0x37e2, 0x380e,
+ 0xb868, 0x3841, 0x37dc, 0x3811,
+ 0xb86c, 0x383e, 0x37d6, 0x3814,
+ 0xb86f, 0x383b, 0x37d0, 0x3817,
+ 0xb872, 0x3838, 0x37ca, 0x381a,
+ 0xb876, 0x3835, 0x37c4, 0x381d,
+ 0xb879, 0x3831, 0x37be, 0x3820,
+ 0xb87c, 0x382e, 0x37b8, 0x3823,
+ 0xb87f, 0x382b, 0x37b2, 0x3826,
+ 0xb883, 0x3828, 0x37ac, 0x3829,
+ 0xb886, 0x3824, 0x37a6, 0x382c,
+ 0xb889, 0x3821, 0x37a0, 0x382f,
+ 0xb88d, 0x381e, 0x379a, 0x3832,
+ 0xb890, 0x381b, 0x3794, 0x3835,
+ 0xb893, 0x3818, 0x378e, 0x3838,
+ 0xb897, 0x3815, 0x3788, 0x383b,
+ 0xb89a, 0x3811, 0x3782, 0x383e,
+ 0xb89d, 0x380e, 0x377c, 0x3841,
+ 0xb8a0, 0x380b, 0x3776, 0x3844,
+ 0xb8a4, 0x3808, 0x3770, 0x3847,
+ 0xb8a7, 0x3805, 0x376a, 0x384a,
+ 0xb8aa, 0x3801, 0x3764, 0x384d,
+ 0xb8ae, 0x37fd, 0x375e, 0x3850,
+ 0xb8b1, 0x37f7, 0x3758, 0x3853,
+ 0xb8b5, 0x37f1, 0x3752, 0x3856,
+ 0xb8b8, 0x37ea, 0x374c, 0x3859,
+ 0xb8bb, 0x37e4, 0x3746, 0x385c,
+ 0xb8bf, 0x37de, 0x3740, 0x385f,
+ 0xb8c2, 0x37d7, 0x373a, 0x3862,
+ 0xb8c5, 0x37d1, 0x3734, 0x3865,
+ 0xb8c9, 0x37cb, 0x372e, 0x3868,
+ 0xb8cc, 0x37c5, 0x3728, 0x386b,
+ 0xb8cf, 0x37be, 0x3722, 0x386e,
+ 0xb8d3, 0x37b8, 0x371c, 0x3871,
+ 0xb8d6, 0x37b2, 0x3716, 0x3874,
+ 0xb8da, 0x37ac, 0x3710, 0x3877,
+ 0xb8dd, 0x37a5, 0x370a, 0x387a,
+ 0xb8e0, 0x379f, 0x3704, 0x387d,
+ 0xb8e4, 0x3799, 0x36fe, 0x3880,
+ 0xb8e7, 0x3793, 0x36f8, 0x3883,
+ 0xb8eb, 0x378d, 0x36f2, 0x3886,
+ 0xb8ee, 0x3787, 0x36ec, 0x3889,
+ 0xb8f1, 0x3780, 0x36e7, 0x388c,
+ 0xb8f5, 0x377a, 0x36e1, 0x388f,
+ 0xb8f8, 0x3774, 0x36db, 0x3892,
+ 0xb8fc, 0x376e, 0x36d5, 0x3895,
+ 0xb8ff, 0x3768, 0x36cf, 0x3898,
+ 0xb902, 0x3762, 0x36c9, 0x389b,
+ 0xb906, 0x375b, 0x36c3, 0x389e,
+ 0xb909, 0x3755, 0x36bd, 0x38a1,
+ 0xb90d, 0x374f, 0x36b7, 0x38a4,
+ 0xb910, 0x3749, 0x36b1, 0x38a7,
+ 0xb914, 0x3743, 0x36ab, 0x38aa,
+ 0xb917, 0x373d, 0x36a5, 0x38ad,
+ 0xb91a, 0x3737, 0x36a0, 0x38af,
+ 0xb91e, 0x3731, 0x369a, 0x38b2,
+ 0xb921, 0x372b, 0x3694, 0x38b5,
+ 0xb925, 0x3725, 0x368e, 0x38b8,
+ 0xb928, 0x371f, 0x3688, 0x38bb,
+ 0xb92c, 0x3719, 0x3682, 0x38be,
+ 0xb92f, 0x3712, 0x367c, 0x38c1,
+ 0xb933, 0x370c, 0x3676, 0x38c4,
+ 0xb936, 0x3706, 0x3671, 0x38c7,
+ 0xb93a, 0x3700, 0x366b, 0x38ca,
+ 0xb93d, 0x36fa, 0x3665, 0x38cd,
+ 0xb941, 0x36f4, 0x365f, 0x38d0,
+ 0xb944, 0x36ee, 0x3659, 0x38d3,
+ 0xb948, 0x36e8, 0x3653, 0x38d6,
+ 0xb94b, 0x36e2, 0x364d, 0x38d9,
+ 0xb94f, 0x36dc, 0x3648, 0x38db,
+ 0xb952, 0x36d6, 0x3642, 0x38de,
+ 0xb956, 0x36d1, 0x363c, 0x38e1,
+ 0xb959, 0x36cb, 0x3636, 0x38e4,
+ 0xb95d, 0x36c5, 0x3630, 0x38e7,
+ 0xb960, 0x36bf, 0x362b, 0x38ea,
+ 0xb964, 0x36b9, 0x3625, 0x38ed,
+ 0xb967, 0x36b3, 0x361f, 0x38f0,
+ 0xb96b, 0x36ad, 0x3619, 0x38f3,
+ 0xb96e, 0x36a7, 0x3613, 0x38f6,
+ 0xb972, 0x36a1, 0x360e, 0x38f8,
+ 0xb975, 0x369b, 0x3608, 0x38fb,
+ 0xb979, 0x3695, 0x3602, 0x38fe,
+ 0xb97c, 0x368f, 0x35fc, 0x3901,
+ 0xb980, 0x368a, 0x35f6, 0x3904,
+ 0xb983, 0x3684, 0x35f1, 0x3907,
+ 0xb987, 0x367e, 0x35eb, 0x390a,
+ 0xb98a, 0x3678, 0x35e5, 0x390d,
+ 0xb98e, 0x3672, 0x35df, 0x3910,
+ 0xb992, 0x366c, 0x35da, 0x3912,
+ 0xb995, 0x3667, 0x35d4, 0x3915,
+ 0xb999, 0x3661, 0x35ce, 0x3918,
+ 0xb99c, 0x365b, 0x35c9, 0x391b,
+ 0xb9a0, 0x3655, 0x35c3, 0x391e,
+ 0xb9a3, 0x364f, 0x35bd, 0x3921,
+ 0xb9a7, 0x364a, 0x35b7, 0x3924,
+ 0xb9ab, 0x3644, 0x35b2, 0x3926,
+ 0xb9ae, 0x363e, 0x35ac, 0x3929,
+ 0xb9b2, 0x3638, 0x35a6, 0x392c,
+ 0xb9b5, 0x3633, 0x35a1, 0x392f,
+ 0xb9b9, 0x362d, 0x359b, 0x3932,
+ 0xb9bd, 0x3627, 0x3595, 0x3935,
+ 0xb9c0, 0x3621, 0x3590, 0x3937,
+ 0xb9c4, 0x361c, 0x358a, 0x393a,
+ 0xb9c7, 0x3616, 0x3584, 0x393d,
+ 0xb9cb, 0x3610, 0x357f, 0x3940,
+ 0xb9cf, 0x360b, 0x3579, 0x3943,
+ 0xb9d2, 0x3605, 0x3573, 0x3946,
+ 0xb9d6, 0x35ff, 0x356e, 0x3948,
+ 0xb9d9, 0x35fa, 0x3568, 0x394b,
+ 0xb9dd, 0x35f4, 0x3563, 0x394e,
+ 0xb9e1, 0x35ee, 0x355d, 0x3951,
+ 0xb9e4, 0x35e9, 0x3557, 0x3954,
+ 0xb9e8, 0x35e3, 0x3552, 0x3956,
+ 0xb9ec, 0x35dd, 0x354c, 0x3959,
+ 0xb9ef, 0x35d8, 0x3547, 0x395c,
+ 0xb9f3, 0x35d2, 0x3541, 0x395f,
+ 0xb9f7, 0x35cd, 0x353c, 0x3961,
+ 0xb9fa, 0x35c7, 0x3536, 0x3964,
+ 0xb9fe, 0x35c1, 0x3530, 0x3967,
+ 0xba02, 0x35bc, 0x352b, 0x396a,
+ 0xba05, 0x35b6, 0x3525, 0x396d,
+ 0xba09, 0x35b1, 0x3520, 0x396f,
+ 0xba0d, 0x35ab, 0x351a, 0x3972,
+ 0xba10, 0x35a6, 0x3515, 0x3975,
+ 0xba14, 0x35a0, 0x350f, 0x3978,
+ 0xba18, 0x359b, 0x350a, 0x397a,
+ 0xba1b, 0x3595, 0x3504, 0x397d,
+ 0xba1f, 0x3590, 0x34ff, 0x3980,
+ 0xba23, 0x358a, 0x34f9, 0x3983,
+ 0xba26, 0x3585, 0x34f4, 0x3985,
+ 0xba2a, 0x357f, 0x34ef, 0x3988,
+ 0xba2e, 0x357a, 0x34e9, 0x398b,
+ 0xba32, 0x3574, 0x34e4, 0x398d,
+ 0xba35, 0x356f, 0x34de, 0x3990,
+ 0xba39, 0x3569, 0x34d9, 0x3993,
+ 0xba3d, 0x3564, 0x34d3, 0x3996,
+ 0xba40, 0x355e, 0x34ce, 0x3998,
+ 0xba44, 0x3559, 0x34c9, 0x399b,
+ 0xba48, 0x3554, 0x34c3, 0x399e,
+ 0xba4c, 0x354e, 0x34be, 0x39a0,
+ 0xba4f, 0x3549, 0x34b9, 0x39a3,
+ 0xba53, 0x3543, 0x34b3, 0x39a6,
+ 0xba57, 0x353e, 0x34ae, 0x39a8,
+ 0xba5a, 0x3539, 0x34a8, 0x39ab,
+ 0xba5e, 0x3533, 0x34a3, 0x39ae,
+ 0xba62, 0x352e, 0x349e, 0x39b0,
+ 0xba66, 0x3529, 0x3499, 0x39b3,
+ 0xba6a, 0x3523, 0x3493, 0x39b6,
+ 0xba6d, 0x351e, 0x348e, 0x39b8,
+ 0xba71, 0x3519, 0x3489, 0x39bb,
+ 0xba75, 0x3513, 0x3483, 0x39be,
+ 0xba79, 0x350e, 0x347e, 0x39c0,
+ 0xba7c, 0x3509, 0x3479, 0x39c3,
+ 0xba80, 0x3504, 0x3474, 0x39c5,
+ 0xba84, 0x34fe, 0x346e, 0x39c8,
+ 0xba88, 0x34f9, 0x3469, 0x39cb,
+ 0xba8b, 0x34f4, 0x3464, 0x39cd,
+ 0xba8f, 0x34ef, 0x345f, 0x39d0,
+ 0xba93, 0x34e9, 0x345a, 0x39d2,
+ 0xba97, 0x34e4, 0x3454, 0x39d5,
+ 0xba9b, 0x34df, 0x344f, 0x39d8,
+ 0xba9e, 0x34da, 0x344a, 0x39da,
+ 0xbaa2, 0x34d5, 0x3445, 0x39dd,
+ 0xbaa6, 0x34cf, 0x3440, 0x39df,
+ 0xbaaa, 0x34ca, 0x343b, 0x39e2,
+ 0xbaae, 0x34c5, 0x3435, 0x39e5,
+ 0xbab1, 0x34c0, 0x3430, 0x39e7,
+ 0xbab5, 0x34bb, 0x342b, 0x39ea,
+ 0xbab9, 0x34b6, 0x3426, 0x39ec,
+ 0xbabd, 0x34b1, 0x3421, 0x39ef,
+ 0xbac1, 0x34ac, 0x341c, 0x39f1,
+ 0xbac5, 0x34a6, 0x3417, 0x39f4,
+ 0xbac8, 0x34a1, 0x3412, 0x39f6,
+ 0xbacc, 0x349c, 0x340d, 0x39f9,
+ 0xbad0, 0x3497, 0x3408, 0x39fb,
+ 0xbad4, 0x3492, 0x3403, 0x39fe,
+ 0xbad8, 0x348d, 0x33fc, 0x3a00,
+ 0xbadc, 0x3488, 0x33f2, 0x3a03,
+ 0xbae0, 0x3483, 0x33e8, 0x3a05,
+ 0xbae3, 0x347e, 0x33de, 0x3a08,
+ 0xbae7, 0x3479, 0x33d4, 0x3a0a,
+ 0xbaeb, 0x3474, 0x33ca, 0x3a0d,
+ 0xbaef, 0x346f, 0x33c1, 0x3a0f,
+ 0xbaf3, 0x346a, 0x33b7, 0x3a12,
+ 0xbaf7, 0x3465, 0x33ad, 0x3a14,
+ 0xbafb, 0x3460, 0x33a3, 0x3a17,
+ 0xbafe, 0x345b, 0x3399, 0x3a19,
+ 0xbb02, 0x3456, 0x3390, 0x3a1c,
+ 0xbb06, 0x3451, 0x3386, 0x3a1e,
+ 0xbb0a, 0x344d, 0x337c, 0x3a20,
+ 0xbb0e, 0x3448, 0x3372, 0x3a23,
+ 0xbb12, 0x3443, 0x3369, 0x3a25,
+ 0xbb16, 0x343e, 0x335f, 0x3a28,
+ 0xbb1a, 0x3439, 0x3355, 0x3a2a,
+ 0xbb1e, 0x3434, 0x334c, 0x3a2c,
+ 0xbb21, 0x342f, 0x3342, 0x3a2f,
+ 0xbb25, 0x342a, 0x3339, 0x3a31,
+ 0xbb29, 0x3426, 0x332f, 0x3a34,
+ 0xbb2d, 0x3421, 0x3326, 0x3a36,
+ 0xbb31, 0x341c, 0x331c, 0x3a38,
+ 0xbb35, 0x3417, 0x3313, 0x3a3b,
+ 0xbb39, 0x3412, 0x3309, 0x3a3d,
+ 0xbb3d, 0x340e, 0x3300, 0x3a3f,
+ 0xbb41, 0x3409, 0x32f7, 0x3a42,
+ 0xbb45, 0x3404, 0x32ed, 0x3a44,
+ 0xbb49, 0x33ff, 0x32e4, 0x3a46,
+ 0xbb4d, 0x33f6, 0x32db, 0x3a49,
+ 0xbb51, 0x33ed, 0x32d1, 0x3a4b,
+ 0xbb54, 0x33e3, 0x32c8, 0x3a4d,
+ 0xbb58, 0x33da, 0x32bf, 0x3a50,
+ 0xbb5c, 0x33d0, 0x32b6, 0x3a52,
+ 0xbb60, 0x33c7, 0x32ad, 0x3a54,
+ 0xbb64, 0x33be, 0x32a3, 0x3a57,
+ 0xbb68, 0x33b5, 0x329a, 0x3a59,
+ 0xbb6c, 0x33ab, 0x3291, 0x3a5b,
+ 0xbb70, 0x33a2, 0x3288, 0x3a5d,
+ 0xbb74, 0x3399, 0x327f, 0x3a60,
+ 0xbb78, 0x3390, 0x3276, 0x3a62,
+ 0xbb7c, 0x3387, 0x326d, 0x3a64,
+ 0xbb80, 0x337d, 0x3264, 0x3a66,
+ 0xbb84, 0x3374, 0x325b, 0x3a69,
+ 0xbb88, 0x336b, 0x3252, 0x3a6b,
+ 0xbb8c, 0x3362, 0x3249, 0x3a6d,
+ 0xbb90, 0x3359, 0x3241, 0x3a6f,
+ 0xbb94, 0x3350, 0x3238, 0x3a71,
+ 0xbb98, 0x3347, 0x322f, 0x3a74,
+ 0xbb9c, 0x333e, 0x3226, 0x3a76,
+ 0xbba0, 0x3335, 0x321e, 0x3a78,
+ 0xbba4, 0x332c, 0x3215, 0x3a7a,
+ 0xbba8, 0x3323, 0x320c, 0x3a7c,
+ 0xbbac, 0x331a, 0x3204, 0x3a7e,
+ 0xbbb0, 0x3312, 0x31fb, 0x3a81,
+ 0xbbb4, 0x3309, 0x31f2, 0x3a83,
+ 0xbbb8, 0x3300, 0x31ea, 0x3a85,
+ 0xbbbc, 0x32f7, 0x31e1, 0x3a87,
+ 0xbbc0, 0x32ee, 0x31d9, 0x3a89,
+ 0xbbc4, 0x32e6, 0x31d0, 0x3a8b,
+ 0xbbc8, 0x32dd, 0x31c8, 0x3a8d,
+ 0xbbcc, 0x32d4, 0x31bf, 0x3a90,
+ 0xbbd0, 0x32cc, 0x31b7, 0x3a92,
+ 0xbbd4, 0x32c3, 0x31af, 0x3a94,
+ 0xbbd8, 0x32ba, 0x31a6, 0x3a96,
+ 0xbbdc, 0x32b2, 0x319e, 0x3a98,
+ 0xbbe0, 0x32a9, 0x3196, 0x3a9a,
+ 0xbbe4, 0x32a1, 0x318e, 0x3a9c,
+ 0xbbe8, 0x3298, 0x3185, 0x3a9e,
+ 0xbbec, 0x3290, 0x317d, 0x3aa0,
+ 0xbbf0, 0x3287, 0x3175, 0x3aa2,
+ 0xbbf4, 0x327f, 0x316d, 0x3aa4,
+ 0xbbf8, 0x3277, 0x3165, 0x3aa6,
+ 0xbbfc, 0x326e, 0x315d, 0x3aa8,
0 };
diff --git a/src/bicubic_table.py b/src/bicubic_table.py
index 3657cbc..232ccb7 100755
--- a/src/bicubic_table.py
+++ b/src/bicubic_table.py
@@ -2,6 +2,32 @@
import struct
+def half(i):
+ fs, fe, fm = ((i >> 31) & 0x1, (i >> 23) & 0xff, i & 0x7fffff)
+ s, e, m = (fs, 0, 0)
+
+ if (fe == 0x0):
+ pass
+ if ((fe == 0xff) and (fm == 0x0)):
+ e = 31
+ elif (fe == 0xff):
+ m = 1
+ e = 31
+ else:
+ exp = fe - 127;
+ if (exp < -24):
+ pass
+ elif (exp < -14):
+ temp = 10 - (-14 - exp)
+ m = 2**temp + (m >> (23 - temp))
+ elif (exp > 15):
+ e = 31
+ else:
+ e = exp + 15
+ m = fm >> 13
+
+ return ((s << 15) | (e << 10) | m)
+
def texgen(pix):
tex = []
@@ -26,14 +52,15 @@ def texgen(pix):
def printrow(l, offset):
- seq = [ hex(struct.unpack('<I',struct.pack('f',i))[0]) for i in l[offset:offset+4] ]
+ seq = [ struct.unpack('<I',struct.pack('f',i))[0] for i in l[offset:offset+4] ]
+ seq = [ hex(half(i)) for i in seq ]
return "\t" + ", ".join(seq) + ","
def maketable(pix):
l = texgen(pix)
- print "static const uint32_t bicubic_tex_" + str(pix) + "[] = {"
+ print "static const uint16_t bicubic_tex_" + str(pix) + "[] = {"
for i in range(0, pix, 4):
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index cc13933..8162281 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -283,7 +283,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
/* Upload bicubic filter tex */
if (pPriv->bicubic_enabled)
- RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_512, (uint8_t *)(info->FB + pPriv->bicubic_offset), 2048, 2048, 1, 512, 4);
+ RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_512, (uint8_t *)(info->FB + pPriv->bicubic_offset), 1024, 1024, 1, 512, 2);
/* update cliplist */
if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 88b4f2a..dbcd353 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -221,7 +221,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(0x0 << R300_TXHEIGHT_SHIFT) |
R300_TXPITCH_EN;
/* Format is 32-bit floats, 4bpp */
- txformat1 = R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32);
+ txformat1 = R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16);
/* Pitch is 127 (128-1) */
txpitch = 0x7f;
/* Tex filter */
commit ebbb7fb634fcadf28ff99c1df2c3db89fd56932d
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Sat Aug 2 01:45:43 2008 -0700
Change floats to uint32_t hex.
Useful for moving to 16-bit half-floats.
diff --git a/src/bicubic_table.h b/src/bicubic_table.h
index 126e64d..3b728fa 100644
--- a/src/bicubic_table.h
+++ b/src/bicubic_table.h
@@ -1,646 +1,646 @@
-static const float bicubic_tex_512[] = {
- -0.2, 1.0, 0.833333333333, 0.166666666667,
- -0.204088720925, 0.992187965834, 0.829396724701, 0.170603275299,
- -0.208229306439, 0.984378641369, 0.825400034587, 0.174599965413,
- -0.212420907874, 0.976574510623, 0.821344216665, 0.178655783335,
- -0.216662699005, 0.968777828797, 0.817230224609, 0.182769775391,
- -0.220953875426, 0.960990640339, 0.813059012095, 0.186940987905,
- -0.225293653935, 0.953214795864, 0.808831532796, 0.191168467204,
- -0.229681271957, 0.945451967972, 0.804548740387, 0.195451259613,
- -0.234115986983, 0.937703665988, 0.800211588542, 0.199788411458,
- -0.238597076022, 0.929971249668, 0.795821030935, 0.204178969065,
- -0.243123835089, 0.922255941932, 0.79137802124, 0.20862197876,
- -0.247695578698, 0.914558840653, 0.786883513133, 0.213116486867,
- -0.252311639383, 0.90688092957, 0.782338460286, 0.217661539714,
- -0.256971367229, 0.899223088369, 0.777743816376, 0.222256183624,
- -0.261674129428, 0.891586101989, 0.773100535075, 0.226899464925,
- -0.266419309847, 0.883970669194, 0.768409570058, 0.231590429942,
- -0.27120630861, 0.876377410468, 0.763671875, 0.236328125,
- -0.276034541704, 0.868806875283, 0.758888403575, 0.241111596425,
- -0.280903440584, 0.861259548768, 0.754060109456, 0.245939890544,
- -0.285812451814, 0.853735857846, 0.74918794632, 0.25081205368,
- -0.290761036698, 0.846236176857, 0.744272867839, 0.255727132161,
- -0.295748670944, 0.838760832722, 0.739315827688, 0.260684172312,
- -0.300774844327, 0.831310109672, 0.734317779541, 0.265682220459,
- -0.305839060373, 0.823884253585, 0.729279677073, 0.270720322927,
- -0.310940836049, 0.816483475952, 0.724202473958, 0.275797526042,
- -0.316079701469, 0.80910795751, 0.719087123871, 0.280912876129,
- -0.321255199604, 0.801757851568, 0.713934580485, 0.286065419515,
- -0.326466886014, 0.794433287044, 0.708745797475, 0.291254202525,
- -0.331714328576, 0.787134371247, 0.703521728516, 0.296478271484,
- -0.336997107235, 0.779861192413, 0.698263327281, 0.301736672719,
- -0.342314813753, 0.772613822026, 0.692971547445, 0.307028452555,
- -0.347667051478, 0.76539231694, 0.687647342682, 0.312352657318,
- -0.353053435115, 0.758196721311, 0.682291666667, 0.317708333333,
- -0.358473590501, 0.751027068365, 0.676905473073, 0.323094526927,
- -0.363927154404, 0.743883382007, 0.671489715576, 0.328510284424,
- -0.369413774313, 0.736765678299, 0.66604534785, 0.33395465215,
- -0.374933108243, 0.729673966794, 0.660573323568, 0.339426676432,
- -0.380484824551, 0.722608251764, 0.655074596405, 0.344925403595,
- -0.386068601748, 0.715568533318, 0.649550120036, 0.350449879964,
- -0.391684128331, 0.708554808415, 0.644000848134, 0.355999151866,
- -0.397331102613, 0.701567071798, 0.638427734375, 0.361572265625,
- -0.403009232558, 0.694605316836, 0.632831732432, 0.367168267568,
- -0.40871823563, 0.687669536295, 0.62721379598, 0.37278620402,
- -0.414457838638, 0.680759723045, 0.621574878693, 0.378425121307,
- -0.420227777594, 0.673875870699, 0.615915934245, 0.384084065755,
- -0.426027797575, 0.6670179742, 0.610237916311, 0.389762083689,
- -0.431857652583, 0.66018603035, 0.604541778564, 0.395458221436,
- -0.437717105418, 0.653380038302, 0.598828474681, 0.401171525319,
- -0.443605927552, 0.6466, 0.593098958333, 0.406901041667,
- -0.449523899007, 0.639845920588, 0.587354183197, 0.412645816803,
- -0.455470808236, 0.633117808778, 0.581595102946, 0.418404897054,
- -0.461446452007, 0.626415677192, 0.575822671254, 0.424177328746,
- -0.467450635295, 0.619739542669, 0.570037841797, 0.429962158203,
- -0.473483171168, 0.613089426553, 0.564241568247, 0.435758431753,
- -0.479543880687, 0.606465354949, 0.558434804281, 0.441565195719,
- -0.485632592794, 0.59986735897, 0.552618503571, 0.447381496429,
- -0.491749144218, 0.593295474951, 0.546793619792, 0.453206380208,
- -0.497893379365, 0.586749744657, 0.540961106618, 0.459038893382,
- -0.504065150224, 0.580230215471, 0.535121917725, 0.464878082275,
- -0.510264316266, 0.573736940568, 0.529277006785, 0.470722993215,
- -0.51649074434, 0.567269979082, 0.523427327474, 0.476572672526,
- -0.522744308578, 0.560829396251, 0.517573833466, 0.482426166534,
- -0.529024890292, 0.554415263567, 0.511717478434, 0.488282521566,
- -0.535332377868, 0.548027658908, 0.505859216054, 0.494140783946,
- -0.541666666667, 0.541666666667, 0.5, 0.5,
- -0.548027658908, 0.535332377868, 0.494140783946, 0.505859216054,
- -0.554415263567, 0.529024890292, 0.488282521566, 0.511717478434,
- -0.560829396251, 0.522744308578, 0.482426166534, 0.517573833466,
- -0.567269979082, 0.51649074434, 0.476572672526, 0.523427327474,
- -0.573736940568, 0.510264316266, 0.470722993215, 0.529277006785,
- -0.580230215471, 0.504065150224, 0.464878082275, 0.535121917725,
- -0.586749744657, 0.497893379365, 0.459038893382, 0.540961106618,
- -0.593295474951, 0.491749144218, 0.453206380208, 0.546793619792,
- -0.59986735897, 0.485632592794, 0.447381496429, 0.552618503571,
- -0.606465354949, 0.479543880687, 0.441565195719, 0.558434804281,
- -0.613089426553, 0.473483171168, 0.435758431753, 0.564241568247,
- -0.619739542669, 0.467450635295, 0.429962158203, 0.570037841797,
- -0.626415677192, 0.461446452007, 0.424177328746, 0.575822671254,
- -0.633117808778, 0.455470808236, 0.418404897054, 0.581595102946,
- -0.639845920588, 0.449523899007, 0.412645816803, 0.587354183197,
- -0.6466, 0.443605927552, 0.406901041667, 0.593098958333,
- -0.653380038302, 0.437717105418, 0.401171525319, 0.598828474681,
- -0.66018603035, 0.431857652583, 0.395458221436, 0.604541778564,
- -0.6670179742, 0.426027797575, 0.389762083689, 0.610237916311,
- -0.673875870699, 0.420227777594, 0.384084065755, 0.615915934245,
- -0.680759723045, 0.414457838638, 0.378425121307, 0.621574878693,
- -0.687669536295, 0.40871823563, 0.37278620402, 0.62721379598,
- -0.694605316836, 0.403009232558, 0.367168267568, 0.632831732432,
- -0.701567071798, 0.397331102613, 0.361572265625, 0.638427734375,
- -0.708554808415, 0.391684128331, 0.355999151866, 0.644000848134,
- -0.715568533318, 0.386068601748, 0.350449879964, 0.649550120036,
- -0.722608251764, 0.380484824551, 0.344925403595, 0.655074596405,
- -0.729673966794, 0.374933108243, 0.339426676432, 0.660573323568,
- -0.736765678299, 0.369413774313, 0.33395465215, 0.66604534785,
- -0.743883382007, 0.363927154404, 0.328510284424, 0.671489715576,
- -0.751027068365, 0.358473590501, 0.323094526927, 0.676905473073,
- -0.758196721311, 0.353053435115, 0.317708333333, 0.682291666667,
- -0.76539231694, 0.347667051478, 0.312352657318, 0.687647342682,
- -0.772613822026, 0.342314813753, 0.307028452555, 0.692971547445,
- -0.779861192413, 0.336997107235, 0.301736672719, 0.698263327281,
- -0.787134371247, 0.331714328576, 0.296478271484, 0.703521728516,
- -0.794433287044, 0.326466886014, 0.291254202525, 0.708745797475,
- -0.801757851568, 0.321255199604, 0.286065419515, 0.713934580485,
- -0.80910795751, 0.316079701469, 0.280912876129, 0.719087123871,
- -0.816483475952, 0.310940836049, 0.275797526042, 0.724202473958,
- -0.823884253585, 0.305839060373, 0.270720322927, 0.729279677073,
- -0.831310109672, 0.300774844327, 0.265682220459, 0.734317779541,
- -0.838760832722, 0.295748670944, 0.260684172312, 0.739315827688,
- -0.846236176857, 0.290761036698, 0.255727132161, 0.744272867839,
- -0.853735857846, 0.285812451814, 0.25081205368, 0.74918794632,
- -0.861259548768, 0.280903440584, 0.245939890544, 0.754060109456,
- -0.868806875283, 0.276034541704, 0.241111596425, 0.758888403575,
- -0.876377410468, 0.27120630861, 0.236328125, 0.763671875,
- -0.883970669194, 0.266419309847, 0.231590429942, 0.768409570058,
- -0.891586101989, 0.261674129428, 0.226899464925, 0.773100535075,
- -0.899223088369, 0.256971367229, 0.222256183624, 0.777743816376,
- -0.90688092957, 0.252311639383, 0.217661539714, 0.782338460286,
- -0.914558840653, 0.247695578698, 0.213116486867, 0.786883513133,
- -0.922255941932, 0.243123835089, 0.20862197876, 0.79137802124,
- -0.929971249668, 0.238597076022, 0.204178969065, 0.795821030935,
- -0.937703665988, 0.234115986983, 0.199788411458, 0.800211588542,
- -0.945451967972, 0.229681271957, 0.195451259613, 0.804548740387,
- -0.953214795864, 0.225293653935, 0.191168467204, 0.808831532796,
- -0.960990640339, 0.220953875426, 0.186940987905, 0.813059012095,
- -0.968777828797, 0.216662699005, 0.182769775391, 0.817230224609,
- -0.976574510623, 0.212420907874, 0.178655783335, 0.821344216665,
- -0.984378641369, 0.208229306439, 0.174599965413, 0.825400034587,
- -0.992187965834, 0.204088720925, 0.170603275299, 0.829396724701,
+static const uint32_t bicubic_tex_512[] = {
+ 0xbe4ccccd, 0x3f800000, 0x3f555555, 0x3e2aaaab,
+ 0xbe50fca2, 0x3f7e0008, 0x3f545358, 0x3e2eb2a0,
+ 0xbe553a10, 0x3f7c003d, 0x3f534d6b, 0x3e32ca55,
+ 0xbe5984de, 0x3f7a00ca, 0x3f52439d, 0x3e36f18b,
+ 0xbe5ddcd4, 0x3f7801d3, 0x3f513600, 0x3e3b2800,
+ 0xbe6241bc, 0x3f76037c, 0x3f5024a3, 0x3e3f6d75,
+ 0xbe66b361, 0x3f7405e3, 0x3f4f0f95, 0x3e43c1ab,
+ 0xbe6b3191, 0x3f720924, 0x3f4df6e8, 0x3e482460,
+ 0xbe6fbc1a, 0x3f700d59, 0x3f4cdaab, 0x3e4c9555,
+ 0xbe7452cb, 0x3f6e1299, 0x3f4bbaed, 0x3e51144b,
+ 0xbe78f574, 0x3f6c18f7, 0x3f4a97c0, 0x3e55a100,
+ 0xbe7da3e9, 0x3f6a2087, 0x3f497133, 0x3e5a3b35,
+ 0xbe812efe, 0x3f682959, 0x3f484755, 0x3e5ee2ab,
+ 0xbe8391c0, 0x3f66337c, 0x3f471a38, 0x3e639720,
+ 0xbe85fa27, 0x3f643efd, 0x3f45e9eb, 0x3e685855,
+ 0xbe88681d, 0x3f624be7, 0x3f44b67d, 0x3e6d260b,
+ 0xbe8adb8e, 0x3f605a45, 0x3f438000, 0x3e720000,
+ 0xbe8d5466, 0x3f5e6a21, 0x3f424683, 0x3e76e5f5,
+ 0xbe8fd293, 0x3f5c7b81, 0x3f410a15, 0x3e7bd7ab,
+ 0xbe925602, 0x3f5a8e6f, 0x3f3fcac8, 0x3e806a70,
+ 0xbe94dea1, 0x3f58a2ef, 0x3f3e88ab, 0x3e82eeab,
+ 0xbe976c5f, 0x3f56b908, 0x3f3d43cd, 0x3e857865,
+ 0xbe99ff29, 0x3f54d0bd, 0x3f3bfc40, 0x3e880780,
+ 0xbe9c96f0, 0x3f52ea14, 0x3f3ab213, 0x3e8a9bdb,
+ 0xbe9f33a3, 0x3f510510, 0x3f396555, 0x3e8d3555,
+ 0xbea1d533, 0x3f4f21b3, 0x3f381618, 0x3e8fd3d0,
+ 0xbea47b90, 0x3f4d4001, 0x3f36c46b, 0x3e92772b,
+ 0xbea726ab, 0x3f4b5ffb, 0x3f35705d, 0x3e951f45,
+ 0xbea9d676, 0x3f4981a3, 0x3f341a00, 0x3e97cc00,
+ 0xbeac8ae3, 0x3f47a4fc, 0x3f32c163, 0x3e9a7d3b,
+ 0xbeaf43e3, 0x3f45ca05, 0x3f316695, 0x3e9d32d5,
+ 0xbeb2016a, 0x3f43f0c0, 0x3f3009a8, 0x3e9fecb0,
+ 0xbeb4c36b, 0x3f42192e, 0x3f2eaaab, 0x3ea2aaab,
+ 0xbeb789da, 0x3f40434f, 0x3f2d49ad, 0x3ea56ca5,
+ 0xbeba54a9, 0x3f3e6f24, 0x3f2be6c0, 0x3ea83280,
+ 0xbebd23cd, 0x3f3c9cad, 0x3f2a81f3, 0x3eaafc1b,
+ 0xbebff73b, 0x3f3acbea, 0x3f291b55, 0x3eadc955,
+ 0xbec2cee8, 0x3f38fcdb, 0x3f27b2f8, 0x3eb09a10,
+ 0xbec5aac9, 0x3f372f80, 0x3f2648eb, 0x3eb36e2b,
+ 0xbec88ad2, 0x3f3563d9, 0x3f24dd3d, 0x3eb64585,
+ 0xbecb6efb, 0x3f3399e6, 0x3f237000, 0x3eb92000,
+ 0xbece573a, 0x3f31d1a7, 0x3f220143, 0x3ebbfd7b,
+ 0xbed14384, 0x3f300b1c, 0x3f209115, 0x3ebeddd5,
+ 0xbed433d1, 0x3f2e4645, 0x3f1f1f88, 0x3ec1c0f0,
+ 0xbed72818, 0x3f2c8321, 0x3f1dacab, 0x3ec4a6ab,
+ 0xbeda2051, 0x3f2ac1b1, 0x3f1c388d, 0x3ec78ee5,
+ 0xbedd1c72, 0x3f2901f4, 0x3f1ac340, 0x3eca7980,
+ 0xbee01c75, 0x3f2743ea, 0x3f194cd3, 0x3ecd665b,
+ 0xbee32051, 0x3f258794, 0x3f17d555, 0x3ed05555,
+ 0xbee627ff, 0x3f23ccf1, 0x3f165cd8, 0x3ed34650,
+ 0xbee93378, 0x3f221402, 0x3f14e36b, 0x3ed6392b,
+ 0xbeec42b6, 0x3f205cc7, 0x3f13691d, 0x3ed92dc5,
+ 0xbeef55b1, 0x3f1ea740, 0x3f11ee00, 0x3edc2400,
+ 0xbef26c63, 0x3f1cf36e, 0x3f107223, 0x3edf1bbb,
+ 0xbef586c7, 0x3f1b4150, 0x3f0ef595, 0x3ee214d5,
+ 0xbef8a4d6, 0x3f1990e8, 0x3f0d7868, 0x3ee50f30,
+ 0xbefbc68b, 0x3f17e236, 0x3f0bfaab, 0x3ee80aab,
+ 0xbefeebe2, 0x3f16353b, 0x3f0a7c6d, 0x3eeb0725,
+ 0xbf010a6a, 0x3f1489f8, 0x3f08fdc0, 0x3eee0480,
+ 0xbf02a0af, 0x3f12e06d, 0x3f077eb3, 0x3ef1029b,
+ 0xbf0438bd, 0x3f11389b, 0x3f05ff55, 0x3ef40155,
+ 0xbf05d292, 0x3f0f9284, 0x3f047fb8, 0x3ef70090,
+ 0xbf076e2d, 0x3f0dee29, 0x3f02ffeb, 0x3efa002b,
+ 0xbf090b8b, 0x3f0c4b8a, 0x3f017ffd, 0x3efd0005,
+ 0xbf0aaaab, 0x3f0aaaab, 0x3f000000, 0x3f000000,
+ 0xbf0c4b8a, 0x3f090b8b, 0x3efd0005, 0x3f017ffd,
+ 0xbf0dee29, 0x3f076e2d, 0x3efa002b, 0x3f02ffeb,
+ 0xbf0f9284, 0x3f05d292, 0x3ef70090, 0x3f047fb8,
+ 0xbf11389b, 0x3f0438bd, 0x3ef40155, 0x3f05ff55,
+ 0xbf12e06d, 0x3f02a0af, 0x3ef1029b, 0x3f077eb3,
+ 0xbf1489f8, 0x3f010a6a, 0x3eee0480, 0x3f08fdc0,
+ 0xbf16353b, 0x3efeebe2, 0x3eeb0725, 0x3f0a7c6d,
+ 0xbf17e236, 0x3efbc68b, 0x3ee80aab, 0x3f0bfaab,
+ 0xbf1990e8, 0x3ef8a4d6, 0x3ee50f30, 0x3f0d7868,
+ 0xbf1b4150, 0x3ef586c7, 0x3ee214d5, 0x3f0ef595,
+ 0xbf1cf36e, 0x3ef26c63, 0x3edf1bbb, 0x3f107223,
+ 0xbf1ea740, 0x3eef55b1, 0x3edc2400, 0x3f11ee00,
+ 0xbf205cc7, 0x3eec42b6, 0x3ed92dc5, 0x3f13691d,
+ 0xbf221402, 0x3ee93378, 0x3ed6392b, 0x3f14e36b,
+ 0xbf23ccf1, 0x3ee627ff, 0x3ed34650, 0x3f165cd8,
+ 0xbf258794, 0x3ee32051, 0x3ed05555, 0x3f17d555,
+ 0xbf2743ea, 0x3ee01c75, 0x3ecd665b, 0x3f194cd3,
+ 0xbf2901f4, 0x3edd1c72, 0x3eca7980, 0x3f1ac340,
+ 0xbf2ac1b1, 0x3eda2051, 0x3ec78ee5, 0x3f1c388d,
+ 0xbf2c8321, 0x3ed72818, 0x3ec4a6ab, 0x3f1dacab,
+ 0xbf2e4645, 0x3ed433d1, 0x3ec1c0f0, 0x3f1f1f88,
+ 0xbf300b1c, 0x3ed14384, 0x3ebeddd5, 0x3f209115,
+ 0xbf31d1a7, 0x3ece573a, 0x3ebbfd7b, 0x3f220143,
+ 0xbf3399e6, 0x3ecb6efb, 0x3eb92000, 0x3f237000,
+ 0xbf3563d9, 0x3ec88ad2, 0x3eb64585, 0x3f24dd3d,
+ 0xbf372f80, 0x3ec5aac9, 0x3eb36e2b, 0x3f2648eb,
+ 0xbf38fcdb, 0x3ec2cee8, 0x3eb09a10, 0x3f27b2f8,
+ 0xbf3acbea, 0x3ebff73b, 0x3eadc955, 0x3f291b55,
+ 0xbf3c9cad, 0x3ebd23cd, 0x3eaafc1b, 0x3f2a81f3,
+ 0xbf3e6f24, 0x3eba54a9, 0x3ea83280, 0x3f2be6c0,
+ 0xbf40434f, 0x3eb789da, 0x3ea56ca5, 0x3f2d49ad,
+ 0xbf42192e, 0x3eb4c36b, 0x3ea2aaab, 0x3f2eaaab,
+ 0xbf43f0c0, 0x3eb2016a, 0x3e9fecb0, 0x3f3009a8,
+ 0xbf45ca05, 0x3eaf43e3, 0x3e9d32d5, 0x3f316695,
+ 0xbf47a4fc, 0x3eac8ae3, 0x3e9a7d3b, 0x3f32c163,
+ 0xbf4981a3, 0x3ea9d676, 0x3e97cc00, 0x3f341a00,
+ 0xbf4b5ffb, 0x3ea726ab, 0x3e951f45, 0x3f35705d,
+ 0xbf4d4001, 0x3ea47b90, 0x3e92772b, 0x3f36c46b,
+ 0xbf4f21b3, 0x3ea1d533, 0x3e8fd3d0, 0x3f381618,
+ 0xbf510510, 0x3e9f33a3, 0x3e8d3555, 0x3f396555,
+ 0xbf52ea14, 0x3e9c96f0, 0x3e8a9bdb, 0x3f3ab213,
+ 0xbf54d0bd, 0x3e99ff29, 0x3e880780, 0x3f3bfc40,
+ 0xbf56b908, 0x3e976c5f, 0x3e857865, 0x3f3d43cd,
+ 0xbf58a2ef, 0x3e94dea1, 0x3e82eeab, 0x3f3e88ab,
+ 0xbf5a8e6f, 0x3e925602, 0x3e806a70, 0x3f3fcac8,
+ 0xbf5c7b81, 0x3e8fd293, 0x3e7bd7ab, 0x3f410a15,
+ 0xbf5e6a21, 0x3e8d5466, 0x3e76e5f5, 0x3f424683,
+ 0xbf605a45, 0x3e8adb8e, 0x3e720000, 0x3f438000,
+ 0xbf624be7, 0x3e88681d, 0x3e6d260b, 0x3f44b67d,
+ 0xbf643efd, 0x3e85fa27, 0x3e685855, 0x3f45e9eb,
+ 0xbf66337c, 0x3e8391c0, 0x3e639720, 0x3f471a38,
+ 0xbf682959, 0x3e812efe, 0x3e5ee2ab, 0x3f484755,
+ 0xbf6a2087, 0x3e7da3e9, 0x3e5a3b35, 0x3f497133,
+ 0xbf6c18f7, 0x3e78f574, 0x3e55a100, 0x3f4a97c0,
+ 0xbf6e1299, 0x3e7452cb, 0x3e51144b, 0x3f4bbaed,
+ 0xbf700d59, 0x3e6fbc1a, 0x3e4c9555, 0x3f4cdaab,
+ 0xbf720924, 0x3e6b3191, 0x3e482460, 0x3f4df6e8,
+ 0xbf7405e3, 0x3e66b361, 0x3e43c1ab, 0x3f4f0f95,
+ 0xbf76037c, 0x3e6241bc, 0x3e3f6d75, 0x3f5024a3,
+ 0xbf7801d3, 0x3e5ddcd4, 0x3e3b2800, 0x3f513600,
+ 0xbf7a00ca, 0x3e5984de, 0x3e36f18b, 0x3f52439d,
+ 0xbf7c003d, 0x3e553a10, 0x3e32ca55, 0x3f534d6b,
+ 0xbf7e0008, 0x3e50fca2, 0x3e2eb2a0, 0x3f545358,
0 };
-static const float bicubic_tex_2048[] = {
- -0.2, 1.0, 0.833333333333, 0.166666666667,
- -0.201017270652, 0.998046882407, 0.832354865968, 0.167645134032,
- -0.202037823453, 0.996093808912, 0.831372598807, 0.168627401193,
- -0.203061644735, 0.994140822671, 0.830386546751, 0.169613453249,
- -0.204088720925, 0.992187965834, 0.829396724701, 0.170603275299,
- -0.205119038539, 0.990235279565, 0.828403147558, 0.171596852442,
- -0.206152584184, 0.988282804055, 0.827405830224, 0.172594169776,
- -0.207189344555, 0.986330578552, 0.8264047876, 0.1735952124,
- -0.208229306439, 0.984378641369, 0.825400034587, 0.174599965413,
- -0.209272456708, 0.98242702991, 0.824391586085, 0.175608413915,
- -0.210318782324, 0.980475780685, 0.823379456997, 0.176620543003,
- -0.211368270334, 0.97852492933, 0.822363662223, 0.177636337777,
- -0.212420907874, 0.976574510623, 0.821344216665, 0.178655783335,
- -0.213476682163, 0.974624558501, 0.820321135223, 0.179678864777,
- -0.214535580507, 0.972675106081, 0.819294432799, 0.180705567201,
- -0.215597590297, 0.970726185673, 0.818264124294, 0.181735875706,
- -0.216662699005, 0.968777828797, 0.817230224609, 0.182769775391,
- -0.217730894191, 0.966830066203, 0.816192748646, 0.183807251354,
- -0.218802163495, 0.964882927881, 0.815151711305, 0.184848288695,
- -0.219876494638, 0.962936443085, 0.814107127488, 0.185892872512,
- -0.220953875426, 0.960990640339, 0.813059012095, 0.186940987905,
- -0.222034293743, 0.959045547461, 0.812007380029, 0.187992619971,
- -0.223117737557, 0.957101191572, 0.810952246189, 0.189047753811,
- -0.224204194912, 0.955157599114, 0.809893625478, 0.190106374522,
- -0.225293653935, 0.953214795864, 0.808831532796, 0.191168467204,
- -0.226386102829, 0.951272806947, 0.807765983045, 0.192234016955,
- -0.227481529878, 0.949331656851, 0.806696991126, 0.193303008874,
- -0.228579923441, 0.947391369442, 0.805624571939, 0.194375428061,
- -0.229681271957, 0.945451967972, 0.804548740387, 0.195451259613,
- -0.230785563941, 0.943513475102, 0.80346951137, 0.19653048863,
- -0.231892787983, 0.941575912905, 0.802386899789, 0.197613100211,
- -0.233002932749, 0.939639302885, 0.801300920546, 0.198699079454,
- -0.234115986983, 0.937703665988, 0.800211588542, 0.199788411458,
- -0.235231939499, 0.935769022612, 0.799118918677, 0.200881081323,
- -0.236350779189, 0.933835392623, 0.798022925854, 0.201977074146,
- -0.237472495017, 0.931902795364, 0.796923624973, 0.203076375027,
- -0.238597076022, 0.929971249668, 0.795821030935, 0.204178969065,
- -0.239724511313, 0.928040773869, 0.794715158641, 0.205284841359,
- -0.240854790073, 0.926111385811, 0.793606022994, 0.206393977006,
- -0.241987901556, 0.924183102865, 0.792493638893, 0.207506361107,
- -0.243123835089, 0.922255941932, 0.79137802124, 0.20862197876,
- -0.244262580067, 0.92032991946, 0.790259184937, 0.209740815063,
- -0.245404125959, 0.918405051449, 0.789137144883, 0.210862855117,
- -0.2465484623, 0.916481353466, 0.788011915982, 0.211988084018,
- -0.247695578698, 0.914558840653, 0.786883513133, 0.213116486867,
- -0.248845464827, 0.912637527735, 0.785751951238, 0.214248048762,
- -0.249998110432, 0.91071742903, 0.784617245197, 0.215382754803,
- -0.251153505324, 0.908798558464, 0.783479409913, 0.216520590087,
- -0.252311639383, 0.90688092957, 0.782338460286, 0.217661539714,
- -0.253472502556, 0.904964555505, 0.781194411218, 0.218805588782,
- -0.254636084857, 0.903049449058, 0.78004727761, 0.21995272239,
- -0.255802376366, 0.901135622655, 0.778897074362, 0.221102925638,
- -0.256971367229, 0.899223088369, 0.777743816376, 0.222256183624,
- -0.258143047657, 0.897311857929, 0.776587518553, 0.223412481447,
- -0.259317407928, 0.89540194273, 0.775428195794, 0.224571804206,
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- -0.97852492933, 0.211368270334, 0.177636337777, 0.822363662223,
- -0.980475780685, 0.210318782324, 0.176620543003, 0.823379456997,
- -0.98242702991, 0.209272456708, 0.175608413915, 0.824391586085,
- -0.984378641369, 0.208229306439, 0.174599965413, 0.825400034587,
- -0.986330578552, 0.207189344555, 0.1735952124, 0.8264047876,
- -0.988282804055, 0.206152584184, 0.172594169776, 0.827405830224,
- -0.990235279565, 0.205119038539, 0.171596852442, 0.828403147558,
- -0.992187965834, 0.204088720925, 0.170603275299, 0.829396724701,
- -0.994140822671, 0.203061644735, 0.169613453249, 0.830386546751,
- -0.996093808912, 0.202037823453, 0.168627401193, 0.831372598807,
- -0.998046882407, 0.201017270652, 0.167645134032, 0.832354865968,
+static const uint32_t bicubic_tex_2048[] = {
+ 0xbe4ccccd, 0x3f800000, 0x3f555555, 0x3e2aaaab,
+ 0xbe4dd779, 0x3f7f8000, 0x3f551535, 0x3e2bab2a,
+ 0xbe4ee301, 0x3f7f0001, 0x3f54d4d6, 0x3e2caca9,
+ 0xbe4fef64, 0x3f7e8003, 0x3f549436, 0x3e2daf26,
+ 0xbe50fca2, 0x3f7e0008, 0x3f545358, 0x3e2eb2a0,
+ 0xbe520aba, 0x3f7d800f, 0x3f54123b, 0x3e2fb716,
+ 0xbe5319aa, 0x3f7d001a, 0x3f53d0de, 0x3e30bc87,
+ 0xbe542972, 0x3f7c8029, 0x3f538f44, 0x3e31c2f2,
+ 0xbe553a10, 0x3f7c003d, 0x3f534d6b, 0x3e32ca55,
+ 0xbe564b85, 0x3f7b8056, 0x3f530b54, 0x3e33d2b1,
+ 0xbe575dcf, 0x3f7b0076, 0x3f52c8ff, 0x3e34dc04,
+ 0xbe5870ed, 0x3f7a809c, 0x3f52866d, 0x3e35e64d,
+ 0xbe5984de, 0x3f7a00ca, 0x3f52439d, 0x3e36f18b,
+ 0xbe5a99a2, 0x3f7980ff, 0x3f520091, 0x3e37fdbc,
+ 0xbe5baf37, 0x3f79013c, 0x3f51bd48, 0x3e390ae1,
+ 0xbe5cc59d, 0x3f788183, 0x3f5179c2, 0x3e3a18f8,
+ 0xbe5ddcd4, 0x3f7801d3, 0x3f513600, 0x3e3b2800,
+ 0xbe5ef4d9, 0x3f77822d, 0x3f50f202, 0x3e3c37f8,
+ 0xbe600dad, 0x3f770291, 0x3f50adc8, 0x3e3d48df,
+ 0xbe61274e, 0x3f768301, 0x3f506953, 0x3e3e5ab4,
+ 0xbe6241bc, 0x3f76037c, 0x3f5024a3, 0x3e3f6d75,
+ 0xbe635cf5, 0x3f758402, 0x3f4fdfb7, 0x3e408123,
+ 0xbe6478fa, 0x3f750495, 0x3f4f9a91, 0x3e4195bc,
+ 0xbe6595c9, 0x3f748535, 0x3f4f5530, 0x3e42ab3f,
+ 0xbe66b361, 0x3f7405e3, 0x3f4f0f95, 0x3e43c1ab,
+ 0xbe67d1c2, 0x3f73869d, 0x3f4ec9c0, 0x3e44d8fe,
+ 0xbe68f0eb, 0x3f730766, 0x3f4e83b2, 0x3e45f139,
+ 0xbe6a10db, 0x3f72883e, 0x3f4e3d69, 0x3e470a5a,
+ 0xbe6b3191, 0x3f720924, 0x3f4df6e8, 0x3e482460,
+ 0xbe6c530d, 0x3f718a19, 0x3f4db02e, 0x3e493f4a,
+ 0xbe6d754e, 0x3f710b1e, 0x3f4d693a, 0x3e4a5b17,
+ 0xbe6e9852, 0x3f708c34, 0x3f4d220f, 0x3e4b77c6,
+ 0xbe6fbc1a, 0x3f700d59, 0x3f4cdaab, 0x3e4c9555,
+ 0xbe70e0a4, 0x3f6f8e8f, 0x3f4c930f, 0x3e4db3c5,
+ 0xbe7205f0, 0x3f6f0fd6, 0x3f4c4b3b, 0x3e4ed314,
+ 0xbe732bfd, 0x3f6e912e, 0x3f4c0330, 0x3e4ff341,
+ 0xbe7452cb, 0x3f6e1299, 0x3f4bbaed, 0x3e51144b,
+ 0xbe757a58, 0x3f6d9415, 0x3f4b7274, 0x3e523630,
+ 0xbe76a2a3, 0x3f6d15a3, 0x3f4b29c4, 0x3e5358f1,
+ 0xbe77cbad, 0x3f6c9744, 0x3f4ae0dd, 0x3e547c8c,
+ 0xbe78f574, 0x3f6c18f7, 0x3f4a97c0, 0x3e55a100,
+ 0xbe7a1ff8, 0x3f6b9abe, 0x3f4a4e6d, 0x3e56c64c,
+ 0xbe7b4b38, 0x3f6b1c98, 0x3f4a04e4, 0x3e57ec6f,
+ 0xbe7c7733, 0x3f6a9e86, 0x3f49bb26, 0x3e591368,
+ 0xbe7da3e9, 0x3f6a2087, 0x3f497133, 0x3e5a3b35,
+ 0xbe7ed158, 0x3f69a29d, 0x3f49270a, 0x3e5b63d7,
+ 0xbe7fff81, 0x3f6924c7, 0x3f48dcad, 0x3e5c8d4c,
+ 0xbe809731, 0x3f68a706, 0x3f48921b, 0x3e5db793,
+ 0xbe812efe, 0x3f682959, 0x3f484755, 0x3e5ee2ab,
+ 0xbe81c726, 0x3f67abc2, 0x3f47fc5b, 0x3e600e92,
+ 0xbe825fa9, 0x3f672e40, 0x3f47b12e, 0x3e613b49,
+ 0xbe82f887, 0x3f66b0d3, 0x3f4765cc, 0x3e6268ce,
+ 0xbe8391c0, 0x3f66337c, 0x3f471a38, 0x3e639720,
+ 0xbe842b53, 0x3f65b63b, 0x3f46ce71, 0x3e64c63e,
+ 0xbe84c540, 0x3f653910, 0x3f468276, 0x3e65f627,
+ 0xbe855f87, 0x3f64bbfb, 0x3f46364a, 0x3e6726da,
+ 0xbe85fa27, 0x3f643efd, 0x3f45e9eb, 0x3e685855,
+ 0xbe869520, 0x3f63c215, 0x3f459d5a, 0x3e698a99,
+ 0xbe873071, 0x3f634544, 0x3f455097, 0x3e6abda4,
+ 0xbe87cc1b, 0x3f62c88a, 0x3f4503a3, 0x3e6bf175,
+ 0xbe88681d, 0x3f624be7, 0x3f44b67d, 0x3e6d260b,
+ 0xbe890476, 0x3f61cf5b, 0x3f446927, 0x3e6e5b64,
+ 0xbe89a127, 0x3f6152e7, 0x3f441ba0, 0x3e6f9181,
+ 0xbe8a3e2f, 0x3f60d68a, 0x3f43cde8, 0x3e70c860,
+ 0xbe8adb8e, 0x3f605a45, 0x3f438000, 0x3e720000,
+ 0xbe8b7943, 0x3f5fde18, 0x3f4331e8, 0x3e733860,
+ 0xbe8c174e, 0x3f5f6203, 0x3f42e3a0, 0x3e74717f,
+ 0xbe8cb5af, 0x3f5ee606, 0x3f429529, 0x3e75ab5c,
+ 0xbe8d5466, 0x3f5e6a21, 0x3f424683, 0x3e76e5f5,
+ 0xbe8df372, 0x3f5dee54, 0x3f41f7ad, 0x3e78214b,
+ 0xbe8e92d3, 0x3f5d72a0, 0x3f41a8a9, 0x3e795d5c,
+ 0xbe8f3289, 0x3f5cf704, 0x3f415976, 0x3e7a9a27,
+ 0xbe8fd293, 0x3f5c7b81, 0x3f410a15, 0x3e7bd7ab,
+ 0xbe9072f2, 0x3f5c0017, 0x3f40ba86, 0x3e7d15e6,
+ 0xbe9113a4, 0x3f5b84c6, 0x3f406aca, 0x3e7e54d9,
+ 0xbe91b4aa, 0x3f5b098e, 0x3f401adf, 0x3e7f9482,
+ 0xbe925602, 0x3f5a8e6f, 0x3f3fcac8, 0x3e806a70,
+ 0xbe92f7ae, 0x3f5a1369, 0x3f3f7a84, 0x3e810af9,
+ 0xbe9399ad, 0x3f59987c, 0x3f3f2a12, 0x3e81abdb,
+ 0xbe943bfe, 0x3f591da9, 0x3f3ed975, 0x3e824d17,
+ 0xbe94dea1, 0x3f58a2ef, 0x3f3e88ab, 0x3e82eeab,
+ 0xbe958197, 0x3f58284f, 0x3f3e37b5, 0x3e839097,
+ 0xbe9624dd, 0x3f57adc8, 0x3f3de693, 0x3e8432da,
+ 0xbe96c875, 0x3f57335b, 0x3f3d9546, 0x3e84d574,
+ 0xbe976c5f, 0x3f56b908, 0x3f3d43cd, 0x3e857865,
+ 0xbe981099, 0x3f563ece, 0x3f3cf22a, 0x3e861bac,
+ 0xbe98b523, 0x3f55c4af, 0x3f3ca05c, 0x3e86bf49,
+ 0xbe9959fe, 0x3f554aa9, 0x3f3c4e63, 0x3e87633a,
+ 0xbe99ff29, 0x3f54d0bd, 0x3f3bfc40, 0x3e880780,
+ 0xbe9aa4a4, 0x3f5456ec, 0x3f3ba9f3, 0x3e88ac1a,
+ 0xbe9b4a6e, 0x3f53dd34, 0x3f3b577c, 0x3e895107,
+ 0xbe9bf087, 0x3f536397, 0x3f3b04dc, 0x3e89f648,
+ 0xbe9c96f0, 0x3f52ea14, 0x3f3ab213, 0x3e8a9bdb,
+ 0xbe9d3da7, 0x3f5270ab, 0x3f3a5f20, 0x3e8b41c0,
+ 0xbe9de4ad, 0x3f51f75d, 0x3f3a0c05, 0x3e8be7f6,
+ 0xbe9e8c01, 0x3f517e29, 0x3f39b8c1, 0x3e8c8e7d,
+ 0xbe9f33a3, 0x3f510510, 0x3f396555, 0x3e8d3555,
+ 0xbe9fdb93, 0x3f508c11, 0x3f3911c1, 0x3e8ddc7d,
+ 0xbea083d0, 0x3f50132c, 0x3f38be06, 0x3e8e83f5,
+ 0xbea12c5b, 0x3f4f9a62, 0x3f386a22, 0x3e8f2bbb,
+ 0xbea1d533, 0x3f4f21b3, 0x3f381618, 0x3e8fd3d0,
+ 0xbea27e57, 0x3f4ea91e, 0x3f37c1e7, 0x3e907c33,
+ 0xbea327c9, 0x3f4e30a4, 0x3f376d8e, 0x3e9124e3,
+ 0xbea3d186, 0x3f4db845, 0x3f371910, 0x3e91cde1,
+ 0xbea47b90, 0x3f4d4001, 0x3f36c46b, 0x3e92772b,
+ 0xbea525e5, 0x3f4cc7d7, 0x3f366fa0, 0x3e9320c1,
+ 0xbea5d086, 0x3f4c4fc8, 0x3f361aaf, 0x3e93caa2,
+ 0xbea67b73, 0x3f4bd7d4, 0x3f35c599, 0x3e9474ce,
+ 0xbea726ab, 0x3f4b5ffb, 0x3f35705d, 0x3e951f45,
+ 0xbea7d22e, 0x3f4ae83d, 0x3f351afd, 0x3e95ca06,
+ 0xbea87dfb, 0x3f4a7099, 0x3f34c578, 0x3e967511,
+ 0xbea92a13, 0x3f49f911, 0x3f346fce, 0x3e972064,
+ 0xbea9d676, 0x3f4981a3, 0x3f341a00, 0x3e97cc00,
+ 0xbeaa8322, 0x3f490a51, 0x3f33c40e, 0x3e9877e4,
+ 0xbeab3019, 0x3f489319, 0x3f336df8, 0x3e99240f,
+ 0xbeabdd59, 0x3f481bfd, 0x3f3317bf, 0x3e99d082,
+ 0xbeac8ae3, 0x3f47a4fc, 0x3f32c163, 0x3e9a7d3b,
+ 0xbead38b5, 0x3f472e15, 0x3f326ae3, 0x3e9b2a3a,
+ 0xbeade6d1, 0x3f46b74a, 0x3f321441, 0x3e9bd77e,
+ 0xbeae9536, 0x3f46409a, 0x3f31bd7c, 0x3e9c8507,
+ 0xbeaf43e3, 0x3f45ca05, 0x3f316695, 0x3e9d32d5,
+ 0xbeaff2d9, 0x3f45538b, 0x3f310f8c, 0x3e9de0e7,
+ 0xbeb0a217, 0x3f44dd2c, 0x3f30b862, 0x3e9e8f3d,
+ 0xbeb1519d, 0x3f4466e9, 0x3f306115, 0x3e9f3dd5,
+ 0xbeb2016a, 0x3f43f0c0, 0x3f3009a8, 0x3e9fecb0,
+ 0xbeb2b180, 0x3f437ab3, 0x3f2fb21a, 0x3ea09bcd,
+ 0xbeb361dd, 0x3f4304c1, 0x3f2f5a6a, 0x3ea14b2b,
+ 0xbeb41280, 0x3f428eea, 0x3f2f029b, 0x3ea1facb,
+ 0xbeb4c36b, 0x3f42192e, 0x3f2eaaab, 0x3ea2aaab,
+ 0xbeb5749d, 0x3f41a38e, 0x3f2e529b, 0x3ea35acb,
+ 0xbeb62616, 0x3f412e08, 0x3f2dfa6b, 0x3ea40b2a,
+ 0xbeb6d7d5, 0x3f40b89e, 0x3f2da21c, 0x3ea4bbc8,
+ 0xbeb789da, 0x3f40434f, 0x3f2d49ad, 0x3ea56ca5,
+ 0xbeb83c25, 0x3f3fce1c, 0x3f2cf120, 0x3ea61dc0,
+ 0xbeb8eeb6, 0x3f3f5903, 0x3f2c9874, 0x3ea6cf19,
+ 0xbeb9a18d, 0x3f3ee406, 0x3f2c3fa9, 0x3ea780ae,
+ 0xbeba54a9, 0x3f3e6f24, 0x3f2be6c0, 0x3ea83280,
+ 0xbebb080b, 0x3f3dfa5d, 0x3f2b8db9, 0x3ea8e48e,
+ 0xbebbbbb1, 0x3f3d85b2, 0x3f2b3494, 0x3ea996d7,
+ 0xbebc6f9d, 0x3f3d1122, 0x3f2adb52, 0x3eaa495c,
+ 0xbebd23cd, 0x3f3c9cad, 0x3f2a81f3, 0x3eaafc1b,
+ 0xbebdd842, 0x3f3c2853, 0x3f2a2876, 0x3eabaf14,
+ 0xbebe8cfc, 0x3f3bb415, 0x3f29cedd, 0x3eac6246,
+ 0xbebf41fa, 0x3f3b3ff2, 0x3f297527, 0x3ead15b1,
+ 0xbebff73b, 0x3f3acbea, 0x3f291b55, 0x3eadc955,
+ 0xbec0acc1, 0x3f3a57fd, 0x3f28c167, 0x3eae7d31,
+ 0xbec1628b, 0x3f39e42c, 0x3f28675e, 0x3eaf3145,
+ 0xbec21898, 0x3f397076, 0x3f280d38, 0x3eafe58f,
+ 0xbec2cee8, 0x3f38fcdb, 0x3f27b2f8, 0x3eb09a10,
+ 0xbec3857c, 0x3f38895b, 0x3f27589d, 0x3eb14ec7,
+ 0xbec43c53, 0x3f3815f7, 0x3f26fe26, 0x3eb203b3,
+ 0xbec4f36c, 0x3f37a2ae, 0x3f26a396, 0x3eb2b8d5,
+ 0xbec5aac9, 0x3f372f80, 0x3f2648eb, 0x3eb36e2b,
+ 0xbec66268, 0x3f36bc6d, 0x3f25ee26, 0x3eb423b5,
+ 0xbec71a49, 0x3f364976, 0x3f259347, 0x3eb4d972,
+ 0xbec7d26d, 0x3f35d69a, 0x3f25384f, 0x3eb58f62,
+ 0xbec88ad2, 0x3f3563d9, 0x3f24dd3d, 0x3eb64585,
+ 0xbec9437a, 0x3f34f134, 0x3f248213, 0x3eb6fbda,
+ 0xbec9fc64, 0x3f347ea9, 0x3f2426d0, 0x3eb7b261,
+ 0xbecab58f, 0x3f340c3a, 0x3f23cb74, 0x3eb86918,
+ 0xbecb6efb, 0x3f3399e6, 0x3f237000, 0x3eb92000,
+ 0xbecc28a9, 0x3f3327ae, 0x3f231474, 0x3eb9d718,
+ 0xbecce299, 0x3f32b590, 0x3f22b8d0, 0x3eba8e5f,
+ 0xbecd9cc9, 0x3f32438e, 0x3f225d15, 0x3ebb45d6,
+ 0xbece573a, 0x3f31d1a7, 0x3f220143, 0x3ebbfd7b,
+ 0xbecf11ec, 0x3f315fdc, 0x3f21a559, 0x3ebcb54e,
+ 0xbecfccde, 0x3f30ee2b, 0x3f214959, 0x3ebd6d4e,
+ 0xbed08811, 0x3f307c96, 0x3f20ed42, 0x3ebe257b,
+ 0xbed14384, 0x3f300b1c, 0x3f209115, 0x3ebeddd5,
+ 0xbed1ff38, 0x3f2f99be, 0x3f2034d2, 0x3ebf965b,
+ 0xbed2bb2b, 0x3f2f287a, 0x3f1fd87a, 0x3ec04f0d,
+ 0xbed3775e, 0x3f2eb752, 0x3f1f7c0b, 0x3ec107e9,
+ 0xbed433d1, 0x3f2e4645, 0x3f1f1f88, 0x3ec1c0f0,
+ 0xbed4f084, 0x3f2dd553, 0x3f1ec2f0, 0x3ec27a21,
+ 0xbed5ad76, 0x3f2d647d, 0x3f1e6642, 0x3ec3337b,
+ 0xbed66aa8, 0x3f2cf3c1, 0x3f1e0981, 0x3ec3ecff,
+ 0xbed72818, 0x3f2c8321, 0x3f1dacab, 0x3ec4a6ab,
+ 0xbed7e5c8, 0x3f2c129c, 0x3f1d4fc1, 0x3ec5607f,
+ 0xbed8a3b7, 0x3f2ba232, 0x3f1cf2c3, 0x3ec61a7a,
+ 0xbed961e4, 0x3f2b31e4, 0x3f1c95b2, 0x3ec6d49c,
+ 0xbeda2051, 0x3f2ac1b1, 0x3f1c388d, 0x3ec78ee5,
+ 0xbedadefc, 0x3f2a5199, 0x3f1bdb56, 0x3ec84954,
+ 0xbedb9de5, 0x3f29e19c, 0x3f1b7e0c, 0x3ec903e9,
+ 0xbedc5d0c, 0x3f2971ba, 0x3f1b20af, 0x3ec9bea2,
+ 0xbedd1c72, 0x3f2901f4, 0x3f1ac340, 0x3eca7980,
+ 0xbedddc16, 0x3f289248, 0x3f1a65bf, 0x3ecb3482,
+ 0xbede9bf8, 0x3f2822b8, 0x3f1a082c, 0x3ecbefa7,
+ 0xbedf5c18, 0x3f27b344, 0x3f19aa88, 0x3eccaaf0,
+ 0xbee01c75, 0x3f2743ea, 0x3f194cd3, 0x3ecd665b,
+ 0xbee0dd10, 0x3f26d4ac, 0x3f18ef0c, 0x3ece21e8,
+ 0xbee19de8, 0x3f266589, 0x3f189135, 0x3ecedd96,
+ 0xbee25efe, 0x3f25f681, 0x3f18334d, 0x3ecf9965,
+ 0xbee32051, 0x3f258794, 0x3f17d555, 0x3ed05555,
+ 0xbee3e1e1, 0x3f2518c2, 0x3f17774d, 0x3ed11165,
+ 0xbee4a3ae, 0x3f24aa0c, 0x3f171936, 0x3ed1cd95,
+ 0xbee565b8, 0x3f243b71, 0x3f16bb0e, 0x3ed289e3,
+ 0xbee627ff, 0x3f23ccf1, 0x3f165cd8, 0x3ed34650,
+ 0xbee6ea83, 0x3f235e8d, 0x3f15fe93, 0x3ed402db,
+ 0xbee7ad43, 0x3f22f043, 0x3f15a03e, 0x3ed4bf83,
+ 0xbee8703f, 0x3f228215, 0x3f1541dc, 0x3ed57c49,
+ 0xbee93378, 0x3f221402, 0x3f14e36b, 0x3ed6392b,
+ 0xbee9f6ed, 0x3f21a60b, 0x3f1484ec, 0x3ed6f629,
+ 0xbeeaba9f, 0x3f21382e, 0x3f14265f, 0x3ed7b342,
+ 0xbeeb7e8c, 0x3f20ca6d, 0x3f13c7c5, 0x3ed87076,
+ 0xbeec42b6, 0x3f205cc7, 0x3f13691d, 0x3ed92dc5,
+ 0xbeed071b, 0x3f1fef3c, 0x3f130a69, 0x3ed9eb2e,
+ 0xbeedcbbc, 0x3f1f81cd, 0x3f12aba8, 0x3edaa8b1,
+ 0xbeee9098, 0x3f1f1479, 0x3f124cda, 0x3edb664c,
+ 0xbeef55b1, 0x3f1ea740, 0x3f11ee00, 0x3edc2400,
+ 0xbef01b04, 0x3f1e3a23, 0x3f118f1a, 0x3edce1cc,
+ 0xbef0e093, 0x3f1dcd20, 0x3f113028, 0x3edd9faf,
+ 0xbef1a65d, 0x3f1d6039, 0x3f10d12b, 0x3ede5daa,
+ 0xbef26c63, 0x3f1cf36e, 0x3f107223, 0x3edf1bbb,
+ 0xbef332a3, 0x3f1c86bd, 0x3f10130f, 0x3edfd9e2,
+ 0xbef3f91f, 0x3f1c1a28, 0x3f0fb3f1, 0x3ee0981e,
+ 0xbef4bfd5, 0x3f1badaf, 0x3f0f54c8, 0x3ee1566f,
+ 0xbef586c7, 0x3f1b4150, 0x3f0ef595, 0x3ee214d5,
+ 0xbef64df2, 0x3f1ad50d, 0x3f0e9658, 0x3ee2d34f,
+ 0xbef71559, 0x3f1a68e6, 0x3f0e3712, 0x3ee391dd,
+ 0xbef7dcfa, 0x3f19fcd9, 0x3f0dd7c1, 0x3ee4507d,
+ 0xbef8a4d6, 0x3f1990e8, 0x3f0d7868, 0x3ee50f30,
+ 0xbef96cec, 0x3f192513, 0x3f0d1906, 0x3ee5cdf5,
+ 0xbefa353c, 0x3f18b958, 0x3f0cb99a, 0x3ee68ccb,
+ 0xbefafdc7, 0x3f184dba, 0x3f0c5a27, 0x3ee74bb3,
+ 0xbefbc68b, 0x3f17e236, 0x3f0bfaab, 0x3ee80aab,
+ 0xbefc8f8a, 0x3f1776ce, 0x3f0b9b27, 0x3ee8c9b3,
+ 0xbefd58c3, 0x3f170b82, 0x3f0b3b9b, 0x3ee988ca,
+ 0xbefe2235, 0x3f16a051, 0x3f0adc08, 0x3eea47f0,
+ 0xbefeebe2, 0x3f16353b, 0x3f0a7c6d, 0x3eeb0725,
+ 0xbeffb5c8, 0x3f15ca41, 0x3f0a1ccc, 0x3eebc668,
+ 0xbf003ff4, 0x3f155f62, 0x3f09bd24, 0x3eec85b9,
+ 0xbf00a520, 0x3f14f49f, 0x3f095d75, 0x3eed4516,
+ 0xbf010a6a, 0x3f1489f8, 0x3f08fdc0, 0x3eee0480,
+ 0xbf016fd0, 0x3f141f6c, 0x3f089e05, 0x3eeec3f6,
+ 0xbf01d553, 0x3f13b4fb, 0x3f083e44, 0x3eef8377,
+ 0xbf023af2, 0x3f134aa6, 0x3f07de7e, 0x3ef04304,
+ 0xbf02a0af, 0x3f12e06d, 0x3f077eb3, 0x3ef1029b,
+ 0xbf030687, 0x3f12764f, 0x3f071ee2, 0x3ef1c23c,
+ 0xbf036c7d, 0x3f120c4d, 0x3f06bf0d, 0x3ef281e6,
+ 0xbf03d28e, 0x3f11a266, 0x3f065f33, 0x3ef34199,
+ 0xbf0438bd, 0x3f11389b, 0x3f05ff55, 0x3ef40155,
+ 0xbf049f08, 0x3f10ceec, 0x3f059f73, 0x3ef4c119,
+ 0xbf05056f, 0x3f106558, 0x3f053f8e, 0x3ef580e5,
+ 0xbf056bf2, 0x3f0ffbe0, 0x3f04dfa4, 0x3ef640b7,
+ 0xbf05d292, 0x3f0f9284, 0x3f047fb8, 0x3ef70090,
+ 0xbf06394e, 0x3f0f2943, 0x3f041fc9, 0x3ef7c06f,
+ 0xbf06a027, 0x3f0ec01f, 0x3f03bfd6, 0x3ef88053,
+ 0xbf07071c, 0x3f0e5716, 0x3f035fe2, 0x3ef9403d,
+ 0xbf076e2d, 0x3f0dee29, 0x3f02ffeb, 0x3efa002b,
+ 0xbf07d55a, 0x3f0d8557, 0x3f029ff2, 0x3efac01d,
+ 0xbf083ca4, 0x3f0d1ca2, 0x3f023ff7, 0x3efb8012,
+ 0xbf08a409, 0x3f0cb408, 0x3f01dffb, 0x3efc400a,
+ 0xbf090b8b, 0x3f0c4b8a, 0x3f017ffd, 0x3efd0005,
+ 0xbf097329, 0x3f0be329, 0x3f011fff, 0x3efdc002,
+ 0xbf09dae3, 0x3f0b7ae3, 0x3f00c000, 0x3efe8001,
+ 0xbf0a42b9, 0x3f0b12b9, 0x3f006000, 0x3eff4000,
+ 0xbf0aaaab, 0x3f0aaaab, 0x3f000000, 0x3f000000,
+ 0xbf0b12b9, 0x3f0a42b9, 0x3eff4000, 0x3f006000,
+ 0xbf0b7ae3, 0x3f09dae3, 0x3efe8001, 0x3f00c000,
+ 0xbf0be329, 0x3f097329, 0x3efdc002, 0x3f011fff,
+ 0xbf0c4b8a, 0x3f090b8b, 0x3efd0005, 0x3f017ffd,
+ 0xbf0cb408, 0x3f08a409, 0x3efc400a, 0x3f01dffb,
+ 0xbf0d1ca2, 0x3f083ca4, 0x3efb8012, 0x3f023ff7,
+ 0xbf0d8557, 0x3f07d55a, 0x3efac01d, 0x3f029ff2,
+ 0xbf0dee29, 0x3f076e2d, 0x3efa002b, 0x3f02ffeb,
+ 0xbf0e5716, 0x3f07071c, 0x3ef9403d, 0x3f035fe2,
+ 0xbf0ec01f, 0x3f06a027, 0x3ef88053, 0x3f03bfd6,
+ 0xbf0f2943, 0x3f06394e, 0x3ef7c06f, 0x3f041fc9,
+ 0xbf0f9284, 0x3f05d292, 0x3ef70090, 0x3f047fb8,
+ 0xbf0ffbe0, 0x3f056bf2, 0x3ef640b7, 0x3f04dfa4,
+ 0xbf106558, 0x3f05056f, 0x3ef580e5, 0x3f053f8e,
+ 0xbf10ceec, 0x3f049f08, 0x3ef4c119, 0x3f059f73,
+ 0xbf11389b, 0x3f0438bd, 0x3ef40155, 0x3f05ff55,
+ 0xbf11a266, 0x3f03d28e, 0x3ef34199, 0x3f065f33,
+ 0xbf120c4d, 0x3f036c7d, 0x3ef281e6, 0x3f06bf0d,
+ 0xbf12764f, 0x3f030687, 0x3ef1c23c, 0x3f071ee2,
+ 0xbf12e06d, 0x3f02a0af, 0x3ef1029b, 0x3f077eb3,
+ 0xbf134aa6, 0x3f023af2, 0x3ef04304, 0x3f07de7e,
+ 0xbf13b4fb, 0x3f01d553, 0x3eef8377, 0x3f083e44,
+ 0xbf141f6c, 0x3f016fd0, 0x3eeec3f6, 0x3f089e05,
+ 0xbf1489f8, 0x3f010a6a, 0x3eee0480, 0x3f08fdc0,
+ 0xbf14f49f, 0x3f00a520, 0x3eed4516, 0x3f095d75,
+ 0xbf155f62, 0x3f003ff4, 0x3eec85b9, 0x3f09bd24,
+ 0xbf15ca41, 0x3effb5c8, 0x3eebc668, 0x3f0a1ccc,
+ 0xbf16353b, 0x3efeebe2, 0x3eeb0725, 0x3f0a7c6d,
+ 0xbf16a051, 0x3efe2235, 0x3eea47f0, 0x3f0adc08,
+ 0xbf170b82, 0x3efd58c3, 0x3ee988ca, 0x3f0b3b9b,
+ 0xbf1776ce, 0x3efc8f8a, 0x3ee8c9b3, 0x3f0b9b27,
+ 0xbf17e236, 0x3efbc68b, 0x3ee80aab, 0x3f0bfaab,
+ 0xbf184dba, 0x3efafdc7, 0x3ee74bb3, 0x3f0c5a27,
+ 0xbf18b958, 0x3efa353c, 0x3ee68ccb, 0x3f0cb99a,
+ 0xbf192513, 0x3ef96cec, 0x3ee5cdf5, 0x3f0d1906,
+ 0xbf1990e8, 0x3ef8a4d6, 0x3ee50f30, 0x3f0d7868,
+ 0xbf19fcd9, 0x3ef7dcfa, 0x3ee4507d, 0x3f0dd7c1,
+ 0xbf1a68e6, 0x3ef71559, 0x3ee391dd, 0x3f0e3712,
+ 0xbf1ad50d, 0x3ef64df2, 0x3ee2d34f, 0x3f0e9658,
+ 0xbf1b4150, 0x3ef586c7, 0x3ee214d5, 0x3f0ef595,
+ 0xbf1badaf, 0x3ef4bfd5, 0x3ee1566f, 0x3f0f54c8,
+ 0xbf1c1a28, 0x3ef3f91f, 0x3ee0981e, 0x3f0fb3f1,
+ 0xbf1c86bd, 0x3ef332a3, 0x3edfd9e2, 0x3f10130f,
+ 0xbf1cf36e, 0x3ef26c63, 0x3edf1bbb, 0x3f107223,
+ 0xbf1d6039, 0x3ef1a65d, 0x3ede5daa, 0x3f10d12b,
+ 0xbf1dcd20, 0x3ef0e093, 0x3edd9faf, 0x3f113028,
+ 0xbf1e3a23, 0x3ef01b04, 0x3edce1cc, 0x3f118f1a,
+ 0xbf1ea740, 0x3eef55b1, 0x3edc2400, 0x3f11ee00,
+ 0xbf1f1479, 0x3eee9098, 0x3edb664c, 0x3f124cda,
+ 0xbf1f81cd, 0x3eedcbbc, 0x3edaa8b1, 0x3f12aba8,
+ 0xbf1fef3c, 0x3eed071b, 0x3ed9eb2e, 0x3f130a69,
+ 0xbf205cc7, 0x3eec42b6, 0x3ed92dc5, 0x3f13691d,
+ 0xbf20ca6d, 0x3eeb7e8c, 0x3ed87076, 0x3f13c7c5,
+ 0xbf21382e, 0x3eeaba9f, 0x3ed7b342, 0x3f14265f,
+ 0xbf21a60b, 0x3ee9f6ed, 0x3ed6f629, 0x3f1484ec,
+ 0xbf221402, 0x3ee93378, 0x3ed6392b, 0x3f14e36b,
+ 0xbf228215, 0x3ee8703f, 0x3ed57c49, 0x3f1541dc,
+ 0xbf22f043, 0x3ee7ad43, 0x3ed4bf83, 0x3f15a03e,
+ 0xbf235e8d, 0x3ee6ea83, 0x3ed402db, 0x3f15fe93,
+ 0xbf23ccf1, 0x3ee627ff, 0x3ed34650, 0x3f165cd8,
+ 0xbf243b71, 0x3ee565b8, 0x3ed289e3, 0x3f16bb0e,
+ 0xbf24aa0c, 0x3ee4a3ae, 0x3ed1cd95, 0x3f171936,
+ 0xbf2518c2, 0x3ee3e1e1, 0x3ed11165, 0x3f17774d,
+ 0xbf258794, 0x3ee32051, 0x3ed05555, 0x3f17d555,
+ 0xbf25f681, 0x3ee25efe, 0x3ecf9965, 0x3f18334d,
+ 0xbf266589, 0x3ee19de8, 0x3ecedd96, 0x3f189135,
+ 0xbf26d4ac, 0x3ee0dd10, 0x3ece21e8, 0x3f18ef0c,
+ 0xbf2743ea, 0x3ee01c75, 0x3ecd665b, 0x3f194cd3,
+ 0xbf27b344, 0x3edf5c18, 0x3eccaaf0, 0x3f19aa88,
+ 0xbf2822b8, 0x3ede9bf8, 0x3ecbefa7, 0x3f1a082c,
+ 0xbf289248, 0x3edddc16, 0x3ecb3482, 0x3f1a65bf,
+ 0xbf2901f4, 0x3edd1c72, 0x3eca7980, 0x3f1ac340,
+ 0xbf2971ba, 0x3edc5d0c, 0x3ec9bea2, 0x3f1b20af,
+ 0xbf29e19c, 0x3edb9de5, 0x3ec903e9, 0x3f1b7e0c,
+ 0xbf2a5199, 0x3edadefc, 0x3ec84954, 0x3f1bdb56,
+ 0xbf2ac1b1, 0x3eda2051, 0x3ec78ee5, 0x3f1c388d,
+ 0xbf2b31e4, 0x3ed961e4, 0x3ec6d49c, 0x3f1c95b2,
+ 0xbf2ba232, 0x3ed8a3b7, 0x3ec61a7a, 0x3f1cf2c3,
+ 0xbf2c129c, 0x3ed7e5c8, 0x3ec5607f, 0x3f1d4fc1,
+ 0xbf2c8321, 0x3ed72818, 0x3ec4a6ab, 0x3f1dacab,
+ 0xbf2cf3c1, 0x3ed66aa8, 0x3ec3ecff, 0x3f1e0981,
+ 0xbf2d647d, 0x3ed5ad76, 0x3ec3337b, 0x3f1e6642,
+ 0xbf2dd553, 0x3ed4f084, 0x3ec27a21, 0x3f1ec2f0,
+ 0xbf2e4645, 0x3ed433d1, 0x3ec1c0f0, 0x3f1f1f88,
+ 0xbf2eb752, 0x3ed3775e, 0x3ec107e9, 0x3f1f7c0b,
+ 0xbf2f287a, 0x3ed2bb2b, 0x3ec04f0d, 0x3f1fd87a,
+ 0xbf2f99be, 0x3ed1ff38, 0x3ebf965b, 0x3f2034d2,
+ 0xbf300b1c, 0x3ed14384, 0x3ebeddd5, 0x3f209115,
+ 0xbf307c96, 0x3ed08811, 0x3ebe257b, 0x3f20ed42,
+ 0xbf30ee2b, 0x3ecfccde, 0x3ebd6d4e, 0x3f214959,
+ 0xbf315fdc, 0x3ecf11ec, 0x3ebcb54e, 0x3f21a559,
+ 0xbf31d1a7, 0x3ece573a, 0x3ebbfd7b, 0x3f220143,
+ 0xbf32438e, 0x3ecd9cc9, 0x3ebb45d6, 0x3f225d15,
+ 0xbf32b590, 0x3ecce299, 0x3eba8e5f, 0x3f22b8d0,
+ 0xbf3327ae, 0x3ecc28a9, 0x3eb9d718, 0x3f231474,
+ 0xbf3399e6, 0x3ecb6efb, 0x3eb92000, 0x3f237000,
+ 0xbf340c3a, 0x3ecab58f, 0x3eb86918, 0x3f23cb74,
+ 0xbf347ea9, 0x3ec9fc64, 0x3eb7b261, 0x3f2426d0,
+ 0xbf34f134, 0x3ec9437a, 0x3eb6fbda, 0x3f248213,
+ 0xbf3563d9, 0x3ec88ad2, 0x3eb64585, 0x3f24dd3d,
+ 0xbf35d69a, 0x3ec7d26d, 0x3eb58f62, 0x3f25384f,
+ 0xbf364976, 0x3ec71a49, 0x3eb4d972, 0x3f259347,
+ 0xbf36bc6d, 0x3ec66268, 0x3eb423b5, 0x3f25ee26,
+ 0xbf372f80, 0x3ec5aac9, 0x3eb36e2b, 0x3f2648eb,
+ 0xbf37a2ae, 0x3ec4f36c, 0x3eb2b8d5, 0x3f26a396,
+ 0xbf3815f7, 0x3ec43c53, 0x3eb203b3, 0x3f26fe26,
+ 0xbf38895b, 0x3ec3857c, 0x3eb14ec7, 0x3f27589d,
+ 0xbf38fcdb, 0x3ec2cee8, 0x3eb09a10, 0x3f27b2f8,
+ 0xbf397076, 0x3ec21898, 0x3eafe58f, 0x3f280d38,
+ 0xbf39e42c, 0x3ec1628b, 0x3eaf3145, 0x3f28675e,
+ 0xbf3a57fd, 0x3ec0acc1, 0x3eae7d31, 0x3f28c167,
+ 0xbf3acbea, 0x3ebff73b, 0x3eadc955, 0x3f291b55,
+ 0xbf3b3ff2, 0x3ebf41fa, 0x3ead15b1, 0x3f297527,
+ 0xbf3bb415, 0x3ebe8cfc, 0x3eac6246, 0x3f29cedd,
+ 0xbf3c2853, 0x3ebdd842, 0x3eabaf14, 0x3f2a2876,
+ 0xbf3c9cad, 0x3ebd23cd, 0x3eaafc1b, 0x3f2a81f3,
+ 0xbf3d1122, 0x3ebc6f9d, 0x3eaa495c, 0x3f2adb52,
+ 0xbf3d85b2, 0x3ebbbbb1, 0x3ea996d7, 0x3f2b3494,
+ 0xbf3dfa5d, 0x3ebb080b, 0x3ea8e48e, 0x3f2b8db9,
+ 0xbf3e6f24, 0x3eba54a9, 0x3ea83280, 0x3f2be6c0,
+ 0xbf3ee406, 0x3eb9a18d, 0x3ea780ae, 0x3f2c3fa9,
+ 0xbf3f5903, 0x3eb8eeb6, 0x3ea6cf19, 0x3f2c9874,
+ 0xbf3fce1c, 0x3eb83c25, 0x3ea61dc0, 0x3f2cf120,
+ 0xbf40434f, 0x3eb789da, 0x3ea56ca5, 0x3f2d49ad,
+ 0xbf40b89e, 0x3eb6d7d5, 0x3ea4bbc8, 0x3f2da21c,
+ 0xbf412e08, 0x3eb62616, 0x3ea40b2a, 0x3f2dfa6b,
+ 0xbf41a38e, 0x3eb5749d, 0x3ea35acb, 0x3f2e529b,
+ 0xbf42192e, 0x3eb4c36b, 0x3ea2aaab, 0x3f2eaaab,
+ 0xbf428eea, 0x3eb41280, 0x3ea1facb, 0x3f2f029b,
+ 0xbf4304c1, 0x3eb361dd, 0x3ea14b2b, 0x3f2f5a6a,
+ 0xbf437ab3, 0x3eb2b180, 0x3ea09bcd, 0x3f2fb21a,
+ 0xbf43f0c0, 0x3eb2016a, 0x3e9fecb0, 0x3f3009a8,
+ 0xbf4466e9, 0x3eb1519d, 0x3e9f3dd5, 0x3f306115,
+ 0xbf44dd2c, 0x3eb0a217, 0x3e9e8f3d, 0x3f30b862,
+ 0xbf45538b, 0x3eaff2d9, 0x3e9de0e7, 0x3f310f8c,
+ 0xbf45ca05, 0x3eaf43e3, 0x3e9d32d5, 0x3f316695,
+ 0xbf46409a, 0x3eae9536, 0x3e9c8507, 0x3f31bd7c,
+ 0xbf46b74a, 0x3eade6d1, 0x3e9bd77e, 0x3f321441,
+ 0xbf472e15, 0x3ead38b5, 0x3e9b2a3a, 0x3f326ae3,
+ 0xbf47a4fc, 0x3eac8ae3, 0x3e9a7d3b, 0x3f32c163,
+ 0xbf481bfd, 0x3eabdd59, 0x3e99d082, 0x3f3317bf,
+ 0xbf489319, 0x3eab3019, 0x3e99240f, 0x3f336df8,
+ 0xbf490a51, 0x3eaa8322, 0x3e9877e4, 0x3f33c40e,
+ 0xbf4981a3, 0x3ea9d676, 0x3e97cc00, 0x3f341a00,
+ 0xbf49f911, 0x3ea92a13, 0x3e972064, 0x3f346fce,
+ 0xbf4a7099, 0x3ea87dfb, 0x3e967511, 0x3f34c578,
+ 0xbf4ae83d, 0x3ea7d22e, 0x3e95ca06, 0x3f351afd,
+ 0xbf4b5ffb, 0x3ea726ab, 0x3e951f45, 0x3f35705d,
+ 0xbf4bd7d4, 0x3ea67b73, 0x3e9474ce, 0x3f35c599,
+ 0xbf4c4fc8, 0x3ea5d086, 0x3e93caa2, 0x3f361aaf,
+ 0xbf4cc7d7, 0x3ea525e5, 0x3e9320c1, 0x3f366fa0,
+ 0xbf4d4001, 0x3ea47b90, 0x3e92772b, 0x3f36c46b,
+ 0xbf4db845, 0x3ea3d186, 0x3e91cde1, 0x3f371910,
+ 0xbf4e30a4, 0x3ea327c9, 0x3e9124e3, 0x3f376d8e,
+ 0xbf4ea91e, 0x3ea27e57, 0x3e907c33, 0x3f37c1e7,
+ 0xbf4f21b3, 0x3ea1d533, 0x3e8fd3d0, 0x3f381618,
+ 0xbf4f9a62, 0x3ea12c5b, 0x3e8f2bbb, 0x3f386a22,
+ 0xbf50132c, 0x3ea083d0, 0x3e8e83f5, 0x3f38be06,
+ 0xbf508c11, 0x3e9fdb93, 0x3e8ddc7d, 0x3f3911c1,
+ 0xbf510510, 0x3e9f33a3, 0x3e8d3555, 0x3f396555,
+ 0xbf517e29, 0x3e9e8c01, 0x3e8c8e7d, 0x3f39b8c1,
+ 0xbf51f75d, 0x3e9de4ad, 0x3e8be7f6, 0x3f3a0c05,
+ 0xbf5270ab, 0x3e9d3da7, 0x3e8b41c0, 0x3f3a5f20,
+ 0xbf52ea14, 0x3e9c96f0, 0x3e8a9bdb, 0x3f3ab213,
+ 0xbf536397, 0x3e9bf087, 0x3e89f648, 0x3f3b04dc,
+ 0xbf53dd34, 0x3e9b4a6e, 0x3e895107, 0x3f3b577c,
+ 0xbf5456ec, 0x3e9aa4a4, 0x3e88ac1a, 0x3f3ba9f3,
+ 0xbf54d0bd, 0x3e99ff29, 0x3e880780, 0x3f3bfc40,
+ 0xbf554aa9, 0x3e9959fe, 0x3e87633a, 0x3f3c4e63,
+ 0xbf55c4af, 0x3e98b523, 0x3e86bf49, 0x3f3ca05c,
+ 0xbf563ece, 0x3e981099, 0x3e861bac, 0x3f3cf22a,
+ 0xbf56b908, 0x3e976c5f, 0x3e857865, 0x3f3d43cd,
+ 0xbf57335b, 0x3e96c875, 0x3e84d574, 0x3f3d9546,
+ 0xbf57adc8, 0x3e9624dd, 0x3e8432da, 0x3f3de693,
+ 0xbf58284f, 0x3e958197, 0x3e839097, 0x3f3e37b5,
+ 0xbf58a2ef, 0x3e94dea1, 0x3e82eeab, 0x3f3e88ab,
+ 0xbf591da9, 0x3e943bfe, 0x3e824d17, 0x3f3ed975,
+ 0xbf59987c, 0x3e9399ad, 0x3e81abdb, 0x3f3f2a12,
+ 0xbf5a1369, 0x3e92f7ae, 0x3e810af9, 0x3f3f7a84,
+ 0xbf5a8e6f, 0x3e925602, 0x3e806a70, 0x3f3fcac8,
+ 0xbf5b098e, 0x3e91b4aa, 0x3e7f9482, 0x3f401adf,
+ 0xbf5b84c6, 0x3e9113a4, 0x3e7e54d9, 0x3f406aca,
+ 0xbf5c0017, 0x3e9072f2, 0x3e7d15e6, 0x3f40ba86,
+ 0xbf5c7b81, 0x3e8fd293, 0x3e7bd7ab, 0x3f410a15,
+ 0xbf5cf704, 0x3e8f3289, 0x3e7a9a27, 0x3f415976,
+ 0xbf5d72a0, 0x3e8e92d3, 0x3e795d5c, 0x3f41a8a9,
+ 0xbf5dee54, 0x3e8df372, 0x3e78214b, 0x3f41f7ad,
+ 0xbf5e6a21, 0x3e8d5466, 0x3e76e5f5, 0x3f424683,
+ 0xbf5ee606, 0x3e8cb5af, 0x3e75ab5c, 0x3f429529,
+ 0xbf5f6203, 0x3e8c174e, 0x3e74717f, 0x3f42e3a0,
+ 0xbf5fde18, 0x3e8b7943, 0x3e733860, 0x3f4331e8,
+ 0xbf605a45, 0x3e8adb8e, 0x3e720000, 0x3f438000,
+ 0xbf60d68a, 0x3e8a3e2f, 0x3e70c860, 0x3f43cde8,
+ 0xbf6152e7, 0x3e89a127, 0x3e6f9181, 0x3f441ba0,
+ 0xbf61cf5b, 0x3e890476, 0x3e6e5b64, 0x3f446927,
+ 0xbf624be7, 0x3e88681d, 0x3e6d260b, 0x3f44b67d,
+ 0xbf62c88a, 0x3e87cc1b, 0x3e6bf175, 0x3f4503a3,
+ 0xbf634544, 0x3e873071, 0x3e6abda4, 0x3f455097,
+ 0xbf63c215, 0x3e869520, 0x3e698a99, 0x3f459d5a,
+ 0xbf643efd, 0x3e85fa27, 0x3e685855, 0x3f45e9eb,
+ 0xbf64bbfb, 0x3e855f87, 0x3e6726da, 0x3f46364a,
+ 0xbf653910, 0x3e84c540, 0x3e65f627, 0x3f468276,
+ 0xbf65b63b, 0x3e842b53, 0x3e64c63e, 0x3f46ce71,
+ 0xbf66337c, 0x3e8391c0, 0x3e639720, 0x3f471a38,
+ 0xbf66b0d3, 0x3e82f887, 0x3e6268ce, 0x3f4765cc,
+ 0xbf672e40, 0x3e825fa9, 0x3e613b49, 0x3f47b12e,
+ 0xbf67abc2, 0x3e81c726, 0x3e600e92, 0x3f47fc5b,
+ 0xbf682959, 0x3e812efe, 0x3e5ee2ab, 0x3f484755,
+ 0xbf68a706, 0x3e809731, 0x3e5db793, 0x3f48921b,
+ 0xbf6924c7, 0x3e7fff81, 0x3e5c8d4c, 0x3f48dcad,
+ 0xbf69a29d, 0x3e7ed158, 0x3e5b63d7, 0x3f49270a,
+ 0xbf6a2087, 0x3e7da3e9, 0x3e5a3b35, 0x3f497133,
+ 0xbf6a9e86, 0x3e7c7733, 0x3e591368, 0x3f49bb26,
+ 0xbf6b1c98, 0x3e7b4b38, 0x3e57ec6f, 0x3f4a04e4,
+ 0xbf6b9abe, 0x3e7a1ff8, 0x3e56c64c, 0x3f4a4e6d,
+ 0xbf6c18f7, 0x3e78f574, 0x3e55a100, 0x3f4a97c0,
+ 0xbf6c9744, 0x3e77cbad, 0x3e547c8c, 0x3f4ae0dd,
+ 0xbf6d15a3, 0x3e76a2a3, 0x3e5358f1, 0x3f4b29c4,
+ 0xbf6d9415, 0x3e757a58, 0x3e523630, 0x3f4b7274,
+ 0xbf6e1299, 0x3e7452cb, 0x3e51144b, 0x3f4bbaed,
+ 0xbf6e912e, 0x3e732bfd, 0x3e4ff341, 0x3f4c0330,
+ 0xbf6f0fd6, 0x3e7205f0, 0x3e4ed314, 0x3f4c4b3b,
+ 0xbf6f8e8f, 0x3e70e0a4, 0x3e4db3c5, 0x3f4c930f,
+ 0xbf700d59, 0x3e6fbc1a, 0x3e4c9555, 0x3f4cdaab,
+ 0xbf708c34, 0x3e6e9852, 0x3e4b77c6, 0x3f4d220f,
+ 0xbf710b1e, 0x3e6d754e, 0x3e4a5b17, 0x3f4d693a,
+ 0xbf718a19, 0x3e6c530d, 0x3e493f4a, 0x3f4db02e,
+ 0xbf720924, 0x3e6b3191, 0x3e482460, 0x3f4df6e8,
+ 0xbf72883e, 0x3e6a10db, 0x3e470a5a, 0x3f4e3d69,
+ 0xbf730766, 0x3e68f0eb, 0x3e45f139, 0x3f4e83b2,
+ 0xbf73869d, 0x3e67d1c2, 0x3e44d8fe, 0x3f4ec9c0,
+ 0xbf7405e3, 0x3e66b361, 0x3e43c1ab, 0x3f4f0f95,
+ 0xbf748535, 0x3e6595c9, 0x3e42ab3f, 0x3f4f5530,
+ 0xbf750495, 0x3e6478fa, 0x3e4195bc, 0x3f4f9a91,
+ 0xbf758402, 0x3e635cf5, 0x3e408123, 0x3f4fdfb7,
+ 0xbf76037c, 0x3e6241bc, 0x3e3f6d75, 0x3f5024a3,
+ 0xbf768301, 0x3e61274e, 0x3e3e5ab4, 0x3f506953,
+ 0xbf770291, 0x3e600dad, 0x3e3d48df, 0x3f50adc8,
+ 0xbf77822d, 0x3e5ef4d9, 0x3e3c37f8, 0x3f50f202,
+ 0xbf7801d3, 0x3e5ddcd4, 0x3e3b2800, 0x3f513600,
+ 0xbf788183, 0x3e5cc59d, 0x3e3a18f8, 0x3f5179c2,
+ 0xbf79013c, 0x3e5baf37, 0x3e390ae1, 0x3f51bd48,
+ 0xbf7980ff, 0x3e5a99a2, 0x3e37fdbc, 0x3f520091,
+ 0xbf7a00ca, 0x3e5984de, 0x3e36f18b, 0x3f52439d,
+ 0xbf7a809c, 0x3e5870ed, 0x3e35e64d, 0x3f52866d,
+ 0xbf7b0076, 0x3e575dcf, 0x3e34dc04, 0x3f52c8ff,
+ 0xbf7b8056, 0x3e564b85, 0x3e33d2b1, 0x3f530b54,
+ 0xbf7c003d, 0x3e553a10, 0x3e32ca55, 0x3f534d6b,
+ 0xbf7c8029, 0x3e542972, 0x3e31c2f2, 0x3f538f44,
+ 0xbf7d001a, 0x3e5319aa, 0x3e30bc87, 0x3f53d0de,
+ 0xbf7d800f, 0x3e520aba, 0x3e2fb716, 0x3f54123b,
+ 0xbf7e0008, 0x3e50fca2, 0x3e2eb2a0, 0x3f545358,
+ 0xbf7e8003, 0x3e4fef64, 0x3e2daf26, 0x3f549436,
+ 0xbf7f0001, 0x3e4ee301, 0x3e2caca9, 0x3f54d4d6,
+ 0xbf7f8000, 0x3e4dd779, 0x3e2bab2a, 0x3f551535,
0 };
diff --git a/src/bicubic_table.py b/src/bicubic_table.py
index 69cd402..3657cbc 100755
--- a/src/bicubic_table.py
+++ b/src/bicubic_table.py
@@ -1,5 +1,7 @@
#!/usr/bin/python
+import struct
+
def texgen(pix):
tex = []
@@ -24,14 +26,14 @@ def texgen(pix):
def printrow(l, offset):
- seq = [ str(i) for i in l[offset:offset+4] ]
+ seq = [ hex(struct.unpack('<I',struct.pack('f',i))[0]) for i in l[offset:offset+4] ]
return "\t" + ", ".join(seq) + ","
def maketable(pix):
l = texgen(pix)
- print "static const float bicubic_tex_" + str(pix) + "[] = {"
+ print "static const uint32_t bicubic_tex_" + str(pix) + "[] = {"
for i in range(0, pix, 4):
@@ -40,4 +42,4 @@ def maketable(pix):
print "\t0 };\n"
maketable(512)
-maketable(2048)
\ No newline at end of file
+maketable(2048)
commit 3b46162d8a90be3524cb513d42b9ad3d0bea45f5
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Fri Aug 1 15:24:01 2008 +0200
Move some ALU instructions after the TEX instructions, so we can do something usefull while we are waiting for the texture values.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index d436c03..88b4f2a 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -514,42 +514,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0));
- /* MAD temp4, const1, temp1.yyyy, temp2 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(5) |
- R500_RGB_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(5) |
- R500_ALPHA_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_0 |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_0 |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_G |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(1) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_G |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(1) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
-
/* MAD temp2, const1, temp1.xxxx, temp2 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
@@ -572,13 +536,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_G |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -603,42 +567,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_R |
- R500_ALU_RGBA_A_SWIZ_G));
-
- /* ADD temp4, temp4, input0 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(1) |
- R500_RGB_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(1) |
- R500_ALPHA_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
- R500_ALU_RGB_G_SWIZ_A_1 |
- R500_ALU_RGB_B_SWIZ_A_1 |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_1 |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -655,7 +589,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
R500_TEX_SRC_S_SWIZ_B |
R500_TEX_SRC_T_SWIZ_A |
R500_TEX_SRC_R_SWIZ_R |
@@ -669,7 +603,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp5, temp5, tex0, 1D */
+ /* TEX temp2, temp2, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -680,9 +614,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
- R500_TEX_SRC_S_SWIZ_B |
- R500_TEX_SRC_T_SWIZ_A |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_B |
R500_TEX_SRC_Q_SWIZ_A |
R500_TEX_DST_ADDR(3) |
@@ -694,7 +628,73 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp2, temp2, tex0, 1D */
+ /* MAD temp4, const1, temp1.yyyy, temp2 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(5) |
+ R500_RGB_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(5) |
+ R500_ALPHA_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_0 |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_0 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_G |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_G));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
+ R500_ALPHA_SWIZ_A_G |
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_G));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* ADD temp4, temp4, input0 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
+ R500_RGB_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
+ R500_ALPHA_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_R |
+ R500_ALU_RGBA_A_SWIZ_G));
+
+ /* TEX temp5, temp5, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -704,9 +704,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(4) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_B |
+ R500_TEX_SRC_T_SWIZ_A |
R500_TEX_SRC_R_SWIZ_B |
R500_TEX_SRC_Q_SWIZ_A |
R500_TEX_DST_ADDR(4) |
@@ -754,11 +754,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(1) |
- R500_RGB_ADDR2(5)));
+ R500_RGB_ADDR2(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(1) |
- R500_ALPHA_ADDR1(5)));
+ R500_ALPHA_ADDR1(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
@@ -767,13 +767,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -793,11 +793,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(4) |
- R500_RGB_ADDR2(5)));
+ R500_RGB_ADDR2(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(4) |
- R500_ALPHA_ADDR1(5)));
+ R500_ALPHA_ADDR2(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
@@ -820,7 +820,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
-
/* LRP output, temp0.zzzz, temp3, temp2 ->
* - PRESUB temps, temp3 - temp2
* - MAD temp0.zzzz, temps, temp2 */
@@ -837,12 +836,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_OMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
- R500_RGB_ADDR1(1) |
- R500_RGB_ADDR2(2)));
+ R500_RGB_ADDR1(3) |
+ R500_RGB_ADDR2(5)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
- R500_ALPHA_ADDR1(1) |
- R500_ALPHA_ADDR1(2)));
+ R500_ALPHA_ADDR1(3) |
+ R500_ALPHA_ADDR2(5)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
commit 2ecdec4bafc97212dde4d6908ee4ccf618adc0e1
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Fri Aug 1 04:03:12 2008 +0200
Another uneeded SEM_AQUIRE.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index fea3cf4..d436c03 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -654,7 +654,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(4) |
R500_TEX_SRC_S_SWIZ_B |
commit e93b5d1b80d6203f63543b7b678e2f1d9221b5b3
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Fri Aug 1 03:00:26 2008 +0200
Smarter usage of the texture semaphore.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index d9de5d0..fea3cf4 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -436,13 +436,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* TEX temp0, input1.xxxx, tex1, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
R500_TEX_SRC_S_SWIZ_R |
@@ -473,7 +471,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_G |
R500_TEX_SRC_Q_SWIZ_G |
- R500_TEX_DST_ADDR(1) |
+ R500_TEX_DST_ADDR(5) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
@@ -524,11 +522,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(1) |
+ R500_RGB_ADDR1(5) |
R500_RGB_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(1) |
+ R500_ALPHA_ADDR1(5) |
R500_ALPHA_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_0 |
@@ -538,13 +536,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(1) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_G |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(1) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -560,11 +558,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(1) |
+ R500_RGB_ADDR1(5) |
R500_RGB_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(1) |
+ R500_ALPHA_ADDR1(5) |
R500_ALPHA_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_0 |
@@ -624,9 +622,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(5) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(5) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR2(0)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
R500_ALU_RGB_G_SWIZ_A_1 |
@@ -650,7 +648,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* TEX temp3, temp3, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
@@ -664,7 +661,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_SRC_T_SWIZ_A |
R500_TEX_SRC_R_SWIZ_R |
R500_TEX_SRC_Q_SWIZ_G |
- R500_TEX_DST_ADDR(5) |
+ R500_TEX_DST_ADDR(1) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
@@ -673,7 +670,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp2, temp2, tex0, 1D */
+ /* TEX temp5, temp5, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -684,12 +681,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(4) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_B |
+ R500_TEX_SRC_T_SWIZ_A |
R500_TEX_SRC_R_SWIZ_B |
R500_TEX_SRC_Q_SWIZ_A |
- R500_TEX_DST_ADDR(4) |
+ R500_TEX_DST_ADDR(3) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
@@ -698,7 +695,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp5, temp5, tex0, 1D */
+ /* TEX temp2, temp2, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -707,14 +704,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
- R500_TEX_SRC_S_SWIZ_B |
- R500_TEX_SRC_T_SWIZ_A |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(4) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_B |
R500_TEX_SRC_Q_SWIZ_A |
- R500_TEX_DST_ADDR(3) |
+ R500_TEX_DST_ADDR(4) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
@@ -752,19 +748,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
* - PRESUB temps, temp3 - temp5
* - MAD temp1.zzzz, temps, temp5 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
- R500_RGB_ADDR1(5) |
- R500_RGB_ADDR2(1)));
+ R500_RGB_ADDR1(1) |
+ R500_RGB_ADDR2(5)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
- R500_ALPHA_ADDR1(5) |
- R500_ALPHA_ADDR1(1)));
+ R500_ALPHA_ADDR1(1) |
+ R500_ALPHA_ADDR1(5)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
@@ -773,13 +768,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(1) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(1) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -799,11 +794,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(4) |
- R500_RGB_ADDR2(1)));
+ R500_RGB_ADDR2(5)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(4) |
- R500_ALPHA_ADDR1(1)));
+ R500_ALPHA_ADDR1(5)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
@@ -843,11 +838,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_OMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
- R500_RGB_ADDR1(5) |
+ R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
- R500_ALPHA_ADDR1(5) |
+ R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR1(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
commit 286f7aa18f19bd21b263701adab38b736dbeda0f
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Thu Jul 31 17:01:44 2008 -0700
Enable bicubic filtering for all r5xx HW.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index aee081f..cc13933 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -389,9 +389,9 @@ RADEONSetTexPortAttribute(ScrnInfoPtr pScrn,
RADEON_SYNC(info, pScrn);
if (attribute == xvBicubic)
- /* -1 -> set default (disable for RV515 and punier) */
+ /* -1 -> set default */
pPriv->bicubic_enabled = (value == -1) ?
- (info->ChipFamily == CHIP_FAMILY_R580) : value;
+ (info->ChipFamily >= CHIP_FAMILY_RV515) : value;
else
return BadMatch;
@@ -454,7 +454,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
pPriv->videoStatus = 0;
pPriv->currentBuffer = 0;
pPriv->doubleBuffer = 0;
- pPriv->bicubic_enabled = (info->ChipFamily == CHIP_FAMILY_R580);
+ pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_RV515);
/* gotta uninit this someplace, XXX: shouldn't be necessary for textured */
REGION_NULL(pScreen, &pPriv->clip);
commit 242aa4f630b4c60aefa3c12dc459a4d4d0b334a0
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Fri Aug 1 01:11:28 2008 +0200
Remove one constant.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 59f569d..d9de5d0 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -427,7 +427,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
FINISH_VIDEO();
- BEGIN_VIDEO(93);
+ BEGIN_VIDEO(89);
/* Pixel shader.
* I've gone ahead and annotated each instruction, since this
* thing is MASSIVE. :3
@@ -497,7 +497,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALPHA_ADDR1(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_G_SWIZ_A_0 |
R500_ALU_RGB_B_SWIZ_A_R |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_G |
@@ -506,7 +506,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_G |
+ R500_ALPHA_SWIZ_A_0 |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
@@ -522,18 +522,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_R_SWIZ_A_0 |
R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_R |
+ R500_ALU_RGB_B_SWIZ_A_0 |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_G |
@@ -558,18 +558,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_R_SWIZ_A_0 |
R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_R |
+ R500_ALU_RGB_B_SWIZ_A_0 |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_R |
@@ -876,11 +876,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* const0 = {1 / texture[0].width, 0, 0, 0} */
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w));
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
- /* const0 = {1 / texture[0].height, 0, 0, 0} */
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->h));
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
commit 413eacb0538977b0b3c92df074d40510f4539abc
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Fri Aug 1 00:52:09 2008 +0200
Heavy optimizations.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 14fc5ab..59f569d 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -414,20 +414,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
/* Pixel stack frame size. */
- OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(12));
+ OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(5));
/* FP length. */
OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(19)));
+ R500_US_CODE_END_ADDR(13)));
OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(19)));
+ R500_US_CODE_RANGE_SIZE(13)));
/* Prepare for FP emission. */
OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
FINISH_VIDEO();
- BEGIN_VIDEO(123);
+ BEGIN_VIDEO(93);
/* Pixel shader.
* I've gone ahead and annotated each instruction, since this
* thing is MASSIVE. :3
@@ -439,8 +439,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_RGB_WMASK_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
@@ -464,8 +463,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_RGB_WMASK_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
@@ -475,7 +473,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_G |
R500_TEX_SRC_Q_SWIZ_G |
- R500_TEX_DST_ADDR(3) |
+ R500_TEX_DST_ADDR(1) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
@@ -500,51 +498,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_R |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 |
- R500_ALU_RGBA_G_SWIZ_0 |
- R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));
-
- /* MUL temp3, const0, temp0.xxxx */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(2)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(2)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_A_G |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
@@ -559,63 +524,27 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(3) |
+ R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(3) |
+ R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_G |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
-
- /* MAD temp5, const1, temp1.yyyy, temp3 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
- R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(3) |
- R500_RGB_ADDR2(5)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
- R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(3) |
- R500_ALPHA_ADDR2(5)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_R |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_A_G |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_G));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -631,16 +560,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(3) |
+ R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(3) |
+ R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_R |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_R |
@@ -648,7 +577,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_A_G |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
@@ -659,42 +588,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* MAD temp3, const1, temp1.xxxx, temp3 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
- R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(3) |
- R500_RGB_ADDR2(5)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
- R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(3) |
- R500_ALPHA_ADDR2(5)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_R |
- R500_ALU_RGB_B_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
- R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
-
/* ADD temp2, temp2, input0 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
@@ -722,10 +615,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
+ R500_ALU_RGBA_B_SWIZ_R |
+ R500_ALU_RGBA_A_SWIZ_G));
- /* ADD temp3, temp3, input0 */
+ /* ADD temp4, temp4, input0 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -742,80 +635,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_1 |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
-
- /* ADD temp4, temp4, input0 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(6) |
- R500_RGB_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(6) |
- R500_ALPHA_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
- R500_ALU_RGB_G_SWIZ_A_1 |
- R500_ALU_RGB_B_SWIZ_A_1 |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_1 |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
-
- /* ADD temp5, temp5, input0 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(7) |
- R500_RGB_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(7) |
- R500_ALPHA_ADDR2(0)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
- R500_ALU_RGB_G_SWIZ_A_1 |
- R500_ALU_RGB_B_SWIZ_A_1 |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A));
+ R500_ALU_RGBA_B_SWIZ_R |
+ R500_ALU_RGBA_A_SWIZ_G));
- /* TEX temp2, temp2, tex0, 1D */
+ /* TEX temp3, temp3, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -827,11 +660,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(4) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_SRC_R_SWIZ_B |
- R500_TEX_SRC_Q_SWIZ_A |
- R500_TEX_DST_ADDR(4) |
+ R500_TEX_SRC_S_SWIZ_B |
+ R500_TEX_SRC_T_SWIZ_A |
+ R500_TEX_SRC_R_SWIZ_R |
+ R500_TEX_SRC_Q_SWIZ_G |
+ R500_TEX_DST_ADDR(5) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
@@ -840,7 +673,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp3, temp3, tex0, 1D */
+ /* TEX temp2, temp2, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -851,12 +684,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(5) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(4) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_B |
R500_TEX_SRC_Q_SWIZ_A |
- R500_TEX_DST_ADDR(5) |
+ R500_TEX_DST_ADDR(4) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
@@ -865,7 +698,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp4, temp4, tex0, 1D */
+ /* TEX temp5, temp5, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -876,12 +709,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(6) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_B |
+ R500_TEX_SRC_T_SWIZ_A |
R500_TEX_SRC_R_SWIZ_B |
R500_TEX_SRC_Q_SWIZ_A |
- R500_TEX_DST_ADDR(6) |
+ R500_TEX_DST_ADDR(3) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
@@ -890,7 +723,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp5, temp5, tex0, 1D */
+ /* TEX temp4, temp4, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -901,12 +734,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(7) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_B |
R500_TEX_SRC_Q_SWIZ_A |
- R500_TEX_DST_ADDR(7) |
+ R500_TEX_DST_ADDR(0) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
@@ -924,14 +757,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(7) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(5) |
- R500_RGB_ADDR2(3)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(7) |
+ R500_RGB_ADDR2(1)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(5) |
- R500_ALPHA_ADDR1(3)));
+ R500_ALPHA_ADDR1(1)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
@@ -963,14 +796,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(6) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(4) |
- R500_RGB_ADDR2(3)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(6) |
+ R500_RGB_ADDR2(1)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(4) |
- R500_ALPHA_ADDR1(3)));
+ R500_ALPHA_ADDR1(1)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
@@ -979,13 +812,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -1008,11 +841,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
R500_INST_ALPHA_OMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(5) |
R500_RGB_ADDR2(2)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(4) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(5) |
R500_ALPHA_ADDR1(2)));
@@ -1046,7 +879,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
- /* const1 = {0, 1 / -texture[0].height, 0, 0) */
+ /* const0 = {1 / texture[0].height, 0, 0, 0} */
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->h));
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
commit a0c4a949cb49e5ac1e857aef08a8742b9f7b49da
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Thu Jul 31 21:19:18 2008 +0200
Remove uneeded negations.
diff --git a/src/bicubic_table.h b/src/bicubic_table.h
index 6f0169e..126e64d 100644
--- a/src/bicubic_table.h
+++ b/src/bicubic_table.h
@@ -1,646 +1,646 @@
static const float bicubic_tex_512[] = {
- 0.2, 1.0, 0.833333333333, 0.166666666667,
- 0.204088720925, 0.992187965834, 0.829396724701, 0.170603275299,
- 0.208229306439, 0.984378641369, 0.825400034587, 0.174599965413,
- 0.212420907874, 0.976574510623, 0.821344216665, 0.178655783335,
- 0.216662699005, 0.968777828797, 0.817230224609, 0.182769775391,
- 0.220953875426, 0.960990640339, 0.813059012095, 0.186940987905,
- 0.225293653935, 0.953214795864, 0.808831532796, 0.191168467204,
- 0.229681271957, 0.945451967972, 0.804548740387, 0.195451259613,
- 0.234115986983, 0.937703665988, 0.800211588542, 0.199788411458,
- 0.238597076022, 0.929971249668, 0.795821030935, 0.204178969065,
- 0.243123835089, 0.922255941932, 0.79137802124, 0.20862197876,
- 0.247695578698, 0.914558840653, 0.786883513133, 0.213116486867,
- 0.252311639383, 0.90688092957, 0.782338460286, 0.217661539714,
- 0.256971367229, 0.899223088369, 0.777743816376, 0.222256183624,
- 0.261674129428, 0.891586101989, 0.773100535075, 0.226899464925,
- 0.266419309847, 0.883970669194, 0.768409570058, 0.231590429942,
- 0.27120630861, 0.876377410468, 0.763671875, 0.236328125,
- 0.276034541704, 0.868806875283, 0.758888403575, 0.241111596425,
- 0.280903440584, 0.861259548768, 0.754060109456, 0.245939890544,
- 0.285812451814, 0.853735857846, 0.74918794632, 0.25081205368,
- 0.290761036698, 0.846236176857, 0.744272867839, 0.255727132161,
- 0.295748670944, 0.838760832722, 0.739315827688, 0.260684172312,
- 0.300774844327, 0.831310109672, 0.734317779541, 0.265682220459,
- 0.305839060373, 0.823884253585, 0.729279677073, 0.270720322927,
- 0.310940836049, 0.816483475952, 0.724202473958, 0.275797526042,
- 0.316079701469, 0.80910795751, 0.719087123871, 0.280912876129,
- 0.321255199604, 0.801757851568, 0.713934580485, 0.286065419515,
- 0.326466886014, 0.794433287044, 0.708745797475, 0.291254202525,
- 0.331714328576, 0.787134371247, 0.703521728516, 0.296478271484,
- 0.336997107235, 0.779861192413, 0.698263327281, 0.301736672719,
- 0.342314813753, 0.772613822026, 0.692971547445, 0.307028452555,
- 0.347667051478, 0.76539231694, 0.687647342682, 0.312352657318,
- 0.353053435115, 0.758196721311, 0.682291666667, 0.317708333333,
- 0.358473590501, 0.751027068365, 0.676905473073, 0.323094526927,
- 0.363927154404, 0.743883382007, 0.671489715576, 0.328510284424,
- 0.369413774313, 0.736765678299, 0.66604534785, 0.33395465215,
- 0.374933108243, 0.729673966794, 0.660573323568, 0.339426676432,
- 0.380484824551, 0.722608251764, 0.655074596405, 0.344925403595,
- 0.386068601748, 0.715568533318, 0.649550120036, 0.350449879964,
- 0.391684128331, 0.708554808415, 0.644000848134, 0.355999151866,
- 0.397331102613, 0.701567071798, 0.638427734375, 0.361572265625,
- 0.403009232558, 0.694605316836, 0.632831732432, 0.367168267568,
- 0.40871823563, 0.687669536295, 0.62721379598, 0.37278620402,
- 0.414457838638, 0.680759723045, 0.621574878693, 0.378425121307,
- 0.420227777594, 0.673875870699, 0.615915934245, 0.384084065755,
- 0.426027797575, 0.6670179742, 0.610237916311, 0.389762083689,
- 0.431857652583, 0.66018603035, 0.604541778564, 0.395458221436,
- 0.437717105418, 0.653380038302, 0.598828474681, 0.401171525319,
- 0.443605927552, 0.6466, 0.593098958333, 0.406901041667,
- 0.449523899007, 0.639845920588, 0.587354183197, 0.412645816803,
- 0.455470808236, 0.633117808778, 0.581595102946, 0.418404897054,
- 0.461446452007, 0.626415677192, 0.575822671254, 0.424177328746,
- 0.467450635295, 0.619739542669, 0.570037841797, 0.429962158203,
- 0.473483171168, 0.613089426553, 0.564241568247, 0.435758431753,
- 0.479543880687, 0.606465354949, 0.558434804281, 0.441565195719,
- 0.485632592794, 0.59986735897, 0.552618503571, 0.447381496429,
- 0.491749144218, 0.593295474951, 0.546793619792, 0.453206380208,
- 0.497893379365, 0.586749744657, 0.540961106618, 0.459038893382,
- 0.504065150224, 0.580230215471, 0.535121917725, 0.464878082275,
- 0.510264316266, 0.573736940568, 0.529277006785, 0.470722993215,
- 0.51649074434, 0.567269979082, 0.523427327474, 0.476572672526,
- 0.522744308578, 0.560829396251, 0.517573833466, 0.482426166534,
- 0.529024890292, 0.554415263567, 0.511717478434, 0.488282521566,
- 0.535332377868, 0.548027658908, 0.505859216054, 0.494140783946,
- 0.541666666667, 0.541666666667, 0.5, 0.5,
- 0.548027658908, 0.535332377868, 0.494140783946, 0.505859216054,
- 0.554415263567, 0.529024890292, 0.488282521566, 0.511717478434,
- 0.560829396251, 0.522744308578, 0.482426166534, 0.517573833466,
- 0.567269979082, 0.51649074434, 0.476572672526, 0.523427327474,
- 0.573736940568, 0.510264316266, 0.470722993215, 0.529277006785,
- 0.580230215471, 0.504065150224, 0.464878082275, 0.535121917725,
- 0.586749744657, 0.497893379365, 0.459038893382, 0.540961106618,
- 0.593295474951, 0.491749144218, 0.453206380208, 0.546793619792,
- 0.59986735897, 0.485632592794, 0.447381496429, 0.552618503571,
- 0.606465354949, 0.479543880687, 0.441565195719, 0.558434804281,
- 0.613089426553, 0.473483171168, 0.435758431753, 0.564241568247,
- 0.619739542669, 0.467450635295, 0.429962158203, 0.570037841797,
- 0.626415677192, 0.461446452007, 0.424177328746, 0.575822671254,
- 0.633117808778, 0.455470808236, 0.418404897054, 0.581595102946,
- 0.639845920588, 0.449523899007, 0.412645816803, 0.587354183197,
- 0.6466, 0.443605927552, 0.406901041667, 0.593098958333,
- 0.653380038302, 0.437717105418, 0.401171525319, 0.598828474681,
- 0.66018603035, 0.431857652583, 0.395458221436, 0.604541778564,
- 0.6670179742, 0.426027797575, 0.389762083689, 0.610237916311,
- 0.673875870699, 0.420227777594, 0.384084065755, 0.615915934245,
- 0.680759723045, 0.414457838638, 0.378425121307, 0.621574878693,
- 0.687669536295, 0.40871823563, 0.37278620402, 0.62721379598,
- 0.694605316836, 0.403009232558, 0.367168267568, 0.632831732432,
- 0.701567071798, 0.397331102613, 0.361572265625, 0.638427734375,
- 0.708554808415, 0.391684128331, 0.355999151866, 0.644000848134,
- 0.715568533318, 0.386068601748, 0.350449879964, 0.649550120036,
- 0.722608251764, 0.380484824551, 0.344925403595, 0.655074596405,
- 0.729673966794, 0.374933108243, 0.339426676432, 0.660573323568,
- 0.736765678299, 0.369413774313, 0.33395465215, 0.66604534785,
- 0.743883382007, 0.363927154404, 0.328510284424, 0.671489715576,
- 0.751027068365, 0.358473590501, 0.323094526927, 0.676905473073,
- 0.758196721311, 0.353053435115, 0.317708333333, 0.682291666667,
- 0.76539231694, 0.347667051478, 0.312352657318, 0.687647342682,
- 0.772613822026, 0.342314813753, 0.307028452555, 0.692971547445,
- 0.779861192413, 0.336997107235, 0.301736672719, 0.698263327281,
- 0.787134371247, 0.331714328576, 0.296478271484, 0.703521728516,
- 0.794433287044, 0.326466886014, 0.291254202525, 0.708745797475,
- 0.801757851568, 0.321255199604, 0.286065419515, 0.713934580485,
- 0.80910795751, 0.316079701469, 0.280912876129, 0.719087123871,
- 0.816483475952, 0.310940836049, 0.275797526042, 0.724202473958,
- 0.823884253585, 0.305839060373, 0.270720322927, 0.729279677073,
- 0.831310109672, 0.300774844327, 0.265682220459, 0.734317779541,
- 0.838760832722, 0.295748670944, 0.260684172312, 0.739315827688,
- 0.846236176857, 0.290761036698, 0.255727132161, 0.744272867839,
- 0.853735857846, 0.285812451814, 0.25081205368, 0.74918794632,
- 0.861259548768, 0.280903440584, 0.245939890544, 0.754060109456,
- 0.868806875283, 0.276034541704, 0.241111596425, 0.758888403575,
- 0.876377410468, 0.27120630861, 0.236328125, 0.763671875,
- 0.883970669194, 0.266419309847, 0.231590429942, 0.768409570058,
- 0.891586101989, 0.261674129428, 0.226899464925, 0.773100535075,
- 0.899223088369, 0.256971367229, 0.222256183624, 0.777743816376,
- 0.90688092957, 0.252311639383, 0.217661539714, 0.782338460286,
- 0.914558840653, 0.247695578698, 0.213116486867, 0.786883513133,
- 0.922255941932, 0.243123835089, 0.20862197876, 0.79137802124,
- 0.929971249668, 0.238597076022, 0.204178969065, 0.795821030935,
- 0.937703665988, 0.234115986983, 0.199788411458, 0.800211588542,
- 0.945451967972, 0.229681271957, 0.195451259613, 0.804548740387,
- 0.953214795864, 0.225293653935, 0.191168467204, 0.808831532796,
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+ -0.943513475102, 0.230785563941, 0.19653048863, 0.80346951137,
+ -0.945451967972, 0.229681271957, 0.195451259613, 0.804548740387,
+ -0.947391369442, 0.228579923441, 0.194375428061, 0.805624571939,
+ -0.949331656851, 0.227481529878, 0.193303008874, 0.806696991126,
+ -0.951272806947, 0.226386102829, 0.192234016955, 0.807765983045,
+ -0.953214795864, 0.225293653935, 0.191168467204, 0.808831532796,
+ -0.955157599114, 0.224204194912, 0.190106374522, 0.809893625478,
+ -0.957101191572, 0.223117737557, 0.189047753811, 0.810952246189,
+ -0.959045547461, 0.222034293743, 0.187992619971, 0.812007380029,
+ -0.960990640339, 0.220953875426, 0.186940987905, 0.813059012095,
+ -0.962936443085, 0.219876494638, 0.185892872512, 0.814107127488,
+ -0.964882927881, 0.218802163495, 0.184848288695, 0.815151711305,
+ -0.966830066203, 0.217730894191, 0.183807251354, 0.816192748646,
+ -0.968777828797, 0.216662699005, 0.182769775391, 0.817230224609,
+ -0.970726185673, 0.215597590297, 0.181735875706, 0.818264124294,
+ -0.972675106081, 0.214535580507, 0.180705567201, 0.819294432799,
+ -0.974624558501, 0.213476682163, 0.179678864777, 0.820321135223,
+ -0.976574510623, 0.212420907874, 0.178655783335, 0.821344216665,
+ -0.97852492933, 0.211368270334, 0.177636337777, 0.822363662223,
+ -0.980475780685, 0.210318782324, 0.176620543003, 0.823379456997,
+ -0.98242702991, 0.209272456708, 0.175608413915, 0.824391586085,
+ -0.984378641369, 0.208229306439, 0.174599965413, 0.825400034587,
+ -0.986330578552, 0.207189344555, 0.1735952124, 0.8264047876,
+ -0.988282804055, 0.206152584184, 0.172594169776, 0.827405830224,
+ -0.990235279565, 0.205119038539, 0.171596852442, 0.828403147558,
+ -0.992187965834, 0.204088720925, 0.170603275299, 0.829396724701,
+ -0.994140822671, 0.203061644735, 0.169613453249, 0.830386546751,
+ -0.996093808912, 0.202037823453, 0.168627401193, 0.831372598807,
+ -0.998046882407, 0.201017270652, 0.167645134032, 0.832354865968,
0 };
diff --git a/src/bicubic_table.py b/src/bicubic_table.py
index 53c5c3b..69cd402 100755
--- a/src/bicubic_table.py
+++ b/src/bicubic_table.py
@@ -15,7 +15,7 @@ def texgen(pix):
w2 = 1 / 6.0 * (-3 * a3 + 3 * a2 + 3 * a + 1)
w3 = 1 / 6.0 * a3
- tex.append(1 - (w1 / (w0 + w1)) + a)
+ tex.append(-(1 - (w1 / (w0 + w1)) + a))
tex.append(1 + (w3 / (w2 + w3)) - a)
tex.append(w0 + w1)
tex.append(w2 + w3)
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 79f2b8e..14fc5ab 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -414,7 +414,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
/* Pixel stack frame size. */
- OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(8));
+ OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(12));
/* FP length. */
OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
@@ -518,7 +518,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0));
- /* MUL temp3, const0, -temp0.xxxx */
+ /* MUL temp3, const0, temp0.xxxx */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -537,15 +537,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_R |
- R500_ALU_RGB_B_SWIZ_B_R |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_A |
R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_R |
- R500_ALPHA_MOD_B_NEG));
+ R500_ALPHA_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_R_SWIZ_0 |
@@ -625,7 +623,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* MAD temp2, const1, -temp1.xxxx, temp2 */
+ /* MAD temp2, const1, temp1.xxxx, temp2 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -646,15 +644,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_R |
- R500_ALU_RGB_B_SWIZ_B_R |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_A |
R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_R |
- R500_ALPHA_MOD_B_NEG));
+ R500_ALPHA_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -663,7 +659,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* MAD temp3, const1, -temp1.xxxx, temp3 */
+ /* MAD temp3, const1, temp1.xxxx, temp3 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -684,15 +680,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_R |
- R500_ALU_RGB_B_SWIZ_B_R |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_A |
R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_R |
- R500_ALPHA_MOD_B_NEG));
+ R500_ALPHA_SWIZ_B_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -717,14 +711,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A |
- R500_ALPHA_MOD_B_NEG));
+ R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -749,14 +741,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A |
- R500_ALPHA_MOD_B_NEG));
+ R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -781,14 +771,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A |
- R500_ALPHA_MOD_B_NEG));
+ R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -813,14 +801,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A |
- R500_ALPHA_MOD_B_NEG));
+ R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -1056,13 +1042,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, (1 << 16));
/* const0 = {1 / texture[0].width, 0, 0, 0} */
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (-1.0/(float)pPriv->w));
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w));
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
/* const1 = {0, 1 / -texture[0].height, 0, 0) */
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (-1.0/(float)pPriv->h));
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->h));
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
commit abb2b2e757d92591ab9277824b9d9746ba98f875
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Thu Jul 31 20:31:03 2008 +0200
Implement LPR in one instruction.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index f197c0a..79f2b8e 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -418,16 +418,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* FP length. */
OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(22)));
+ R500_US_CODE_END_ADDR(19)));
OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(22)));
+ R500_US_CODE_RANGE_SIZE(19)));
/* Prepare for FP emission. */
OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
FINISH_VIDEO();
- BEGIN_VIDEO(141);
+ BEGIN_VIDEO(123);
/* Pixel shader.
* I've gone ahead and annotated each instruction, since this
* thing is MASSIVE. :3
@@ -930,180 +930,87 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* LRP temp3, temp1.zzzz, temp3, temp5 ->
- * - PRESUB temps, 1 - temp1.zzzz
- * - MUL temp5, temps, temp5
- * - MAD temp3, temp1.zzzz, temp3, temp5 */
+ * - PRESUB temps, temp3 - temp5
+ * - MAD temp1.zzzz, temps, temp5 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
- R500_RGB_SRCP_OP_1_MINUS_RGB0 |
- R500_RGB_ADDR1(7)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
- R500_ALPHA_SRCP_OP_1_MINUS_A0 |
- R500_ALPHA_ADDR1(7)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRCP |
- R500_ALU_RGB_R_SWIZ_A_B |
- R500_ALU_RGB_G_SWIZ_A_B |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRCP |
- R500_ALPHA_SWIZ_A_B |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 |
- R500_ALU_RGBA_G_SWIZ_0 |
- R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));
- /* 2nd inst */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(7) |
+ R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(5) |
- R500_RGB_ADDR2(7)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
+ R500_RGB_ADDR2(3)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(7) |
+ R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(5) |
- R500_ALPHA_ADDR2(7)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALPHA_ADDR1(3)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_SEL_B_SRCP |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
+ R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
- R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
R500_ALU_RGBA_G_SWIZ_G |
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
/* LRP temp2, temp1.zzzz, temp2, temp4 ->
- * - PRESUB temps, 1 - temp1.zzzz
- * - ADD temp4, temps, temp4
- * - MAD temp2, temp1.zzzz, temp2, temp4 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
- R500_RGB_SRCP_OP_1_MINUS_RGB0 |
- R500_RGB_ADDR1(6)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
- R500_ALPHA_SRCP_OP_1_MINUS_A0 |
- R500_ALPHA_ADDR1(6)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRCP |
- R500_ALU_RGB_R_SWIZ_A_B |
- R500_ALU_RGB_G_SWIZ_A_B |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRCP |
- R500_ALPHA_SWIZ_A_B |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 |
- R500_ALU_RGBA_G_SWIZ_0 |
- R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));
- /* 2nd inst */
+ * - PRESUB temps, temp2 - temp4
+ * - MAD temp1.zzzz, temps, temp4 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(6) |
+ R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(4) |
- R500_RGB_ADDR2(6)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
+ R500_RGB_ADDR2(3)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(6) |
+ R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(4) |
- R500_ALPHA_ADDR2(6)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALPHA_ADDR1(3)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_SEL_B_SRCP |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
+ R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
- R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
R500_ALU_RGBA_G_SWIZ_G |
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
+
/* LRP output, temp0.zzzz, temp3, temp2 ->
- * - PRESUB temps, 1 - temp0.zzzz
- * - MUL temp2, temps, temp2
- * - MAD output, temp0.zzzz, temp3, temp2 */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) |
- R500_RGB_SRCP_OP_1_MINUS_RGB0 |
- R500_RGB_ADDR1(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(2) |
- R500_ALPHA_SRCP_OP_1_MINUS_A0 |
- R500_ALPHA_ADDR1(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRCP |
- R500_ALU_RGB_R_SWIZ_A_B |
- R500_ALU_RGB_G_SWIZ_A_B |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC1 |
- R500_ALU_RGB_R_SWIZ_B_R |
- R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
- R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRCP |
- R500_ALPHA_SWIZ_A_B |
- R500_ALPHA_SEL_B_SRC1 |
- R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
- R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 |
- R500_ALU_RGBA_G_SWIZ_0 |
- R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));
- /* 2nd inst */
+ * - PRESUB temps, temp3 - temp2
+ * - MAD temp0.zzzz, temps, temp2 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_LAST |
R500_INST_TEX_SEM_WAIT |
@@ -1115,29 +1022,31 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
R500_INST_ALPHA_OMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(4) |
+ R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(5) |
- R500_RGB_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(2) |
+ R500_RGB_ADDR2(2)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(4) |
+ R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(5) |
- R500_ALPHA_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALPHA_ADDR1(2)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_SEL_B_SRCP |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
R500_ALPHA_OP_MAD |
- R500_ALPHA_SEL_A_SRC0 |
+ R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
- R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
R500_ALU_RGBA_G_SWIZ_G |
R500_ALU_RGBA_B_SWIZ_B |
commit c370b74bec13194573348583c38adf710b880e79
Author: Dennis Kasprzyk <onestone at opencompositing.org>
Date: Thu Jul 31 19:50:49 2008 +0200
Set helper texture filter correctly.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 51e86ae..f197c0a 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -227,7 +227,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* Tex filter */
txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP) |
R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP) |
- R300_TX_MAG_FILTER_NEAREST |
+ R300_TX_MIN_FILTER_NEAREST |
R300_TX_MAG_FILTER_NEAREST |
(1 << R300_TX_ID_SHIFT);
@@ -1147,7 +1147,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, (1 << 16));
/* const0 = {1 / texture[0].width, 0, 0, 0} */
- OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w));
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (-1.0/(float)pPriv->w));
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
commit 5e85d5a5d0c50b29086ec0c219c8b52d25dbc2e9
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Wed Jul 30 19:45:15 2008 -0700
Update bicubic tables.
Now including the 2048x1 texture as well.
diff --git a/src/bicubic_table.h b/src/bicubic_table.h
index 721af1a..6f0169e 100644
--- a/src/bicubic_table.h
+++ b/src/bicubic_table.h
@@ -1,4 +1,4 @@
-static const float bicubic_tex_128[] = {
+static const float bicubic_tex_512[] = {
0.2, 1.0, 0.833333333333, 0.166666666667,
0.204088720925, 0.992187965834, 0.829396724701, 0.170603275299,
0.208229306439, 0.984378641369, 0.825400034587, 0.174599965413,
@@ -128,3 +128,519 @@ static const float bicubic_tex_128[] = {
0.984378641369, 0.208229306439, 0.174599965413, 0.825400034587,
0.992187965834, 0.204088720925, 0.170603275299, 0.829396724701,
0 };
+
+static const float bicubic_tex_2048[] = {
+ 0.2, 1.0, 0.833333333333, 0.166666666667,
+ 0.201017270652, 0.998046882407, 0.832354865968, 0.167645134032,
+ 0.202037823453, 0.996093808912, 0.831372598807, 0.168627401193,
+ 0.203061644735, 0.994140822671, 0.830386546751, 0.169613453249,
+ 0.204088720925, 0.992187965834, 0.829396724701, 0.170603275299,
+ 0.205119038539, 0.990235279565, 0.828403147558, 0.171596852442,
+ 0.206152584184, 0.988282804055, 0.827405830224, 0.172594169776,
+ 0.207189344555, 0.986330578552, 0.8264047876, 0.1735952124,
+ 0.208229306439, 0.984378641369, 0.825400034587, 0.174599965413,
+ 0.209272456708, 0.98242702991, 0.824391586085, 0.175608413915,
+ 0.210318782324, 0.980475780685, 0.823379456997, 0.176620543003,
+ 0.211368270334, 0.97852492933, 0.822363662223, 0.177636337777,
+ 0.212420907874, 0.976574510623, 0.821344216665, 0.178655783335,
+ 0.213476682163, 0.974624558501, 0.820321135223, 0.179678864777,
+ 0.214535580507, 0.972675106081, 0.819294432799, 0.180705567201,
+ 0.215597590297, 0.970726185673, 0.818264124294, 0.181735875706,
+ 0.216662699005, 0.968777828797, 0.817230224609, 0.182769775391,
+ 0.217730894191, 0.966830066203, 0.816192748646, 0.183807251354,
+ 0.218802163495, 0.964882927881, 0.815151711305, 0.184848288695,
+ 0.219876494638, 0.962936443085, 0.814107127488, 0.185892872512,
+ 0.220953875426, 0.960990640339, 0.813059012095, 0.186940987905,
+ 0.222034293743, 0.959045547461, 0.812007380029, 0.187992619971,
+ 0.223117737557, 0.957101191572, 0.810952246189, 0.189047753811,
+ 0.224204194912, 0.955157599114, 0.809893625478, 0.190106374522,
+ 0.225293653935, 0.953214795864, 0.808831532796, 0.191168467204,
+ 0.226386102829, 0.951272806947, 0.807765983045, 0.192234016955,
+ 0.227481529878, 0.949331656851, 0.806696991126, 0.193303008874,
+ 0.228579923441, 0.947391369442, 0.805624571939, 0.194375428061,
+ 0.229681271957, 0.945451967972, 0.804548740387, 0.195451259613,
+ 0.230785563941, 0.943513475102, 0.80346951137, 0.19653048863,
+ 0.231892787983, 0.941575912905, 0.802386899789, 0.197613100211,
+ 0.233002932749, 0.939639302885, 0.801300920546, 0.198699079454,
+ 0.234115986983, 0.937703665988, 0.800211588542, 0.199788411458,
+ 0.235231939499, 0.935769022612, 0.799118918677, 0.200881081323,
+ 0.236350779189, 0.933835392623, 0.798022925854, 0.201977074146,
+ 0.237472495017, 0.931902795364, 0.796923624973, 0.203076375027,
+ 0.238597076022, 0.929971249668, 0.795821030935, 0.204178969065,
+ 0.239724511313, 0.928040773869, 0.794715158641, 0.205284841359,
+ 0.240854790073, 0.926111385811, 0.793606022994, 0.206393977006,
+ 0.241987901556, 0.924183102865, 0.792493638893, 0.207506361107,
+ 0.243123835089, 0.922255941932, 0.79137802124, 0.20862197876,
+ 0.244262580067, 0.92032991946, 0.790259184937, 0.209740815063,
+ 0.245404125959, 0.918405051449, 0.789137144883, 0.210862855117,
+ 0.2465484623, 0.916481353466, 0.788011915982, 0.211988084018,
+ 0.247695578698, 0.914558840653, 0.786883513133, 0.213116486867,
+ 0.248845464827, 0.912637527735, 0.785751951238, 0.214248048762,
+ 0.249998110432, 0.91071742903, 0.784617245197, 0.215382754803,
+ 0.251153505324, 0.908798558464, 0.783479409913, 0.216520590087,
+ 0.252311639383, 0.90688092957, 0.782338460286, 0.217661539714,
+ 0.253472502556, 0.904964555505, 0.781194411218, 0.218805588782,
+ 0.254636084857, 0.903049449058, 0.78004727761, 0.21995272239,
+ 0.255802376366, 0.901135622655, 0.778897074362, 0.221102925638,
+ 0.256971367229, 0.899223088369, 0.777743816376, 0.222256183624,
+ 0.258143047657, 0.897311857929, 0.776587518553, 0.223412481447,
+ 0.259317407928, 0.89540194273, 0.775428195794, 0.224571804206,
+ 0.260494438383, 0.893493353835, 0.774265863001, 0.225734136999,
+ 0.261674129428, 0.891586101989, 0.773100535075, 0.226899464925,
+ 0.262856471532, 0.889680197624, 0.771932226916, 0.228067773084,
+ 0.264041455228, 0.887775650866, 0.770760953426, 0.229239046574,
+ 0.265229071114, 0.885872471544, 0.769586729507, 0.230413270493,
+ 0.266419309847, 0.883970669194, 0.768409570058, 0.231590429942,
+ 0.267612162149, 0.882070253069, 0.767229489982, 0.232770510018,
+ 0.268807618804, 0.880171232147, 0.76604650418, 0.23395349582,
+ 0.270005670655, 0.878273615133, 0.764860627552, 0.235139372448,
+ 0.27120630861, 0.876377410468, 0.763671875, 0.236328125,
+ 0.272409523636, 0.874482626339, 0.762480261425, 0.237519738575,
+ 0.273615306758, 0.872589270679, 0.761285801729, 0.238714198271,
+ 0.274823649065, 0.870697351177, 0.760088510811, 0.239911489189,
+ 0.276034541704, 0.868806875283, 0.758888403575, 0.241111596425,
+ 0.27724797588, 0.866917850215, 0.75768549492, 0.24231450508,
+ 0.27846394286, 0.865030282963, 0.756479799747, 0.243520200253,
+ 0.279682433967, 0.863144180297, 0.755271332959, 0.244728667041,
+ 0.280903440584, 0.861259548768, 0.754060109456, 0.245939890544,
+ 0.282126954151, 0.859376394721, 0.75284614414, 0.24715385586,
+ 0.283352966165, 0.857494724292, 0.751629451911, 0.248370548089,
+ 0.284581468182, 0.855614543419, 0.75041004767, 0.24958995233,
+ 0.285812451814, 0.853735857846, 0.74918794632, 0.25081205368,
+ 0.287045908728, 0.851858673124, 0.74796316276, 0.25203683724,
+ 0.288281830651, 0.849982994623, 0.746735711892, 0.253264288108,
+ 0.289520209362, 0.84810882753, 0.745505608618, 0.254494391382,
+ 0.290761036698, 0.846236176857, 0.744272867839, 0.255727132161,
+ 0.29200430455, 0.844365047445, 0.743037504454, 0.256962495546,
+ 0.293250004865, 0.84249544397, 0.741799533367, 0.258200466633,
+ 0.294498129645, 0.840627370944, 0.740558969478, 0.259441030522,
+ 0.295748670944, 0.838760832722, 0.739315827688, 0.260684172312,
+ 0.297001620871, 0.836895833504, 0.738070122898, 0.261929877102,
+ 0.298256971591, 0.835032377343, 0.736821870009, 0.263178129991,
+ 0.29951471532, 0.833170468144, 0.735571083923, 0.264428916077,
+ 0.300774844327, 0.831310109672, 0.734317779541, 0.265682220459,
+ 0.302037350934, 0.829451305553, 0.733061971764, 0.266938028236,
+ 0.303302227518, 0.827594059278, 0.731803675493, 0.268196324507,
+ 0.304569466504, 0.825738374211, 0.730542905629, 0.269457094371,
+ 0.305839060373, 0.823884253585, 0.729279677073, 0.270720322927,
+ 0.307111001654, 0.822031700513, 0.728014004727, 0.271985995273,
+ 0.30838528293, 0.820180717985, 0.726745903492, 0.273254096508,
+ 0.309661896833, 0.818331308878, 0.725475388269, 0.274524611731,
+ 0.310940836049, 0.816483475952, 0.724202473958, 0.275797526042,
+ 0.312222093311, 0.814637221859, 0.722927175462, 0.277072824538,
+ 0.313505661403, 0.812792549144, 0.721649507682, 0.278350492318,
+ 0.314791533161, 0.810949460248, 0.720369485517, 0.279630514483,
+ 0.316079701469, 0.80910795751, 0.719087123871, 0.280912876129,
+ 0.317370159259, 0.807268043172, 0.717802437643, 0.282197562357,
+ 0.318662899516, 0.805429719381, 0.716515441736, 0.283484558264,
+ 0.319957915271, 0.803592988191, 0.715226151049, 0.284773848951,
+ 0.321255199604, 0.801757851568, 0.713934580485, 0.286065419515,
+ 0.322554745644, 0.799924311388, 0.712640744944, 0.287359255056,
+ 0.323856546568, 0.798092369446, 0.711344659328, 0.288655340672,
+ 0.325160595601, 0.796262027454, 0.710046338538, 0.289953661462,
+ 0.326466886014, 0.794433287044, 0.708745797475, 0.291254202525,
+ 0.327775411128, 0.792606149773, 0.70744305104, 0.29255694896,
+ 0.329086164309, 0.790780617121, 0.706138114134, 0.293861885866,
+ 0.330399138972, 0.7889566905, 0.704831001659, 0.295168998341,
+ 0.331714328576, 0.787134371247, 0.703521728516, 0.296478271484,
+ 0.333031726629, 0.785313660637, 0.702210309605, 0.297789690395,
+ 0.334351326682, 0.783494559875, 0.700896759828, 0.299103240172,
+ 0.335673122336, 0.781677070106, 0.699581094086, 0.300418905914,
+ 0.336997107235, 0.779861192413, 0.698263327281, 0.301736672719,
+ 0.338323275068, 0.778046927819, 0.696943474313, 0.303056525687,
+ 0.339651619571, 0.776234277291, 0.695621550083, 0.304378449917,
+ 0.340982134524, 0.774423241741, 0.694297569493, 0.305702430507,
+ 0.342314813753, 0.772613822026, 0.692971547445, 0.307028452555,
+ 0.343649651127, 0.770806018955, 0.691643498838, 0.308356501162,
+ 0.344986640559, 0.768999833285, 0.690313438574, 0.309686561426,
+ 0.346325776009, 0.767195265725, 0.688981381555, 0.311018618445,
+ 0.347667051478, 0.76539231694, 0.687647342682, 0.312352657318,
+ 0.349010461013, 0.76359098755, 0.686311336855, 0.313688663145,
+ 0.350355998701, 0.761791278131, 0.684973378976, 0.315026621024,
+ 0.351703658677, 0.759993189219, 0.683633483946, 0.316366516054,
+ 0.353053435115, 0.758196721311, 0.682291666667, 0.317708333333,
+ 0.354405322233, 0.756401874867, 0.680947942038, 0.319052057962,
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+ 0.772613822026, 0.342314813753, 0.307028452555, 0.692971547445,
+ 0.774423241741, 0.340982134524, 0.305702430507, 0.694297569493,
+ 0.776234277291, 0.339651619571, 0.304378449917, 0.695621550083,
+ 0.778046927819, 0.338323275068, 0.303056525687, 0.696943474313,
+ 0.779861192413, 0.336997107235, 0.301736672719, 0.698263327281,
+ 0.781677070106, 0.335673122336, 0.300418905914, 0.699581094086,
+ 0.783494559875, 0.334351326682, 0.299103240172, 0.700896759828,
+ 0.785313660637, 0.333031726629, 0.297789690395, 0.702210309605,
+ 0.787134371247, 0.331714328576, 0.296478271484, 0.703521728516,
+ 0.7889566905, 0.330399138972, 0.295168998341, 0.704831001659,
+ 0.790780617121, 0.329086164309, 0.293861885866, 0.706138114134,
+ 0.792606149773, 0.327775411128, 0.29255694896, 0.70744305104,
+ 0.794433287044, 0.326466886014, 0.291254202525, 0.708745797475,
+ 0.796262027454, 0.325160595601, 0.289953661462, 0.710046338538,
+ 0.798092369446, 0.323856546568, 0.288655340672, 0.711344659328,
+ 0.799924311388, 0.322554745644, 0.287359255056, 0.712640744944,
+ 0.801757851568, 0.321255199604, 0.286065419515, 0.713934580485,
+ 0.803592988191, 0.319957915271, 0.284773848951, 0.715226151049,
+ 0.805429719381, 0.318662899516, 0.283484558264, 0.716515441736,
+ 0.807268043172, 0.317370159259, 0.282197562357, 0.717802437643,
+ 0.80910795751, 0.316079701469, 0.280912876129, 0.719087123871,
+ 0.810949460248, 0.314791533161, 0.279630514483, 0.720369485517,
+ 0.812792549144, 0.313505661403, 0.278350492318, 0.721649507682,
+ 0.814637221859, 0.312222093311, 0.277072824538, 0.722927175462,
+ 0.816483475952, 0.310940836049, 0.275797526042, 0.724202473958,
+ 0.818331308878, 0.309661896833, 0.274524611731, 0.725475388269,
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+ 0.822031700513, 0.307111001654, 0.271985995273, 0.728014004727,
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+ 0.825738374211, 0.304569466504, 0.269457094371, 0.730542905629,
+ 0.827594059278, 0.303302227518, 0.268196324507, 0.731803675493,
+ 0.829451305553, 0.302037350934, 0.266938028236, 0.733061971764,
+ 0.831310109672, 0.300774844327, 0.265682220459, 0.734317779541,
+ 0.833170468144, 0.29951471532, 0.264428916077, 0.735571083923,
+ 0.835032377343, 0.298256971591, 0.263178129991, 0.736821870009,
+ 0.836895833504, 0.297001620871, 0.261929877102, 0.738070122898,
+ 0.838760832722, 0.295748670944, 0.260684172312, 0.739315827688,
+ 0.840627370944, 0.294498129645, 0.259441030522, 0.740558969478,
+ 0.84249544397, 0.293250004865, 0.258200466633, 0.741799533367,
+ 0.844365047445, 0.29200430455, 0.256962495546, 0.743037504454,
+ 0.846236176857, 0.290761036698, 0.255727132161, 0.744272867839,
+ 0.84810882753, 0.289520209362, 0.254494391382, 0.745505608618,
+ 0.849982994623, 0.288281830651, 0.253264288108, 0.746735711892,
+ 0.851858673124, 0.287045908728, 0.25203683724, 0.74796316276,
+ 0.853735857846, 0.285812451814, 0.25081205368, 0.74918794632,
+ 0.855614543419, 0.284581468182, 0.24958995233, 0.75041004767,
+ 0.857494724292, 0.283352966165, 0.248370548089, 0.751629451911,
+ 0.859376394721, 0.282126954151, 0.24715385586, 0.75284614414,
+ 0.861259548768, 0.280903440584, 0.245939890544, 0.754060109456,
+ 0.863144180297, 0.279682433967, 0.244728667041, 0.755271332959,
+ 0.865030282963, 0.27846394286, 0.243520200253, 0.756479799747,
+ 0.866917850215, 0.27724797588, 0.24231450508, 0.75768549492,
+ 0.868806875283, 0.276034541704, 0.241111596425, 0.758888403575,
+ 0.870697351177, 0.274823649065, 0.239911489189, 0.760088510811,
+ 0.872589270679, 0.273615306758, 0.238714198271, 0.761285801729,
+ 0.874482626339, 0.272409523636, 0.237519738575, 0.762480261425,
+ 0.876377410468, 0.27120630861, 0.236328125, 0.763671875,
+ 0.878273615133, 0.270005670655, 0.235139372448, 0.764860627552,
+ 0.880171232147, 0.268807618804, 0.23395349582, 0.76604650418,
+ 0.882070253069, 0.267612162149, 0.232770510018, 0.767229489982,
+ 0.883970669194, 0.266419309847, 0.231590429942, 0.768409570058,
+ 0.885872471544, 0.265229071114, 0.230413270493, 0.769586729507,
+ 0.887775650866, 0.264041455228, 0.229239046574, 0.770760953426,
+ 0.889680197624, 0.262856471532, 0.228067773084, 0.771932226916,
+ 0.891586101989, 0.261674129428, 0.226899464925, 0.773100535075,
+ 0.893493353835, 0.260494438383, 0.225734136999, 0.774265863001,
+ 0.89540194273, 0.259317407928, 0.224571804206, 0.775428195794,
+ 0.897311857929, 0.258143047657, 0.223412481447, 0.776587518553,
+ 0.899223088369, 0.256971367229, 0.222256183624, 0.777743816376,
+ 0.901135622655, 0.255802376366, 0.221102925638, 0.778897074362,
+ 0.903049449058, 0.254636084857, 0.21995272239, 0.78004727761,
+ 0.904964555505, 0.253472502556, 0.218805588782, 0.781194411218,
+ 0.90688092957, 0.252311639383, 0.217661539714, 0.782338460286,
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+ 0.91071742903, 0.249998110432, 0.215382754803, 0.784617245197,
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+ 0.916481353466, 0.2465484623, 0.211988084018, 0.788011915982,
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+ 0.92032991946, 0.244262580067, 0.209740815063, 0.790259184937,
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+ 0.924183102865, 0.241987901556, 0.207506361107, 0.792493638893,
+ 0.926111385811, 0.240854790073, 0.206393977006, 0.793606022994,
+ 0.928040773869, 0.239724511313, 0.205284841359, 0.794715158641,
+ 0.929971249668, 0.238597076022, 0.204178969065, 0.795821030935,
+ 0.931902795364, 0.237472495017, 0.203076375027, 0.796923624973,
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+ 0.943513475102, 0.230785563941, 0.19653048863, 0.80346951137,
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+ 0.949331656851, 0.227481529878, 0.193303008874, 0.806696991126,
+ 0.951272806947, 0.226386102829, 0.192234016955, 0.807765983045,
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+ 0.974624558501, 0.213476682163, 0.179678864777, 0.820321135223,
+ 0.976574510623, 0.212420907874, 0.178655783335, 0.821344216665,
+ 0.97852492933, 0.211368270334, 0.177636337777, 0.822363662223,
+ 0.980475780685, 0.210318782324, 0.176620543003, 0.823379456997,
+ 0.98242702991, 0.209272456708, 0.175608413915, 0.824391586085,
+ 0.984378641369, 0.208229306439, 0.174599965413, 0.825400034587,
+ 0.986330578552, 0.207189344555, 0.1735952124, 0.8264047876,
+ 0.988282804055, 0.206152584184, 0.172594169776, 0.827405830224,
+ 0.990235279565, 0.205119038539, 0.171596852442, 0.828403147558,
+ 0.992187965834, 0.204088720925, 0.170603275299, 0.829396724701,
+ 0.994140822671, 0.203061644735, 0.169613453249, 0.830386546751,
+ 0.996093808912, 0.202037823453, 0.168627401193, 0.831372598807,
+ 0.998046882407, 0.201017270652, 0.167645134032, 0.832354865968,
+ 0 };
+
diff --git a/src/bicubic_table.py b/src/bicubic_table.py
index d9b3c46..53c5c3b 100755
--- a/src/bicubic_table.py
+++ b/src/bicubic_table.py
@@ -1,12 +1,12 @@
#!/usr/bin/python
-def texgen():
+def texgen(pix):
tex = []
- for i in range(0,512,4):
+ for i in range(0,pix,4):
- a = i / 512.0
+ a = i / float(pix)
a2 = a ** 2
a3 = a ** 3
@@ -27,12 +27,17 @@ def printrow(l, offset):
seq = [ str(i) for i in l[offset:offset+4] ]
return "\t" + ", ".join(seq) + ","
-l = texgen()
+def maketable(pix):
-print "static const float bicubic_tex_128[] = {"
+ l = texgen(pix)
-for i in range(0, 512, 4):
+ print "static const float bicubic_tex_" + str(pix) + "[] = {"
- print printrow(l, i)
+ for i in range(0, pix, 4):
-print "\t0 };"
+ print printrow(l, i)
+
+ print "\t0 };\n"
+
+maketable(512)
+maketable(2048)
\ No newline at end of file
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 1a822e0..aee081f 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -207,7 +207,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) {
pPriv->bicubic_offset = RADEONAllocateMemory(pScrn,
&pPriv->bicubic_memory,
- sizeof(bicubic_tex_128));
+ sizeof(bicubic_tex_512));
pPriv->bicubic_src_offset = pPriv->bicubic_offset + info->fbLocation + pScrn->fbOffset;
if (pPriv->bicubic_offset == 0)
pPriv->bicubic_enabled = FALSE;
@@ -283,7 +283,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
/* Upload bicubic filter tex */
if (pPriv->bicubic_enabled)
- RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_128, (uint8_t *)(info->FB + pPriv->bicubic_offset), 2048, 2048, 1, 512, 4);
+ RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_512, (uint8_t *)(info->FB + pPriv->bicubic_offset), 2048, 2048, 1, 512, 4);
/* update cliplist */
if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
commit 17e5e9573e59c3d82d51c261b9c5005f6aec7d43
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Wed Jul 30 11:57:25 2008 -0700
Force R580-only for bicubic.
Initial reading of docs suggest RV560 and RV570 can't handle it,
but they're welcome to test.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 366a254..1a822e0 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -391,7 +391,7 @@ RADEONSetTexPortAttribute(ScrnInfoPtr pScrn,
if (attribute == xvBicubic)
/* -1 -> set default (disable for RV515 and punier) */
pPriv->bicubic_enabled = (value == -1) ?
- (info->ChipFamily >= CHIP_FAMILY_R580) : value;
+ (info->ChipFamily == CHIP_FAMILY_R580) : value;
else
return BadMatch;
@@ -454,7 +454,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
pPriv->videoStatus = 0;
pPriv->currentBuffer = 0;
pPriv->doubleBuffer = 0;
- pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_R580);
+ pPriv->bicubic_enabled = (info->ChipFamily == CHIP_FAMILY_R580);
/* gotta uninit this someplace, XXX: shouldn't be necessary for textured */
REGION_NULL(pScreen, &pPriv->clip);
commit 83b52473d0e7102265918b07be053fcda17a14b4
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Wed Jul 30 01:03:57 2008 -0700
Bump bicubic cutoff to R580.
RV530 chipsets can't handle fullscreen bicubic...
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 8075ef2..366a254 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -391,7 +391,7 @@ RADEONSetTexPortAttribute(ScrnInfoPtr pScrn,
if (attribute == xvBicubic)
/* -1 -> set default (disable for RV515 and punier) */
pPriv->bicubic_enabled = (value == -1) ?
- (info->ChipFamily >= CHIP_FAMILY_RV530) : value;
+ (info->ChipFamily >= CHIP_FAMILY_R580) : value;
else
return BadMatch;
@@ -454,7 +454,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
pPriv->videoStatus = 0;
pPriv->currentBuffer = 0;
pPriv->doubleBuffer = 0;
- pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_RV530);
+ pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_R580);
/* gotta uninit this someplace, XXX: shouldn't be necessary for textured */
REGION_NULL(pScreen, &pPriv->clip);
commit 69a4998d1286bcdd7bfe874cd5628bc1cc232bae
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Wed Jul 30 01:03:46 2008 -0700
Oops, made a mistake with vertices.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 93d48b2..51e86ae 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -1491,9 +1491,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
VTX_OUT_FILTER((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5);
- VTX_OUT_FILTER((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
- xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5);
VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth),
xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0],
xFixedToFloat(srcBottomLeft.x) + 0.5, xFixedToFloat(srcBottomLeft.y) + 0.5);
@@ -1505,11 +1502,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
xFixedToFloat(srcTopRight.x) + 0.5, xFixedToFloat(srcTopRight.y) + 0.5);
} else {
if (info->ChipFamily >= CHIP_FAMILY_R200) {
- VTX_OUT((float)dstX, (float)(dstY + dsth),
+ VTX_OUT((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
}
- VTX_OUT((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
VTX_OUT((float)dstX, (float)(dstY + dsth),
xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]);
VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth),
commit a4ec30a677906ec2ff9824c7ddca586655f6d1a8
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Wed Jul 30 00:54:32 2008 -0700
Merge upstream changes to vertices, and also add Xv attributes for textured video, including bicubic filtering.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index b1b28be..8075ef2 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -93,6 +93,7 @@ static __inline__ uint32_t F_TO_DW(float val)
#undef VIDEO_PREAMBLE
#undef BEGIN_VIDEO
#undef OUT_VIDEO_REG
+#undef OUT_VIDEO_REG_F
#undef FINISH_VIDEO
#ifdef XF86DRI
@@ -103,6 +104,7 @@ static __inline__ uint32_t F_TO_DW(float val)
RADEONCP_REFRESH(pScrn, info)
#define BEGIN_VIDEO(n) BEGIN_RING(2*(n))
#define OUT_VIDEO_REG(reg, val) OUT_RING_REG(reg, val)
+#define OUT_VIDEO_REG_F(reg, val) OUT_VIDEO_REG(reg, F_TO_DW(val))
#define FINISH_VIDEO() ADVANCE_RING()
#define OUT_VIDEO_RING_F(x) OUT_RING(F_TO_DW(x))
@@ -200,7 +202,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
}
/* Bicubic filter loading */
- pPriv->bicubic_enabled = IS_R500_3D;
+ if (!IS_R500_3D)
+ pPriv->bicubic_enabled = FALSE;
if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) {
pPriv->bicubic_offset = RADEONAllocateMemory(pScrn,
&pPriv->bicubic_memory,
@@ -335,12 +338,16 @@ static XF86VideoFormatRec Formats[NUM_FORMATS] =
{15, TrueColor}, {16, TrueColor}, {24, TrueColor}
};
-#define NUM_ATTRIBUTES 0
+#define NUM_ATTRIBUTES 1
-static XF86AttributeRec Attributes[NUM_ATTRIBUTES] =
+static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] =
{
+ {XvSettable | XvGettable, -1, 1, "XV_BICUBIC"},
+ {0, 0, 0, NULL}
};
+static Atom xvBicubic;
+
#define NUM_IMAGES 4
static XF86ImageRec Images[NUM_IMAGES] =
@@ -351,6 +358,46 @@ static XF86ImageRec Images[NUM_IMAGES] =
XVIMAGE_UYVY
};
+int
+RADEONGetTexPortAttribute(ScrnInfoPtr pScrn,
+ Atom attribute,
+ INT32 *value,
+ pointer data)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
+
+ if (info->accelOn) RADEON_SYNC(info, pScrn);
+
+ if (attribute == xvBicubic)
+ *value = pPriv->bicubic_enabled ? 1 : 0;
+ else
+ return BadMatch;
+
+ return Success;
+}
+
+int
+RADEONSetTexPortAttribute(ScrnInfoPtr pScrn,
+ Atom attribute,
+ INT32 value,
+ pointer data)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
+
+ RADEON_SYNC(info, pScrn);
+
+ if (attribute == xvBicubic)
+ /* -1 -> set default (disable for RV515 and punier) */
+ pPriv->bicubic_enabled = (value == -1) ?
+ (info->ChipFamily >= CHIP_FAMILY_RV530) : value;
+ else
+ return BadMatch;
+
+ return Success;
+}
+
XF86VideoAdaptorPtr
RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
{
@@ -366,6 +413,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
if (adapt == NULL)
return NULL;
+ xvBicubic = MAKE_ATOM("XV_BICUBIC");
+
adapt->type = XvWindowMask | XvInputMask | XvImageMask;
adapt->flags = 0;
adapt->name = "Radeon Textured Video";
@@ -391,8 +440,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
adapt->GetVideo = NULL;
adapt->GetStill = NULL;
adapt->StopVideo = RADEONStopVideo;
- adapt->SetPortAttribute = RADEONSetPortAttribute;
- adapt->GetPortAttribute = RADEONGetPortAttribute;
+ adapt->SetPortAttribute = RADEONSetTexPortAttribute;
+ adapt->GetPortAttribute = RADEONGetTexPortAttribute;
adapt->QueryBestSize = RADEONQueryBestSize;
adapt->PutImage = RADEONPutImageTextured;
adapt->ReputImage = NULL;
@@ -405,6 +454,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
pPriv->videoStatus = 0;
pPriv->currentBuffer = 0;
pPriv->doubleBuffer = 0;
+ pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_RV530);
/* gotta uninit this someplace, XXX: shouldn't be necessary for textured */
REGION_NULL(pScreen, &pPriv->clip);
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index ce500a1..93d48b2 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -1147,15 +1147,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, (1 << 16));
/* const0 = {1 / texture[0].width, 0, 0, 0} */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, r300PackFloat32(1.0/(float)pPriv->w));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w));
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
/* const1 = {0, 1 / -texture[0].height, 0, 0) */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, r300PackFloat32(-1.0/(float)pPriv->h));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (-1.0/(float)pPriv->h));
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
FINISH_VIDEO();
@@ -1490,7 +1490,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (pPriv->bicubic_enabled) {
VTX_OUT_FILTER((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
- xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5));
+ xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5);
VTX_OUT_FILTER((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5);
@@ -1504,9 +1504,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0],
xFixedToFloat(srcTopRight.x) + 0.5, xFixedToFloat(srcTopRight.y) + 0.5);
} else {
- if (info->ChipFamily >= CHIP_FAMILY_R200)
+ if (info->ChipFamily >= CHIP_FAMILY_R200) {
VTX_OUT((float)dstX, (float)(dstY + dsth),
xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+ }
VTX_OUT((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
VTX_OUT((float)dstX, (float)(dstY + dsth),
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 4f71e28..46a2e55 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -106,7 +106,6 @@ static Atom xvEncoding, xvFrequency, xvVolume, xvMute,
static Atom xvOvAlpha, xvGrAlpha, xvAlphaMode;
-
#define GET_PORT_PRIVATE(pScrn) \
(RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr)
@@ -1703,9 +1702,6 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn,
Bool setAlpha = FALSE;
unsigned char *RADEONMMIO = info->MMIO;
- if (pPriv->textured)
- return BadMatch;
-
RADEON_SYNC(info, pScrn);
#define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0)
@@ -1932,7 +1928,7 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn,
if(pPriv->fi1236!=NULL){
xf86_fi1236_dump_status(pPriv->fi1236);
}
- }
+ }
else if(attribute == xvAdjustment)
{
pPriv->adjustment=value;
@@ -1977,9 +1973,6 @@ RADEONGetPortAttribute(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
- if (pPriv->textured)
- return BadMatch;
-
if (info->accelOn) RADEON_SYNC(info, pScrn);
if(attribute == xvAutopaintColorkey)
diff --git a/src/radeon_video.h b/src/radeon_video.h
index 34bfb30..abf8d98 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -15,20 +15,6 @@
#include "bicubic_table.h"
-/*
- * This function takes a float and packs it into a uint32_t. Thanks, Mesa!
- */
-static inline uint32_t r300PackFloat32(float fl)
-{
- union {
- float fl;
- uint32_t u;
- } u;
-
- u.fl = fl;
- return u.u;
-}
-
/* Xvideo port struct */
typedef struct {
uint32_t transform_index;
@@ -128,7 +114,6 @@ typedef struct {
int drw_x, drw_y;
} RADEONPortPrivRec, *RADEONPortPrivPtr;
-
void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
commit f3b81c7582aed307fa44e134ee161cd8a3158657
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Mon Jul 28 19:50:10 2008 -0700
Fix constants.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 5b7b787..ce500a1 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -1147,13 +1147,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, (1 << 16));
/* const0 = {1 / texture[0].width, 0, 0, 0} */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (uint32_t)(1/pPriv->w));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, r300PackFloat32(1.0/(float)pPriv->w));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
/* const1 = {0, 1 / -texture[0].height, 0, 0) */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (uint32_t)(-1/pPriv->h));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, r300PackFloat32(-1.0/(float)pPriv->h));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
diff --git a/src/radeon_video.h b/src/radeon_video.h
index b9ead1c..34bfb30 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -15,6 +15,20 @@
#include "bicubic_table.h"
+/*
+ * This function takes a float and packs it into a uint32_t. Thanks, Mesa!
+ */
+static inline uint32_t r300PackFloat32(float fl)
+{
+ union {
+ float fl;
+ uint32_t u;
+ } u;
+
+ u.fl = fl;
+ return u.u;
+}
+
/* Xvideo port struct */
typedef struct {
uint32_t transform_index;
commit 7dbb7023ba023ec1a38be63af9c9f49e40222b7b
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Mon Jul 28 17:30:41 2008 -0700
Finally got the fragment program fully working for bicubic filtering on r5xx.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 58bb0ab..5b7b787 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -414,7 +414,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
/* Pixel stack frame size. */
- OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(15));
+ OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(8));
/* FP length. */
OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
@@ -507,7 +507,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_B_SWIZ_B_G));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_G));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
@@ -539,7 +541,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_R |
R500_ALPHA_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
@@ -573,7 +577,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_B_SWIZ_B_G));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) |
R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_G));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) |
R500_ALU_RGBA_OP_MAD |
@@ -607,7 +613,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_B_SWIZ_B_G));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) |
R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_G));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) |
R500_ALU_RGBA_OP_MAD |
@@ -642,8 +650,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SWIZ_B_R));
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_R |
+ R500_ALPHA_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -677,8 +688,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SWIZ_B_R));
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_R |
+ R500_ALPHA_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -708,7 +722,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
- R500_ALPHA_SWIZ_B_A));
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_A |
+ R500_ALPHA_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -738,7 +754,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
- R500_ALPHA_SWIZ_B_A));
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_A |
+ R500_ALPHA_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -768,7 +786,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
- R500_ALPHA_SWIZ_B_A));
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_A |
+ R500_ALPHA_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -798,7 +818,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
- R500_ALPHA_SWIZ_B_A));
+ R500_ALPHA_SEL_B_SRC1 |
+ R500_ALPHA_SWIZ_B_A |
+ R500_ALPHA_MOD_B_NEG));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
@@ -908,37 +930,41 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* LRP temp3, temp1.zzzz, temp3, temp5 ->
- * - ADD temp6, temp3, -temp5
- * - MAD temp3, temp1.zzzz, temp6, temp5 */
+ * - PRESUB temps, 1 - temp1.zzzz
+ * - MUL temp5, temps, temp5
+ * - MAD temp3, temp1.zzzz, temp3, temp5 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(5) |
- R500_RGB_ADDR2(7)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(5) |
- R500_ALPHA_ADDR2(7)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
- R500_ALU_RGB_G_SWIZ_A_1 |
- R500_ALU_RGB_B_SWIZ_A_1 |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
+ R500_RGB_SRCP_OP_1_MINUS_RGB0 |
+ R500_RGB_ADDR1(7)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
+ R500_ALPHA_SRCP_OP_1_MINUS_A0 |
+ R500_ALPHA_ADDR1(7)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRCP |
+ R500_ALU_RGB_R_SWIZ_A_B |
+ R500_ALU_RGB_G_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_B |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(8) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) |
R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SEL_A_SRCP |
+ R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(8) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) |
R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A |
- R500_ALU_RGBA_ALPHA_MOD_C_NEG));
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));
/* 2nd inst */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
@@ -946,10 +972,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
- R500_RGB_ADDR1(8) |
+ R500_RGB_ADDR1(5) |
R500_RGB_ADDR2(7)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
- R500_ALPHA_ADDR1(8) |
+ R500_ALPHA_ADDR1(5) |
R500_ALPHA_ADDR2(7)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_B |
@@ -961,7 +987,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
R500_ALU_RGBA_OP_MAD |
@@ -972,36 +1000,40 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_A_SWIZ_A));
/* LRP temp2, temp1.zzzz, temp2, temp4 ->
- * - ADD temp6, temp2, -temp4
- * - MAD temp2, temp1.zzzz, temp6, temp4 */
+ * - PRESUB temps, 1 - temp1.zzzz
+ * - ADD temp4, temps, temp4
+ * - MAD temp2, temp1.zzzz, temp2, temp4 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
- R500_RGB_ADDR2(6)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
- R500_ALPHA_ADDR2(6)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
- R500_ALU_RGB_G_SWIZ_A_1 |
- R500_ALU_RGB_B_SWIZ_A_1 |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
+ R500_RGB_SRCP_OP_1_MINUS_RGB0 |
+ R500_RGB_ADDR1(6)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
+ R500_ALPHA_SRCP_OP_1_MINUS_A0 |
+ R500_ALPHA_ADDR1(6)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRCP |
+ R500_ALU_RGB_R_SWIZ_A_B |
+ R500_ALU_RGB_G_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_B |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(8) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) |
R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SEL_A_SRCP |
+ R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(8) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) |
R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A |
- R500_ALU_RGBA_ALPHA_MOD_C_NEG));
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));
/* 2nd inst */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
@@ -1009,10 +1041,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
- R500_RGB_ADDR1(8) |
+ R500_RGB_ADDR1(4) |
R500_RGB_ADDR2(6)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
- R500_ALPHA_ADDR1(8) |
+ R500_ALPHA_ADDR1(4) |
R500_ALPHA_ADDR2(6)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_B |
@@ -1024,7 +1056,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
@@ -1035,36 +1069,40 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_A_SWIZ_A));
/* LRP output, temp0.zzzz, temp3, temp2 ->
- * - ADD temp6, temp3, -temp2
- * - MAD output, temp0.zzzz, temp6, temp2 */
+ * - PRESUB temps, 1 - temp0.zzzz
+ * - MUL temp2, temps, temp2
+ * - MAD output, temp0.zzzz, temp3, temp2 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(5) |
- R500_RGB_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(5) |
- R500_ALPHA_ADDR2(4)));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
- R500_ALU_RGB_G_SWIZ_A_1 |
- R500_ALU_RGB_B_SWIZ_A_1 |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) |
+ R500_RGB_SRCP_OP_1_MINUS_RGB0 |
+ R500_RGB_ADDR1(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(2) |
+ R500_ALPHA_SRCP_OP_1_MINUS_A0 |
+ R500_ALPHA_ADDR1(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRCP |
+ R500_ALU_RGB_R_SWIZ_A_B |
+ R500_ALU_RGB_G_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_B |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(8) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SEL_A_SRCP |
+ R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(8) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_SEL_C_SRC2 |
- R500_ALU_RGBA_R_SWIZ_R |
- R500_ALU_RGBA_G_SWIZ_G |
- R500_ALU_RGBA_B_SWIZ_B |
- R500_ALU_RGBA_A_SWIZ_A |
- R500_ALU_RGBA_ALPHA_MOD_C_NEG));
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));
/* 2nd inst */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_LAST |
@@ -1072,12 +1110,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_OMASK_R |
+ R500_INST_RGB_OMASK_G |
+ R500_INST_RGB_OMASK_B |
+ R500_INST_ALPHA_OMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) |
- R500_RGB_ADDR1(8) |
+ R500_RGB_ADDR1(5) |
R500_RGB_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(2) |
- R500_ALPHA_ADDR1(8) |
+ R500_ALPHA_ADDR1(5) |
R500_ALPHA_ADDR2(4)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_B |
@@ -1087,10 +1129,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
+ R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
R500_ALU_RGBA_G_SWIZ_G |
commit 0e4dd73b9ebc6f608eeff945b4d463a00c02e07c
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Mon Jul 28 12:16:50 2008 -0700
More bicubic FP buggies.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 3cf89fa..58bb0ab 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -430,20 +430,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
BEGIN_VIDEO(141);
/* Pixel shader.
* I've gone ahead and annotated each instruction, since this
- * thing is MASSIVE. :3 */
+ * thing is MASSIVE. :3
+ * Note: In order to avoid buggies with temps and multiple
+ * inputs, all temps are offset by 2. temp0 -> register2. */
- /* TEX temp0, input0.xxxx, tex0, 1D */
+ /* TEX temp0, input1.xxxx, tex1, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_R |
R500_TEX_SRC_R_SWIZ_R |
@@ -457,18 +459,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp1, input0.yyyy, tex0, 1D */
+ /* TEX temp1, input1.yyyy, tex1, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
R500_TEX_SRC_S_SWIZ_G |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_G |
@@ -491,10 +493,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(0)));
+ R500_RGB_ADDR1(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(0)));
+ R500_ALPHA_ADDR1(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
@@ -522,10 +524,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
- R500_RGB_ADDR1(0)));
+ R500_RGB_ADDR1(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
- R500_ALPHA_ADDR1(0)));
+ R500_ALPHA_ADDR1(2)));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
@@ -805,14 +807,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGBA_B_SWIZ_B |
R500_ALU_RGBA_A_SWIZ_A));
- /* TEX temp2, temp2, tex1, 1D */
+ /* TEX temp2, temp2, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
@@ -830,14 +832,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp3, temp3, tex1, 1D */
+ /* TEX temp3, temp3, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
@@ -855,14 +857,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp4, temp4, tex1, 1D */
+ /* TEX temp4, temp4, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
@@ -880,14 +882,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* TEX temp5, temp5, tex1, 1D */
+ /* TEX temp5, temp5, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
@@ -956,8 +958,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_B |
@@ -1020,8 +1021,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_B |
@@ -1086,8 +1086,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
- R500_ALU_RGB_B_SWIZ_B_B |
- R500_ALU_RGB_MOD_B_NEG));
+ R500_ALU_RGB_B_SWIZ_B_B));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SWIZ_B_A));
@@ -1108,7 +1107,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
/* const1 = {0, 1 / -texture[0].height, 0, 0) */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (uint32_t)(1/pPriv->h));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (uint32_t)(-1/pPriv->h));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
commit a87647e0c27e0950f4d0d8203a1242a994ad3419
Author: Dennis Kasprzyk <onestone at compiz-fusion.org>
Date: Sun Jul 27 10:43:01 2008 -0700
Fix texture size, texture filter, vertex offsets, etc.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 94f407f..b1b28be 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -280,7 +280,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
/* Upload bicubic filter tex */
if (pPriv->bicubic_enabled)
- RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_128, (uint8_t *)(info->FB + pPriv->bicubic_offset), 128, 128, 1, 128, 4);
+ RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_128, (uint8_t *)(info->FB + pPriv->bicubic_offset), 2048, 2048, 1, 512, 4);
/* update cliplist */
if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 08dc4a4..3cf89fa 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -221,13 +221,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(0x0 << R300_TXHEIGHT_SHIFT) |
R300_TXPITCH_EN;
/* Format is 32-bit floats, 4bpp */
- txformat1 = R300_TX_FORMAT_FL_R32G32B32A32;
+ txformat1 = R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32);
/* Pitch is 127 (128-1) */
txpitch = 0x7f;
+ /* Tex filter */
+ txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP) |
+ R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP) |
+ R300_TX_MAG_FILTER_NEAREST |
+ R300_TX_MAG_FILTER_NEAREST |
+ (1 << R300_TX_ID_SHIFT);
BEGIN_VIDEO(6);
- /* No filtering */
- OUT_VIDEO_REG(R300_TX_FILTER0_1, 0);
+ OUT_VIDEO_REG(R300_TX_FILTER0_1, txfilter);
OUT_VIDEO_REG(R300_TX_FILTER1_1, 0);
OUT_VIDEO_REG(R300_TX_FORMAT0_1, txformat0);
OUT_VIDEO_REG(R300_TX_FORMAT1_1, txformat1);
@@ -397,18 +402,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_CLAMP));
FINISH_VIDEO();
} else {
- /* These are the same whether or not bicubic is enabled! */
- BEGIN_VIDEO(4);
- OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(1)));
- OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(1)));
- OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
- FINISH_VIDEO();
-
if (pPriv->bicubic_enabled) {
- BEGIN_VIDEO(3);
+ BEGIN_VIDEO(7);
/* 4 components: 2 for tex0 and 2 for tex1 */
OUT_VIDEO_REG(R300_RS_COUNT,
@@ -420,6 +415,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* Pixel stack frame size. */
OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(15));
+
+ /* FP length. */
+ OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ R500_US_CODE_END_ADDR(22)));
+ OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ R500_US_CODE_RANGE_SIZE(22)));
+
+ /* Prepare for FP emission. */
+ OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
FINISH_VIDEO();
BEGIN_VIDEO(141);
@@ -1108,8 +1113,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
FINISH_VIDEO();
+
} else {
- BEGIN_VIDEO(14);
+ BEGIN_VIDEO(19);
/* 2 components: 2 for tex0 */
OUT_VIDEO_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -1118,6 +1124,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* R300_INST_COUNT_RS - highest RS instruction used */
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+ /* Pixel stack frame size. */
+ OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(2));
+
+ /* FP length. */
+ OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ R500_US_CODE_END_ADDR(1)));
+ OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ R500_US_CODE_RANGE_SIZE(1)));
+
+ /* Prepare for FP emission. */
+ OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
+
/* tex inst */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
@@ -1426,19 +1445,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (pPriv->bicubic_enabled) {
VTX_OUT_FILTER((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
- xFixedToFloat(srcTopLeft.x) / 128, xFixedToFloat(srcTopLeft.y) / 1));
+ xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5));
VTX_OUT_FILTER((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
- xFixedToFloat(srcTopLeft.x) / 128, xFixedToFloat(srcTopLeft.y) / 1);
+ xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5);
VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth),
xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0],
- xFixedToFloat(srcBottomLeft.x) / 128, xFixedToFloat(srcBottomLeft.y) / 1);
+ xFixedToFloat(srcBottomLeft.x) + 0.5, xFixedToFloat(srcBottomLeft.y) + 0.5);
VTX_OUT_FILTER((float)(dstX + dstw), (float)(dstY + dsth),
xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0],
- xFixedToFloat(srcBottomRight.x) / 128, xFixedToFloat(srcBottomRight.y) / 1);
+ xFixedToFloat(srcBottomRight.x) + 0.5, xFixedToFloat(srcBottomRight.y) + 0.5);
VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY,
xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0],
- xFixedToFloat(srcTopRight.x) / 128, xFixedToFloat(srcTopRight.y) / 1);
+ xFixedToFloat(srcTopRight.x) + 0.5, xFixedToFloat(srcTopRight.y) + 0.5);
} else {
if (info->ChipFamily >= CHIP_FAMILY_R200)
VTX_OUT((float)dstX, (float)(dstY + dsth),
diff --git a/src/radeon_video.c b/src/radeon_video.c
index d22e00a..4f71e28 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -3261,6 +3261,10 @@ RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now)
RADEONFreeMemory(pScrn, pPriv->video_memory);
pPriv->video_memory = NULL;
}
+ if (pPriv->bicubic_memory != NULL) {
+ RADEONFreeMemory(pScrn, pPriv->bicubic_memory);
+ pPriv->bicubic_memory = NULL;
+ }
pPriv->videoStatus = 0;
info->VideoTimerCallback = NULL;
}
commit 232aa3e943fef4c4037b255c3b64a0aaff90ab5c
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Sat Jul 26 10:56:56 2008 -0700
Make vertices emit properly.
*bangs head against wall*
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 444e61e..94f407f 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -205,7 +205,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->bicubic_offset = RADEONAllocateMemory(pScrn,
&pPriv->bicubic_memory,
sizeof(bicubic_tex_128));
- pPriv->bicubic_src_offset = pPriv->video_offset + info->fbLocation + pScrn->fbOffset;
+ pPriv->bicubic_src_offset = pPriv->bicubic_offset + info->fbLocation + pScrn->fbOffset;
if (pPriv->bicubic_offset == 0)
pPriv->bicubic_enabled = FALSE;
}
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 298dc64..08dc4a4 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -45,10 +45,21 @@
#endif
#endif
+#define VTX_DWORD_COUNT_FILTER 6
#define VTX_DWORD_COUNT 4
#ifdef ACCEL_CP
+#define VTX_OUT_FILTER(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
+do { \
+ OUT_VIDEO_RING_F(_dstX); \
+ OUT_VIDEO_RING_F(_dstY); \
+ OUT_VIDEO_RING_F(_srcX); \
+ OUT_VIDEO_RING_F(_srcY); \
+ OUT_VIDEO_RING_F(_maskX); \
+ OUT_VIDEO_RING_F(_maskY); \
+} while (0)
+
#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
do { \
OUT_VIDEO_RING_F(_dstX); \
@@ -59,6 +70,16 @@ do { \
#else /* ACCEL_CP */
+#define VTX_OUT_FILTER(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
+do { \
+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _maskX); \
+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _maskY); \
+} while (0)
+
#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
do { \
OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
@@ -196,9 +217,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (pPriv->bicubic_enabled) {
/* Size is 128x1 */
- txformat0 = (0x80 << R300_TXWIDTH_SHIFT) | (0x1 << R300_TXHEIGHT_SHIFT);
+ txformat0 = (0x7f << R300_TXWIDTH_SHIFT) |
+ (0x0 << R300_TXHEIGHT_SHIFT) |
+ R300_TXPITCH_EN;
/* Format is 32-bit floats, 4bpp */
txformat1 = R300_TX_FORMAT_FL_R32G32B32A32;
+ /* Pitch is 127 (128-1) */
+ txpitch = 0x7f;
BEGIN_VIDEO(6);
/* No filtering */
@@ -206,8 +231,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R300_TX_FILTER1_1, 0);
OUT_VIDEO_REG(R300_TX_FORMAT0_1, txformat0);
OUT_VIDEO_REG(R300_TX_FORMAT1_1, txformat1);
- /* No pitch changes */
- OUT_VIDEO_REG(R300_TX_FORMAT2_1, 0);
+ OUT_VIDEO_REG(R300_TX_FORMAT2_1, txpitch);
OUT_VIDEO_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset);
FINISH_VIDEO();
@@ -216,10 +240,17 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
}
/* setup the VAP */
- if (info->has_tcl)
- BEGIN_VIDEO(6);
- else
- BEGIN_VIDEO(4);
+ if (info->has_tcl) {
+ if (pPriv->bicubic_enabled)
+ BEGIN_VIDEO(7);
+ else
+ BEGIN_VIDEO(6);
+ } else {
+ if (pPriv->bicubic_enabled)
+ BEGIN_VIDEO(5);
+ else
+ BEGIN_VIDEO(4);
+ }
/* These registers define the number, type, and location of data submitted
* to the PVS unit of GA input (when PVS is disabled)
@@ -234,7 +265,24 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
* Textures 0-7
* Fog
*/
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ if (pPriv->bicubic_enabled) {
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (6 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_SIGNED_1));
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_1,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
+ (0 << R300_SKIP_DWORDS_2_SHIFT) |
+ (7 << R300_DST_VEC_LOC_2_SHIFT) |
+ R300_LAST_VEC_2 |
+ R300_SIGNED_2));
+ } else {
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
(0 << R300_SKIP_DWORDS_0_SHIFT) |
(0 << R300_DST_VEC_LOC_0_SHIFT) |
@@ -244,6 +292,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(6 << R300_DST_VEC_LOC_1_SHIFT) |
R300_LAST_VEC_1 |
R300_SIGNED_1));
+ }
/* load the vertex shader
* We pre-load vertex programs in RADEONInit3DEngine():
@@ -272,11 +321,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* Position and one set of 2 texture coordinates */
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
- if (pPriv->bicubic_enabled)
+ if (pPriv->bicubic_enabled) {
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT) |
(2 << R300_TEX_1_COMP_CNT_SHIFT));
- else
+ } else {
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
+ }
OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt);
FINISH_VIDEO();
@@ -358,7 +408,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_VIDEO();
if (pPriv->bicubic_enabled) {
- BEGIN_VIDEO(144);
+ BEGIN_VIDEO(3);
/* 4 components: 2 for tex0 and 2 for tex1 */
OUT_VIDEO_REG(R300_RS_COUNT,
@@ -369,11 +419,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
/* Pixel stack frame size. */
- OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(16));
+ OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(15));
+ FINISH_VIDEO();
+ BEGIN_VIDEO(141);
/* Pixel shader.
* I've gone ahead and annotated each instruction, since this
* thing is MASSIVE. :3 */
+
/* TEX temp0, input0.xxxx, tex0, 1D */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
@@ -978,7 +1031,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* LRP output, temp0.zzzz, temp3, temp2 ->
* - ADD temp6, temp3, -temp2
- * - MAD temp3, temp0.zzzz, temp6, temp2 */
+ * - MAD output, temp0.zzzz, temp6, temp2 */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -1059,82 +1112,82 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
BEGIN_VIDEO(14);
/* 2 components: 2 for tex0 */
OUT_VIDEO_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
/* tex inst */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK |
- R500_INST_RGB_CLAMP |
- R500_INST_ALPHA_CLAMP));
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
- R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
- R500_TEX_IGNORE_UNCOVERED));
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_DST_ADDR(0) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
- R500_DX_S_SWIZ_R |
- R500_DX_T_SWIZ_R |
- R500_DX_R_SWIZ_R |
- R500_DX_Q_SWIZ_R |
- R500_DY_ADDR(0) |
- R500_DY_S_SWIZ_R |
- R500_DY_T_SWIZ_R |
- R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R));
+ R500_DX_S_SWIZ_R |
+ R500_DX_T_SWIZ_R |
+ R500_DX_R_SWIZ_R |
+ R500_DX_Q_SWIZ_R |
+ R500_DY_ADDR(0) |
+ R500_DY_S_SWIZ_R |
+ R500_DY_T_SWIZ_R |
+ R500_DY_R_SWIZ_R |
+ R500_DY_Q_SWIZ_R));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* ALU inst */
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_LAST |
- R500_INST_RGB_OMASK_R |
- R500_INST_RGB_OMASK_G |
- R500_INST_RGB_OMASK_B |
- R500_INST_ALPHA_OMASK |
- R500_INST_RGB_CLAMP |
- R500_INST_ALPHA_CLAMP));
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_LAST |
+ R500_INST_RGB_OMASK_R |
+ R500_INST_RGB_OMASK_G |
+ R500_INST_RGB_OMASK_B |
+ R500_INST_ALPHA_OMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR1(0) |
- R500_RGB_ADDR1_CONST |
- R500_RGB_ADDR2(0) |
- R500_RGB_ADDR2_CONST));
+ R500_RGB_ADDR1(0) |
+ R500_RGB_ADDR1_CONST |
+ R500_RGB_ADDR2(0) |
+ R500_RGB_ADDR2_CONST));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR1(0) |
- R500_ALPHA_ADDR1_CONST |
- R500_ALPHA_ADDR2(0) |
- R500_ALPHA_ADDR2_CONST));
+ R500_ALPHA_ADDR1(0) |
+ R500_ALPHA_ADDR1_CONST |
+ R500_ALPHA_ADDR2(0) |
+ R500_ALPHA_ADDR2_CONST));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC0 |
- R500_ALU_RGB_R_SWIZ_B_1 |
- R500_ALU_RGB_B_SWIZ_B_1 |
- R500_ALU_RGB_G_SWIZ_B_1));
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC0 |
+ R500_ALU_RGB_R_SWIZ_B_1 |
+ R500_ALU_RGB_B_SWIZ_B_1 |
+ R500_ALU_RGB_G_SWIZ_B_1));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SWIZ_B_1));
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_1));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 |
- R500_ALU_RGBA_G_SWIZ_0 |
- R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));
FINISH_VIDEO();
}
}
@@ -1152,7 +1205,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_VIDEO();
BEGIN_VIDEO(1);
- OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT);
+ if (pPriv->bicubic_enabled)
+ OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT_FILTER);
+ else
+ OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT);
FINISH_VIDEO();
} else {
@@ -1329,18 +1385,27 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
(3 << RADEON_CP_VC_CNTL_NUM_SHIFT));
} else {
- if (IS_R300_3D || IS_R500_3D)
- BEGIN_RING(4 * VTX_DWORD_COUNT + 4);
- else
+ if (IS_R300_3D || IS_R500_3D) {
+ if (pPriv->bicubic_enabled)
+ BEGIN_RING(4 * VTX_DWORD_COUNT_FILTER + 4);
+ else
+ BEGIN_RING(4 * VTX_DWORD_COUNT + 4);
+ } else
BEGIN_RING(4 * VTX_DWORD_COUNT + 2);
- OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
+ if (pPriv->bicubic_enabled)
+ OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
+ 4 * VTX_DWORD_COUNT_FILTER));
+ else
+ OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
4 * VTX_DWORD_COUNT));
OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST |
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
}
#else /* ACCEL_CP */
- if (IS_R300_3D || IS_R500_3D)
+ if (pPriv->bicubic_enabled)
+ BEGIN_VIDEO(2 + VTX_DWORD_COUNT_FILTER * 4);
+ else if (IS_R300_3D || IS_R500_3D)
BEGIN_VIDEO(2 + VTX_DWORD_COUNT * 4);
else if (info->ChipFamily < CHIP_FAMILY_R200)
BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 3);
@@ -1358,16 +1423,35 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(4 << RADEON_VF_NUM_VERTICES_SHIFT)));
}
#endif
- if (info->ChipFamily >= CHIP_FAMILY_R200) {
- VTX_OUT((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
- }
- VTX_OUT((float)dstX, (float)(dstY + dsth),
+ if (pPriv->bicubic_enabled) {
+ VTX_OUT_FILTER((float)dstX, (float)dstY,
+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
+ xFixedToFloat(srcTopLeft.x) / 128, xFixedToFloat(srcTopLeft.y) / 1));
+ VTX_OUT_FILTER((float)dstX, (float)dstY,
+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
+ xFixedToFloat(srcTopLeft.x) / 128, xFixedToFloat(srcTopLeft.y) / 1);
+ VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth),
+ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0],
+ xFixedToFloat(srcBottomLeft.x) / 128, xFixedToFloat(srcBottomLeft.y) / 1);
+ VTX_OUT_FILTER((float)(dstX + dstw), (float)(dstY + dsth),
+ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0],
+ xFixedToFloat(srcBottomRight.x) / 128, xFixedToFloat(srcBottomRight.y) / 1);
+ VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY,
+ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0],
+ xFixedToFloat(srcTopRight.x) / 128, xFixedToFloat(srcTopRight.y) / 1);
+ } else {
+ if (info->ChipFamily >= CHIP_FAMILY_R200)
+ VTX_OUT((float)dstX, (float)(dstY + dsth),
+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+ VTX_OUT((float)dstX, (float)dstY,
+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+ VTX_OUT((float)dstX, (float)(dstY + dsth),
xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]);
- VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth),
+ VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth),
xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0]);
- VTX_OUT((float)(dstX + dstw), (float)dstY,
+ VTX_OUT((float)(dstX + dstw), (float)dstY,
xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]);
+ }
if (IS_R300_3D || IS_R500_3D)
/* flushing is pipelined, free/finish is not */
@@ -1394,4 +1478,5 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
}
#undef VTX_OUT
+#undef VTX_OUT_FILTER
#undef FUNC_NAME
commit 8c84f67b93d926095633830aa8d95930a48b1c7b
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Sun Jul 20 14:25:44 2008 -0700
Try to get tex coords from the VAP to RS properly when bicubic filtering is enabled.
I'm soo bad at this... :c
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 6c0890f..444e61e 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -200,7 +200,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
}
/* Bicubic filter loading */
- pPriv->bicubic_enabled = TRUE;
+ pPriv->bicubic_enabled = IS_R500_3D;
if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) {
pPriv->bicubic_offset = RADEONAllocateMemory(pScrn,
&pPriv->bicubic_memory,
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 2807422..298dc64 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -247,23 +247,36 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
/* load the vertex shader
* We pre-load vertex programs in RADEONInit3DEngine():
- * - exa no mask
+ * - exa no mask/Xv bicubic
* - exa mask
* - Xv
* Here we select the offset of the vertex program we want to use
*/
if (info->has_tcl) {
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
+ if (pPriv->bicubic_enabled) {
+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (2 << R300_PVS_LAST_INST_SHIFT)));
+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
+ (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ } else {
+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
((5 << R300_PVS_FIRST_INST_SHIFT) |
(6 << R300_PVS_XYZW_VALID_INST_SHIFT) |
(6 << R300_PVS_LAST_INST_SHIFT)));
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
(6 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ }
}
/* Position and one set of 2 texture coordinates */
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
+ if (pPriv->bicubic_enabled)
+ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT) |
+ (2 << R300_TEX_1_COMP_CNT_SHIFT));
+ else
+ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt);
FINISH_VIDEO();
@@ -345,19 +358,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_VIDEO();
if (pPriv->bicubic_enabled) {
- BEGIN_VIDEO(142);
- /* This one's set in RADEONInit3DEngine, but we need to set
- * it again, in order to enable all four components! */
-// OUT_VIDEO_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
-// (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
-// (4 << R500_RS_IP_TEX_PTR_R_SHIFT) |
-// (5 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
- /* 6 tex components; 2 from tex0 and all four from tex1 */
-// OUT_VIDEO_REG(R300_RS_COUNT,
-// ((6 << R300_RS_COUNT_IT_COUNT_SHIFT) |
-// R300_RS_COUNT_HIRES_EN));
-// OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) |
-// R300_TX_OFFSET_RS(6));
+ BEGIN_VIDEO(144);
+
+ /* 4 components: 2 for tex0 and 2 for tex1 */
+ OUT_VIDEO_REG(R300_RS_COUNT,
+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+
+ /* R300_INST_COUNT_RS - highest RS instruction used */
+ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
/* Pixel stack frame size. */
OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(16));
commit a4a7d5f5967c51c394229de5eccaec44cfec8f50
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Sat Jul 19 13:02:02 2008 -0700
Upload pixel shader to card for r5xx. This was ridiculous. Also it doesn't work yet...
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 1d35236..8b47dba 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4346,6 +4346,7 @@
#define R300_TX_INVALTAGS 0x4100
#define R300_TX_FILTER0_0 0x4400
+#define R300_TX_FILTER0_1 0x4404
# define R300_TX_CLAMP_S(x) (x << 0)
# define R300_TX_CLAMP_T(x) (x << 3)
# define R300_TX_CLAMP_R(x) (x << 6)
@@ -4363,7 +4364,9 @@
# define R300_TX_MIN_FILTER_LINEAR (2 << 11)
# define R300_TX_ID_SHIFT 28
#define R300_TX_FILTER1_0 0x4440
+#define R300_TX_FILTER1_1 0x4444
#define R300_TX_FORMAT0_0 0x4480
+#define R300_TX_FORMAT0_1 0x4484
# define R300_TXWIDTH_SHIFT 0
# define R300_TXHEIGHT_SHIFT 11
# define R300_NUM_LEVELS_SHIFT 26
@@ -4371,6 +4374,7 @@
# define R300_TXPROJECTED (1 << 30)
# define R300_TXPITCH_EN (1 << 31)
#define R300_TX_FORMAT1_0 0x44c0
+#define R300_TX_FORMAT1_1 0x44c4
# define R300_TX_FORMAT_X8 0x0
# define R300_TX_FORMAT_X16 0x1
# define R300_TX_FORMAT_Y4X4 0x2
@@ -4444,10 +4448,12 @@
# define R300_TX_FORMAT_SWAP_YUV (1 << 24)
#define R300_TX_FORMAT2_0 0x4500
+#define R300_TX_FORMAT2_1 0x4504
# define R500_TXWIDTH_11 (1 << 15)
# define R500_TXHEIGHT_11 (1 << 16)
#define R300_TX_OFFSET_0 0x4540
+#define R300_TX_OFFSET_1 0x4544
# define R300_ENDIAN_SWAP_16_BIT (1 << 0)
# define R300_ENDIAN_SWAP_32_BIT (2 << 0)
# define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 15f1c5c..6c0890f 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -205,6 +205,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->bicubic_offset = RADEONAllocateMemory(pScrn,
&pPriv->bicubic_memory,
sizeof(bicubic_tex_128));
+ pPriv->bicubic_src_offset = pPriv->video_offset + info->fbLocation + pScrn->fbOffset;
if (pPriv->bicubic_offset == 0)
pPriv->bicubic_enabled = FALSE;
}
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index d39f74d..2807422 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -194,6 +194,27 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txenable = R300_TEX_0_ENABLE;
+ if (pPriv->bicubic_enabled) {
+ /* Size is 128x1 */
+ txformat0 = (0x80 << R300_TXWIDTH_SHIFT) | (0x1 << R300_TXHEIGHT_SHIFT);
+ /* Format is 32-bit floats, 4bpp */
+ txformat1 = R300_TX_FORMAT_FL_R32G32B32A32;
+
+ BEGIN_VIDEO(6);
+ /* No filtering */
+ OUT_VIDEO_REG(R300_TX_FILTER0_1, 0);
+ OUT_VIDEO_REG(R300_TX_FILTER1_1, 0);
+ OUT_VIDEO_REG(R300_TX_FORMAT0_1, txformat0);
+ OUT_VIDEO_REG(R300_TX_FORMAT1_1, txformat1);
+ /* No pitch changes */
+ OUT_VIDEO_REG(R300_TX_FORMAT2_1, 0);
+ OUT_VIDEO_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset);
+ FINISH_VIDEO();
+
+ /* Enable tex 1 */
+ txenable |= R300_TEX_1_ENABLE;
+ }
+
/* setup the VAP */
if (info->has_tcl)
BEGIN_VIDEO(6);
@@ -313,24 +334,730 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_CLAMP));
FINISH_VIDEO();
} else {
- BEGIN_VIDEO(18);
- /* 2 components: 2 for tex0 */
- OUT_VIDEO_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
-
- /* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
-
+ /* These are the same whether or not bicubic is enabled! */
+ BEGIN_VIDEO(4);
OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(1)));
+ R500_US_CODE_END_ADDR(1)));
OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(1)));
+ R500_US_CODE_RANGE_SIZE(1)));
OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
+ FINISH_VIDEO();
+
+ if (pPriv->bicubic_enabled) {
+ BEGIN_VIDEO(142);
+ /* This one's set in RADEONInit3DEngine, but we need to set
+ * it again, in order to enable all four components! */
+// OUT_VIDEO_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+// (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+// (4 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+// (5 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+ /* 6 tex components; 2 from tex0 and all four from tex1 */
+// OUT_VIDEO_REG(R300_RS_COUNT,
+// ((6 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+// R300_RS_COUNT_HIRES_EN));
+// OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) |
+// R300_TX_OFFSET_RS(6));
+
+ /* Pixel stack frame size. */
+ OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(16));
+
+ /* Pixel shader.
+ * I've gone ahead and annotated each instruction, since this
+ * thing is MASSIVE. :3 */
+ /* TEX temp0, input0.xxxx, tex0, 1D */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_R |
+ R500_TEX_SRC_R_SWIZ_R |
+ R500_TEX_SRC_Q_SWIZ_R |
+ R500_TEX_DST_ADDR(2) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+
+ /* TEX temp1, input0.yyyy, tex0, 1D */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_G |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_SRC_R_SWIZ_G |
+ R500_TEX_SRC_Q_SWIZ_G |
+ R500_TEX_DST_ADDR(3) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+
+ /* MUL temp2, const0, temp0.yyyy */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_G |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_G));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_G));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));
+
+ /* MUL temp3, const0, -temp0.xxxx */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_R |
+ R500_ALU_RGB_B_SWIZ_B_R |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_R |
+ R500_ALPHA_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));
+
+ /* MAD temp4, const1, temp1.yyyy, temp2 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(3) |
+ R500_RGB_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(3) |
+ R500_ALPHA_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_G |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_G));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_G));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* MAD temp5, const1, temp1.yyyy, temp3 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(3) |
+ R500_RGB_ADDR2(5)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(3) |
+ R500_ALPHA_ADDR2(5)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_G |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_G));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_G));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* MAD temp2, const1, -temp1.xxxx, temp2 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(3) |
+ R500_RGB_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(3) |
+ R500_ALPHA_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_R |
+ R500_ALU_RGB_B_SWIZ_B_R |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_R));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* MAD temp3, const1, -temp1.xxxx, temp3 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
+ R500_RGB_ADDR0_CONST |
+ R500_RGB_ADDR1(3) |
+ R500_RGB_ADDR2(5)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
+ R500_ALPHA_ADDR0_CONST |
+ R500_ALPHA_ADDR1(3) |
+ R500_ALPHA_ADDR2(5)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_R |
+ R500_ALU_RGB_B_SWIZ_B_R |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_R));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* ADD temp2, temp2, input0 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
+ R500_RGB_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
+ R500_ALPHA_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* ADD temp3, temp3, input0 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(5) |
+ R500_RGB_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(5) |
+ R500_ALPHA_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* ADD temp4, temp4, input0 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(6) |
+ R500_RGB_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(6) |
+ R500_ALPHA_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* ADD temp5, temp5, input0 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(7) |
+ R500_RGB_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(7) |
+ R500_ALPHA_ADDR2(0)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* TEX temp2, temp2, tex1, 1D */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(4) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_SRC_R_SWIZ_B |
+ R500_TEX_SRC_Q_SWIZ_A |
+ R500_TEX_DST_ADDR(4) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* tex inst */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ /* TEX temp3, temp3, tex1, 1D */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(5) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_SRC_R_SWIZ_B |
+ R500_TEX_SRC_Q_SWIZ_A |
+ R500_TEX_DST_ADDR(5) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+
+ /* TEX temp4, temp4, tex1, 1D */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(6) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_SRC_R_SWIZ_B |
+ R500_TEX_SRC_Q_SWIZ_A |
+ R500_TEX_DST_ADDR(6) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+
+ /* TEX temp5, temp5, tex1, 1D */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(7) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_SRC_R_SWIZ_B |
+ R500_TEX_SRC_Q_SWIZ_A |
+ R500_TEX_DST_ADDR(7) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+
+ /* LRP temp3, temp1.zzzz, temp3, temp5 ->
+ * - ADD temp6, temp3, -temp5
+ * - MAD temp3, temp1.zzzz, temp6, temp5 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(5) |
+ R500_RGB_ADDR2(7)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(5) |
+ R500_ALPHA_ADDR2(7)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(8) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(8) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A |
+ R500_ALU_RGBA_ALPHA_MOD_C_NEG));
+ /* 2nd inst */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
+ R500_RGB_ADDR1(8) |
+ R500_RGB_ADDR2(7)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
+ R500_ALPHA_ADDR1(8) |
+ R500_ALPHA_ADDR2(7)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_B |
+ R500_ALU_RGB_G_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* LRP temp2, temp1.zzzz, temp2, temp4 ->
+ * - ADD temp6, temp2, -temp4
+ * - MAD temp2, temp1.zzzz, temp6, temp4 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
+ R500_RGB_ADDR2(6)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
+ R500_ALPHA_ADDR2(6)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(8) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(8) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A |
+ R500_ALU_RGBA_ALPHA_MOD_C_NEG));
+ /* 2nd inst */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
+ R500_RGB_ADDR1(8) |
+ R500_RGB_ADDR2(6)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
+ R500_ALPHA_ADDR1(8) |
+ R500_ALPHA_ADDR2(6)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_B |
+ R500_ALU_RGB_G_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* LRP output, temp0.zzzz, temp3, temp2 ->
+ * - ADD temp6, temp3, -temp2
+ * - MAD temp3, temp0.zzzz, temp6, temp2 */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(5) |
+ R500_RGB_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(5) |
+ R500_ALPHA_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1 |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(8) |
+ R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_1 |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(8) |
+ R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A |
+ R500_ALU_RGBA_ALPHA_MOD_C_NEG));
+ /* 2nd inst */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ R500_INST_LAST |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) |
+ R500_RGB_ADDR1(8) |
+ R500_RGB_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(2) |
+ R500_ALPHA_ADDR1(8) |
+ R500_ALPHA_ADDR2(4)));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_B |
+ R500_ALU_RGB_G_SWIZ_A_B |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B |
+ R500_ALU_RGB_MOD_B_NEG));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_B |
+ R500_ALPHA_SWIZ_B_A));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_SEL_C_SRC2 |
+ R500_ALU_RGBA_R_SWIZ_R |
+ R500_ALU_RGBA_G_SWIZ_G |
+ R500_ALU_RGBA_B_SWIZ_B |
+ R500_ALU_RGBA_A_SWIZ_A));
+
+ /* Shader constants. */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, (1 << 16));
+
+ /* const0 = {1 / texture[0].width, 0, 0, 0} */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (uint32_t)(1/pPriv->w));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
+ /* const1 = {0, 1 / -texture[0].height, 0, 0) */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (uint32_t)(1/pPriv->h));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0);
+
+ FINISH_VIDEO();
+ } else {
+ BEGIN_VIDEO(14);
+ /* 2 components: 2 for tex0 */
+ OUT_VIDEO_REG(R300_RS_COUNT,
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+
+ /* R300_INST_COUNT_RS - highest RS instruction used */
+ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+
+ /* tex inst */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -338,13 +1065,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_WMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
-
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
-
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_DST_ADDR(0) |
@@ -352,7 +1077,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
R500_DX_S_SWIZ_R |
R500_DX_T_SWIZ_R |
R500_DX_R_SWIZ_R |
@@ -362,11 +1087,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
R500_DY_Q_SWIZ_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- /* ALU inst */
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ /* ALU inst */
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
R500_INST_RGB_OMASK_R |
@@ -375,19 +1100,17 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_ALPHA_OMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
-
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR1(0) |
R500_RGB_ADDR1_CONST |
R500_RGB_ADDR2(0) |
R500_RGB_ADDR2_CONST));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR1_CONST |
R500_ALPHA_ADDR2(0) |
R500_ALPHA_ADDR2_CONST));
-
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -395,17 +1118,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1 |
R500_ALU_RGB_G_SWIZ_B_1));
-
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_A |
R500_ALPHA_SWIZ_B_1));
-
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0));
- FINISH_VIDEO();
+ FINISH_VIDEO();
+ }
}
BEGIN_VIDEO(5);
diff --git a/src/radeon_video.h b/src/radeon_video.h
index e81ac94..b9ead1c 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -95,6 +95,7 @@ typedef struct {
void *bicubic_memory;
int bicubic_offset;
Bool bicubic_enabled;
+ uint32_t bicubic_src_offset;
Atom device_id, location_id, instance_id;
commit 20c1db2d7c110ab5c1117a57b169baa1ab070518
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Fri Jul 18 13:48:08 2008 -0700
Upload bicubic filter to card. This was a LOT easier than I had feared, to be honest.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 1e4ce1d..15f1c5c 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -200,7 +200,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
}
/* Bicubic filter loading */
- if (pPriv->bicubic_memory == NULL) {
+ pPriv->bicubic_enabled = TRUE;
+ if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) {
pPriv->bicubic_offset = RADEONAllocateMemory(pScrn,
&pPriv->bicubic_memory,
sizeof(bicubic_tex_128));
@@ -276,6 +277,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
break;
}
+ /* Upload bicubic filter tex */
+ if (pPriv->bicubic_enabled)
+ RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_128, (uint8_t *)(info->FB + pPriv->bicubic_offset), 128, 128, 1, 128, 4);
+
/* update cliplist */
if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes);
commit a760e628134c6d7d42ec3c98118b6e5f6fcd3e7f
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Fri Jul 18 12:21:20 2008 -0700
Allocate memory for the bicubic filter texture.
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index cfa349d..1e4ce1d 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -199,6 +199,15 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
return BadAlloc;
}
+ /* Bicubic filter loading */
+ if (pPriv->bicubic_memory == NULL) {
+ pPriv->bicubic_offset = RADEONAllocateMemory(pScrn,
+ &pPriv->bicubic_memory,
+ sizeof(bicubic_tex_128));
+ if (pPriv->bicubic_offset == 0)
+ pPriv->bicubic_enabled = FALSE;
+ }
+
if (pDraw->type == DRAWABLE_WINDOW)
pPriv->pPixmap = (*pScreen->GetWindowPixmap)((WindowPtr)pDraw);
else
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 57dcd8a..d22e00a 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -1678,6 +1678,10 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup)
RADEONFreeMemory(pScrn, pPriv->video_memory);
pPriv->video_memory = NULL;
}
+ if (pPriv->bicubic_memory != NULL) {
+ RADEONFreeMemory(pScrn, pPriv->bicubic_memory);
+ pPriv->bicubic_memory = NULL;
+ }
pPriv->videoStatus = 0;
} else {
if(pPriv->videoStatus & CLIENT_VIDEO_ON) {
diff --git a/src/radeon_video.h b/src/radeon_video.h
index 096de37..e81ac94 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -13,6 +13,8 @@
#include "xf86Crtc.h"
+#include "bicubic_table.h"
+
/* Xvideo port struct */
typedef struct {
uint32_t transform_index;
@@ -37,7 +39,7 @@ typedef struct {
uint32_t radeon_N;
uint32_t i2c_status;
uint32_t i2c_cntl;
-
+
FI1236Ptr fi1236;
uint8_t tuner_type;
MSP3430Ptr msp3430;
@@ -46,7 +48,7 @@ typedef struct {
/* VIP bus and devices */
GENERIC_BUS_Ptr VIP;
- TheatrePtr theatre;
+ TheatrePtr theatre;
Bool video_stream_active;
int encoding;
@@ -56,7 +58,7 @@ typedef struct {
int sap_channel;
int v;
uint32_t adjustment; /* general purpose variable */
-
+
#define METHOD_BOB 0
#define METHOD_SINGLE 1
#define METHOD_WEAVE 2
@@ -89,6 +91,11 @@ typedef struct {
void *video_memory;
int video_offset;
+ /* bicubic filtering */
+ void *bicubic_memory;
+ int bicubic_offset;
+ Bool bicubic_enabled;
+
Atom device_id, location_id, instance_id;
/* textured video */
commit b6c9e2bb5365de82315c6814f915e57b0c4fa444
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Fri Jul 18 11:24:14 2008 -0700
Fixed typos in the bicubic texture tables. Whoops, looks like I'm still asleep.
diff --git a/src/bicubic_table.h b/src/bicubic_table.h
index b61b9ba..721af1a 100644
--- a/src/bicubic_table.h
+++ b/src/bicubic_table.h
@@ -1,4 +1,4 @@
-const float[] bicubic_tex = {
+static const float bicubic_tex_128[] = {
0.2, 1.0, 0.833333333333, 0.166666666667,
0.204088720925, 0.992187965834, 0.829396724701, 0.170603275299,
0.208229306439, 0.984378641369, 0.825400034587, 0.174599965413,
@@ -127,4 +127,4 @@ const float[] bicubic_tex = {
0.976574510623, 0.212420907874, 0.178655783335, 0.821344216665,
0.984378641369, 0.208229306439, 0.174599965413, 0.825400034587,
0.992187965834, 0.204088720925, 0.170603275299, 0.829396724701,
- NULL }
+ 0 };
diff --git a/src/bicubic_table.py b/src/bicubic_table.py
index 4510117..d9b3c46 100755
--- a/src/bicubic_table.py
+++ b/src/bicubic_table.py
@@ -29,10 +29,10 @@ def printrow(l, offset):
l = texgen()
-print "const float[] bicubic_tex = {"
+print "static const float bicubic_tex_128[] = {"
for i in range(0, 512, 4):
print printrow(l, i)
-print "\tNULL }"
+print "\t0 };"
commit ca51f4f37e1dbf53bf7ffc0e8f612e9609e11209
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Fri Jul 18 11:06:34 2008 -0700
Add bicubic texture table, as well as the script used to (re)generate it. To regenerate, just run "python bicubic_table.py > bicubic_table.h".
diff --git a/src/bicubic_table.h b/src/bicubic_table.h
new file mode 100644
index 0000000..b61b9ba
--- /dev/null
+++ b/src/bicubic_table.h
@@ -0,0 +1,130 @@
+const float[] bicubic_tex = {
+ 0.2, 1.0, 0.833333333333, 0.166666666667,
+ 0.204088720925, 0.992187965834, 0.829396724701, 0.170603275299,
+ 0.208229306439, 0.984378641369, 0.825400034587, 0.174599965413,
+ 0.212420907874, 0.976574510623, 0.821344216665, 0.178655783335,
+ 0.216662699005, 0.968777828797, 0.817230224609, 0.182769775391,
+ 0.220953875426, 0.960990640339, 0.813059012095, 0.186940987905,
+ 0.225293653935, 0.953214795864, 0.808831532796, 0.191168467204,
+ 0.229681271957, 0.945451967972, 0.804548740387, 0.195451259613,
+ 0.234115986983, 0.937703665988, 0.800211588542, 0.199788411458,
+ 0.238597076022, 0.929971249668, 0.795821030935, 0.204178969065,
+ 0.243123835089, 0.922255941932, 0.79137802124, 0.20862197876,
+ 0.247695578698, 0.914558840653, 0.786883513133, 0.213116486867,
+ 0.252311639383, 0.90688092957, 0.782338460286, 0.217661539714,
+ 0.256971367229, 0.899223088369, 0.777743816376, 0.222256183624,
+ 0.261674129428, 0.891586101989, 0.773100535075, 0.226899464925,
+ 0.266419309847, 0.883970669194, 0.768409570058, 0.231590429942,
+ 0.27120630861, 0.876377410468, 0.763671875, 0.236328125,
+ 0.276034541704, 0.868806875283, 0.758888403575, 0.241111596425,
+ 0.280903440584, 0.861259548768, 0.754060109456, 0.245939890544,
+ 0.285812451814, 0.853735857846, 0.74918794632, 0.25081205368,
+ 0.290761036698, 0.846236176857, 0.744272867839, 0.255727132161,
+ 0.295748670944, 0.838760832722, 0.739315827688, 0.260684172312,
+ 0.300774844327, 0.831310109672, 0.734317779541, 0.265682220459,
+ 0.305839060373, 0.823884253585, 0.729279677073, 0.270720322927,
+ 0.310940836049, 0.816483475952, 0.724202473958, 0.275797526042,
+ 0.316079701469, 0.80910795751, 0.719087123871, 0.280912876129,
+ 0.321255199604, 0.801757851568, 0.713934580485, 0.286065419515,
+ 0.326466886014, 0.794433287044, 0.708745797475, 0.291254202525,
+ 0.331714328576, 0.787134371247, 0.703521728516, 0.296478271484,
+ 0.336997107235, 0.779861192413, 0.698263327281, 0.301736672719,
+ 0.342314813753, 0.772613822026, 0.692971547445, 0.307028452555,
+ 0.347667051478, 0.76539231694, 0.687647342682, 0.312352657318,
+ 0.353053435115, 0.758196721311, 0.682291666667, 0.317708333333,
+ 0.358473590501, 0.751027068365, 0.676905473073, 0.323094526927,
+ 0.363927154404, 0.743883382007, 0.671489715576, 0.328510284424,
+ 0.369413774313, 0.736765678299, 0.66604534785, 0.33395465215,
+ 0.374933108243, 0.729673966794, 0.660573323568, 0.339426676432,
+ 0.380484824551, 0.722608251764, 0.655074596405, 0.344925403595,
+ 0.386068601748, 0.715568533318, 0.649550120036, 0.350449879964,
+ 0.391684128331, 0.708554808415, 0.644000848134, 0.355999151866,
+ 0.397331102613, 0.701567071798, 0.638427734375, 0.361572265625,
+ 0.403009232558, 0.694605316836, 0.632831732432, 0.367168267568,
+ 0.40871823563, 0.687669536295, 0.62721379598, 0.37278620402,
+ 0.414457838638, 0.680759723045, 0.621574878693, 0.378425121307,
+ 0.420227777594, 0.673875870699, 0.615915934245, 0.384084065755,
+ 0.426027797575, 0.6670179742, 0.610237916311, 0.389762083689,
+ 0.431857652583, 0.66018603035, 0.604541778564, 0.395458221436,
+ 0.437717105418, 0.653380038302, 0.598828474681, 0.401171525319,
+ 0.443605927552, 0.6466, 0.593098958333, 0.406901041667,
+ 0.449523899007, 0.639845920588, 0.587354183197, 0.412645816803,
+ 0.455470808236, 0.633117808778, 0.581595102946, 0.418404897054,
+ 0.461446452007, 0.626415677192, 0.575822671254, 0.424177328746,
+ 0.467450635295, 0.619739542669, 0.570037841797, 0.429962158203,
+ 0.473483171168, 0.613089426553, 0.564241568247, 0.435758431753,
+ 0.479543880687, 0.606465354949, 0.558434804281, 0.441565195719,
+ 0.485632592794, 0.59986735897, 0.552618503571, 0.447381496429,
+ 0.491749144218, 0.593295474951, 0.546793619792, 0.453206380208,
+ 0.497893379365, 0.586749744657, 0.540961106618, 0.459038893382,
+ 0.504065150224, 0.580230215471, 0.535121917725, 0.464878082275,
+ 0.510264316266, 0.573736940568, 0.529277006785, 0.470722993215,
+ 0.51649074434, 0.567269979082, 0.523427327474, 0.476572672526,
+ 0.522744308578, 0.560829396251, 0.517573833466, 0.482426166534,
+ 0.529024890292, 0.554415263567, 0.511717478434, 0.488282521566,
+ 0.535332377868, 0.548027658908, 0.505859216054, 0.494140783946,
+ 0.541666666667, 0.541666666667, 0.5, 0.5,
+ 0.548027658908, 0.535332377868, 0.494140783946, 0.505859216054,
+ 0.554415263567, 0.529024890292, 0.488282521566, 0.511717478434,
+ 0.560829396251, 0.522744308578, 0.482426166534, 0.517573833466,
+ 0.567269979082, 0.51649074434, 0.476572672526, 0.523427327474,
+ 0.573736940568, 0.510264316266, 0.470722993215, 0.529277006785,
+ 0.580230215471, 0.504065150224, 0.464878082275, 0.535121917725,
+ 0.586749744657, 0.497893379365, 0.459038893382, 0.540961106618,
+ 0.593295474951, 0.491749144218, 0.453206380208, 0.546793619792,
+ 0.59986735897, 0.485632592794, 0.447381496429, 0.552618503571,
+ 0.606465354949, 0.479543880687, 0.441565195719, 0.558434804281,
+ 0.613089426553, 0.473483171168, 0.435758431753, 0.564241568247,
+ 0.619739542669, 0.467450635295, 0.429962158203, 0.570037841797,
+ 0.626415677192, 0.461446452007, 0.424177328746, 0.575822671254,
+ 0.633117808778, 0.455470808236, 0.418404897054, 0.581595102946,
+ 0.639845920588, 0.449523899007, 0.412645816803, 0.587354183197,
+ 0.6466, 0.443605927552, 0.406901041667, 0.593098958333,
+ 0.653380038302, 0.437717105418, 0.401171525319, 0.598828474681,
+ 0.66018603035, 0.431857652583, 0.395458221436, 0.604541778564,
+ 0.6670179742, 0.426027797575, 0.389762083689, 0.610237916311,
+ 0.673875870699, 0.420227777594, 0.384084065755, 0.615915934245,
+ 0.680759723045, 0.414457838638, 0.378425121307, 0.621574878693,
+ 0.687669536295, 0.40871823563, 0.37278620402, 0.62721379598,
+ 0.694605316836, 0.403009232558, 0.367168267568, 0.632831732432,
+ 0.701567071798, 0.397331102613, 0.361572265625, 0.638427734375,
+ 0.708554808415, 0.391684128331, 0.355999151866, 0.644000848134,
+ 0.715568533318, 0.386068601748, 0.350449879964, 0.649550120036,
+ 0.722608251764, 0.380484824551, 0.344925403595, 0.655074596405,
+ 0.729673966794, 0.374933108243, 0.339426676432, 0.660573323568,
+ 0.736765678299, 0.369413774313, 0.33395465215, 0.66604534785,
+ 0.743883382007, 0.363927154404, 0.328510284424, 0.671489715576,
+ 0.751027068365, 0.358473590501, 0.323094526927, 0.676905473073,
+ 0.758196721311, 0.353053435115, 0.317708333333, 0.682291666667,
+ 0.76539231694, 0.347667051478, 0.312352657318, 0.687647342682,
+ 0.772613822026, 0.342314813753, 0.307028452555, 0.692971547445,
+ 0.779861192413, 0.336997107235, 0.301736672719, 0.698263327281,
+ 0.787134371247, 0.331714328576, 0.296478271484, 0.703521728516,
+ 0.794433287044, 0.326466886014, 0.291254202525, 0.708745797475,
+ 0.801757851568, 0.321255199604, 0.286065419515, 0.713934580485,
+ 0.80910795751, 0.316079701469, 0.280912876129, 0.719087123871,
+ 0.816483475952, 0.310940836049, 0.275797526042, 0.724202473958,
+ 0.823884253585, 0.305839060373, 0.270720322927, 0.729279677073,
+ 0.831310109672, 0.300774844327, 0.265682220459, 0.734317779541,
+ 0.838760832722, 0.295748670944, 0.260684172312, 0.739315827688,
+ 0.846236176857, 0.290761036698, 0.255727132161, 0.744272867839,
+ 0.853735857846, 0.285812451814, 0.25081205368, 0.74918794632,
+ 0.861259548768, 0.280903440584, 0.245939890544, 0.754060109456,
+ 0.868806875283, 0.276034541704, 0.241111596425, 0.758888403575,
+ 0.876377410468, 0.27120630861, 0.236328125, 0.763671875,
+ 0.883970669194, 0.266419309847, 0.231590429942, 0.768409570058,
+ 0.891586101989, 0.261674129428, 0.226899464925, 0.773100535075,
+ 0.899223088369, 0.256971367229, 0.222256183624, 0.777743816376,
+ 0.90688092957, 0.252311639383, 0.217661539714, 0.782338460286,
+ 0.914558840653, 0.247695578698, 0.213116486867, 0.786883513133,
+ 0.922255941932, 0.243123835089, 0.20862197876, 0.79137802124,
+ 0.929971249668, 0.238597076022, 0.204178969065, 0.795821030935,
+ 0.937703665988, 0.234115986983, 0.199788411458, 0.800211588542,
+ 0.945451967972, 0.229681271957, 0.195451259613, 0.804548740387,
+ 0.953214795864, 0.225293653935, 0.191168467204, 0.808831532796,
+ 0.960990640339, 0.220953875426, 0.186940987905, 0.813059012095,
+ 0.968777828797, 0.216662699005, 0.182769775391, 0.817230224609,
+ 0.976574510623, 0.212420907874, 0.178655783335, 0.821344216665,
+ 0.984378641369, 0.208229306439, 0.174599965413, 0.825400034587,
+ 0.992187965834, 0.204088720925, 0.170603275299, 0.829396724701,
+ NULL }
diff --git a/src/bicubic_table.py b/src/bicubic_table.py
new file mode 100755
index 0000000..4510117
--- /dev/null
+++ b/src/bicubic_table.py
@@ -0,0 +1,38 @@
+#!/usr/bin/python
+
+def texgen():
+
+ tex = []
+
+ for i in range(0,512,4):
+
+ a = i / 512.0
+ a2 = a ** 2
+ a3 = a ** 3
+
+ w0 = 1 / 6.0 * (-a3 + 3 * a2 + -3 * a + 1)
+ w1 = 1 / 6.0 * (3 * a3 + -6 * a2 + 4)
+ w2 = 1 / 6.0 * (-3 * a3 + 3 * a2 + 3 * a + 1)
+ w3 = 1 / 6.0 * a3
+
+ tex.append(1 - (w1 / (w0 + w1)) + a)
+ tex.append(1 + (w3 / (w2 + w3)) - a)
+ tex.append(w0 + w1)
+ tex.append(w2 + w3)
+
+ return tex
+
+def printrow(l, offset):
+
+ seq = [ str(i) for i in l[offset:offset+4] ]
+ return "\t" + ", ".join(seq) + ","
+
+l = texgen()
+
+print "const float[] bicubic_tex = {"
+
+for i in range(0, 512, 4):
+
+ print printrow(l, i)
+
+print "\tNULL }"
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