xf86-video-intel: Branch 'drm-gem' - src/i965_render.c

[Jesse Barnes]

 src/i965_render.c |   34 +++++++++-------------------------
 1 file changed, 9 insertions(+), 25 deletions(-)

New commits:
commit 5c9a62a29f62a9ecce37fae98cb01f8217eaba15
Author: Jesse Barnes <jbarnes at virtuousgeek.org>
Date:   Wed Aug 6 12:39:03 2008 -0700

    Revert "Switch to using a buffer object for the vertex buffer"
    
    This reverts commit 1abf4d3a7a203ff5d6e5ceda29573e7fd69ddf8e.
    
    Conflicts:
    
    	src/i965_render.c - flushing was removed, keep it that way

diff --git a/src/i965_render.c b/src/i965_render.c
index 62d0035..391e063 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -37,7 +37,6 @@
 #include "xf86.h"
 #include "i830.h"
 #include "i915_reg.h"
-#include "i915_drm.h"
 
 /* bring in brw structs */
 #include "brw_defines.h"
@@ -61,7 +60,7 @@ do { 							\
 #endif
 
 #define MAX_VERTEX_PER_COMPOSITE    24
-#define VERTEX_BUFFER_SIZE	    (16 * MAX_VERTEX_PER_COMPOSITE)
+#define MAX_VERTEX_BUFFERS	    256
 
 struct blendinfo {
     Bool dst_alpha;
@@ -503,14 +502,14 @@ typedef struct _gen4_state {
 				     [BRW_BLENDFACTOR_COUNT];
     struct brw_cc_viewport cc_viewport;
     PAD64 (brw_cc_viewport, 0);
+
+    float vb[MAX_VERTEX_PER_COMPOSITE * MAX_VERTEX_BUFFERS];
 } gen4_state_t;
 
 /** Private data for gen4 render accel implementation. */
 struct gen4_render_state {
     gen4_state_t *card_state;
     uint32_t card_state_offset;
-    dri_bo *vb_bo;
-    int vb_bo_busy;
 
     int binding_table_index;
     int surface_state_index;
@@ -1271,11 +1270,12 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
 {
     ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
     I830Ptr pI830 = I830PTR(pScrn);
+    gen4_state_t *card_state = pI830->gen4_render_state->card_state;
     struct gen4_render_state *render_state = pI830->gen4_render_state;
     Bool has_mask;
     Bool is_affine_src, is_affine_mask, is_affine;
     float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
-    float *vb;
+    float *vb = card_state->vb;
     int i;
 
     is_affine_src = i830_transform_is_affine (pI830->transform[0]);
@@ -1352,25 +1352,11 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
 	}
     }
 
-    /* Arrange for a buffer object with sufficient space for our
-     * vertices, and that isn't "busy", that is, it is not already
-     * referenced by a batch that has been flushed. */
-    if (! render_state->vb_bo || render_state->vb_bo_busy ||
-	render_state->vb_offset + MAX_VERTEX_PER_COMPOSITE > VERTEX_BUFFER_SIZE)
-    {
-	if (render_state->vb_bo)
-	    dri_bo_unreference (render_state->vb_bo);
-
-	render_state->vb_bo = dri_bo_alloc (pI830->bufmgr, "vb",
-					    VERTEX_BUFFER_SIZE * sizeof (float),
-					    4096);
+    if (render_state->vb_offset + MAX_VERTEX_PER_COMPOSITE >= ARRAY_SIZE(card_state->vb)) {
+	i830WaitSync(pScrn);
 	render_state->vb_offset = 0;
     }
 
-    /* Map the vertex buffer object so we can write to it. */
-    dri_bo_map (render_state->vb_bo, 1);
-    vb = render_state->vb_bo->virtual;
-
     i = render_state->vb_offset;
     /* rect (x2,y2) */
     vb[i++] = (float)(dstX + w);
@@ -1413,9 +1399,7 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
 	if (!is_affine)
 	    vb[i++] = mask_w[0];
     }
-    assert (i <= VERTEX_BUFFER_SIZE);
-
-    dri_bo_unmap (render_state->vb_bo);
+    assert (i * 4 <= sizeof(card_state->vb));
 
     BEGIN_BATCH(12);
     OUT_BATCH(MI_FLUSH);
@@ -1424,7 +1408,7 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
     OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
 	      VB0_VERTEXDATA |
 	      (render_state->vertex_size << VB0_BUFFER_PITCH_SHIFT));
-    OUT_RELOC(render_state->vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
+    OUT_BATCH(render_state->card_state_offset + offsetof(gen4_state_t, vb) +
 	      render_state->vb_offset * 4);
     OUT_BATCH(3);
     OUT_BATCH(0); // ignore for VERTEXDATA, but still there