xf86-video-intel: src/i830_display.c

[Jesse Barnes]

 src/i830_display.c |    1 +
 1 file changed, 1 insertion(+)

New commits:
commit b434c1a437c407de88396b219560649c2dae82b2
Author: Jesse Barnes <jesse.barnes at intel.com>
Date:   Thu Nov 1 12:06:07 2007 -0700

    Framebuffer compression fix: front buffer may not be at fence 0
    
    Fix a long standing bug in the framebuffer compression code (thanks to
    Pierre Willenbrock!) that prevented FBC from working correctly if the front
    buffer was anywhere but fence register 0.

diff --git a/src/i830_display.c b/src/i830_display.c
index a99b4a5..d988b86 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -611,6 +611,7 @@ i830_enable_fb_compression(xf86CrtcPtr crtc)
     fbc_ctl |= (compressed_stride & 0xff) << FBC_CTL_STRIDE_SHIFT;
     fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
     fbc_ctl |= FBC_CTL_UNCOMPRESSIBLE;
+    fbc_ctl |= pI830->front_buffer->fence_nr;
     OUTREG(FBC_CONTROL, fbc_ctl);
 
     xf86DrvMsg(pScrn->scrnIndex, X_INFO, "fbc enabled on plane %c\n", plane ?