xf86-video-ati: Branch 'randr-1.2' - 13 commits
Dave Airlie
airlied at kemper.freedesktop.org
Wed May 30 00:27:50 PDT 2007
configure.ac | 2
src/radeon.h | 16 --
src/radeon_accel.c | 38 +++---
src/radeon_bios.c | 18 ++
src/radeon_commonfuncs.c | 14 +-
src/radeon_cursor.c | 40 +-----
src/radeon_display.c | 12 +
src/radeon_dri.c | 22 +++
src/radeon_driver.c | 293 +++++++++++++++++++++++++++++------------------
src/radeon_exa.c | 17 ++
src/radeon_reg.h | 8 +
11 files changed, 301 insertions(+), 179 deletions(-)
New commits:
diff-tree 7fc02657c4d740941fbda5a8823cf45de3eca3f8 (from parents)
Merge: 800bf53279e2c2bf854682bbfd6fa16d03afed00 4c61c0ee91a2ffeefce30972a584486f1df1d1ae
Author: Dave Airlie <airlied at nx6125b.(none)>
Date: Wed May 30 17:27:22 2007 +1000
Merge branch 'origin' into randr-1.2-test
Conflicts:
src/radeon_cursor.c
src/radeon_display.c
src/radeon_driver.c
diff --cc src/radeon.h
index d75b154,88402df..eb4902b
@@@ -152,8 -161,31 +152,7 @@@
OPTION_DRI
} RADEONOpts;
-/* ------- mergedfb support ------------- */
- /* Psuedo Xinerama support */
-#define NEED_REPLIES /* ? */
-#define EXTENSION_PROC_ARGS void *
-#include "extnsionst.h" /* required */
-#include <X11/extensions/panoramiXproto.h> /* required */
-#define RADEON_XINERAMA_MAJOR_VERSION 1
-#define RADEON_XINERAMA_MINOR_VERSION 1
-
-
-/* Relative merge position */
-typedef enum {
- radeonLeftOf,
- radeonRightOf,
- radeonAbove,
- radeonBelow,
- radeonClone
-} RADEONScrn2Rel;
-
-typedef struct _region {
- int x0,x1,y0,y1;
-} region;
-
-/* ------------------------------------- */
- #define RADEON_DEBUG 1 /* Turn off debugging output */
#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */
#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */
@@@ -165,18 -197,8 +164,10 @@@
* for something else.
*/
- #if RADEON_DEBUG
- #define RADEONTRACE(x) \
- do { \
- ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex); \
- ErrorF x; \
- } while(0)
- #else
- #define RADEONTRACE(x) do { } while(0)
- #endif
+ #define RADEON_LOGLEVEL_DEBUG 4
+/* for Xv, outputs */
+#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE)
/* Other macros */
#define RADEON_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
diff --cc src/radeon_bios.c
index 25cd1a8,e62fb25..8d5c0ec
@@@ -40,6 -41,21 +41,21 @@@
#include "radeon_probe.h"
#include "vbe.h"
+ int RADEONBIOSApplyConnectorQuirks(ScrnInfoPtr pScrn, int connector_found)
+ {
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+
+ /* quirk for compaq nx6125 - the bios lies about the VGA DDC */
+ if (info->PciInfo->subsysVendor == PCI_VENDOR_HP) {
+ if (info->PciInfo->subsysCard == 0x308b) {
- if (pRADEONEnt->PortInfo[1]->DDCType == DDC_CRT2)
- pRADEONEnt->PortInfo[1]->DDCType = DDC_MONID;
++ if (info->BiosConnector[1].DDCType == DDC_CRT2)
++ info->BiosConnector[1].DDCType = DDC_MONID;
+ }
+ }
+ return connector_found;
+ }
+
/* Read the Video BIOS block and the FP registers (if applicable). */
Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
{
diff --cc src/radeon_cursor.c
index 68771f8,ec80dd8..6746615
@@@ -103,41 -98,6 +97,43 @@@
#endif
+void
+radeon_crtc_show_cursor (xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ int crtc_id = radeon_crtc->crtc_id;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
++ RADEON_SYNC(info, pScrn);
++
+ if (crtc_id == 0)
- OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN,
- ~RADEON_CRTC_CUR_EN);
++ OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN | 2 << 20,
++ ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
+ else if (crtc_id == 1)
- OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN,
- ~RADEON_CRTC2_CUR_EN);
-
-
++ OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN | 2 << 20,
++ ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_CUR_MODE_MASK));
+}
+
+void
+radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ int crtc_id = radeon_crtc->crtc_id;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
++ RADEON_SYNC(info, pScrn);
++
+ if (crtc_id == 0)
+ OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_CUR_EN);
+ else if (crtc_id == 1)
+ OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN);
+
+
+}
/* Set cursor foreground and background colors */
static void RADEONSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
@@@ -277,23 -293,14 +273,11 @@@
unsigned char *RADEONMMIO = info->MMIO;
CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
int x, y, w, h;
- CARD32 save1 = 0;
- CARD32 save2 = 0;
- CARD32 *image = pCurs->bits->argb;
CARD32 *i;
RADEONCTRACE(("RADEONLoadCursorARGB\n"));
- if (crtc_id == 0) {
- save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20);
- save1 |= (CARD32) (2 << 20);
- OUTREG(RADEON_CRTC_GEN_CNTL, save1 & (CARD32)~RADEON_CRTC_CUR_EN);
- } else if (crtc_id == 1) {
- save2 = INREG(RADEON_CRTC2_GEN_CNTL) & ~(CARD32) (3 << 20);
- save2 |= (CARD32) (2 << 20);
- OUTREG(RADEON_CRTC2_GEN_CNTL, save2 & (CARD32)~RADEON_CRTC2_CUR_EN);
- }
-
-#ifdef ARGB_CURSOR
info->cursor_argb = TRUE;
-#endif
CURSOR_SWAPPING_START();
@@@ -320,15 -324,8 +304,9 @@@
for (; y < CURSOR_HEIGHT; y++)
for (x = 0; x < CURSOR_WIDTH; x++)
*d++ = 0;
+#endif
CURSOR_SWAPPING_END ();
-
- if (crtc_id == 0) {
- OUTREG(RADEON_CRTC_GEN_CNTL, save1);
- } else if (crtc_id == 1) {
- OUTREG(RADEON_CRTC2_GEN_CNTL, save2);
- }
}
#endif
diff --cc src/radeon_display.c
index 3bbf371,90fdc54..0442b9a
@@@ -1340,11 -1941,13 +1340,13 @@@
OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
- RADEONTRACE(("GRPH_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg.grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL)));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "GRPH_BUFFER_CNTL from %x to %x\n",
+ (unsigned int)info->SavedReg.grph_buffer_cntl,
+ INREG(RADEON_GRPH_BUFFER_CNTL));
if (mode2) {
- stop_req = mode2->HDisplay * info2->CurrentLayout.pixel_bytes / 16;
+ stop_req = mode2->HDisplay * pixel_bytes2 / 16;
if (stop_req > max_stop_req) stop_req = max_stop_req;
diff --cc src/radeon_driver.c
index 42d1899,25921ad..b399736
@@@ -3331,6 -3816,7 +3338,7 @@@
#ifdef XF86DRI
pScrn->fbOffset = info->frontOffset;
#endif
- if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024;
++
if (!RADEONMapMem(pScrn)) return FALSE;
#ifdef XF86DRI
@@@ -3429,8 -3925,11 +3437,9 @@@
#endif
/* Initial setup of surfaces */
- RADEONTRACE(("Setting up initial surfaces\n"));
- if (!info->IsSecondary) {
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Setting up initial surfaces\n");
- RADEONChangeSurfaces(pScrn);
- }
++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
++ "Setting up initial surfaces\n");
+ RADEONChangeSurfaces(pScrn);
/* Memory manager setup */
@@@ -3612,10 -4105,11 +3623,11 @@@
RADEONSaveScreen(pScreen, SCREEN_SAVER_ON);
- pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
+ // pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
/* Backing store setup */
- RADEONTRACE(("Initializing backing store\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing backing store\n");
miInitializeBackingStore(pScreen);
xf86SetBackingStore(pScreen);
@@@ -3664,8 -4159,15 +3677,10 @@@
#endif
/* Make sure surfaces are allright since DRI setup may have changed them */
- RADEONTRACE(("Setting up final surfaces\n"));
- if (!info->IsSecondary) {
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Setting up final surfaces\n");
- RADEONChangeSurfaces(pScrn);
- }
++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
++ "Setting up final surfaces\n");
+
- if(info->MergedFB)
- /* need this here to fix up sarea values */
- RADEONAdjustFrameMerged(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
+ RADEONChangeSurfaces(pScrn);
/* Enable aceleration */
if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
@@@ -3685,10 -4188,12 +3701,12 @@@
}
/* Init DPMS */
- RADEONTRACE(("Initializing DPMS\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing DPMS\n");
- xf86DPMSInit(pScreen, RADEONDisplayPowerManagementSet, 0);
+ xf86DPMSInit(pScreen, xf86DPMSSet, 0);
- RADEONTRACE(("Initializing Cursor\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing Cursor\n");
/* Set Silken Mouse */
xf86SetSilkenMouse(pScreen);
@@@ -3725,16 -4230,45 +3743,16 @@@
xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n");
}
-
-
- /* Colormap setup */
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing color map\n");
- if (!miCreateDefColormap(pScreen)) return FALSE;
- if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8,
- RADEONLoadPalette, NULL,
- CMAP_PALETTED_TRUECOLOR
-#if 0 /* This option messes up text mode! (eich at suse.de) */
- | CMAP_LOAD_EVEN_IF_OFFSCREEN
-#endif
- | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE;
-
- /* DGA setup */
+ /* DGA setup */
- RADEONTRACE(("Initializing DGA\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing DGA\n");
RADEONDGAInit(pScreen);
- /* Wrap some funcs for MergedFB */
- if(info->MergedFB) {
- info->PointerMoved = pScrn->PointerMoved;
- pScrn->PointerMoved = RADEONMergePointerMoved;
- /* Psuedo xinerama */
- if(info->UseRADEONXinerama) {
- RADEONnoPanoramiXExtension = FALSE;
- RADEONXineramaExtensionInit(pScrn);
- } else {
- info->MouseRestrictions = FALSE;
- }
- }
-
/* Init Xv */
- RADEONTRACE(("Initializing Xv\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing Xv\n");
RADEONInitVideo(pScreen);
- if(info->MergedFB)
- /* need this here to fix up sarea values */
- RADEONAdjustFrameMerged(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
-
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
/* Wrap CloseScreen */
info->CloseScreen = pScreen->CloseScreen;
@@@ -3743,24 -4277,6 +3761,25 @@@
info->BlockHandler = pScreen->BlockHandler;
pScreen->BlockHandler = RADEONBlockHandler;
+ if (!xf86CrtcScreenInit (pScreen))
+ return FALSE;
+
+ /* Wrap pointer motion to flip touch screen around */
+ info->PointerMoved = pScrn->PointerMoved;
+ pScrn->PointerMoved = RADEONPointerMoved;
+
+ /* Colormap setup */
- RADEONTRACE(("Initializing color map\n"));
++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
++ "Initializing color map\n");
+ if (!miCreateDefColormap(pScreen)) return FALSE;
+ if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8,
+ RADEONLoadPalette, NULL,
+ CMAP_PALETTED_TRUECOLOR
+#if 0 /* This option messes up text mode! (eich at suse.de) */
+ | CMAP_LOAD_EVEN_IF_OFFSCREEN
+#endif
+ | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE;
+
/* Note unused options */
if (serverGeneration == 1)
xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
@@@ -4124,11 -4626,18 +4152,12 @@@
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- CARD32 crtc2_gen_cntl;
+ /* CARD32 crtc2_gen_cntl;*/
- RADEONTRACE(("Programming CRTC2, offset: 0x%08lx\n",
- restore->crtc2_offset));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Programming CRTC2, offset: 0x%08lx\n",
+ restore->crtc2_offset);
- crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) &
- (RADEON_CRTC2_VSYNC_DIS |
- RADEON_CRTC2_HSYNC_DIS |
- RADEON_CRTC2_DISP_DIS);
- crtc2_gen_cntl |= restore->crtc2_gen_cntl;
-
/* We prevent the CRTC from hitting the memory controller until
* fully programmed
*/
@@@ -4153,7 -4672,13 +4182,13 @@@
OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
+ if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ OUTREG(RADEON_RS480_UNK_e30, restore->rs480_unk_e30);
+ OUTREG(RADEON_RS480_UNK_e34, restore->rs480_unk_e34);
+ OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38);
+ OUTREG(RADEON_RS480_UNK_e3c, restore->rs480_unk_e3c);
+ }
- OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+ OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
}
@@@ -4605,10 -5134,12 +4642,12 @@@
{
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- RADEONController* pCRTC1 = pRADEONEnt->Controller[0];
- RADEONController* pCRTC2 = pRADEONEnt->Controller[1];
- RADEONConnector *pPort;
+ RADEONCrtcPrivatePtr pCRTC1 = pRADEONEnt->Controller[0];
+ RADEONCrtcPrivatePtr pCRTC2 = pRADEONEnt->Controller[1];
+ xf86OutputPtr output;
- RADEONTRACE(("RADEONRestoreMode(%p)\n", restore));
+
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONRestoreMode(%p)\n", restore);
/* For Non-dual head card, we don't have private field in the Entity */
if (!pRADEONEnt->HasCRTC2) {
@@@ -4876,19 -5449,27 +4926,21 @@@
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONTRACE(("RADEONSaveMode(%p)\n", save));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONSaveMode(%p)\n", save);
- if (info->IsSecondary) {
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- RADEONInfoPtr info0 = RADEONPTR(pRADEONEnt->pPrimaryScrn);
- memcpy(&info->SavedReg, &info0->SavedReg, sizeof(RADEONSaveRec));
- } else {
- RADEONSaveMemMapRegisters(pScrn, save);
- RADEONSaveCommonRegisters(pScrn, save);
- RADEONSavePLLRegisters (pScrn, save);
- RADEONSaveCrtcRegisters (pScrn, save);
- RADEONSaveFPRegisters (pScrn, save);
- RADEONSaveCrtc2Registers (pScrn, save);
- RADEONSavePLL2Registers (pScrn, save);
- /*RADEONSavePalette(pScrn, save);*/
- /*memcpy(&info->ModeReg, &info->SavedReg, sizeof(RADEONSaveRec));*/
- }
+ RADEONSaveMemMapRegisters(pScrn, save);
+ RADEONSaveCommonRegisters(pScrn, save);
+ RADEONSavePLLRegisters (pScrn, save);
+ RADEONSaveCrtcRegisters (pScrn, save);
+ RADEONSaveFPRegisters (pScrn, save);
+ RADEONSaveDACRegisters (pScrn, save);
+ RADEONSaveCrtc2Registers (pScrn, save);
+ RADEONSavePLL2Registers (pScrn, save);
+ /*RADEONSavePalette(pScrn, save);*/
- RADEONTRACE(("RADEONSaveMode returns %p\n", save));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONSaveMode returns %p\n", save);
}
/* Save everything needed to restore the original VC state */
@@@ -5061,19 -5655,17 +5116,19 @@@
RADEON_TV_DAC_GDACPD);
}
/* FIXME: doesn't make sense, this just replaces the previous value... */
- save->tv_dac_cntl = (RADEON_TV_DAC_NBLANK |
+ save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
RADEON_TV_DAC_NHOLD |
- RADEON_TV_DAC_STD_PS2 |
- info->tv_dac_adj);
+ RADEON_TV_DAC_STD_PS2);
+ // info->tv_dac_adj);
}
-static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
DisplayModePtr mode, BOOL IsPrimary)
{
+ ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
int i;
CARD32 tmp = info->SavedReg.tmds_pll_cntl & 0xfffff;
@@@ -5976,10 -6635,21 +6041,11 @@@
}
#endif
- RADEONTRACE(("RADEONSwitchMode() !n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONSwitchMode() !n");
if (info->allowColorTiling) {
- if (info->MergedFB) {
- if ((((RADEONMergedDisplayModePtr)mode->Private)->CRT1->Flags &
- (V_DBLSCAN | V_INTERLACE)) ||
- (((RADEONMergedDisplayModePtr)mode->Private)->CRT2->Flags &
- (V_DBLSCAN | V_INTERLACE)))
- info->tilingEnabled = FALSE;
- else info->tilingEnabled = TRUE;
- }
- else {
- info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
- }
+ info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
#ifdef XF86DRI
if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
RADEONSAREAPrivPtr pSAREAPriv;
@@@ -6226,9 -6893,9 +6293,10 @@@
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- RADEONTRACE(("RADEONEnterVT\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONEnterVT\n");
if (INREG(RADEON_CONFIG_MEMSIZE) == 0) { /* Softboot V_BIOS */
xf86Int10InfoPtr pInt;
diff-tree 4c61c0ee91a2ffeefce30972a584486f1df1d1ae (from 5337e7bd0069a3f2c4ab22b21a19471427ad3d81)
Author: Matthieu Herrb <matthieu at deville.herrb.com>
Date: Tue May 29 21:35:35 2007 -0600
Fix build without XF86DRI
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 5eca577..25921ad 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -3799,15 +3799,23 @@ Bool RADEONScreenInit(int scrnIndex, Scr
char* s;
#endif
+#ifdef XF86DRI
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONScreenInit %lx %ld %d\n",
pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset);
+#else
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONScreenInit %lx %ld\n",
+ pScrn->memPhysBase, pScrn->fbOffset);
+#endif
info->accelOn = FALSE;
#ifdef USE_XAA
info->accel = NULL;
#endif
+#ifdef XF86DRI
pScrn->fbOffset = info->frontOffset;
+#endif
if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024;
if (!RADEONMapMem(pScrn)) return FALSE;
@@ -3997,6 +4005,7 @@ Bool RADEONScreenInit(int scrnIndex, Scr
/* Setup DRI after visuals have been established, but before fbScreenInit is
* called. fbScreenInit will eventually call the driver's InitGLXVisuals
* call back. */
+#ifdef XF86DRI
if (info->directRenderingEnabled) {
/* FIXME: When we move to dynamic allocation of back and depth
* buffers, we will want to revisit the following check for 3
@@ -4020,7 +4029,6 @@ Bool RADEONScreenInit(int scrnIndex, Scr
}
}
-#if defined(XF86DRI)
/* Tell DRI about new memory map */
if (info->directRenderingEnabled && info->newMemoryMap) {
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) {
diff-tree 5337e7bd0069a3f2c4ab22b21a19471427ad3d81 (from bff809dc8ed07ac39e9b576a87916486a5e37156)
Author: Dave Airlie <airlied at nx6125b.(none)>
Date: Wed May 30 08:10:44 2007 +1000
radeon: add bios quirk for nx6125 monid
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index dd3d0a7..e62fb25 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -34,12 +34,28 @@
#include "xf86.h"
#include "xf86_OSproc.h"
+#include "xf86PciInfo.h"
#include "radeon.h"
#include "radeon_reg.h"
#include "radeon_macros.h"
#include "radeon_probe.h"
#include "vbe.h"
+int RADEONBIOSApplyConnectorQuirks(ScrnInfoPtr pScrn, int connector_found)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+
+ /* quirk for compaq nx6125 - the bios lies about the VGA DDC */
+ if (info->PciInfo->subsysVendor == PCI_VENDOR_HP) {
+ if (info->PciInfo->subsysCard == 0x308b) {
+ if (pRADEONEnt->PortInfo[1]->DDCType == DDC_CRT2)
+ pRADEONEnt->PortInfo[1]->DDCType = DDC_MONID;
+ }
+ }
+ return connector_found;
+}
+
/* Read the Video BIOS block and the FP registers (if applicable). */
Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
{
@@ -313,6 +329,8 @@ Bool RADEONGetConnectorInfoFromBIOS (Scr
connector_found = 1;
}
+ connector_found = RADEONBIOSApplyConnectorQuirks(pScrn, connector_found);
+
if (connector_found == 0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No connector found in Connector Info Table.\n");
} else {
diff-tree bff809dc8ed07ac39e9b576a87916486a5e37156 (from 104105fee5c3945d3f210e6a4cb73ab492c61543)
Author: Dave Airlie <airlied at nx6125b.(none)>
Date: Wed May 30 08:02:26 2007 +1000
rs480: more unknown regs
Hardcode the values from a working fglrx run, this works for me now
I've no idea what it might do for anyone else
diff --git a/src/radeon.h b/src/radeon.h
index 3e79c1b..88402df 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -318,7 +318,10 @@ typedef struct {
CARD32 tv_dac_cntl;
+ CARD32 rs480_unk_e30;
+ CARD32 rs480_unk_e34;
CARD32 rs480_unk_e38;
+ CARD32 rs480_unk_e3c;
} RADEONSaveRec, *RADEONSavePtr;
typedef struct {
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index a3d8a03..5eca577 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4665,7 +4665,10 @@ static void RADEONRestoreCrtc2Registers(
OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ OUTREG(RADEON_RS480_UNK_e30, restore->rs480_unk_e30);
+ OUTREG(RADEON_RS480_UNK_e34, restore->rs480_unk_e34);
OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38);
+ OUTREG(RADEON_RS480_UNK_e3c, restore->rs480_unk_e3c);
}
OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
@@ -5363,8 +5366,12 @@ static void RADEONSaveCrtc2Registers(Scr
save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID);
save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID);
- if (info->ChipFamily == CHIP_FAMILY_RS400)
+ if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ save->rs480_unk_e30 = INREG(RADEON_RS480_UNK_e30);
+ save->rs480_unk_e34 = INREG(RADEON_RS480_UNK_e34);
save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38);
+ save->rs480_unk_e3c = INREG(RADEON_RS480_UNK_e3c);
+ }
save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL);
}
@@ -6241,8 +6248,10 @@ static Bool RADEONInitCrtc2Registers(Scr
#endif
if (info->ChipFamily == CHIP_FAMILY_RS400) {
- save->rs480_unk_e38 = info->SavedReg.rs480_unk_e38 & ~(0x300);
- save->rs480_unk_e38 |= 0x100;
+ save->rs480_unk_e30 = 0x105DC1CC; /* because I'm worth it */
+ save->rs480_unk_e34 = 0x2749D000; /* AMD really should */
+ save->rs480_unk_e38 = 0x29ca71dc; /* release docs */
+ save->rs480_unk_e3c = 0x28FBC3AC; /* this is so a trade secret */
}
return TRUE;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 476c56b..01bcec8 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3127,5 +3127,9 @@
# define RADEON_TVPLL_SLEEP (1 << 3)
# define RADEON_TVPLL_REFCLK_SEL (1 << 4)
+#define RADEON_RS480_UNK_e30 0xe30
+#define RADEON_RS480_UNK_e34 0xe34
#define RADEON_RS480_UNK_e38 0xe38
+#define RADEON_RS480_UNK_e3c 0xe3c
+
#endif
diff-tree 104105fee5c3945d3f210e6a4cb73ab492c61543 (from 5aa603bcabbb077dec169c48438c2e2ebe1195d7)
Author: Dave Airlie <airlied at nx6125b.(none)>
Date: Tue May 29 19:09:33 2007 +1000
rs480: make second crtc work with magic number in magic register.
I've no idea why or what this does.
diff --git a/src/radeon.h b/src/radeon.h
index 3ea44f3..3e79c1b 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -318,6 +318,7 @@ typedef struct {
CARD32 tv_dac_cntl;
+ CARD32 rs480_unk_e38;
} RADEONSaveRec, *RADEONSavePtr;
typedef struct {
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index b0e4037..a3d8a03 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4664,6 +4664,9 @@ static void RADEONRestoreCrtc2Registers(
OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
+ if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38);
+ }
OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
}
@@ -4858,11 +4861,10 @@ static void RADEONRestorePLL2Registers(S
OUTPLLP(pScrn,
RADEON_P2PLL_CNTL,
RADEON_P2PLL_RESET
- | RADEON_P2PLL_ATOMIC_UPDATE_EN
- | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN,
+ | RADEON_P2PLL_ATOMIC_UPDATE_EN,
~(RADEON_P2PLL_RESET
- | RADEON_P2PLL_ATOMIC_UPDATE_EN
- | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN));
+ | RADEON_P2PLL_ATOMIC_UPDATE_EN));
+
OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV,
restore->p2pll_ref_div,
@@ -4885,17 +4887,16 @@ static void RADEONRestorePLL2Registers(S
0,
~(RADEON_P2PLL_RESET
| RADEON_P2PLL_SLEEP
- | RADEON_P2PLL_ATOMIC_UPDATE_EN
- | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN));
+ | RADEON_P2PLL_ATOMIC_UPDATE_EN));
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Wrote: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n",
+ "Wrote2: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n",
restore->p2pll_ref_div,
restore->p2pll_div_0,
restore->htotal_cntl2,
INPLL(pScrn, RADEON_P2PLL_CNTL));
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Wrote: rd=%ld, fd=%ld, pd=%ld\n",
+ "Wrote2: rd=%ld, fd=%ld, pd=%ld\n",
restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
(restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16);
@@ -5362,6 +5363,9 @@ static void RADEONSaveCrtc2Registers(Scr
save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID);
save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID);
+ if (info->ChipFamily == CHIP_FAMILY_RS400)
+ save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38);
+
save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL);
}
@@ -5636,10 +5640,10 @@ static void RADEONInitTvDacCntl(ScrnInfo
RADEON_TV_DAC_GDACPD);
}
/* FIXME: doesn't make sense, this just replaces the previous value... */
- save->tv_dac_cntl = (RADEON_TV_DAC_NBLANK |
+ save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
RADEON_TV_DAC_NHOLD |
- RADEON_TV_DAC_STD_PS2 |
- info->tv_dac_adj);
+ RADEON_TV_DAC_STD_PS2);
+ // info->tv_dac_adj);
}
static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
@@ -6236,6 +6240,11 @@ static Bool RADEONInitCrtc2Registers(Scr
}
#endif
+ if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ save->rs480_unk_e38 = info->SavedReg.rs480_unk_e38 & ~(0x300);
+ save->rs480_unk_e38 |= 0x100;
+ }
+
return TRUE;
}
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 81acd46..476c56b 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3126,4 +3126,6 @@
# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
# define RADEON_TVPLL_SLEEP (1 << 3)
# define RADEON_TVPLL_REFCLK_SEL (1 << 4)
+
+#define RADEON_RS480_UNK_e38 0xe38
#endif
diff-tree 5aa603bcabbb077dec169c48438c2e2ebe1195d7 (from c52322354fe64725733842b3356798c50e7735d5)
Author: Dave Airlie <airlied at nx6125b.(none)>
Date: Tue May 29 07:23:24 2007 +1000
rs480: only has single dac
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index a812195..b0e4037 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1720,7 +1720,7 @@ static Bool RADEONPreInitChipType(ScrnIn
case PCI_CHIP_RS482_5974:
info->ChipFamily = CHIP_FAMILY_RS400;
info->IsIGP = TRUE;
- /*info->HasSingleDAC = TRUE;*/ /* ??? */
+ info->HasSingleDAC = TRUE;
break;
case PCI_CHIP_RV410_564A:
diff-tree c52322354fe64725733842b3356798c50e7735d5 (from parents)
Merge: dd6a966e862b774a8e8b9e1a085309219673efad 975da595f032c145ad74079ff8edeaead779dc7b
Author: Dave Airlie <airlied at nx6125b.(none)>
Date: Tue May 29 07:21:48 2007 +1000
Merge branch 'origin'
diff-tree 975da595f032c145ad74079ff8edeaead779dc7b (from 8275151baac22c34149cef0b7d922771d24abc3e)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Tue May 22 10:56:47 2007 +0200
radeon: Provide new DRI texOffsetStart hook when available with EXA.
diff --git a/src/radeon.h b/src/radeon.h
index 8c399cd..3ea44f3 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -851,6 +851,7 @@ extern Bool RADEONAccelInit(Scree
extern Bool RADEONSetupMemEXA (ScreenPtr pScreen);
extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen);
#ifdef XF86DRI
+extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix);
extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type);
extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix,
CARD32 *pitch_offset);
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 24e31ab..39393f5 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -1475,6 +1475,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScre
pDRIInfo->createDummyCtx = TRUE;
pDRIInfo->createDummyCtxPriv = FALSE;
+#ifdef USE_EXA
+ if (info->useEXA) {
+#if DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3
+ int major, minor, patch;
+
+ DRIQueryVersion(&major, &minor, &patch);
+
+ if (minor >= 3)
+#endif
+#if DRIINFO_MAJOR_VERSION > 5 || \
+ (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3)
+ pDRIInfo->texOffsetStart = RADEONTexOffsetStart;
+#endif
+ }
+#endif
+
if (!DRIScreenInit(pScreen, pDRIInfo, &info->drmFD)) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[dri] DRIScreenInit failed. Disabling DRI.\n");
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index f9bcace..d074f08 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -496,3 +496,20 @@ Bool RADEONSetupMemEXA (ScreenPtr pScree
return TRUE;
}
+
+#ifdef XF86DRI
+
+#ifndef ExaOffscreenMarkUsed
+extern void ExaOffscreenMarkUsed(PixmapPtr);
+#endif
+
+unsigned long long
+RADEONTexOffsetStart(PixmapPtr pPix)
+{
+ exaMoveInPixmap(pPix);
+ ExaOffscreenMarkUsed(pPix);
+
+ return RADEONPTR(xf86Screens[pPix->drawable.pScreen->myNum])->fbLocation +
+ exaGetPixmapOffset(pPix);
+}
+#endif
diff-tree 8275151baac22c34149cef0b7d922771d24abc3e (from 137e3fc1899078af0f72303ab0a4e6cf35804a7b)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Mon May 21 10:25:48 2007 +0200
radeon: HW cursor cleanup.
Don't needlessly turn the HW cursor on/off in RADEONLoadCursor*().
Besides cleaning up the code, this semms to avoid some HW cursor related 3D
lockups, see https://bugs.freedesktop.org/show_bug.cgi?id=10815 . My best
guess is that this is because the engine is now always idled before touching
the CRTC registers.
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index a45198a..ec80dd8 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -71,8 +71,6 @@ static CARD32 mono_cursor_color[] = {
#define CURSOR_WIDTH 64
#define CURSOR_HEIGHT 64
-#define COMMON_CURSOR_SWAPPING_START() RADEON_SYNC(info, pScrn)
-
/*
* The cursor bits are always 32bpp. On MSBFirst buses,
* configure byte swapping to swap 32 bit units when writing
@@ -84,7 +82,6 @@ static CARD32 mono_cursor_color[] = {
#define CURSOR_SWAPPING_DECL_MMIO unsigned char *RADEONMMIO = info->MMIO;
#define CURSOR_SWAPPING_START() \
do { \
- COMMON_CURSOR_SWAPPING_START(); \
OUTREG(RADEON_SURFACE_CNTL, \
(info->ModeReg.surface_cntl | \
RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \
@@ -96,10 +93,7 @@ static CARD32 mono_cursor_color[] = {
#else
#define CURSOR_SWAPPING_DECL_MMIO
-#define CURSOR_SWAPPING_START() \
- do { \
- COMMON_CURSOR_SWAPPING_START(); \
- } while (0)
+#define CURSOR_SWAPPING_START()
#define CURSOR_SWAPPING_END()
#endif
@@ -205,25 +199,11 @@ static void RADEONLoadCursorImage(ScrnIn
unsigned char *RADEONMMIO = info->MMIO;
CARD8 *s = (CARD8 *)(pointer)image;
CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
- CARD32 save1 = 0;
- CARD32 save2 = 0;
CARD8 chunk;
CARD32 i, j;
RADEONCTRACE(("RADEONLoadCursorImage (at %x)\n", info->cursor_offset));
- if (!info->IsSecondary) {
- save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20);
- save1 |= (CARD32) (2 << 20);
- OUTREG(RADEON_CRTC_GEN_CNTL, save1 & (CARD32)~RADEON_CRTC_CUR_EN);
- }
-
- if (info->IsSecondary || info->MergedFB) {
- save2 = INREG(RADEON_CRTC2_GEN_CNTL) & ~(CARD32) (3 << 20);
- save2 |= (CARD32) (2 << 20);
- OUTREG(RADEON_CRTC2_GEN_CNTL, save2 & (CARD32)~RADEON_CRTC2_CUR_EN);
- }
-
#ifdef ARGB_CURSOR
info->cursor_argb = FALSE;
#endif
@@ -237,23 +217,18 @@ static void RADEONLoadCursorImage(ScrnIn
* (which actually bit swaps the image) to make the bits LSBFirst
*/
CURSOR_SWAPPING_START();
+
#define ARGB_PER_CHUNK (8 * sizeof (chunk) / 2)
for (i = 0; i < (CURSOR_WIDTH * CURSOR_HEIGHT / ARGB_PER_CHUNK); i++) {
chunk = *s++;
for (j = 0; j < ARGB_PER_CHUNK; j++, chunk >>= 2)
*d++ = mono_cursor_color[chunk & 3];
}
+
CURSOR_SWAPPING_END();
info->cursor_bg = mono_cursor_color[2];
info->cursor_fg = mono_cursor_color[3];
-
- if (!info->IsSecondary)
- OUTREG(RADEON_CRTC_GEN_CNTL, save1);
-
- if (info->IsSecondary || info->MergedFB)
- OUTREG(RADEON_CRTC2_GEN_CNTL, save2);
-
}
/* Hide hardware cursor. */
@@ -264,6 +239,8 @@ static void RADEONHideCursor(ScrnInfoPtr
RADEONCTRACE(("RADEONHideCursor\n"));
+ RADEON_SYNC(info, pScrn);
+
if (info->IsSecondary || info->MergedFB)
OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN);
@@ -279,13 +256,15 @@ static void RADEONShowCursor(ScrnInfoPtr
RADEONCTRACE(("RADEONShowCursor\n"));
+ RADEON_SYNC(info, pScrn);
+
if (info->IsSecondary || info->MergedFB)
- OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN,
- ~RADEON_CRTC2_CUR_EN);
+ OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN | 2 << 20,
+ ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_CUR_MODE_MASK));
if (!info->IsSecondary)
- OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN,
- ~RADEON_CRTC_CUR_EN);
+ OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN | 2 << 20,
+ ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
}
/* Determine if hardware cursor is in use. */
@@ -314,25 +293,11 @@ static void RADEONLoadCursorARGB (ScrnIn
unsigned char *RADEONMMIO = info->MMIO;
CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
int x, y, w, h;
- CARD32 save1 = 0;
- CARD32 save2 = 0;
CARD32 *image = pCurs->bits->argb;
CARD32 *i;
RADEONCTRACE(("RADEONLoadCursorARGB\n"));
- if (!info->IsSecondary) {
- save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20);
- save1 |= (CARD32) (2 << 20);
- OUTREG(RADEON_CRTC_GEN_CNTL, save1 & (CARD32)~RADEON_CRTC_CUR_EN);
- }
-
- if (info->IsSecondary || info->MergedFB) {
- save2 = INREG(RADEON_CRTC2_GEN_CNTL) & ~(CARD32) (3 << 20);
- save2 |= (CARD32) (2 << 20);
- OUTREG(RADEON_CRTC2_GEN_CNTL, save2 & (CARD32)~RADEON_CRTC2_CUR_EN);
- }
-
#ifdef ARGB_CURSOR
info->cursor_argb = TRUE;
#endif
@@ -361,13 +326,6 @@ static void RADEONLoadCursorARGB (ScrnIn
*d++ = 0;
CURSOR_SWAPPING_END ();
-
- if (!info->IsSecondary)
- OUTREG(RADEON_CRTC_GEN_CNTL, save1);
-
- if (info->IsSecondary || info->MergedFB)
- OUTREG(RADEON_CRTC2_GEN_CNTL, save2);
-
}
#endif
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 0d5e586..81acd46 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -308,7 +308,7 @@
# define RADEON_CRTC_CSYNC_EN (1 << 4)
# define RADEON_CRTC_ICON_EN (1 << 15)
# define RADEON_CRTC_CUR_EN (1 << 16)
-# define RADEON_CRTC_CUR_MODE_MASK (7 << 17)
+# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
# define RADEON_CRTC_EXT_DISP_EN (1 << 24)
# define RADEON_CRTC_EN (1 << 25)
# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
diff-tree 137e3fc1899078af0f72303ab0a4e6cf35804a7b (from 09bfc8ed000f95ede5b73f2bad69edc1a4d9bac6)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Mon May 21 10:25:48 2007 +0200
radeon: Suppress debugging output by default.
It can be enabled at runtime by increasing the log verbosity level.
Also change the prefix from (**) to (II) to make grepping the log file for
defaults overridden by xorg.conf more useful again.
Turn some MC related debugging output into normal informational output as it's
useful for recognizing corner cases that can cause stability issues.
diff --git a/src/radeon.h b/src/radeon.h
index ce2fe19..8c399cd 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -186,7 +186,6 @@ typedef struct _region {
/* ------------------------------------- */
-#define RADEON_DEBUG 1 /* Turn off debugging output */
#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */
#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */
@@ -198,15 +197,7 @@ typedef struct _region {
* for something else.
*/
-#if RADEON_DEBUG
-#define RADEONTRACE(x) \
-do { \
- ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex); \
- ErrorF x; \
-} while(0)
-#else
-#define RADEONTRACE(x) do { } while(0)
-#endif
+#define RADEON_LOGLEVEL_DEBUG 4
/* Other macros */
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 41859c4..b739988 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -134,9 +134,10 @@ void RADEONWaitForFifoFunction(ScrnInfoP
INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
if (info->fifo_slots >= entries) return;
}
- RADEONTRACE(("FIFO timed out: %u entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS)));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "FIFO timed out: %u entries, stat=0x%08x\n",
+ INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+ INREG(RADEON_RBBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"FIFO timed out, resetting engine...\n");
RADEONEngineReset(pScrn);
@@ -165,8 +166,9 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn
break;
}
if (i == RADEON_TIMEOUT) {
- RADEONTRACE(("DC flush timeout: %x\n",
- INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "DC flush timeout: %x\n",
+ INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
}
}
@@ -296,9 +298,10 @@ void RADEONEngineRestore(ScrnInfoPtr pSc
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONTRACE(("EngineRestore (%d/%d)\n",
- info->CurrentLayout.pixel_code,
- info->CurrentLayout.bitsPerPixel));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "EngineRestore (%d/%d)\n",
+ info->CurrentLayout.pixel_code,
+ info->CurrentLayout.bitsPerPixel);
/* Setup engine location. This shouldn't be necessary since we
* set them appropriately before any accel ops, but let's avoid
@@ -347,9 +350,10 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONTRACE(("EngineInit (%d/%d)\n",
- info->CurrentLayout.pixel_code,
- info->CurrentLayout.bitsPerPixel));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "EngineInit (%d/%d)\n",
+ info->CurrentLayout.pixel_code,
+ info->CurrentLayout.bitsPerPixel);
OUTREG(RADEON_RB3D_CNTL, 0);
@@ -362,15 +366,17 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
case 24: info->datatype = 5; break;
case 32: info->datatype = 6; break;
default:
- RADEONTRACE(("Unknown depth/bpp = %d/%d (code = %d)\n",
- info->CurrentLayout.depth,
- info->CurrentLayout.bitsPerPixel,
- info->CurrentLayout.pixel_code));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Unknown depth/bpp = %d/%d (code = %d)\n",
+ info->CurrentLayout.depth,
+ info->CurrentLayout.bitsPerPixel,
+ info->CurrentLayout.pixel_code);
}
info->pitch = ((info->CurrentLayout.displayWidth / 8) *
(info->CurrentLayout.pixel_bytes == 3 ? 3 : 1));
- RADEONTRACE(("Pitch for acceleration = %d\n", info->pitch));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Pitch for acceleration = %d\n", info->pitch);
info->dp_gui_master_cntl =
((info->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 70f7ddc..6a999af 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -156,9 +156,10 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnIn
#endif
#if 0
- RADEONTRACE(("WaitForIdle (entering): %d entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS)));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "WaitForIdle (entering): %d entries, stat=0x%08x\n",
+ INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+ INREG(RADEON_RBBM_STATUS));
#endif
/* Wait for the engine to go idle */
@@ -171,9 +172,10 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnIn
return;
}
}
- RADEONTRACE(("Idle timed out: %u entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS)));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Idle timed out: %u entries, stat=0x%08x\n",
+ INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+ INREG(RADEON_RBBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Idle timed out, resetting engine...\n");
RADEONEngineReset(pScrn);
diff --git a/src/radeon_display.c b/src/radeon_display.c
index fb345a9..90fdc54 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -1941,8 +1941,10 @@ void RADEONInitDispBandwidth2(ScrnInfoPt
OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
- RADEONTRACE(("GRPH_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg.grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL)));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "GRPH_BUFFER_CNTL from %x to %x\n",
+ (unsigned int)info->SavedReg.grph_buffer_cntl,
+ INREG(RADEON_GRPH_BUFFER_CNTL));
if (mode2) {
stop_req = mode2->HDisplay * info2->CurrentLayout.pixel_bytes / 16;
@@ -1989,8 +1991,10 @@ void RADEONInitDispBandwidth2(ScrnInfoPt
OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
- RADEONTRACE(("GRPH2_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg.grph2_buffer_cntl, INREG(RADEON_GRPH2_BUFFER_CNTL)));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "GRPH2_BUFFER_CNTL from %x to %x\n",
+ (unsigned int)info->SavedReg.grph2_buffer_cntl,
+ INREG(RADEON_GRPH2_BUFFER_CNTL));
}
}
@@ -2266,7 +2270,9 @@ void RADEONDisplayPowerManagementSet(Scr
RADEONConnector *pPort;
if (!pScrn->vtSema) return;
- RADEONTRACE(("RADEONDisplayPowerManagementSet(%d,0x%x)\n", PowerManagementMode, flags));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONDisplayPowerManagementSet(%d,0x%x)\n",
+ PowerManagementMode, flags);
#ifdef XF86DRI
if (info->CPStarted) DRILock(pScrn->pScreen, 0);
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index b09a8cf..24e31ab 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -1690,7 +1690,8 @@ void RADEONDRIStop(ScreenPtr pScreen)
RADEONInfoPtr info = RADEONPTR(pScrn);
RING_LOCALS;
- RADEONTRACE(("RADEONDRIStop\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONDRIStop\n");
/* Stop the CP */
if (info->directRenderingInited) {
@@ -1712,7 +1713,8 @@ void RADEONDRICloseScreen(ScreenPtr pScr
RADEONInfoPtr info = RADEONPTR(pScrn);
drmRadeonInit drmInfo;
- RADEONTRACE(("RADEONDRICloseScreen\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONDRICloseScreen\n");
if (info->irq) {
drmCtlUninstHandler(info->drmFD);
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 933265f..a812195 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -626,7 +626,8 @@ static Bool RADEONMapFB(ScrnInfoPtr pScr
if (info->FBDev) {
info->FB = fbdevHWMapVidmem(pScrn);
} else {
- RADEONTRACE(("Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize);
info->FB = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_FRAMEBUFFER,
info->PciTag,
@@ -1285,10 +1286,14 @@ static void RADEONInitMemoryMap(ScrnInfo
*/
info->mc_agp_location = 0xffffffc0;
- RADEONTRACE(("RADEONInitMemoryMap() : \n"));
- RADEONTRACE((" mem_size : 0x%08lx\n", mem_size));
- RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location));
- RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location));
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "RADEONInitMemoryMap() : \n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ " mem_size : 0x%08lx\n", mem_size);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ " MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ " MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location);
}
static void RADEONGetVRamType(ScrnInfoPtr pScrn)
@@ -3002,7 +3007,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, in
const char *s;
MessageType from;
- RADEONTRACE(("RADEONPreInit\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONPreInit\n");
if (pScrn->numEntities != 1) return FALSE;
if (!RADEONGetRec(pScrn)) return FALSE;
@@ -3793,8 +3799,9 @@ Bool RADEONScreenInit(int scrnIndex, Scr
char* s;
#endif
- RADEONTRACE(("RADEONScreenInit %lx %ld %d\n",
- pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONScreenInit %lx %ld %d\n",
+ pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset);
info->accelOn = FALSE;
#ifdef USE_XAA
@@ -3911,13 +3918,15 @@ Bool RADEONScreenInit(int scrnIndex, Scr
/* Initial setup of surfaces */
if (!info->IsSecondary) {
- RADEONTRACE(("Setting up initial surfaces\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Setting up initial surfaces\n");
RADEONChangeSurfaces(pScrn);
}
/* Memory manager setup */
- RADEONTRACE(("Setting up accel memmap\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Setting up accel memmap\n");
#ifdef USE_EXA
if (info->useEXA) {
@@ -4022,7 +4031,8 @@ Bool RADEONScreenInit(int scrnIndex, Scr
}
}
#endif
- RADEONTRACE(("Initializing fb layer\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing fb layer\n");
/* Init fb layer */
if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset,
@@ -4090,7 +4100,8 @@ Bool RADEONScreenInit(int scrnIndex, Scr
pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
/* Backing store setup */
- RADEONTRACE(("Initializing backing store\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing backing store\n");
miInitializeBackingStore(pScreen);
xf86SetBackingStore(pScreen);
@@ -4110,7 +4121,8 @@ Bool RADEONScreenInit(int scrnIndex, Scr
}
}
if (info->directRenderingEnabled) {
- RADEONTRACE(("DRI Finishing init !\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "DRI Finishing init !\n");
info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen);
}
if (info->directRenderingEnabled) {
@@ -4140,7 +4152,8 @@ Bool RADEONScreenInit(int scrnIndex, Scr
/* Make sure surfaces are allright since DRI setup may have changed them */
if (!info->IsSecondary) {
- RADEONTRACE(("Setting up final surfaces\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Setting up final surfaces\n");
RADEONChangeSurfaces(pScrn);
}
@@ -4150,7 +4163,8 @@ Bool RADEONScreenInit(int scrnIndex, Scr
/* Enable aceleration */
if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
- RADEONTRACE(("Initializing Acceleration\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing Acceleration\n");
if (RADEONAccelInit(pScreen)) {
xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n");
info->accelOn = TRUE;
@@ -4166,10 +4180,12 @@ Bool RADEONScreenInit(int scrnIndex, Scr
}
/* Init DPMS */
- RADEONTRACE(("Initializing DPMS\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing DPMS\n");
xf86DPMSInit(pScreen, RADEONDisplayPowerManagementSet, 0);
- RADEONTRACE(("Initializing Cursor\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing Cursor\n");
/* Set Silken Mouse */
xf86SetSilkenMouse(pScreen);
@@ -4207,7 +4223,8 @@ Bool RADEONScreenInit(int scrnIndex, Scr
}
/* Colormap setup */
- RADEONTRACE(("Initializing color map\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing color map\n");
if (!miCreateDefColormap(pScreen)) return FALSE;
if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8,
RADEONLoadPalette, NULL,
@@ -4218,7 +4235,8 @@ Bool RADEONScreenInit(int scrnIndex, Scr
| CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE;
/* DGA setup */
- RADEONTRACE(("Initializing DGA\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing DGA\n");
RADEONDGAInit(pScreen);
/* Wrap some funcs for MergedFB */
@@ -4235,7 +4253,8 @@ Bool RADEONScreenInit(int scrnIndex, Scr
}
/* Init Xv */
- RADEONTRACE(("Initializing Xv\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing Xv\n");
RADEONInitVideo(pScreen);
if(info->MergedFB)
@@ -4254,7 +4273,8 @@ Bool RADEONScreenInit(int scrnIndex, Scr
if (serverGeneration == 1)
xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
- RADEONTRACE(("RADEONScreenInit finished\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONScreenInit finished\n");
return TRUE;
}
@@ -4268,9 +4288,12 @@ static void RADEONRestoreMemMapRegisters
unsigned char *RADEONMMIO = info->MMIO;
int timeout;
- RADEONTRACE(("RADEONRestoreMemMapRegisters() : \n"));
- RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location));
- RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location));
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "RADEONRestoreMemMapRegisters() : \n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ " MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ " MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location);
/* Write memory mapping registers only if their value change
* since we must ensure no access is done while they are
@@ -4281,7 +4304,8 @@ static void RADEONRestoreMemMapRegisters
CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl;
CARD32 old_mc_status, status_idle;
- RADEONTRACE((" Map Changed ! Applying ...\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ " Map Changed ! Applying ...\n");
/* Make sure engine is idle. We assume the CCE is stopped
* at this point
@@ -4354,7 +4378,8 @@ static void RADEONRestoreMemMapRegisters
/* Make sure map fully reached the chip */
(void)INREG(RADEON_MC_FB_LOCATION);
- RADEONTRACE((" Map applied, resetting engine ...\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ " Map applied, resetting engine ...\n");
/* Reset the engine and HDP */
RADEONEngineReset(pScrn);
@@ -4391,7 +4416,8 @@ static void RADEONRestoreMemMapRegisters
}
}
- RADEONTRACE(("Updating display base addresses...\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Updating display base addresses...\n");
OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr);
if (pRADEONEnt->HasCRTC2)
@@ -4402,7 +4428,8 @@ static void RADEONRestoreMemMapRegisters
/* More paranoia delays, wait 100ms */
usleep(100000);
- RADEONTRACE(("Memory map updated.\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Memory map updated.\n");
}
#ifdef XF86DRI
@@ -4538,8 +4565,9 @@ static void RADEONRestoreCrtcRegisters(S
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONTRACE(("Programming CRTC1, offset: 0x%08lx\n",
- restore->crtc_offset));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Programming CRTC1, offset: 0x%08lx\n",
+ restore->crtc_offset);
/* We prevent the CRTC from hitting the memory controller until
* fully programmed
@@ -4592,8 +4620,9 @@ static void RADEONRestoreCrtc2Registers(
unsigned char *RADEONMMIO = info->MMIO;
CARD32 crtc2_gen_cntl;
- RADEONTRACE(("Programming CRTC2, offset: 0x%08lx\n",
- restore->crtc2_offset));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Programming CRTC2, offset: 0x%08lx\n",
+ restore->crtc2_offset);
crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) &
(RADEON_CRTC2_VSYNC_DIS |
@@ -4798,15 +4827,17 @@ static void RADEONRestorePLLRegisters(Sc
| RADEON_PPLL_ATOMIC_UPDATE_EN
| RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
- RADEONTRACE(("Wrote: 0x%08x 0x%08x 0x%08lx (0x%08x)\n",
- restore->ppll_ref_div,
- restore->ppll_div_3,
- restore->htotal_cntl,
- INPLL(pScrn, RADEON_PPLL_CNTL)));
- RADEONTRACE(("Wrote: rd=%d, fd=%d, pd=%d\n",
- restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
- restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
- (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Wrote: 0x%08x 0x%08x 0x%08lx (0x%08x)\n",
+ restore->ppll_ref_div,
+ restore->ppll_div_3,
+ restore->htotal_cntl,
+ INPLL(pScrn, RADEON_PPLL_CNTL));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Wrote: rd=%d, fd=%d, pd=%d\n",
+ restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
+ restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
+ (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
usleep(50000); /* Let the clock to lock */
@@ -4857,15 +4888,17 @@ static void RADEONRestorePLL2Registers(S
| RADEON_P2PLL_ATOMIC_UPDATE_EN
| RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN));
- RADEONTRACE(("Wrote: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n",
- restore->p2pll_ref_div,
- restore->p2pll_div_0,
- restore->htotal_cntl2,
- INPLL(pScrn, RADEON_P2PLL_CNTL)));
- RADEONTRACE(("Wrote: rd=%ld, fd=%ld, pd=%ld\n",
- restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
- restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
- (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Wrote: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n",
+ restore->p2pll_ref_div,
+ restore->p2pll_div_0,
+ restore->htotal_cntl2,
+ INPLL(pScrn, RADEON_P2PLL_CNTL));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Wrote: rd=%ld, fd=%ld, pd=%ld\n",
+ restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
+ restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
+ (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16);
usleep(5000); /* Let the clock to lock */
@@ -5092,7 +5125,9 @@ static void RADEONRestoreMode(ScrnInfoPt
RADEONController* pCRTC1 = pRADEONEnt->Controller[0];
RADEONController* pCRTC2 = pRADEONEnt->Controller[1];
RADEONConnector *pPort;
- RADEONTRACE(("RADEONRestoreMode(%p)\n", restore));
+
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONRestoreMode(%p)\n", restore);
/* For Non-dual head card, we don't have private field in the Entity */
if (!pRADEONEnt->HasCRTC2) {
@@ -5338,14 +5373,16 @@ static void RADEONSavePLLRegisters(ScrnI
save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL);
save->vclk_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
- RADEONTRACE(("Read: 0x%08x 0x%08x 0x%08lx\n",
- save->ppll_ref_div,
- save->ppll_div_3,
- save->htotal_cntl));
- RADEONTRACE(("Read: rd=%d, fd=%d, pd=%d\n",
- save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
- save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
- (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Read: 0x%08x 0x%08x 0x%08lx\n",
+ save->ppll_ref_div,
+ save->ppll_div_3,
+ save->htotal_cntl);
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Read: rd=%d, fd=%d, pd=%d\n",
+ save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
+ save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
+ (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
}
/* Read PLL registers */
@@ -5356,14 +5393,16 @@ static void RADEONSavePLL2Registers(Scrn
save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL);
save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- RADEONTRACE(("Read: 0x%08lx 0x%08lx 0x%08lx\n",
- save->p2pll_ref_div,
- save->p2pll_div_0,
- save->htotal_cntl2));
- RADEONTRACE(("Read: rd=%ld, fd=%ld, pd=%ld\n",
- save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
- save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
- (save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >> 16));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Read: 0x%08lx 0x%08lx 0x%08lx\n",
+ save->p2pll_ref_div,
+ save->p2pll_div_0,
+ save->htotal_cntl2);
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Read: rd=%ld, fd=%ld, pd=%ld\n",
+ save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
+ save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
+ (save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >> 16);
}
/* Read palette data */
@@ -5391,7 +5430,8 @@ static void RADEONSaveMode(ScrnInfoPtr p
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONTRACE(("RADEONSaveMode(%p)\n", save));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONSaveMode(%p)\n", save);
if (info->IsSecondary) {
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
@@ -5409,7 +5449,8 @@ static void RADEONSaveMode(ScrnInfoPtr p
/*memcpy(&info->ModeReg, &info->SavedReg, sizeof(RADEONSaveRec));*/
}
- RADEONTRACE(("RADEONSaveMode returns %p\n", save));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONSaveMode returns %p\n", save);
}
/* Save everything needed to restore the original VC state */
@@ -5419,7 +5460,9 @@ static void RADEONSave(ScrnInfoPtr pScrn
unsigned char *RADEONMMIO = info->MMIO;
RADEONSavePtr save = &info->SavedReg;
- RADEONTRACE(("RADEONSave\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONSave\n");
+
if (info->FBDev) {
RADEONSaveMemMapRegisters(pScrn, save);
fbdevHWSave(pScrn);
@@ -5464,7 +5507,8 @@ static void RADEONRestore(ScrnInfoPtr pS
unsigned char *RADEONMMIO = info->MMIO;
RADEONSavePtr restore = &info->SavedReg;
- RADEONTRACE(("RADEONRestore\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONRestore\n");
#if X_BYTE_ORDER == X_BIG_ENDIAN
RADEONWaitForFifo(pScrn, 1);
@@ -6251,11 +6295,12 @@ static void RADEONInitPLLRegisters(ScrnI
pll->reference_freq);
save->post_div = post_div->divider;
- RADEONTRACE(("dc=%ld, of=%ld, fd=%d, pd=%d\n",
- save->dot_clock_freq,
- save->pll_output_freq,
- save->feedback_div,
- save->post_div));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "dc=%ld, of=%ld, fd=%d, pd=%d\n",
+ save->dot_clock_freq,
+ save->pll_output_freq,
+ save->feedback_div,
+ save->post_div);
save->ppll_ref_div = pll->reference_div;
save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
@@ -6318,11 +6363,12 @@ static void RADEONInitPLL2Registers(Scrn
pll->reference_freq);
save->post_div_2 = post_div->divider;
- RADEONTRACE(("dc=%ld, of=%ld, fd=%d, pd=%d\n",
- save->dot_clock_freq_2,
- save->pll_output_freq_2,
- save->feedback_div_2,
- save->post_div_2));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "dc=%ld, of=%ld, fd=%d, pd=%d\n",
+ save->dot_clock_freq_2,
+ save->pll_output_freq_2,
+ save->feedback_div_2,
+ save->post_div_2);
save->p2pll_ref_div = pll->reference_div;
save->p2pll_div_0 = (save->feedback_div_2 |
@@ -6356,23 +6402,23 @@ static Bool RADEONInit2(ScrnInfoPtr pScr
RADEONInfoPtr info0 = NULL;
ScrnInfoPtr pScrn0 = NULL;
-#if RADEON_DEBUG
if (crtc1 && (crtc_mask & 1)) {
- ErrorF("%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)",
- crtc1->name,
- crtc1->Clock/1000.0,
-
- crtc1->HDisplay,
- crtc1->HSyncStart,
- crtc1->HSyncEnd,
- crtc1->HTotal,
-
- crtc1->VDisplay,
- crtc1->VSyncStart,
- crtc1->VSyncEnd,
- crtc1->VTotal,
- pScrn->depth,
- pScrn->bitsPerPixel);
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)",
+ crtc1->name,
+ crtc1->Clock/1000.0,
+
+ crtc1->HDisplay,
+ crtc1->HSyncStart,
+ crtc1->HSyncEnd,
+ crtc1->HTotal,
+
+ crtc1->VDisplay,
+ crtc1->VSyncStart,
+ crtc1->VSyncEnd,
+ crtc1->VTotal,
+ pScrn->depth,
+ pScrn->bitsPerPixel);
if (crtc1->Flags & V_DBLSCAN) ErrorF(" D");
if (crtc1->Flags & V_CSYNC) ErrorF(" C");
if (crtc1->Flags & V_INTERLACE) ErrorF(" I");
@@ -6383,21 +6429,22 @@ static Bool RADEONInit2(ScrnInfoPtr pScr
ErrorF("\n");
}
if (crtc2 && (crtc_mask & 2)) {
- ErrorF("%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)",
- crtc2->name,
- crtc2->Clock/1000.0,
-
- crtc2->CrtcHDisplay,
- crtc2->CrtcHSyncStart,
- crtc2->CrtcHSyncEnd,
- crtc2->CrtcHTotal,
-
- crtc2->CrtcVDisplay,
- crtc2->CrtcVSyncStart,
- crtc2->CrtcVSyncEnd,
- crtc2->CrtcVTotal,
- pScrn->depth,
- pScrn->bitsPerPixel);
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)",
+ crtc2->name,
+ crtc2->Clock/1000.0,
+
+ crtc2->CrtcHDisplay,
+ crtc2->CrtcHSyncStart,
+ crtc2->CrtcHSyncEnd,
+ crtc2->CrtcHTotal,
+
+ crtc2->CrtcVDisplay,
+ crtc2->CrtcVSyncStart,
+ crtc2->CrtcVSyncEnd,
+ crtc2->CrtcVTotal,
+ pScrn->depth,
+ pScrn->bitsPerPixel);
if (crtc2->Flags & V_DBLSCAN) ErrorF(" D");
if (crtc2->Flags & V_CSYNC) ErrorF(" C");
if (crtc2->Flags & V_INTERLACE) ErrorF(" I");
@@ -6407,7 +6454,6 @@ static Bool RADEONInit2(ScrnInfoPtr pScr
if (crtc2->Flags & V_NVSYNC) ErrorF(" -V");
ErrorF("\n");
}
-#endif
if (crtc1 && (crtc_mask & 1))
info->Flags = crtc1->Flags;
@@ -6467,7 +6513,8 @@ static Bool RADEONInit2(ScrnInfoPtr pScr
return FALSE;
}
- RADEONTRACE(("RADEONInit returns %p\n", save));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONInit returns %p\n", save);
return TRUE;
}
@@ -6491,7 +6538,8 @@ static Bool RADEONModeInit(ScrnInfoPtr p
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONTRACE(("RADEONModeInit()\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONModeInit()\n");
if (!RADEONInit(pScrn, mode, &info->ModeReg)) return FALSE;
@@ -6513,7 +6561,8 @@ static Bool RADEONSaveScreen(ScreenPtr p
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
Bool unblank;
- RADEONTRACE(("RADEONSaveScreen(%d)\n", mode));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONSaveScreen(%d)\n", mode);
unblank = xf86IsUnblank(mode);
if (unblank) SetTimeSinceLastInputEvent();
@@ -6560,7 +6609,8 @@ Bool RADEONSwitchMode(int scrnIndex, Dis
}
#endif
- RADEONTRACE(("RADEONSwitchMode() !n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONSwitchMode() !n");
if (info->allowColorTiling) {
if (info->MergedFB) {
@@ -6678,7 +6728,8 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pSc
#endif
#if 0 /* Verbose */
- RADEONTRACE(("RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone);
#endif
if (info->showCache && y) {
@@ -6817,7 +6868,8 @@ Bool RADEONEnterVT(int scrnIndex, int fl
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONTRACE(("RADEONEnterVT\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONEnterVT\n");
if (INREG(RADEON_CONFIG_MEMSIZE) == 0) { /* Softboot V_BIOS */
xf86Int10InfoPtr pInt;
@@ -6888,7 +6940,8 @@ void RADEONLeaveVT(int scrnIndex, int fl
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONSavePtr save = &info->ModeReg;
- RADEONTRACE(("RADEONLeaveVT\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONLeaveVT\n");
#ifdef XF86DRI
if (RADEONPTR(pScrn)->directRenderingInited) {
DRILock(pScrn->pScreen, 0);
@@ -6926,7 +6979,8 @@ void RADEONLeaveVT(int scrnIndex, int fl
RADEONRestore(pScrn);
- RADEONTRACE(("Ok, leaving now...\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Ok, leaving now...\n");
}
/* Called at the end of each server generation. Restore the original
@@ -6938,7 +6992,8 @@ static Bool RADEONCloseScreen(int scrnIn
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONTRACE(("RADEONCloseScreen\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONCloseScreen\n");
/* Mark acceleration as stopped or we might try to access the engine at
* wrong times, especially if we had DRI, after DRI has been stopped
@@ -6971,7 +7026,8 @@ static Bool RADEONCloseScreen(int scrnIn
RADEONRestore(pScrn);
}
- RADEONTRACE(("Disposing accel...\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Disposing accel...\n");
#ifdef USE_EXA
if (info->exa) {
exaDriverFini(pScreen);
@@ -6991,14 +7047,17 @@ static Bool RADEONCloseScreen(int scrnIn
}
#endif /* USE_XAA */
- RADEONTRACE(("Disposing cusor info\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Disposing cusor info\n");
if (info->cursor) xf86DestroyCursorInfoRec(info->cursor);
info->cursor = NULL;
- RADEONTRACE(("Disposing DGA\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Disposing DGA\n");
if (info->DGAModes) xfree(info->DGAModes);
info->DGAModes = NULL;
- RADEONTRACE(("Unmapping memory\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Unmapping memory\n");
RADEONUnmapMem(pScrn);
pScrn->vtSema = FALSE;
@@ -7015,7 +7074,8 @@ void RADEONFreeScreen(int scrnIndex, int
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONTRACE(("RADEONFreeScreen\n"));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONFreeScreen\n");
/* when server quits at PreInit, we don't need do this anymore*/
if (!info) return;
diff-tree 09bfc8ed000f95ede5b73f2bad69edc1a4d9bac6 (from 764cb73e8dec4040cdd418d249fc504399fca3ee)
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Sun May 20 18:06:22 2007 -0400
update to 6.6.192 for rc release
diff --git a/configure.ac b/configure.ac
index ddfa7c8..8b29d8d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.6.191,
+ 6.6.192,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
diff-tree 764cb73e8dec4040cdd418d249fc504399fca3ee (from a3ee42207aab77d93655a82fdcb32be38268b85f)
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Sun May 20 17:26:26 2007 -0400
Fix regular/"xinerama"/zaphod dualhead mode
- logic in RADEONUnblank() was wrong
- Calling RADEONSetupConnectors() on second instance screwed up the port info
- still seem to be HW cursor issues with zaphod mode
diff --git a/src/radeon_display.c b/src/radeon_display.c
index f3b86e6..fb345a9 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -2135,7 +2135,9 @@ void RADEONUnblank(ScrnInfoPtr pScrn)
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONConnector *pPort;
- if (!pRADEONEnt->HasSecondary || (info->IsSwitching && !info->IsSecondary)) {
+ if (!pRADEONEnt->HasSecondary ||
+ (pRADEONEnt->HasSecondary && !info->IsSwitching) ||
+ (info->IsSwitching && (!info->IsSecondary))) {
pPort = RADEONGetCrtcConnector(pScrn, 1);
if (pPort)
RADEONUnblankSet(pScrn, pPort);
@@ -2158,7 +2160,8 @@ void RADEONUnblank(ScrnInfoPtr pScrn)
}
}
- if (info->IsSwitching && info->IsSecondary) {
+ if ((pRADEONEnt->HasSecondary && !info->IsSwitching) ||
+ (info->IsSwitching && info->IsSecondary)) {
pPort = RADEONGetCrtcConnector(pScrn, 2);
if (pPort)
RADEONUnblankSet(pScrn, pPort);
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index b9cce22..933265f 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2971,7 +2971,9 @@ static Bool RADEONPreInitControllers(Scr
RADEONGetBIOSInfo(pScrn, pInt10);
- RADEONSetupConnectors(pScrn);
+ if (!info->IsSecondary) {
+ RADEONSetupConnectors(pScrn);
+ }
RADEONMapControllers(pScrn);
RADEONGetClockInfo(pScrn);
diff-tree dd6a966e862b774a8e8b9e1a085309219673efad (from c81ed9bd7b37c9d02141d10f6c7bad3d0c57032f)
Author: Dave Airlie <airlied at nx6125b.(none)>
Date: Sun Apr 22 11:36:00 2007 +1000
radeon: add support for DDC on some laptop chipsets
I noticed fglrx has DDC for the panel in the rs480 laptop, however radeon
didn't pick it up, so I valgrinded fglrx and spotted 0x1a0/0x1a4 accesses
I actually noticed this before from the BIOS but never figured it out.
So now I get DDC from the LCD on this laptop.
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 1d4c9bb..dd3d0a7 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -181,6 +181,9 @@ Bool RADEONGetConnectorInfoFromBIOS (Scr
case RADEON_GPIO_CRT2_DDC:
pRADEONEnt->PortInfo[crtc]->DDCType = DDC_CRT2;
break;
+ case RADEON_LCD_GPIO_MASK:
+ pRADEONEnt->PortInfo[crtc]->DDCType = DDC_LCD;
+ break;
default:
pRADEONEnt->PortInfo[crtc]->DDCType = DDC_NONE_DETECTED;
break;
@@ -290,7 +293,7 @@ Bool RADEONGetConnectorInfoFromBIOS (Scr
if ((tmp0 = RADEON_BIOS16(tmp + 0x15))) {
if ((tmp1 = RADEON_BIOS8(tmp0+2) & 0x07)) {
pRADEONEnt->PortInfo[0]->DDCType = tmp1;
- if (pRADEONEnt->PortInfo[0]->DDCType > DDC_CRT2) {
+ if (pRADEONEnt->PortInfo[0]->DDCType > DDC_LCD) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Unknown DDCType %d found\n",
pRADEONEnt->PortInfo[0]->DDCType);
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 57e752e..f3b86e6 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -75,12 +75,13 @@ const char *TMDSTypeName[3] = {
"External"
};
-const char *DDCTypeName[5] = {
+const char *DDCTypeName[6] = {
"NONE",
"MONID",
"DVI_DDC",
"VGA_DDC",
- "CRT2_DDC"
+ "CRT2_DDC",
+ "LCD_DDC"
};
const char *DACTypeName[3] = {
@@ -166,10 +167,16 @@ static void RADEONI2CGetBits(I2CBusPtr b
unsigned char *RADEONMMIO = info->MMIO;
/* Get the result */
- val = INREG(info->DDCReg);
- *Clock = (val & RADEON_GPIO_Y_1) != 0;
- *data = (val & RADEON_GPIO_Y_0) != 0;
+ if (info->DDCReg == RADEON_LCD_GPIO_MASK) {
+ val = INREG(info->DDCReg+4);
+ *Clock = (val & (1<<13)) != 0;
+ *data = (val & (1<<12)) != 0;
+ } else {
+ val = INREG(info->DDCReg);
+ *Clock = (val & RADEON_GPIO_Y_1) != 0;
+ *data = (val & RADEON_GPIO_Y_0) != 0;
+ }
}
static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data)
@@ -179,11 +186,17 @@ static void RADEONI2CPutBits(I2CBusPtr b
unsigned long val;
unsigned char *RADEONMMIO = info->MMIO;
- val = INREG(info->DDCReg) & (CARD32)~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1);
- val |= (Clock ? 0:RADEON_GPIO_EN_1);
- val |= (data ? 0:RADEON_GPIO_EN_0);
- OUTREG(info->DDCReg, val);
-
+ if (info->DDCReg == RADEON_LCD_GPIO_MASK) {
+ val = INREG(info->DDCReg) & (CARD32)~((1<<12) | (1<<13));
+ val |= (Clock ? 0:(1<<13));
+ val |= (data ? 0:(1<<12));
+ OUTREG(info->DDCReg, val);
+ } else {
+ val = INREG(info->DDCReg) & (CARD32)~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1);
+ val |= (Clock ? 0:RADEON_GPIO_EN_1);
+ val |= (data ? 0:RADEON_GPIO_EN_0);
+ OUTREG(info->DDCReg, val);
+ }
/* read back to improve reliability on some cards. */
val = INREG(info->DDCReg);
}
@@ -562,13 +575,16 @@ static RADEONMonitorType RADEONDisplayDD
case DDC_CRT2:
info->DDCReg = RADEON_GPIO_CRT2_DDC;
break;
+ case DDC_LCD:
+ info->DDCReg = RADEON_LCD_GPIO_MASK;
+ break;
default:
info->DDCReg = DDCReg;
return MT_NONE;
}
/* Read and output monitor info using DDC2 over I2C bus */
- if (info->pI2CBus && info->ddc2) {
+ if (info->pI2CBus && info->ddc2 && (info->DDCReg != RADEON_LCD_GPIO_MASK)) {
OUTREG(info->DDCReg, INREG(info->DDCReg) &
(CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1));
@@ -620,15 +636,17 @@ static RADEONMonitorType RADEONDisplayDD
OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_1);
OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_0);
usleep(15000);
- if(*MonInfo) break;
+ if(*MonInfo) break;
}
+ } else if (info->pI2CBus && info->ddc2 && info->DDCReg == RADEON_LCD_GPIO_MASK) {
+ *MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, info->pI2CBus);
} else {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n");
MonType = MT_NONE;
}
OUTREG(info->DDCReg, INREG(info->DDCReg) &
- ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1));
+ ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1));
if (*MonInfo) {
if ((*MonInfo)->rawData[0x14] & 0x80) {
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index f446516..dc30e2e 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -48,7 +48,8 @@ typedef enum
DDC_MONID,
DDC_DVI,
DDC_VGA,
- DDC_CRT2
+ DDC_CRT2,
+ DDC_LCD,
} RADEONDDCType;
typedef enum
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index b50fcf0..0d5e586 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -907,6 +907,8 @@
# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13)
# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
+#define RADEON_LCD_GPIO_MASK 0x01a0
+#define RADEON_LCD_GPIO_Y_REG 0x01a4
#define RADEON_MDGPIO_A_REG 0x01ac
#define RADEON_MDGPIO_EN_REG 0x01b0
#define RADEON_MDGPIO_MASK 0x0198
More information about the xorg-commit
mailing list