xf86-video-ati: Branch 'master'

[Dave Airlie]

 src/radeon.h        |    1 +
 src/radeon_driver.c |   31 ++++++++++++++++++++-----------
 src/radeon_reg.h    |    2 ++
 3 files changed, 23 insertions(+), 11 deletions(-)

New commits:
diff-tree 104105fee5c3945d3f210e6a4cb73ab492c61543 (from 5aa603bcabbb077dec169c48438c2e2ebe1195d7)
Author: Dave Airlie <airlied at nx6125b.(none)>
Date:   Tue May 29 19:09:33 2007 +1000

    rs480: make second crtc work with magic number in magic register.
    
    I've no idea why or what this does.

diff --git a/src/radeon.h b/src/radeon.h
index 3ea44f3..3e79c1b 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -318,6 +318,7 @@ typedef struct {
 
     CARD32            tv_dac_cntl;
 
+    CARD32            rs480_unk_e38;
 } RADEONSaveRec, *RADEONSavePtr;
 
 typedef struct {
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index b0e4037..a3d8a03 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4664,6 +4664,9 @@ static void RADEONRestoreCrtc2Registers(
     OUTREG(RADEON_CRTC2_PITCH,           restore->crtc2_pitch);
     OUTREG(RADEON_DISP2_MERGE_CNTL,      restore->disp2_merge_cntl);
 
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38);
+    }
     OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 
 }
@@ -4858,11 +4861,10 @@ static void RADEONRestorePLL2Registers(S
     OUTPLLP(pScrn,
 	    RADEON_P2PLL_CNTL,
 	    RADEON_P2PLL_RESET
-	    | RADEON_P2PLL_ATOMIC_UPDATE_EN
-	    | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN,
+	    | RADEON_P2PLL_ATOMIC_UPDATE_EN,
 	    ~(RADEON_P2PLL_RESET
-	      | RADEON_P2PLL_ATOMIC_UPDATE_EN
-	      | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN));
+	      | RADEON_P2PLL_ATOMIC_UPDATE_EN));
+
 
     OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV,
 	    restore->p2pll_ref_div,
@@ -4885,17 +4887,16 @@ static void RADEONRestorePLL2Registers(S
 	    0,
 	    ~(RADEON_P2PLL_RESET
 	      | RADEON_P2PLL_SLEEP
-	      | RADEON_P2PLL_ATOMIC_UPDATE_EN
-	      | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN));
+	      | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-		   "Wrote: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n",
+		   "Wrote2: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n",
 		   restore->p2pll_ref_div,
 		   restore->p2pll_div_0,
 		   restore->htotal_cntl2,
 		   INPLL(pScrn, RADEON_P2PLL_CNTL));
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-		   "Wrote: rd=%ld, fd=%ld, pd=%ld\n",
+		   "Wrote2: rd=%ld, fd=%ld, pd=%ld\n",
 		   restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 		   restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
 		   (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16);
@@ -5362,6 +5363,9 @@ static void RADEONSaveCrtc2Registers(Scr
     save->fp_h2_sync_strt_wid   = INREG (RADEON_FP_H2_SYNC_STRT_WID);
     save->fp_v2_sync_strt_wid   = INREG (RADEON_FP_V2_SYNC_STRT_WID);
 
+    if (info->ChipFamily == CHIP_FAMILY_RS400)
+	save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38);
+    
     save->disp2_merge_cntl      = INREG(RADEON_DISP2_MERGE_CNTL);
 }
 
@@ -5636,10 +5640,10 @@ static void RADEONInitTvDacCntl(ScrnInfo
 			       RADEON_TV_DAC_GDACPD);
     }
     /* FIXME: doesn't make sense, this just replaces the previous value... */
-    save->tv_dac_cntl = (RADEON_TV_DAC_NBLANK |
+    save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 			 RADEON_TV_DAC_NHOLD |
-			 RADEON_TV_DAC_STD_PS2 |
-			 info->tv_dac_adj);
+			  RADEON_TV_DAC_STD_PS2);
+			  //			 info->tv_dac_adj);
 }
 
 static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
@@ -6236,6 +6240,11 @@ static Bool RADEONInitCrtc2Registers(Scr
     }
 #endif
  
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	save->rs480_unk_e38 = info->SavedReg.rs480_unk_e38 & ~(0x300);
+	save->rs480_unk_e38 |= 0x100;
+    }
+
     return TRUE;
 }
 
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 81acd46..476c56b 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3126,4 +3126,6 @@
 #       define RADEON_TVCLK_SRC_SEL_TVPLL        (1 << 30)
 #       define RADEON_TVPLL_SLEEP                (1 <<  3)
 #       define RADEON_TVPLL_REFCLK_SEL           (1 <<  4)
+
+#define RADEON_RS480_UNK_e38			0xe38
 #endif