xf86-video-ati: Branch 'randr-1.2'
Alex Deucher
agd5f at kemper.freedesktop.org
Thu May 10 06:21:10 PDT 2007
src/radeon.h | 2 +
src/radeon_display.c | 87 ++++++++++++++++++++++++++++++++++++++++++--------
src/radeon_driver.c | 88 ++++++++++++++++++++++++++++-----------------------
3 files changed, 125 insertions(+), 52 deletions(-)
New commits:
diff-tree 0cb23277666db3b30438c6f88840d861e04df414 (from 33c370b1d8350945f80ac12097d3e91243a400f2)
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Thu May 10 15:20:56 2007 +0200
RADEON: randr driver re-org checkpoint
- split the mode setting per-crtc
- reduce start up flicker
diff --git a/src/radeon.h b/src/radeon.h
index 6afed66..98ca96b 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -884,6 +884,8 @@ void
radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg);
void
radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image);
+void
+RADEONEnableOutputs(ScrnInfoPtr pScrn, int crtc_num);
#ifdef XF86DRI
#ifdef USE_XAA
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 7fb2b77..3c75149 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -2217,6 +2217,11 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int m
mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS);
+ if (radeon_crtc->crtc_id)
+ ErrorF("crtc2 mode: %d", mode);
+ else
+ ErrorF("crtc1 mode: %d", mode);
+
switch(mode) {
case DPMSModeOn:
if (radeon_crtc->crtc_id) {
@@ -2274,6 +2279,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, D
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONMonitorType montype;
int i = 0;
+ double dot_clock = 0;
for (i = 0; i < xf86_config->num_output; i++) {
xf86OutputPtr output = xf86_config->output[i];
@@ -2286,30 +2292,85 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, D
}
}
+ ErrorF("init memmap\n");
+ RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info);
+ ErrorF("init common\n");
+ RADEONInitCommonRegisters(&info->ModeReg, info);
+
switch (radeon_crtc->crtc_id) {
- case 0:
- RADEONInit2(pScrn, adjusted_mode, NULL, 1, &info->ModeReg, montype);
- break;
+ case 0:
+ ErrorF("init crtc1\n");
+ RADEONInitCrtcRegisters(pScrn, &info->ModeReg, adjusted_mode, info);
+ dot_clock = adjusted_mode->Clock / 1000.0;
+ if (dot_clock) {
+ ErrorF("init pll1\n");
+ RADEONInitPLLRegisters(pScrn, info, &info->ModeReg, &info->pll, dot_clock);
+ } else {
+ info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
+ info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
+ info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
+ }
+ /*RADEONInit2(pScrn, adjusted_mode, NULL, 1, &info->ModeReg, montype);*/
+ break;
case 1:
- RADEONInit2(pScrn, NULL, adjusted_mode, 2, &info->ModeReg, montype);
- break;
- }
+ ErrorF("init crtc2\n");
+ RADEONInitCrtc2Registers(pScrn, &info->ModeReg, adjusted_mode, info);
+ dot_clock = adjusted_mode->Clock / 1000.0;
+ if (dot_clock) {
+ ErrorF("init pll2\n");
+ RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, dot_clock, montype != MT_CRT);
+ }
+ /*RADEONInit2(pScrn, NULL, adjusted_mode, 2, &info->ModeReg, montype);*/
+ break;
+ }
+
+ radeon_crtc_dpms(crtc, DPMSModeOff);
+
+ ErrorF("restore memmap\n");
+ RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg);
+ ErrorF("restore common\n");
+ RADEONRestoreCommonRegisters(pScrn, &info->ModeReg);
- RADEONBlank(pScrn);
- if (radeon_crtc->crtc_id == 0)
+ switch (radeon_crtc->crtc_id) {
+ case 0:
+ ErrorF("adjustframe 1\n");
RADEONDoAdjustFrame(pScrn, x, y, FALSE);
- else if (radeon_crtc->crtc_id == 1)
+ ErrorF("restore crtc1\n");
+ RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
+ ErrorF("restore FP1\n");
+ RADEONRestoreFPRegisters(pScrn, &info->ModeReg);
+ ErrorF("restore dac\n");
+ RADEONRestoreDACRegisters(pScrn, &info->ModeReg);
+ ErrorF("restore pll1\n");
+ RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
+ ErrorF("enable 1\n");
+ RADEONEnableOutputs(pScrn, 1);
+ break;
+ case 1:
+ ErrorF("adjustframe 2\n");
RADEONDoAdjustFrame(pScrn, x, y, TRUE);
- RADEONRestoreMode(pScrn, &info->ModeReg);
+ ErrorF("restore crtc2\n");
+ RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg);
+ ErrorF("restore fp2\n");
+ RADEONRestoreFPRegisters(pScrn, &info->ModeReg);
+ ErrorF("restore dac2\n");
+ RADEONRestoreDACRegisters(pScrn, &info->ModeReg);
+ ErrorF("restore pll2\n");
+ RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
+ ErrorF("enable 2\n");
+ RADEONEnableOutputs(pScrn, 2);
+ break;
+ }
- ErrorF("mode restored\n");
- ErrorF("frame adjusted\n");
+ /* RADEONRestoreMode(pScrn, &info->ModeReg);*/
if (info->DispPriority)
RADEONInitDispBandwidth(pScrn);
ErrorF("bandwidth set\n");
- RADEONUnblank(pScrn);
+ /*RADEONUnblank(pScrn);*/
+ radeon_crtc_dpms(crtc, DPMSModeOn);
+
ErrorF("unblank\n");
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 1e94c58..ab67f49 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1169,7 +1169,7 @@ static Bool RADEONPreInitWeight(ScrnInfo
return TRUE;
}
-static void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
RADEONInfoPtr info)
{
save->mc_fb_location = info->mc_fb_location;
@@ -3825,7 +3825,7 @@ Bool RADEONScreenInit(int scrnIndex, Scr
}
/* Write memory mapping registers */
-static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
+void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -4031,7 +4031,7 @@ static void RADEONAdjustMemMapRegisters(
#endif
/* Write common registers */
-static void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
+void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -4094,8 +4094,36 @@ static void RADEONRestoreFBDevRegisters(
#endif
}
+void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ OUTREGP(RADEON_DAC_CNTL,
+ restore->dac_cntl,
+ RADEON_DAC_RANGE_CNTL |
+ RADEON_DAC_BLANKING);
+
+ OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
+
+ //OUTREG(RADEON_TV_DAC_CNTL, 0x00280203);
+ if ((info->ChipFamily != CHIP_FAMILY_RADEON) &&
+ (info->ChipFamily != CHIP_FAMILY_R200))
+ OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
+
+ if ((info->ChipFamily == CHIP_FAMILY_R200) ||
+ IS_R300_VARIANT) {
+ OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
+ OUTREG(RADEON_DISP_TV_OUT_CNTL, restore->disp_tv_out_cntl);
+ } else {
+ OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
+ }
+
+}
+
/* Write CRTC registers */
-static void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
+void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -4116,11 +4144,6 @@ static void RADEONRestoreCrtcRegisters(S
RADEON_CRTC_HSYNC_DIS |
RADEON_CRTC_DISPLAY_DIS);
- OUTREGP(RADEON_DAC_CNTL,
- restore->dac_cntl,
- RADEON_DAC_RANGE_CNTL |
- RADEON_DAC_BLANKING);
-
OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
@@ -4148,42 +4171,29 @@ static void RADEONRestoreCrtcRegisters(S
}
/* Write CRTC2 registers */
-static void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
+void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- CARD32 crtc2_gen_cntl;
+ /* CARD32 crtc2_gen_cntl;*/
RADEONTRACE(("Programming CRTC2, offset: 0x%08lx\n",
restore->crtc2_offset));
- crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) &
+ /* crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) &
(RADEON_CRTC2_VSYNC_DIS |
RADEON_CRTC2_HSYNC_DIS |
RADEON_CRTC2_DISP_DIS);
- crtc2_gen_cntl |= restore->crtc2_gen_cntl;
+ crtc2_gen_cntl |= restore->crtc2_gen_cntl;*/
/* We prevent the CRTC from hitting the memory controller until
* fully programmed
*/
OUTREG(RADEON_CRTC2_GEN_CNTL,
- crtc2_gen_cntl | RADEON_CRTC2_DISP_REQ_EN_B);
-
- OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
-
- //OUTREG(RADEON_TV_DAC_CNTL, 0x00280203);
- if ((info->ChipFamily != CHIP_FAMILY_RADEON) &&
- (info->ChipFamily != CHIP_FAMILY_R200))
- OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
-
- if ((info->ChipFamily == CHIP_FAMILY_R200) ||
- IS_R300_VARIANT) {
- OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
- OUTREG(RADEON_DISP_TV_OUT_CNTL, restore->disp_tv_out_cntl);
- } else {
- OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
- }
+ restore->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
+ RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
+ RADEON_CRTC2_DISP_REQ_EN_B);
OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
@@ -4198,12 +4208,12 @@ static void RADEONRestoreCrtc2Registers(
OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
- OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+ OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
}
/* Write flat panel registers */
-static void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
@@ -4277,7 +4287,7 @@ static void RADEONPLL2WriteUpdate(ScrnIn
}
/* Write PLL registers */
-static void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
+void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -4383,7 +4393,7 @@ static void RADEONRestorePLLRegisters(Sc
/* Write PLL2 registers */
-static void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
+void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
RADEONSavePtr restore)
{
OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL,
@@ -4627,7 +4637,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pS
RADEONSaveSurfaces(pScrn, &info->ModeReg);
}
-static void
+void
RADEONEnableOutputs(ScrnInfoPtr pScrn, int crtc_num)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -5105,7 +5115,7 @@ void RADEONRestore(ScrnInfoPtr pScrn)
}
/* Define common registers for requested video mode */
-static void RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
+void RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
{
save->ovr_clr = 0;
save->ovr_wid_left_right = 0;
@@ -5430,7 +5440,7 @@ static void RADEONInitOutputRegisters(Sc
}
/* Define CRTC registers for requested video mode */
-static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
DisplayModePtr mode, RADEONInfoPtr info)
{
int format;
@@ -5623,7 +5633,7 @@ static Bool RADEONInitCrtcRegisters(Scrn
}
/* Define CRTC2 registers for requested video mode */
-static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
+Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
DisplayModePtr mode, RADEONInfoPtr info)
{
int format;
@@ -5766,7 +5776,7 @@ static Bool RADEONInitCrtc2Registers(Scr
/* Define PLL registers for requested video mode */
-static void RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
+void RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
RADEONSavePtr save, RADEONPLLPtr pll,
double dot_clock)
{
@@ -5836,7 +5846,7 @@ static void RADEONInitPLLRegisters(ScrnI
}
/* Define PLL2 registers for requested video mode */
-static void RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
+void RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
RADEONPLLPtr pll, double dot_clock,
int no_odd_postdiv)
{
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