xf86-video-intel: src/i830_memory.c

[Eric Anholt]

 src/i830_memory.c |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletion(-)

New commits:
diff-tree 1ed3843f73a0d8efa405daff3483ebe70bf6134f (from 7aa257154685bd2520649ce87a3a84e55644d02c)
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Mar 12 17:47:32 2007 -0700

    Make the 965 use Y-major tiling for the depth buffer, as required by the spec.
    
    An example of the failure can be seen with the reflect demo when set to
    depth buffer mode.
    
    Reported by:	Haihao Xiang <haihao.xiang at intel.com>

diff --git a/src/i830_memory.c b/src/i830_memory.c
index e5168e1..0742d8c 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1122,12 +1122,19 @@ i830_allocate_depthbuffer(ScrnInfoPtr pS
     /* First try allocating it tiled */
     if (!pI830->disableTiling && IsTileable(pScrn, pitch))
     {
+	enum tile_format tile_format;
+
 	size = ROUND_TO_PAGE(pitch * ALIGN(height, 16));
 
+	/* The 965 requires that the depth buffer be in Y Major format, while
+	 * the rest appear to fail when handed that format.
+	 */
+	tile_format = IS_I965G(pI830) ? TILING_YMAJOR: TILING_XMAJOR;
+
 	pI830->depth_buffer =
 	    i830_allocate_memory_tiled(pScrn, "depth buffer", size, pitch,
 				       GTT_PAGE_SIZE, ALIGN_BOTH_ENDS,
-				       TILING_XMAJOR);
+				       tile_format);
 	pI830->depth_tiled = FENCE_XMAJOR;
     }