xf86-video-ati: Branch 'randr-1.2' - 6 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Thu Jun 28 21:45:59 PDT 2007
src/radeon.h | 2
src/radeon_crtc.c | 380 ++++++++++++++++++++++++++--------------------------
src/radeon_cursor.c | 11 -
src/radeon_driver.c | 59 +-------
src/radeon_modes.c | 2
src/radeon_output.c | 2
6 files changed, 212 insertions(+), 244 deletions(-)
New commits:
diff-tree 21be0d3a1f4700572c6425800596785d6850626f (from d9bf28b55d98fea2d285c9c46362aaf2175d0a46)
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Fri Jun 29 00:38:50 2007 -0400
RADEON: simplify console restore
- still need to track crtcs for blank/unblank when restoring text console
diff --git a/src/radeon.h b/src/radeon.h
index a3aa074..c8b18b0 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -238,7 +238,7 @@ typedef struct {
/* CRTC2 registers */
CARD32 crtc2_gen_cntl;
-
+ CARD32 dac_macro_cntl;
CARD32 dac2_cntl;
CARD32 disp_output_cntl;
CARD32 disp_tv_out_cntl;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 655e8ee..c555869 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4118,6 +4118,8 @@ void RADEONRestoreDACRegisters(ScrnInfoP
OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
}
+ OUTREG(RADEON_DAC_MACRO_CNTL, restore->dac_macro_cntl);
+
/* R200 DAC connected via DVO */
if (info->ChipFamily == CHIP_FAMILY_R200)
OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl);
@@ -4678,23 +4680,6 @@ void RADEONChangeSurfaces(ScrnInfoPtr pS
RADEONSaveSurfaces(pScrn, &info->ModeReg);
}
-void
-RADEONEnableOutputs(ScrnInfoPtr pScrn, int crtc_num)
-{
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- xf86CrtcPtr crtc = pRADEONEnt->pCrtc[crtc_num];
- int i;
-
- /* get the output connected to this CRTC */
- for (i = 0; i < xf86_config->num_output; i++) {
- xf86OutputPtr output = xf86_config->output[i];
- if (output->crtc == crtc) {
- RADEONEnableDisplay(output, TRUE);
- }
- }
-}
-
/* Write out state to define a new video mode */
void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore)
{
@@ -4703,25 +4688,6 @@ void RADEONRestoreMode(ScrnInfoPtr pScrn
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONRestoreMode(%p)\n", restore);
- /* For Non-dual head card, we don't have private field in the Entity */
- if (!pRADEONEnt->HasCRTC2) {
- RADEONRestoreMemMapRegisters(pScrn, restore);
- RADEONRestoreCommonRegisters(pScrn, restore);
- RADEONRestoreCrtcRegisters(pScrn, restore);
- RADEONRestoreRMXRegisters(pScrn, restore);
- RADEONRestoreFPRegisters(pScrn, restore);
- RADEONRestoreFP2Registers(pScrn, restore);
- RADEONRestoreLVDSRegisters(pScrn, restore);
- RADEONRestoreDACRegisters(pScrn, restore);
- RADEONRestorePLLRegisters(pScrn, restore);
- return;
- }
-
- /* Disable all outputs at initial mode set. the ones we want will
- get set by RADEONEnableDisplay()
- */
- RADEONDisableDisplays(pScrn);
-
/* When changing mode with Dual-head card, care must be taken for
* the special order in setting registers. CRTC2 has to be set
* before changing CRTC_EXT register. In the dual-head setup, X
@@ -4736,8 +4702,11 @@ void RADEONRestoreMode(ScrnInfoPtr pScrn
*/
RADEONRestoreMemMapRegisters(pScrn, restore);
RADEONRestoreCommonRegisters(pScrn, restore);
- RADEONRestoreCrtc2Registers(pScrn, restore);
- RADEONRestorePLL2Registers(pScrn, restore);
+
+ if (pRADEONEnt->HasCRTC2) {
+ RADEONRestoreCrtc2Registers(pScrn, restore);
+ RADEONRestorePLL2Registers(pScrn, restore);
+ }
RADEONRestoreCrtcRegisters(pScrn, restore);
RADEONRestorePLLRegisters(pScrn, restore);
@@ -4747,9 +4716,6 @@ void RADEONRestoreMode(ScrnInfoPtr pScrn
RADEONRestoreLVDSRegisters(pScrn, restore);
RADEONRestoreDACRegisters(pScrn, restore);
- RADEONEnableOutputs(pScrn, 0);
- RADEONEnableOutputs(pScrn, 1);
-
#if 0
RADEONRestorePalette(pScrn, &info->SavedReg);
#endif
@@ -4860,7 +4826,7 @@ static void RADEONSaveDACRegisters(ScrnI
save->disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL);
save->disp_tv_out_cntl = INREG(RADEON_DISP_TV_OUT_CNTL);
save->disp_hw_debug = INREG(RADEON_DISP_HW_DEBUG);
-
+ save->dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL);
}
/* Read flat panel registers */
@@ -4881,9 +4847,6 @@ static void RADEONSaveFPRegisters(ScrnIn
save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH);
save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
-
if (info->ChipFamily == CHIP_FAMILY_RV280) {
/* bit 22 of TMDS_PLL_CNTL is read-back inverted */
save->tmds_pll_cntl ^= (1 << 22);
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 5585345..e431bf5 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -857,6 +857,8 @@ static void RADEONInitDACRegisters(xf86O
save->dac_cntl = (RADEON_DAC_MASK_ALL
| RADEON_DAC_VGA_ADR_EN
| (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN));
+
+ save->dac_macro_cntl = info->SavedReg.dac_macro_cntl;
}
/* XXX: fix me */
diff-tree d9bf28b55d98fea2d285c9c46362aaf2175d0a46 (from 9f193985627be8e6ea1418a424e825ddbc4957b2)
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Thu Jun 28 23:52:28 2007 -0400
RADEON: factor out surface_cntl init into one function
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index df75bc3..e1196b3 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -143,6 +143,32 @@ RADEONInitCommonRegisters(RADEONSavePtr
save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
}
+static void
+RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+
+ save->surface_cntl = 0;
+
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ /* We must set both apertures as they can be both used to map the entire
+ * video memory. -BenH.
+ */
+ switch (pScrn->bitsPerPixel) {
+ case 16:
+ save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
+ save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
+ break;
+
+ case 32:
+ save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
+ save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
+ break;
+ }
+#endif
+
+}
+
static Bool
RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
int x, int y)
@@ -301,27 +327,9 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc
RADEON_CRTC_HSYNC_DIS |
RADEON_CRTC_DISPLAY_DIS);
- save->surface_cntl = 0;
save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* We must set both apertures as they can be both used to map the entire
- * video memory. -BenH.
- */
- switch (pScrn->bitsPerPixel) {
- case 16:
- save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
- save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
- break;
-
- case 32:
- save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
- save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
- break;
- }
-#endif
-
save->crtc_more_cntl = 0;
if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200)) {
@@ -577,25 +585,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crt
save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
- /* We must set SURFACE_CNTL properly on the second screen too */
- save->surface_cntl = 0;
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* We must set both apertures as they can be both used to map the entire
- * video memory. -BenH.
- */
- switch (pScrn->bitsPerPixel) {
- case 16:
- save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
- save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
- break;
-
- case 32:
- save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
- save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
- break;
- }
-#endif
-
if (info->ChipFamily == CHIP_FAMILY_RS400) {
save->rs480_unk_e30 = 0x105DC1CC; /* because I'm worth it */
save->rs480_unk_e34 = 0x2749D000; /* AMD really should */
@@ -798,6 +787,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, D
ErrorF("init common\n");
RADEONInitCommonRegisters(&info->ModeReg, info);
+ RADEONInitSurfaceCntl(crtc, &info->ModeReg);
+
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("init crtc1\n");
diff-tree 9f193985627be8e6ea1418a424e825ddbc4957b2 (from 0f361e9e80a29d287fa42436c32c657e3c102539)
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Thu Jun 28 23:43:13 2007 -0400
RADEON: move crtc base setups to new functions
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index d7eadd8..df75bc3 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -143,25 +143,131 @@ RADEONInitCommonRegisters(RADEONSavePtr
save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
}
-/* Define CRTC registers for requested video mode */
static Bool
-RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
- DisplayModePtr mode, int x, int y)
+RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
+ int x, int y)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- //RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- int format;
- int hsync_start;
- int hsync_wid;
- int vsync_wid;
int Base;
#ifdef XF86DRI
RADEONSAREAPrivPtr pSAREAPriv;
XF86DRISAREAPtr pSAREA;
#endif
+ save->crtc_offset = pScrn->fbOffset;
+#ifdef XF86DRI
+ if (info->allowPageFlip)
+ save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
+#endif
+
+
+ if (info->tilingEnabled) {
+ if (IS_R300_VARIANT)
+ save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
+ R300_CRTC_MICRO_TILE_BUFFER_DIS |
+ R300_CRTC_MACRO_TILE_EN);
+ else
+ save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
+ }
+ else {
+ if (IS_R300_VARIANT)
+ save->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
+ R300_CRTC_MICRO_TILE_BUFFER_DIS |
+ R300_CRTC_MACRO_TILE_EN);
+ else
+ save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
+ }
+
+ Base = pScrn->fbOffset;
+
+ if (info->tilingEnabled) {
+ if (IS_R300_VARIANT) {
+ /* On r300/r400 when tiling is enabled crtc_offset is set to the address of
+ * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc
+ * Makes tiling MUCH easier.
+ */
+ save->crtc_tile_x0_y0 = x | (y << 16);
+ Base &= ~0x7ff;
+ } else {
+ /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
+ drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes
+ flickering when scrolling vertically in a virtual screen, possibly because crtc will
+ pick up the new offset value at the end of each scanline, but the new offset_cntl value
+ only after a vsync. We'd probably need to wait (in drm) for vsync and only then update
+ OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */
+ save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL) & ~0xf;
+#if 0
+ /* try to get rid of flickering when scrolling at least for 2d */
+#ifdef XF86DRI
+ if (!info->have3DWindows)
+#endif
+ save->crtc_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
+#endif
+
+ int byteshift = info->CurrentLayout.bitsPerPixel >> 4;
+ /* crtc uses 256(bytes)x8 "half-tile" start addresses? */
+ int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11;
+ Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
+ save->crtc_offset_cntl = save->crtc_offset_cntl | (y % 16);
+ }
+ }
+ else {
+ int offset = y * info->CurrentLayout.displayWidth + x;
+ switch (info->CurrentLayout.pixel_code) {
+ case 15:
+ case 16: offset *= 2; break;
+ case 24: offset *= 3; break;
+ case 32: offset *= 4; break;
+ }
+ Base += offset;
+ }
+
+ Base &= ~7; /* 3 lower bits are always 0 */
+
+
+#ifdef XF86DRI
+ if (info->directRenderingInited) {
+ /* note cannot use pScrn->pScreen since this is unitialized when called from
+ RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */
+ /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for
+ *** pageflipping!
+ ***/
+ pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
+ /* can't get at sarea in a semi-sane way? */
+ pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec));
+
+ pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes)
+ % info->CurrentLayout.displayWidth;
+ pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes)
+ / info->CurrentLayout.displayWidth;
+ pSAREA->frame.width = pScrn->frameX1 - x + 1;
+ pSAREA->frame.height = pScrn->frameY1 - y + 1;
+
+ if (pSAREAPriv->pfCurrentPage == 1) {
+ Base += info->backOffset - info->frontOffset;
+ }
+ }
+#endif
+ save->crtc_offset = Base;
+
+ return TRUE;
+
+}
+
+/* Define CRTC registers for requested video mode */
+static Bool
+RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
+ DisplayModePtr mode)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ int format;
+ int hsync_start;
+ int hsync_wid;
+ int vsync_wid;
+
switch (info->CurrentLayout.pixel_code) {
case 4: format = 1; break;
case 8: format = 2; break;
@@ -254,39 +360,74 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc
? RADEON_CRTC_V_SYNC_POL
: 0));
- save->crtc_offset = pScrn->fbOffset;
+ save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) +
+ ((pScrn->bitsPerPixel * 8) -1)) /
+ (pScrn->bitsPerPixel * 8));
+ save->crtc_pitch |= save->crtc_pitch << 16;
+
+ save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
+ save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
+ save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
+ save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
+
+ if (info->IsDellServer) {
+ save->dac2_cntl = info->SavedReg.dac2_cntl;
+ save->tv_dac_cntl = info->SavedReg.tv_dac_cntl;
+ save->crtc2_gen_cntl = info->SavedReg.crtc2_gen_cntl;
+ save->disp_hw_debug = info->SavedReg.disp_hw_debug;
+
+ save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
+ save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
+
+ /* For CRT on DAC2, don't turn it on if BIOS didn't
+ enable it, even it's detected.
+ */
+ save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+ save->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
+ save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
+ }
+
+ return TRUE;
+}
+
+static Bool
+RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
+ int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ int Base;
+#ifdef XF86DRI
+ RADEONSAREAPrivPtr pSAREAPriv;
+ XF86DRISAREAPtr pSAREA;
+#endif
+
+ /* It seems all fancy options apart from pflip can be safely disabled
+ */
+ save->crtc2_offset = pScrn->fbOffset;
#ifdef XF86DRI
if (info->allowPageFlip)
- save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
+ save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
#endif
if (info->tilingEnabled) {
if (IS_R300_VARIANT)
- save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
- R300_CRTC_MICRO_TILE_BUFFER_DIS |
- R300_CRTC_MACRO_TILE_EN);
+ save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
+ R300_CRTC_MICRO_TILE_BUFFER_DIS |
+ R300_CRTC_MACRO_TILE_EN);
else
- save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
+ save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
}
else {
if (IS_R300_VARIANT)
- save->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
+ save->crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
R300_CRTC_MICRO_TILE_BUFFER_DIS |
R300_CRTC_MACRO_TILE_EN);
else
- save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
+ save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
}
- save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) +
- ((pScrn->bitsPerPixel * 8) -1)) /
- (pScrn->bitsPerPixel * 8));
- save->crtc_pitch |= save->crtc_pitch << 16;
-
- save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
- save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
- save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
- save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
-
Base = pScrn->fbOffset;
if (info->tilingEnabled) {
@@ -295,7 +436,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc
* the surface. the x/y offsets are handled by the X_Y tile reg for each crtc
* Makes tiling MUCH easier.
*/
- save->crtc_tile_x0_y0 = x | (y << 16);
+ save->crtc2_tile_x0_y0 = x | (y << 16);
Base &= ~0x7ff;
} else {
/* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
@@ -304,20 +445,20 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc
pick up the new offset value at the end of each scanline, but the new offset_cntl value
only after a vsync. We'd probably need to wait (in drm) for vsync and only then update
OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */
- save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL) & ~0xf;
+ save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & ~0xf;
#if 0
/* try to get rid of flickering when scrolling at least for 2d */
#ifdef XF86DRI
if (!info->have3DWindows)
#endif
- save->crtc_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
+ save->crtc2_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
#endif
-
+
int byteshift = info->CurrentLayout.bitsPerPixel >> 4;
/* crtc uses 256(bytes)x8 "half-tile" start addresses? */
int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11;
Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
- save->crtc_offset_cntl = save->crtc_offset_cntl | (y % 16);
+ save->crtc2_offset_cntl = save->crtc_offset_cntl | (y % 16);
}
}
else {
@@ -333,7 +474,6 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc
Base &= ~7; /* 3 lower bits are always 0 */
-
#ifdef XF86DRI
if (info->directRenderingInited) {
/* note cannot use pScrn->pScreen since this is unitialized when called from
@@ -345,37 +485,14 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc
/* can't get at sarea in a semi-sane way? */
pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec));
- pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes)
- % info->CurrentLayout.displayWidth;
- pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes)
- / info->CurrentLayout.displayWidth;
- pSAREA->frame.width = pScrn->frameX1 - x + 1;
- pSAREA->frame.height = pScrn->frameY1 - y + 1;
+ pSAREAPriv->crtc2_base = Base;
if (pSAREAPriv->pfCurrentPage == 1) {
Base += info->backOffset - info->frontOffset;
}
}
#endif
- save->crtc_offset = Base;
-
-
- if (info->IsDellServer) {
- save->dac2_cntl = info->SavedReg.dac2_cntl;
- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl;
- save->crtc2_gen_cntl = info->SavedReg.crtc2_gen_cntl;
- save->disp_hw_debug = info->SavedReg.disp_hw_debug;
-
- save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
- save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
-
- /* For CRT on DAC2, don't turn it on if BIOS didn't
- enable it, even it's detected.
- */
- save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
- save->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
- save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
- }
+ save->crtc2_offset = Base;
return TRUE;
}
@@ -383,21 +500,14 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc
/* Define CRTC2 registers for requested video mode */
static Bool
RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
- DisplayModePtr mode, int x, int y)
+ DisplayModePtr mode)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- //RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
int format;
int hsync_start;
int hsync_wid;
int vsync_wid;
- int Base;
-#ifdef XF86DRI
- RADEONSAREAPrivPtr pSAREAPriv;
- XF86DRISAREAPtr pSAREA;
-#endif
switch (info->CurrentLayout.pixel_code) {
case 4: format = 1; break;
@@ -442,31 +552,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crt
? RADEON_CRTC2_V_SYNC_POL
: 0));
- /* It seems all fancy options apart from pflip can be safely disabled
- */
- save->crtc2_offset = pScrn->fbOffset;
-#ifdef XF86DRI
- if (info->allowPageFlip)
- save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
-#endif
-
- if (info->tilingEnabled) {
- if (IS_R300_VARIANT)
- save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
- R300_CRTC_MICRO_TILE_BUFFER_DIS |
- R300_CRTC_MACRO_TILE_EN);
- else
- save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
- }
- else {
- if (IS_R300_VARIANT)
- save->crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
- R300_CRTC_MICRO_TILE_BUFFER_DIS |
- R300_CRTC_MACRO_TILE_EN);
- else
- save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
- }
-
save->crtc2_pitch = ((info->CurrentLayout.displayWidth * pScrn->bitsPerPixel) +
((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8);
save->crtc2_pitch |= save->crtc2_pitch << 16;
@@ -492,72 +577,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crt
save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
- Base = pScrn->fbOffset;
-
- if (info->tilingEnabled) {
- if (IS_R300_VARIANT) {
- /* On r300/r400 when tiling is enabled crtc_offset is set to the address of
- * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc
- * Makes tiling MUCH easier.
- */
- save->crtc2_tile_x0_y0 = x | (y << 16);
- Base &= ~0x7ff;
- } else {
- /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
- drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes
- flickering when scrolling vertically in a virtual screen, possibly because crtc will
- pick up the new offset value at the end of each scanline, but the new offset_cntl value
- only after a vsync. We'd probably need to wait (in drm) for vsync and only then update
- OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */
- save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & ~0xf;
-#if 0
- /* try to get rid of flickering when scrolling at least for 2d */
-#ifdef XF86DRI
- if (!info->have3DWindows)
-#endif
- save->crtc2_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
-#endif
-
- int byteshift = info->CurrentLayout.bitsPerPixel >> 4;
- /* crtc uses 256(bytes)x8 "half-tile" start addresses? */
- int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11;
- Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
- save->crtc2_offset_cntl = save->crtc_offset_cntl | (y % 16);
- }
- }
- else {
- int offset = y * info->CurrentLayout.displayWidth + x;
- switch (info->CurrentLayout.pixel_code) {
- case 15:
- case 16: offset *= 2; break;
- case 24: offset *= 3; break;
- case 32: offset *= 4; break;
- }
- Base += offset;
- }
-
- Base &= ~7; /* 3 lower bits are always 0 */
-
-#ifdef XF86DRI
- if (info->directRenderingInited) {
- /* note cannot use pScrn->pScreen since this is unitialized when called from
- RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */
- /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for
- *** pageflipping!
- ***/
- pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
- /* can't get at sarea in a semi-sane way? */
- pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec));
-
- pSAREAPriv->crtc2_base = Base;
-
- if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
- }
- }
-#endif
- save->crtc2_offset = Base;
-
/* We must set SURFACE_CNTL properly on the second screen too */
save->surface_cntl = 0;
#if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -782,7 +801,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, D
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("init crtc1\n");
- RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode, x, y);
+ RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode);
+ RADEONInitCrtcBase(crtc, &info->ModeReg, x, y);
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
@@ -795,7 +815,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, D
break;
case 1:
ErrorF("init crtc2\n");
- RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode, x, y);
+ RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode);
+ RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y);
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll2\n");
diff-tree 0f361e9e80a29d287fa42436c32c657e3c102539 (from 1d4630067d293d26284d5fe230debef3913ec6cf)
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Thu Jun 28 23:08:07 2007 -0400
RADEON: fix corruption after 3D apps run
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 048175b..655e8ee 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2540,7 +2540,7 @@ RADEONCRTCResize(ScrnInfoPtr scrn, int w
{
scrn->virtualX = width;
scrn->virtualY = height;
- RADEONSetPitch(scrn);
+ /* RADEONSetPitch(scrn); */
return TRUE;
}
@@ -2792,7 +2792,7 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr
ErrorF("after xf86InitialConfiguration\n");
- RADEONSetPitch(pScrn);
+ RADEONSetPitch(pScrn);
/* Set display resolution */
xf86SetDpi(pScrn, 0, 0);
diff-tree 1d4630067d293d26284d5fe230debef3913ec6cf (from 2754d1ba01fc3367019487e0c0f59d74c950aaa7)
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Thu Jun 28 22:24:04 2007 -0400
RADEON: set info->CurrentLayout.displayWidth in RADEONSetPitch()
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 42565e4..048175b 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2810,8 +2810,6 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr
if (!RADEONPreInitXv(pScrn)) goto fail;
- info->CurrentLayout.displayWidth = pScrn->displayWidth;
-
if (!xf86RandR12PreInit (pScrn))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n");
diff --git a/src/radeon_modes.c b/src/radeon_modes.c
index 6952dd5..66d8a7f 100644
--- a/src/radeon_modes.c
+++ b/src/radeon_modes.c
@@ -74,6 +74,8 @@ void RADEONSetPitch (ScrnInfoPtr pScrn)
break;
}
pScrn->displayWidth = dummy;
+ info->CurrentLayout.displayWidth = pScrn->displayWidth;
+
}
/* This is used only when no mode is specified for FP and no ddc is
diff-tree 2754d1ba01fc3367019487e0c0f59d74c950aaa7 (from 7901bcafa92dccd319ddb5de4627d806a39f15f9)
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Thu Jun 28 22:15:22 2007 -0400
RADEON: Switch cursor back to memcpy()
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index e59d2b3..f19f2bc 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -219,8 +219,6 @@ radeon_crtc_load_cursor_argb (xf86CrtcPt
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
- int x, y, w, h;
- CARD32 *i;
RADEONCTRACE(("RADEONLoadCursorARGB\n"));
@@ -228,14 +226,7 @@ radeon_crtc_load_cursor_argb (xf86CrtcPt
CURSOR_SWAPPING_START();
- w = CURSOR_WIDTH;
- h = CURSOR_HEIGHT;
- for (y = 0; y < h; y++) {
- i = image;
- image += w;
- for (x = 0; x < w; x++)
- *d++ = *i++;
- }
+ memcpy (d, image, CURSOR_HEIGHT * CURSOR_WIDTH * 4);
CURSOR_SWAPPING_END ();
}
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