xf86-video-intel: 2 commits - src/i830_display.c

[Keith Packard]

 src/i830_display.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

New commits:
diff-tree ec236c76b93aea5f2ee1e8b8509cde4625974fcb (from d957c6b8e1dde8e11c1db3431e0ff58c5d984880)
Author: Keith Packard <keithp at neko.keithp.com>
Date:   Fri Jun 22 16:32:46 2007 +0100

    I830 needs to have plane/pipe/pll started in mode_set.
    
    The patch for the i855 to stop enabling plane/pipe/pll in mode_set broke the
    i830. Revert that just for the i830, leaving it enabled for the i855.

diff --git a/src/i830_display.c b/src/i830_display.c
index 1f0f5b8..f6e99be 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -963,7 +963,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
      * will be run after the mode is set. On 9xx, it helps.
      * On 855, it can lock up the chip (and the entire machine)
      */
-    if (IS_I9XX (pI830))
+    if (!IS_I85X (pI830))
     {
 	dspcntr |= DISPLAY_PLANE_ENABLE;
 	pipeconf |= PIPEACONF_ENABLE;
diff-tree d957c6b8e1dde8e11c1db3431e0ff58c5d984880 (from a67c2965385001bcb8987265f698ff0f5809cd11)
Author: Keith Packard <keithp at neko.keithp.com>
Date:   Fri Jun 22 01:32:02 2007 +0100

    Increase vblank wait timeout from 20ms to 30ms. 49.6Hz < 20ms.
    
    The x40 LVDS mode has a 49.6Hz vertical refresh. Waiting for only 20ms can
    sometimes cause the driver to start programming the hardware before the
    vblank has occurred, which will lock up the i855 chipset. Extend this to
    30ms (the maximum timeout used by the BIOS) to ensure this doesn't happen.
    
    Detecting actual vblank occurance using the various status registers should
    also be possible but isn't yet working.

diff --git a/src/i830_display.c b/src/i830_display.c
index 2df1fcc..1f0f5b8 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -362,7 +362,7 @@ void
 i830WaitForVblank(ScrnInfoPtr pScreen)
 {
     /* Wait for 20ms, i.e. one cycle at 50hz. */
-    usleep(20000);
+    usleep(30000);
 }
 
 void