xf86-video-intel: src/i810_reg.h

[Keith Packard]

 src/i810_reg.h |   23 ++++++++++++++++++++++-
 1 files changed, 22 insertions(+), 1 deletion(-)

New commits:
diff-tree 15caa64a497dcc0eacb0f91166d9b70206a8db35 (from 404fd47573f855b0442d49a383542fc093825ad0)
Author: Keith Packard <keithp at neko.keithp.com>
Date:   Fri Jun 8 18:44:28 2007 -0700

    Add description for how to use the frame and pixel counter registers.
    
    The 24-bit frame and pixel counters were not described in detail and
    will be useful for DRM.

diff --git a/src/i810_reg.h b/src/i810_reg.h
index 8df664e..6001297 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -1967,9 +1967,30 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
 #define DSPFW1			0x70034
 #define DSPFW2			0x70038
 #define DSPFW3			0x7003c
+/*
+ * The two pipe frame counter registers are not synchronized, so
+ * reading a stable value is somewhat tricky. The following code 
+ * should work:
+ *
+ *  do {
+ *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT;
+ *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> PIPE_FRAME_LOW_SHIFT);
+ *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT);
+ *  } while (high1 != high2);
+ *  frame = (high1 << 8) | low1;
+ */
 #define PIPEAFRAMEHIGH		0x70040
+#define PIPE_FRAME_HIGH_MASK	0x0000ffff
+#define PIPE_FRAME_HIGH_SHIFT	0
 #define PIPEAFRAMEPIXEL		0x70044
-
+#define PIPE_FRAME_LOW_MASK	0xff000000
+#define PIPE_FRAME_LOW_SHIFT	24
+/*
+ * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register
+ * and is 24 bits wide.
+ */
+#define PIPE_PIXEL_MASK		0x00ffffff
+#define PIPE_PIXEL_SHIFT	0
 
 #define PIPEB_DSL		0x71000