xserver: Branch 'pci-rework' - 2 commits
Ian Romanick
idr at kemper.freedesktop.org
Mon Jan 15 22:08:15 EET 2007
configure.ac | 2 +-
hw/xfree86/common/xf86pciBus.c | 30 +++++++++++++++---------------
hw/xfree86/int10/helper_exec.c | 6 +++---
hw/xfree86/int10/xf86int10.c | 6 +++---
4 files changed, 22 insertions(+), 22 deletions(-)
New commits:
diff-tree 079a6a55a516778871a8b2f8e9c8dd9162105a76 (from d8bd0c41de11d12976a5ea9f185b7ac6c7060b71)
Author: Ian Romanick <idr at us.ibm.com>
Date: Mon Jan 15 11:39:24 2007 -0800
Convert to new pci_device_cfg_write_u* interface.
diff --git a/configure.ac b/configure.ac
index 524f90a..5fc1768 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1263,7 +1263,7 @@ dnl has it in libc), or if libdl is need
AC_CHECK_FUNC([dlopen], [],
AC_CHECK_LIB([dl], [dlopen], XORG_LIBS="$XORG_LIBS -ldl"))
- PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.5.0])
+ PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.8.0])
XSERVER_LIBS="$XSERVER_LIBS $PCIACCESS_LIBS"
XORG_CFLAGS="$XORG_CFLAGS $PCIACCESS_CFLAGS"
diff-tree d8bd0c41de11d12976a5ea9f185b7ac6c7060b71 (from a87af8218f97da76433a5192d5e51aca0d5c3ed0)
Author: Ian Romanick <idr at us.ibm.com>
Date: Mon Jan 15 11:38:22 2007 -0800
Convert to new pci_device_cfg_write_u* interface.
diff --git a/hw/xfree86/common/xf86pciBus.c b/hw/xfree86/common/xf86pciBus.c
index 00aad15..89543e1 100644
--- a/hw/xfree86/common/xf86pciBus.c
+++ b/hw/xfree86/common/xf86pciBus.c
@@ -260,7 +260,7 @@ pciIoAccessEnable(void* arg)
ErrorF("pciIoAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
- pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
+ pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
#endif
}
@@ -272,7 +272,7 @@ pciIoAccessDisable(void* arg)
ErrorF("pciIoAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl &= ~SETBITS;
- pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
+ pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
#endif
}
@@ -286,7 +286,7 @@ pciIo_MemAccessEnable(void* arg)
ErrorF("pciIo_MemAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
- pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
+ pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
#endif
}
@@ -298,7 +298,7 @@ pciIo_MemAccessDisable(void* arg)
ErrorF("pciIo_MemAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl &= ~SETBITS;
- pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
+ pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
#endif
}
@@ -312,7 +312,7 @@ pciMemAccessEnable(void* arg)
ErrorF("pciMemAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
- pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
+ pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
#endif
}
@@ -324,7 +324,7 @@ pciMemAccessDisable(void* arg)
ErrorF("pciMemAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl &= ~SETBITS;
- pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
+ pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
#endif
}
#undef SETBITS
@@ -347,7 +347,7 @@ pciBusAccessEnable(BusAccPtr ptr)
if ((ctrl & MASKBITS) != PCI_PCI_BRIDGE_VGA_EN) {
ctrl = (ctrl | PCI_PCI_BRIDGE_VGA_EN) &
~(PCI_PCI_BRIDGE_MASTER_ABORT_EN | PCI_PCI_BRIDGE_SECONDARY_RESET);
- pci_device_cfg_write_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
+ pci_device_cfg_write_u16(dev, ctrl, PCI_PCI_BRIDGE_CONTROL_REG);
}
#endif
}
@@ -366,7 +366,7 @@ pciBusAccessDisable(BusAccPtr ptr)
pci_device_cfg_read_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
if (ctrl & MASKBITS) {
ctrl &= ~(MASKBITS | PCI_PCI_BRIDGE_SECONDARY_RESET);
- pci_device_cfg_write_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
+ pci_device_cfg_write_u16(dev, ctrl, PCI_PCI_BRIDGE_CONTROL_REG);
}
#endif
}
@@ -459,17 +459,17 @@ restorePciState( struct pci_device * dev
int i;
/* disable card before setting anything */
- pci_device_cfg_write_bits( dev, PCI_CMD_MEM_ENABLE | PCI_CMD_IO_ENABLE, 0,
- PCI_CMD_STAT_REG );
+ pci_device_cfg_write_bits(dev, PCI_CMD_MEM_ENABLE | PCI_CMD_IO_ENABLE, 0,
+ PCI_CMD_STAT_REG);
- pci_device_cfg_write_u32( dev, & ptr->biosBase, PCI_CMD_BIOS_REG );
+ pci_device_cfg_write_u32(dev, ptr->biosBase, PCI_CMD_BIOS_REG);
for ( i = 0; i < 6; i++ ) {
- pci_device_cfg_write_u32( dev, & ptr->base[i],
- PCI_CMD_BASE_REG + (i * 4) );
+ pci_device_cfg_write_u32(dev, ptr->base[i],
+ PCI_CMD_BASE_REG + (i * 4));
}
- pci_device_cfg_write_u32( dev, & ptr->command, PCI_CMD_STAT_REG );
+ pci_device_cfg_write_u32(dev, ptr->command, PCI_CMD_STAT_REG);
#endif
}
@@ -507,7 +507,7 @@ restorePciBusState(BusAccPtr ptr)
if ((ctrl ^ ptr->busdep.pci.save.control) & MASKBITS) {
ctrl &= ~(MASKBITS | PCI_PCI_BRIDGE_SECONDARY_RESET);
ctrl |= ptr->busdep.pci.save.control & MASKBITS;
- pci_device_cfg_write_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
+ pci_device_cfg_write_u16(dev, ctrl, PCI_PCI_BRIDGE_CONTROL_REG);
}
#endif
}
diff --git a/hw/xfree86/int10/helper_exec.c b/hw/xfree86/int10/helper_exec.c
index 9937d65..aef24cc 100644
--- a/hw/xfree86/int10/helper_exec.c
+++ b/hw/xfree86/int10/helper_exec.c
@@ -494,7 +494,7 @@ pciCfg1out(CARD16 addr, CARD32 val)
return 1;
}
if (addr == 0xCFC) {
- pci_device_cfg_write_u32(Int10Current->dev, & val, OFFSET(PciCfg1Addr));
+ pci_device_cfg_write_u32(Int10Current->dev, val, OFFSET(PciCfg1Addr));
return 1;
}
return 0;
@@ -533,7 +533,7 @@ pciCfg1outw(CARD16 addr, CARD16 val)
if ((addr >= 0xCFC) && (addr <= 0xCFF)) {
const unsigned offset = addr - 0xCFC;
- pci_device_cfg_write_u16(Int10Current->dev, & val, OFFSET(PciCfg1Addr) + offset);
+ pci_device_cfg_write_u16(Int10Current->dev, val, OFFSET(PciCfg1Addr) + offset);
return 1;
}
return 0;
@@ -572,7 +572,7 @@ pciCfg1outb(CARD16 addr, CARD8 val)
if ((addr >= 0xCFC) && (addr <= 0xCFF)) {
const unsigned offset = addr - 0xCFC;
- pci_device_cfg_write_u8(Int10Current->dev, & val, OFFSET(PciCfg1Addr) + offset);
+ pci_device_cfg_write_u8(Int10Current->dev, val, OFFSET(PciCfg1Addr) + offset);
return 1;
}
return 0;
diff --git a/hw/xfree86/int10/xf86int10.c b/hw/xfree86/int10/xf86int10.c
index 1b58b92..535978b 100644
--- a/hw/xfree86/int10/xf86int10.c
+++ b/hw/xfree86/int10/xf86int10.c
@@ -769,7 +769,7 @@ int1A_handler(xf86Int10InfoPtr pInt)
return 1;
case 0xb10b:
if ((dev = findPci(pInt, X86_EBX)) != NULL) {
- pci_device_cfg_write_u8(dev, & X86_CL, X86_EDI);
+ pci_device_cfg_write_u8(dev, X86_CL, X86_EDI);
X86_EAX = X86_AL | (SUCCESSFUL << 8);
X86_EFLAGS &= ~((unsigned long)0x01); /* clear carry flag */
} else {
@@ -782,7 +782,7 @@ int1A_handler(xf86Int10InfoPtr pInt)
return 1;
case 0xb10c:
if ((dev = findPci(pInt, X86_EBX)) != NULL) {
- pci_device_cfg_write_u16(dev, & X86_CX, X86_EDI);
+ pci_device_cfg_write_u16(dev, X86_CX, X86_EDI);
X86_EAX = X86_AL | (SUCCESSFUL << 8);
X86_EFLAGS &= ~((unsigned long)0x01); /* clear carry flag */
} else {
@@ -795,7 +795,7 @@ int1A_handler(xf86Int10InfoPtr pInt)
return 1;
case 0xb10d:
if ((dev = findPci(pInt, X86_EBX)) != NULL) {
- pci_device_cfg_write_u32(dev, & X86_ECX, X86_EDI);
+ pci_device_cfg_write_u32(dev, X86_ECX, X86_EDI);
X86_EAX = X86_AL | (SUCCESSFUL << 8);
X86_EFLAGS &= ~((unsigned long)0x01); /* clear carry flag */
} else {
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