xf86-video-intel: Branch 'modesetting' - 2 commits - src/i810_reg.h src/i830_debug.c src/i830_display.c

[Eric Anholt]

 src/i810_reg.h     |   14 +++++++++
 src/i830_debug.c   |    8 ++++-
 src/i830_display.c |   75 ++++++++++++++++++++++++++++++++++++++++++-----------
 3 files changed, 80 insertions(+), 17 deletions(-)

New commits:
diff-tree 6e33c4c44030e05d6d07ca9274cfe4d6df2c0387 (from 4541150cdce3f2f83b8530d0863aecf28c6610a9)
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Feb 15 09:54:43 2007 -0800

    Print the correct meaning of bit 30 of pipeconf for 965 in debug output.

diff --git a/src/i810_reg.h b/src/i810_reg.h
index 2c06056..455c226 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -1690,6 +1690,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
 #define PIPEACONF_ENABLE	(1<<31)
 #define PIPEACONF_DISABLE	0
 #define PIPEACONF_DOUBLE_WIDE	(1<<30)
+#define I965_PIPECONF_ACTIVE	(1<<30)
 #define PIPEACONF_SINGLE_WIDE	0
 #define PIPEACONF_PIPE_UNLOCKED 0
 #define PIPEACONF_PIPE_LOCKED	(1<<25)
diff --git a/src/i830_debug.c b/src/i830_debug.c
index e0be0a4..6716eaa 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -69,8 +69,12 @@ DEBUGSTRING(i830_debug_dspcntr)
 DEBUGSTRING(i830_debug_pipeconf)
 {
     char *enabled = val & PIPEACONF_ENABLE ? "enabled" : "disabled";
-    char *wide = val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
-    return XNFprintf("%s, %s", enabled, wide);
+    char *bit30;
+    if (IS_I965G(pI830))
+	bit30 = val & I965_PIPECONF_ACTIVE ? "active" : "inactive";
+    else
+	bit30 = val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
+    return XNFprintf("%s, %s", enabled, bit30);
 }
 
 DEBUGSTRING(i830_debug_hvtotal)
diff-tree 4541150cdce3f2f83b8530d0863aecf28c6610a9 (from d1be0dc4e9d443dcbd218a083cfb21a0b5d634ee)
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Feb 15 09:51:04 2007 -0800

    Detect core clock frequencies, to avoid double-wide mode when possible.
    
    Additionally, don't attempt to set double-wide on the 965, where there is
    no such thing any more (not that we'd ever see modes high enough to trigger
    it).

diff --git a/src/i810_reg.h b/src/i810_reg.h
index 68cce93..2c06056 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -1848,6 +1848,19 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
 #define I852_GME				0x2
 #define I852_GM					0x5
 
+#define I915_GCFGC			0xf0
+#define I915_LOW_FREQUENCY_ENABLE		(1 << 7)
+#define I915_DISPLAY_CLOCK_190_200_MHZ		(0 << 4)
+#define I915_DISPLAY_CLOCK_333_MHZ		(4 << 4)
+#define I915_DISPLAY_CLOCK_MASK			(7 << 4)
+
+#define I855_HPLLCC			0xc0
+#define I855_CLOCK_CONTROL_MASK			(3 << 0)
+#define I855_CLOCK_133_200			(0 << 0)
+#define I855_CLOCK_100_200			(1 << 0)
+#define I855_CLOCK_100_133			(2 << 0)
+#define I855_CLOCK_166_250			(3 << 0)
+
 /* BLT commands */
 #define COLOR_BLT_CMD		((2<<29)|(0x40<<22)|(0x3))
 #define COLOR_BLT_WRITE_ALPHA	(1<<21)
diff --git a/src/i830_display.c b/src/i830_display.c
index 345eea9..f44a8bf 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -591,6 +591,59 @@ i830_crtc_mode_fixup(xf86CrtcPtr crtc, D
     return TRUE;
 }
 
+/** Returns the core display clock speed for i830 - i945 */
+static int
+i830_get_core_clock_speed(ScrnInfoPtr pScrn)
+{
+    I830Ptr pI830 = I830PTR(pScrn);
+
+    /* Core clock values taken from the published datasheets.
+     * The 830 may go up to 166 Mhz, which we should check.
+     */
+    if (IS_I945G(pI830))
+	return 400000;
+    else if (IS_I915G(pI830))
+	return 333000;
+    else if (IS_I945GM(pI830) || IS_845G(pI830))
+	return 200000;
+    else if (IS_I915GM(pI830)) {
+	CARD16 gcfgc = pciReadWord(pI830->PciTag, I915_GCFGC);
+
+	if (gcfgc & I915_LOW_FREQUENCY_ENABLE)
+	    return 133000;
+	else {
+	    switch (gcfgc & I915_DISPLAY_CLOCK_MASK) {
+	    case I915_DISPLAY_CLOCK_333_MHZ:
+		return 333000;
+	    default:
+	    case I915_DISPLAY_CLOCK_190_200_MHZ:
+		return 190000;
+	    }
+	}
+    } else if (IS_I865G(pI830))
+	return 266000;
+    else if (IS_I855(pI830)) {
+	PCITAG bridge = pciTag(0, 0, 0); /* This is always the host bridge */
+	CARD16 hpllcc = pciReadWord(bridge, I855_HPLLCC);
+
+	/* Assume that the hardware is in the high speed state.  This
+	 * should be the default.
+	 */
+	switch (hpllcc & I855_CLOCK_CONTROL_MASK) {
+	case I855_CLOCK_133_200:
+	case I855_CLOCK_100_200:
+	    return 200000;
+	case I855_CLOCK_166_250:
+	    return 250000;
+	case I855_CLOCK_100_133:
+	    return 133000;
+	}
+    } else /* 852, 830 */
+	return 133000;
+
+    return 0; /* Silence gcc warning */
+}
+
 /**
  * Sets up registers for the given mode/adjusted_mode pair.
  *
@@ -749,23 +802,15 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
 	dspcntr |= DISPPLANE_SEL_PIPE_B;
 
     pipeconf = INREG(pipeconf_reg);
-    if (pipe == 0) 
+    if (pipe == 0 && !IS_I965G(pI830))
     {
-	/*
-	 * The docs say this is needed when the dot clock is > 90% of the
-	 * core speed. Core speeds are indicated by bits in the PCI
-	 * config space, but that's a pain to go read, so we just guess
-	 * based on the hardware age. AGP hardware is assumed to run
-	 * at 133MHz while PCI-E hardware is assumed to run at 200MHz
+	/* Enable pixel doubling when the dot clock is > 90% of the (display)
+	 * core speed.
+	 *
+	 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
+	 * pipe == 0 check?
 	 */
-	int core_clock;
-	
-	if (IS_I9XX(pI830))
-	    core_clock = 200000;
-	else
-	    core_clock = 133000;
-	
-	if (mode->Clock > core_clock * 9 / 10)
+	if (mode->Clock > i830_get_core_clock_speed(pScrn) * 9 / 10)
 	    pipeconf |= PIPEACONF_DOUBLE_WIDE;
 	else
 	    pipeconf &= ~PIPEACONF_DOUBLE_WIDE;