xf86-video-ati: Branch 'master' - 150 commits
Dave Airlie
airlied at kemper.freedesktop.org
Thu Dec 20 15:36:35 PST 2007
configure.ac | 53
src/AtomBios/CD_Operations.c | 954 +++++++
src/AtomBios/Decoder.c | 235 +
src/AtomBios/hwserv_drv.c | 348 ++
src/AtomBios/includes/CD_Common_Types.h | 154 +
src/AtomBios/includes/CD_Definitions.h | 49
src/AtomBios/includes/CD_Opcodes.h | 181 +
src/AtomBios/includes/CD_Structs.h | 464 +++
src/AtomBios/includes/CD_binding.h | 46
src/AtomBios/includes/CD_hw_services.h | 318 ++
src/AtomBios/includes/Decoder.h | 86
src/AtomBios/includes/ObjectID.h | 448 +++
src/AtomBios/includes/atombios.h | 4306 ++++++++++++++++++++++++++++++++
src/AtomBios/includes/regsdef.h | 25
src/Makefile.am | 48
src/ati_pciids_gen.h | 132
src/atipciids.h | 7
src/atombios_crtc.c | 381 ++
src/atombios_output.c | 613 ++++
src/pcidb/ati_pciids.csv | 132
src/radeon.h | 214 -
src/radeon_accel.c | 9
src/radeon_accelfuncs.c | 2
src/radeon_atombios.c | 2625 +++++++++++++++++++
src/radeon_atombios.h | 235 +
src/radeon_atomwrapper.c | 101
src/radeon_atomwrapper.h | 31
src/radeon_bios.c | 313 +-
src/radeon_chipinfo_gen.h | 132
src/radeon_chipset_gen.h | 132
src/radeon_crtc.c | 254 +
src/radeon_cursor.c | 144 -
src/radeon_display.c | 15
src/radeon_dri.c | 4
src/radeon_driver.c | 1341 +++++++--
src/radeon_exa_funcs.c | 8
src/radeon_macros.h | 53
src/radeon_modes.c | 16
src/radeon_output.c | 962 ++++---
src/radeon_pci_chipset_gen.h | 132
src/radeon_probe.c | 2
src/radeon_probe.h | 361 ++
src/radeon_reg.h | 461 +++
src/radeon_render.c | 4
src/radeon_tv.c | 4
src/radeon_tv.h | 5
src/radeon_video.c | 18
47 files changed, 15403 insertions(+), 1155 deletions(-)
New commits:
commit 3c31b96afa20913ad947e68fe0c3a662e5eafbdd
Merge: eb99c3c... f5e8c18...
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Dec 21 09:36:22 2007 +1000
Merge remote branch 'origin/atombios-support'
Conflicts:
src/radeon_display.c
src/radeon_driver.c
diff --cc src/radeon_display.c
index ea31a82,1cd8b05..2043f24
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@@ -742,8 -742,8 +742,8 @@@ void RADEONInitDispBandwidth2(ScrnInfoP
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg.grph_buffer_cntl,
+ (unsigned int)info->SavedReg->grph_buffer_cntl,
- INREG(RADEON_GRPH_BUFFER_CNTL));
+ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
if (mode2) {
stop_req = mode2->HDisplay * pixel_bytes2 / 16;
@@@ -792,8 -792,8 +792,8 @@@
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH2_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg.grph2_buffer_cntl,
+ (unsigned int)info->SavedReg->grph2_buffer_cntl,
- INREG(RADEON_GRPH2_BUFFER_CNTL));
+ (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL));
}
}
diff --cc src/radeon_output.c
index 64c0438,519626f..30a73ab
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@@ -789,22 -851,8 +854,21 @@@ static in
radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+
+ /*
+ * RN50 has effective maximum mode bandwidth of about 300MiB/s.
+ * XXX should really do this for all chips by properly computing
+ * memory bandwidth and an overhead factor.
+ */
+ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
+ if (xf86ModeBandwidth(pMode, pScrn->bitsPerPixel) > 300)
+ return MODE_BANDWIDTH;
+ }
- if (radeon_output->type == OUTPUT_STV ||
- radeon_output->type == OUTPUT_CTV) {
+ if (OUTPUT_IS_TV) {
/* FIXME: Update when more modes are added */
if (pMode->HDisplay == 800 && pMode->VDisplay == 600)
return MODE_OK;
commit f5e8c185001e62e744310667c2d1bd3fe6542a62
Author: Dave Airlie <airlied at clockmaker.usersys.redhat.com>
Date: Wed Dec 19 10:38:58 2007 +1000
more endian related fixage
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 2b7f0e8..278d5a7 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -251,7 +251,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h,
#endif
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg.surface_cntl &
+ unsigned int swapper = info->ModeReg->surface_cntl &
~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
#endif
@@ -311,7 +311,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h,
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
return TRUE;
@@ -354,7 +354,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
RINFO_FROM_SCREEN(pSrc->drawable.pScreen);
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg.surface_cntl &
+ unsigned int swapper = info->ModeReg->surface_cntl &
~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
#endif
@@ -492,7 +492,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
return TRUE;
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 99b74eb..a84662e 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -2156,7 +2156,7 @@ RADEONCopyData(
{
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg.surface_cntl &
+ unsigned int swapper = info->ModeReg->surface_cntl &
~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
@@ -2182,7 +2182,7 @@ RADEONCopyData(
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
}
}
@@ -2238,7 +2238,7 @@ RADEONCopyRGB24Data(
{
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl
+ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl
| RADEON_NONSURF_AP0_SWP_32BPP)
& ~RADEON_NONSURF_AP0_SWP_16BPP);
#endif
@@ -2254,7 +2254,7 @@ RADEONCopyRGB24Data(
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
}
}
@@ -2333,7 +2333,7 @@ RADEONCopyMungedData(
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl
+ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl
| RADEON_NONSURF_AP0_SWP_32BPP)
& ~RADEON_NONSURF_AP0_SWP_16BPP);
#endif
@@ -2371,7 +2371,7 @@ RADEONCopyMungedData(
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
}
}
commit 98b247066d00db66abe91f518cd93b5c4da4cfb4
Author: Dave Airlie <airlied at clockmaker.usersys.redhat.com>
Date: Wed Dec 19 10:25:41 2007 +1000
fix big endian build since zaphod fixups
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 6133b2c..5b04848 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -74,12 +74,12 @@
#define CURSOR_SWAPPING_START() \
do { \
OUTREG(RADEON_SURFACE_CNTL, \
- (info->ModeReg.surface_cntl | \
+ (info->ModeReg->surface_cntl | \
RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \
~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \
} while (0)
#define CURSOR_SWAPPING_END() (OUTREG(RADEON_SURFACE_CNTL, \
- info->ModeReg.surface_cntl))
+ info->ModeReg->surface_cntl))
#else
diff --git a/src/radeon_render.c b/src/radeon_render.c
index 490dec1..a80d136 100644
--- a/src/radeon_render.c
+++ b/src/radeon_render.c
@@ -317,7 +317,7 @@ static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- CARD32 swapper = info->ModeReg.surface_cntl;
+ CARD32 swapper = info->ModeReg->surface_cntl;
swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP |
RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP);
@@ -345,7 +345,7 @@ static void RADEONRestoreByteswap(RADEONInfoPtr info)
{
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
}
#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */
commit bd7206fa120495037e3fea0c920d0031d7715bf6
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Dec 18 03:03:11 2007 -0500
RADEON: fix another merge error
this broken legacy radeons
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index eb892f2..2d4ac15 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -953,7 +953,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags);
+ RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
} else {
info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
@@ -967,7 +967,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags);
+ RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
}
break;
}
commit 65a3ac7530e11bb7d818a988fd0cf1dde7688fa4
Author: Alex Deucher <alex at samba.(none)>
Date: Tue Dec 18 00:15:38 2007 -0500
RADEON: more PLL tweaks
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index ea12556..eb892f2 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -620,7 +620,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
}
-static int RADEONDiv(int n, int d)
+static CARD32 RADEONDiv(CARD64 n, CARD32 d)
{
return (n + (d / 2)) / d;
}
@@ -645,7 +645,7 @@ RADEONComputePLL(RADEONPLLPtr pll,
CARD32 best_vco_diff = 1;
CARD32 post_div;
- freq = freq / 10;
+ freq = freq * 1000;
ErrorF("freq: %lu\n", freq);
@@ -654,7 +654,7 @@ RADEONComputePLL(RADEONPLLPtr pll,
for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
CARD32 ref_div;
- CARD32 vco = freq * post_div;
+ CARD32 vco = (freq / 10000) * post_div;
if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
continue;
@@ -679,21 +679,22 @@ RADEONComputePLL(RADEONPLLPtr pll,
if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
continue;
- feedback_div = RADEONDiv(freq * ref_div * post_div,
- pll->reference_freq);
+ feedback_div = RADEONDiv((CARD64)freq * ref_div * post_div,
+ pll->reference_freq * 10000);
if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div)
continue;
- current_freq = RADEONDiv(pll->reference_freq * feedback_div,
+ current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div,
ref_div * post_div);
error = abs(current_freq - freq);
vco_diff = abs(vco - best_vco);
if ((best_vco == 0 && error < best_error) ||
+ (ref_div == pll->reference_div) ||
(best_vco != 0 &&
- (error < best_error - 1000 ||
+ (error < best_error - 100 ||
(abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) {
best_post_div = post_div;
best_ref_div = ref_div;
@@ -710,7 +711,7 @@ RADEONComputePLL(RADEONPLLPtr pll,
ErrorF("best_ref_div: %u\n", best_ref_div);
ErrorF("best_post_div: %u\n", best_post_div);
- *chosen_dot_clock_freq = best_freq;
+ *chosen_dot_clock_freq = best_freq / 10000;
*chosen_feedback_div = best_feedback_div;
*chosen_reference_div = best_ref_div;
*chosen_post_div = best_post_div;
commit d93a0e10b8bc6e3797a3cf6c1e28ca413a7c38e4
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Dec 17 20:32:45 2007 -0500
RADEON: post div tweaks for legacy radeon
diff --git a/src/radeon.h b/src/radeon.h
index a5717a0..7d57ca5 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -203,6 +203,7 @@ typedef struct {
#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
#define RADEON_PLL_USE_REF_DIV (1 << 2)
+#define RADEON_PLL_LEGACY (1 << 3)
typedef struct {
CARD16 reference_freq;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 5e9db39..ea12556 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -659,6 +659,16 @@ RADEONComputePLL(RADEONPLLPtr pll,
if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
continue;
+ /* legacy radeons only have a few post_divs */
+ if (flags & RADEON_PLL_LEGACY) {
+ if ((post_div == 5) ||
+ (post_div == 7) ||
+ (post_div == 9) ||
+ (post_div == 10) ||
+ (post_div == 11))
+ continue;
+ }
+
if (vco < pll->pll_out_min || vco > pll->pll_out_max)
continue;
@@ -893,7 +903,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
Bool tilingOld = info->tilingEnabled;
int i = 0;
double dot_clock = 0;
- int pll_flags = 0;
+ int pll_flags = RADEON_PLL_LEGACY;
Bool update_tv_routing = FALSE;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 3eecedb..2002dd3 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1239,7 +1239,7 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
pll->min_post_div = 2;
pll->max_post_div = 0x7f;
} else {
- pll->min_post_div = 2;
+ pll->min_post_div = 1;
pll->max_post_div = 12; //16 on crtc0
}
pll->min_ref_div = 2;
commit 03b8b49f6f502c45552b018fd8c44d366b2d576f
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Dec 17 20:20:04 2007 -0500
RADEON: fix typo from merge
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index d2271b0..5e9db39 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -625,7 +625,7 @@ static int RADEONDiv(int n, int d)
return (n + (d / 2)) / d;
}
-static void
+void
RADEONComputePLL(RADEONPLLPtr pll,
unsigned long freq,
CARD32 *chosen_dot_clock_freq,
commit 19b9d3708852b7efe2b05249c8359dadb924dd94
Merge: cf685f3... 29706ca...
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Dec 17 20:07:32 2007 -0500
Merge branch 'atombios-support' of git+ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
commit cf685f37ec874f0aacd09e7c4eb0402c6daec1b0
Merge: 2a134af... 44d07c4...
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Dec 17 20:07:07 2007 -0500
Merge branch 'master' of git+ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
merge master and fix conflicts
diff --cc src/atombios_crtc.c
index 6c7828b,0000000..e7ad4a9
mode 100644,000000..100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@@ -1,381 -1,0 +1,381 @@@
+ /*
+ * Copyright © 2007 Red Hat, Inc.
+ *
+ * PLL code is:
+ * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+ * Copyright 2007 Matthias Hopf <mhopf at novell.com>
+ * Copyright 2007 Egbert Eich <eich at novell.com>
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Dave Airlie <airlied at redhat.com>
+ *
+ */
+/*
+ * avivo crtc handling functions.
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+/* DPMS */
+#define DPMS_SERVER
+#include <X11/extensions/dpms.h>
+
+#include "radeon.h"
+#include "radeon_reg.h"
+#include "radeon_macros.h"
+#include "radeon_atombios.h"
+
+#ifdef XF86DRI
+#define _XF86DRI_SERVER_
+#include "radeon_dri.h"
+#include "radeon_sarea.h"
+#include "sarea.h"
+#endif
+
+AtomBiosResult
+atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
+{
+ ENABLE_CRTC_PS_ALLOCATION crtc_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucEnable = state;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Enable":"Disable", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Enable CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+AtomBiosResult
+atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
+{
+ BLANK_CRTC_PS_ALLOCATION crtc_data;
+ unsigned char *space;
+ AtomBiosArgRec data;
+
+ memset(&crtc_data, 0, sizeof(crtc_data));
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucBlanking = state;
+
+ data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Blank":"Unblank", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Blank CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+static void
+atombios_crtc_enable(xf86CrtcPtr crtc, int enable)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable);
+
+ //TODOavivo_wait_idle(avivo);
+}
+
+void
+atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ switch (mode) {
+ case DPMSModeOn:
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ case DPMSModeOff:
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ }
+}
+
+static AtomBiosResult
+atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
+{
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = crtc_param;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC Timing success\n");
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Set CRTC Timing failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+void
+atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ CARD32 sclock = mode->Clock;
+ CARD32 ref_div = 0, fb_div = 0, post_div = 0;
+ int major, minor;
+ SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
+ void *ptr;
+ AtomBiosArgRec data;
+ unsigned char *space;
+ RADEONSavePtr save = info->ModeReg;
+
+ if (IS_AVIVO_VARIANT) {
+ CARD32 temp;
- RADEONComputePLL(&info->pll, mode->Clock * 1000, &temp, &fb_div, &ref_div, &post_div);
- sclock = temp / 10000;
++ RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, 0);
++ sclock = temp;
+
+ /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
+ if (radeon_crtc->crtc_id == 0) {
+ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ } else {
+ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ }
+ } else {
+ sclock = save->dot_clock_freq;
+ fb_div = save->feedback_div;
+ post_div = save->post_div;
+ ref_div = save->ppll_ref_div;
+ }
+
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) Clock: mode %d, PLL %u\n",
+ radeon_crtc->crtc_id, mode->Clock, sclock * 10);
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n",
+ radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ ErrorF("table is %d %d\n", major, minor);
+ switch(major) {
+ case 1:
+ switch(minor) {
+ case 1:
+ case 2: {
+ spc_param.sPCLKInput.usPixelClock = sclock;
+ spc_param.sPCLKInput.usRefDiv = ref_div;
+ spc_param.sPCLKInput.usFbDiv = fb_div;
+ spc_param.sPCLKInput.ucPostDiv = post_div;
+ spc_param.sPCLKInput.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+ spc_param.sPCLKInput.ucCRTC = radeon_crtc->crtc_id;
+ spc_param.sPCLKInput.ucRefDivSrc = 1;
+
+ ptr = &spc_param;
+ break;
+ }
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = ptr;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC PLL success\n");
+ return;
+ }
+
+ ErrorF("Set CRTC PLL failed\n");
+ return;
+}
+
+void
+atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode,
+ int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
+ Bool tilingOld = info->tilingEnabled;
+
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
+
+ memset(&crtc_timing, 0, sizeof(crtc_timing));
+
+ if (info->allowColorTiling) {
+ info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
+#ifdef XF86DRI
+ if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
+ RADEONSAREAPrivPtr pSAREAPriv;
+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "[drm] failed changing tiling status\n");
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
+ info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
+ }
+#endif
+ }
+
+ crtc_timing.ucCRTC = radeon_crtc->crtc_id;
+ crtc_timing.usH_Total = adjusted_mode->CrtcHTotal;
+ crtc_timing.usH_Disp = adjusted_mode->CrtcHDisplay;
+ crtc_timing.usH_SyncStart = adjusted_mode->CrtcHSyncStart;
+ crtc_timing.usH_SyncWidth = adjusted_mode->CrtcHSyncEnd - adjusted_mode->CrtcHSyncStart;
+
+ crtc_timing.usV_Total = adjusted_mode->CrtcVTotal;
+ crtc_timing.usV_Disp = adjusted_mode->CrtcVDisplay;
+ crtc_timing.usV_SyncStart = adjusted_mode->CrtcVSyncStart;
+ crtc_timing.usV_SyncWidth = adjusted_mode->CrtcVSyncEnd - adjusted_mode->CrtcVSyncStart;
+
+ if (adjusted_mode->Flags & V_NVSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
+
+ if (adjusted_mode->Flags & V_NHSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
+
+ ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
+ adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
+
+ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+
+ if (IS_AVIVO_VARIANT) {
+ radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_height = pScrn->virtualY;
+ radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4;
+ switch (crtc->scrn->bitsPerPixel) {
+ case 15:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
+ break;
+ case 16:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
+ break;
+ case 24:
+ case 32:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
+ break;
+ default:
+ FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
+ }
+
+ if (info->tilingEnabled && (crtc->rotatedData == NULL)) {
+ radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
+ }
+
+ if (radeon_crtc->crtc_id == 0)
+ OUTREG(AVIVO_D1VGA_CONTROL, 0);
+ else
+ OUTREG(AVIVO_D2VGA_CONTROL, 0);
+
+ /* setup fb format and location
+ */
+ if (crtc->rotatedData != NULL) {
+ /* x/y offset is already included */
+ x = 0;
+ y = 0;
+ fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB;
+ }
+
+ /* lock the grph regs */
+ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK);
+
+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset,
+ radeon_crtc->fb_format);
+
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualX);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualY);
+ OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
+ crtc->scrn->displayWidth);
+ OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+
+ /* unlock the grph regs */
+ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0);
+
+ /* lock the mode regs */
+ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK);
+
+ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualY);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
+ (mode->HDisplay << 16) | mode->VDisplay);
+ /* unlock the mode regs */
+ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0);
+
+ }
+
+ atombios_crtc_set_pll(crtc, adjusted_mode);
+
+ atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
+
+ if (info->tilingEnabled != tilingOld) {
+ /* need to redraw front buffer, I guess this can be considered a hack ? */
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE);
+ RADEONChangeSurfaces(pScrn);
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE);
+ /* xf86SetRootClip would do, but can't access that here */
+ }
+
+}
+
diff --cc src/radeon.h
index 6cc2b6f,03db360..a5717a0
--- a/src/radeon.h
+++ b/src/radeon.h
@@@ -200,6 -200,176 +200,10 @@@ typedef struct
CARD16 rr4_offset;
} RADEONBIOSInitTable;
-typedef struct {
- /* Common registers */
- CARD32 ovr_clr;
- CARD32 ovr_wid_left_right;
- CARD32 ovr_wid_top_bottom;
- CARD32 ov0_scale_cntl;
- CARD32 mpp_tb_config;
- CARD32 mpp_gp_config;
- CARD32 subpic_cntl;
- CARD32 viph_control;
- CARD32 i2c_cntl_1;
- CARD32 gen_int_cntl;
- CARD32 cap0_trig_cntl;
- CARD32 cap1_trig_cntl;
- CARD32 bus_cntl;
- CARD32 bios_4_scratch;
- CARD32 bios_5_scratch;
- CARD32 bios_6_scratch;
- CARD32 surface_cntl;
- CARD32 surfaces[8][3];
- CARD32 mc_agp_location;
- CARD32 mc_fb_location;
- CARD32 display_base_addr;
- CARD32 display2_base_addr;
- CARD32 ov0_base_addr;
-
- /* Other registers to save for VT switches */
- CARD32 dp_datatype;
- CARD32 rbbm_soft_reset;
- CARD32 clock_cntl_index;
- CARD32 amcgpio_en_reg;
- CARD32 amcgpio_mask;
-
- /* CRTC registers */
- CARD32 crtc_gen_cntl;
- CARD32 crtc_ext_cntl;
- CARD32 dac_cntl;
- CARD32 crtc_h_total_disp;
- CARD32 crtc_h_sync_strt_wid;
- CARD32 crtc_v_total_disp;
- CARD32 crtc_v_sync_strt_wid;
- CARD32 crtc_offset;
- CARD32 crtc_offset_cntl;
- CARD32 crtc_pitch;
- CARD32 disp_merge_cntl;
- CARD32 grph_buffer_cntl;
- CARD32 crtc_more_cntl;
- CARD32 crtc_tile_x0_y0;
-
- /* CRTC2 registers */
- CARD32 crtc2_gen_cntl;
- CARD32 dac_macro_cntl;
- CARD32 dac2_cntl;
- CARD32 disp_output_cntl;
- CARD32 disp_tv_out_cntl;
- CARD32 disp_hw_debug;
- CARD32 disp2_merge_cntl;
- CARD32 grph2_buffer_cntl;
- CARD32 crtc2_h_total_disp;
- CARD32 crtc2_h_sync_strt_wid;
- CARD32 crtc2_v_total_disp;
- CARD32 crtc2_v_sync_strt_wid;
- CARD32 crtc2_offset;
- CARD32 crtc2_offset_cntl;
- CARD32 crtc2_pitch;
- CARD32 crtc2_tile_x0_y0;
-
- /* Flat panel registers */
- CARD32 fp_crtc_h_total_disp;
- CARD32 fp_crtc_v_total_disp;
- CARD32 fp_gen_cntl;
- CARD32 fp2_gen_cntl;
- CARD32 fp_h_sync_strt_wid;
- CARD32 fp_h2_sync_strt_wid;
- CARD32 fp_horz_stretch;
- CARD32 fp_panel_cntl;
- CARD32 fp_v_sync_strt_wid;
- CARD32 fp_v2_sync_strt_wid;
- CARD32 fp_vert_stretch;
- CARD32 lvds_gen_cntl;
- CARD32 lvds_pll_cntl;
- CARD32 tmds_pll_cntl;
- CARD32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- CARD32 dot_clock_freq;
- CARD32 pll_output_freq;
- int feedback_div;
- int reference_div;
- int post_div;
-
- /* PLL registers */
- unsigned ppll_ref_div;
- unsigned ppll_div_3;
- CARD32 htotal_cntl;
- CARD32 vclk_ecp_cntl;
-
- /* Computed values for PLL2 */
- CARD32 dot_clock_freq_2;
- CARD32 pll_output_freq_2;
- int feedback_div_2;
- int reference_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- CARD32 p2pll_ref_div;
- CARD32 p2pll_div_0;
- CARD32 htotal_cntl2;
- CARD32 pixclks_cntl;
-
- /* Pallet */
- Bool palette_valid;
- CARD32 palette[256];
- CARD32 palette2[256];
-
- CARD32 rs480_unk_e30;
- CARD32 rs480_unk_e34;
- CARD32 rs480_unk_e38;
- CARD32 rs480_unk_e3c;
-
- /* TV out registers */
- CARD32 tv_master_cntl;
- CARD32 tv_htotal;
- CARD32 tv_hsize;
- CARD32 tv_hdisp;
- CARD32 tv_hstart;
- CARD32 tv_vtotal;
- CARD32 tv_vdisp;
- CARD32 tv_timing_cntl;
- CARD32 tv_vscaler_cntl1;
- CARD32 tv_vscaler_cntl2;
- CARD32 tv_sync_size;
- CARD32 tv_vrestart;
- CARD32 tv_hrestart;
- CARD32 tv_frestart;
- CARD32 tv_ftotal;
- CARD32 tv_clock_sel_cntl;
- CARD32 tv_clkout_cntl;
- CARD32 tv_data_delay_a;
- CARD32 tv_data_delay_b;
- CARD32 tv_dac_cntl;
- CARD32 tv_pll_cntl;
- CARD32 tv_pll_cntl1;
- CARD32 tv_pll_fine_cntl;
- CARD32 tv_modulator_cntl1;
- CARD32 tv_modulator_cntl2;
- CARD32 tv_frame_lock_cntl;
- CARD32 tv_pre_dac_mux_cntl;
- CARD32 tv_rgb_cntl;
- CARD32 tv_y_saw_tooth_cntl;
- CARD32 tv_y_rise_cntl;
- CARD32 tv_y_fall_cntl;
- CARD32 tv_uv_adr;
- CARD32 tv_upsamp_and_gain_cntl;
- CARD32 tv_gain_limit_settings;
- CARD32 tv_linear_gain_settings;
- CARD32 tv_crc_cntl;
- CARD32 tv_sync_cntl;
- CARD32 gpiopad_a;
- CARD32 pll_test_cntl;
-
- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
-
-} RADEONSaveRec, *RADEONSavePtr;
-
+ #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
+ #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
+ #define RADEON_PLL_USE_REF_DIV (1 << 2)
+
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
@@@ -699,10 -850,14 +703,18 @@@ typedef struct
#endif
RADEONExtTMDSChip ext_tmds_chip;
+ atomBiosHandlePtr atomBIOS;
+ unsigned long FbFreeStart, FbFreeSize;
+ unsigned char* BIOSCopy;
+
+ /* output enable masks for outputs shared across connectors */
+ int output_crt1;
+ int output_crt2;
+ int output_dfp1;
+ int output_dfp2;
+ int output_lcd1;
+ int output_tv1;
+
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
diff --cc src/radeon_bios.c
index 9730119,d150c4b..46a58ca
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@@ -633,13 -473,8 +633,13 @@@ Bool RADEONGetClockInfoFromBIOS (ScrnIn
pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e);
pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10);
- pll->min_pll_freq = RADEON_BIOS32 (pll_info_block + 0x12);
- pll->max_pll_freq = RADEON_BIOS32 (pll_info_block + 0x16);
+ pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12);
+ pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16);
+
+ /* not available in the bios */
+ pll->pll_in_min = 40;
- pll->pll_in_max = 100;
++ pll->pll_in_max = 500;
+
pll->xclk = RADEON_BIOS16 (pll_info_block + 0x08);
info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0;
diff --cc src/radeon_crtc.c
index 611c9ab,41375da..d2271b0
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@@ -637,8 -617,15 +631,11 @@@ RADEONComputePLL(RADEONPLLPtr pll
CARD32 *chosen_dot_clock_freq,
CARD32 *chosen_feedback_div,
CARD32 *chosen_reference_div,
- CARD32 *chosen_post_div)
+ CARD32 *chosen_post_div,
+ int flags)
{
- int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0};
-
- int i;
-
+ CARD32 min_ref_div = pll->min_ref_div;
+ CARD32 max_ref_div = pll->max_ref_div;
CARD32 best_vco = pll->best_vco;
CARD32 best_post_div = 1;
CARD32 best_ref_div = 1;
@@@ -646,18 -633,26 +643,26 @@@
CARD32 best_freq = 1;
CARD32 best_error = 0xffffffff;
CARD32 best_vco_diff = 1;
+ CARD32 post_div;
+ freq = freq / 10;
+
ErrorF("freq: %lu\n", freq);
+ if (flags & RADEON_PLL_USE_REF_DIV)
+ min_ref_div = max_ref_div = pll->reference_div;
+
- for (i = 0; post_divs[i]; i++) {
- int post_div = post_divs[i];
+ for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
CARD32 ref_div;
- CARD32 vco = (freq / 10000) * post_div;
+ CARD32 vco = freq * post_div;
+
+ if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
+ continue;
- if (vco < pll->min_pll_freq || vco > pll->max_pll_freq)
+ if (vco < pll->pll_out_min || vco > pll->pll_out_max)
continue;
- for (ref_div = pll->min_ref_div; ref_div <= pll->max_ref_div; ++ref_div) {
+ for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
CARD32 feedback_div, current_freq, error, vco_diff;
CARD32 pll_in = pll->reference_freq / ref_div;
@@@ -670,8 -665,8 +675,8 @@@
if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div)
continue;
- current_freq = RADEONDiv64((CARD64)pll->reference_freq * 10000 * feedback_div,
- ref_div * post_div);
- current_freq = RADEONDiv(pll->reference_freq * feedback_div,
++ current_freq = RADEONDiv(pll->reference_freq * feedback_div,
+ ref_div * post_div);
error = abs(current_freq - freq);
vco_diff = abs(vco - best_vco);
@@@ -927,11 -934,11 +942,11 @@@ legacy_crtc_mode_set(xf86CrtcPtr crtc,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode);
+ RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags);
} else {
- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
+ info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
+ info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
+ info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl;
}
break;
case 1:
diff --cc src/radeon_driver.c
index 62e7cd0,25b2119..a9756fa
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@@ -1196,15 -1029,11 +1196,15 @@@ static void RADEONGetClockInfo(ScrnInfo
/* Default min/max PLL values */
if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) {
- pll->min_pll_freq = 20000;
- pll->max_pll_freq = 50000;
+ pll->pll_in_min = 100;
+ pll->pll_in_max = 1350;
+ pll->pll_out_min = 20000;
+ pll->pll_out_max = 50000;
} else {
- pll->min_pll_freq = 12500;
- pll->max_pll_freq = 35000;
+ pll->pll_in_min = 40;
- pll->pll_in_max = 100;
++ pll->pll_in_max = 500;
+ pll->pll_out_min = 12500;
+ pll->pll_out_max = 35000;
}
if (RADEONProbePLLParameters(pScrn))
diff --cc src/radeon_output.c
index 02c96ae,c60ece8..519626f
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@@ -1045,9 -985,12 +1049,12 @@@ static void RADEONInitLVDSRegisters(xf8
save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
- save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl;
+ save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl;
save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON |
+ RADEON_LVDS_BLON |
+ RADEON_LVDS_EN |
+ RADEON_LVDS_RST_FM);
if (IS_R300_VARIANT)
save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
commit 29706ca585ebd9b7b3521521a17016322e9ecccb
Author: Dave Airlie <airlied at linux.ie>
Date: Tue Dec 18 10:55:38 2007 +1000
fixup shadow setup on !r600
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 62e7cd0..3d2c802 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -3939,8 +3939,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONInitVideo(pScreen);
}
- if (!shadowSetup(pScreen)) {
- return FALSE;
+ if (info->r600_shadow_fb == TRUE) {
+ if (!shadowSetup(pScreen)) {
+ return FALSE;
+ }
}
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
commit 2a134af01bc85de758ad83a85b23d1bba4a1a0f5
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Dec 17 15:00:36 2007 +1000
r600: add shadow support to r600 driver to at least make 2d useable
diff --git a/src/radeon.h b/src/radeon.h
index 6c38826..6cc2b6f 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -710,6 +710,9 @@ typedef struct {
Bool IsSecondary;
Bool IsPrimary;
+
+ Bool r600_shadow_fb;
+ void *fb_shadow;
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index ac307ab..62e7cd0 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -97,6 +97,7 @@
#include "xf86cmap.h"
#include "vbe.h"
+#include "shadow.h"
/* vgaHW definitions */
#ifdef WITH_VGAHW
#include "vgaHW.h"
@@ -347,6 +348,15 @@ static const char *i2cSymbols[] = {
NULL
};
+static const char *shadowSymbols[] = {
+ "shadowAdd",
+ "shadowInit",
+ "shadowSetup",
+ "shadowUpdatePacked",
+ "shadowUpdatePackedWeak",
+ NULL
+};
+
void RADEONLoaderRefSymLists(void)
{
/*
@@ -405,23 +415,41 @@ struct RADEONInt10Save {
static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);
static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn);
-#if 0
+static void *
+radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
+ CARD32 *size, void *closure)
+{
+ ScrnInfoPtr pScrn = xf86Screens[screen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ int stride;
+
+ stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
+ *size = stride;
+
+ return ((CARD8 *)info->FB + pScrn->fbOffset +
+ row * stride + offset);
+}
static Bool
RADEONCreateScreenResources (ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
+ PixmapPtr pixmap;
pScreen->CreateScreenResources = info->CreateScreenResources;
if (!(*pScreen->CreateScreenResources)(pScreen))
return FALSE;
+ pScreen->CreateScreenResources = RADEONCreateScreenResources;
- if (!xf86RandR12CreateScreenResources(pScreen))
- return FALSE;
+ if (info->r600_shadow_fb) {
+ pixmap = pScreen->GetScreenPixmap(pScreen);
- return TRUE;
+ if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(),
+ radeonShadowWindow, 0, NULL))
+ return FALSE;
+ }
+ return TRUE;
}
-#endif
RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn)
{
@@ -1930,6 +1958,14 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->Chipset != PCI_CHIP_RN50_5969);
#endif
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ info->r600_shadow_fb = TRUE;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "using shadow framebuffer\n");
+ if (!xf86LoadSubModule(pScrn, "shadow"))
+ return FALSE;
+ xf86LoaderReqSymLists(shadowSymbols, NULL);
+ }
return TRUE;
}
@@ -3697,13 +3733,32 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Initializing fb layer\n");
+
+ if (info->r600_shadow_fb) {
+ info->fb_shadow = xcalloc(1,
+ pScrn->displayWidth * pScrn->virtualY *
+ ((pScrn->bitsPerPixel + 7) >> 3));
+ if (info->fb_shadow == NULL) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Failed to allocate shadow framebuffer\n");
+ info->r600_shadow_fb = FALSE;
+ } else {
+ if (!fbScreenInit(pScreen, info->fb_shadow,
+ pScrn->virtualX, pScrn->virtualY,
+ pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
+ pScrn->bitsPerPixel))
+ return FALSE;
+ }
+ }
- /* Init fb layer */
- if (!fbScreenInit(pScreen, info->FB,
- pScrn->virtualX, pScrn->virtualY,
- pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
- pScrn->bitsPerPixel))
- return FALSE;
+ if (info->r600_shadow_fb == FALSE) {
+ /* Init fb layer */
+ if (!fbScreenInit(pScreen, info->FB,
+ pScrn->virtualX, pScrn->virtualY,
+ pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
+ pScrn->bitsPerPixel))
+ return FALSE;
+ }
xf86SetBlackWhitePixels(pScreen);
@@ -3815,6 +3870,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONChangeSurfaces(pScrn);
+
/* Enable aceleration */
if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
@@ -3883,6 +3939,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONInitVideo(pScreen);
}
+ if (!shadowSetup(pScreen)) {
+ return FALSE;
+ }
+
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
/* Wrap CloseScreen */
info->CloseScreen = pScreen->CloseScreen;
@@ -3890,6 +3950,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
pScreen->SaveScreen = RADEONSaveScreen;
info->BlockHandler = pScreen->BlockHandler;
pScreen->BlockHandler = RADEONBlockHandler;
+ info->CreateScreenResources = pScreen->CreateScreenResources;
+ pScreen->CreateScreenResources = RADEONCreateScreenResources;
if (!xf86CrtcScreenInit (pScreen))
return FALSE;
commit 614414611a9f246cbc74f579a79987fff97cf571
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Dec 17 11:10:14 2007 +1000
radeon: cleanup pitch calculation and make r600 work again
diff --git a/src/radeon_modes.c b/src/radeon_modes.c
index 21fb659..c9e99b8 100644
--- a/src/radeon_modes.c
+++ b/src/radeon_modes.c
@@ -59,20 +59,22 @@ void RADEONSetPitch (ScrnInfoPtr pScrn)
{
int dummy = pScrn->virtualX;
RADEONInfoPtr info = RADEONPTR(pScrn);
+ int pitch_mask = 0;
+ int align_large;
+
+ align_large = info->allowColorTiling || IS_AVIVO_VARIANT;
/* FIXME: May need to validate line pitch here */
switch (pScrn->depth / 8) {
- case 1: if (info->allowColorTiling) dummy = (pScrn->virtualX + 255) & ~255;
- else dummy = (pScrn->virtualX + 127) & ~127;
+ case 1: pitch_mask = align_large ? 255 : 127;
break;
- case 2: if (info->allowColorTiling) dummy = (pScrn->virtualX + 127) & ~127;
- else dummy = (pScrn->virtualX + 31) & ~31;
+ case 2: pitch_mask = align_large ? 127 : 31;
break;
case 3:
- case 4: if (info->allowColorTiling) dummy = (pScrn->virtualX + 63) & ~63;
- else dummy = (pScrn->virtualX + 15) & ~15;
+ case 4: pitch_mask = align_large ? 63 : 15;
break;
}
+ dummy = (pScrn->virtualX + pitch_mask) & ~pitch_mask;
pScrn->displayWidth = dummy;
info->CurrentLayout.displayWidth = pScrn->displayWidth;
commit 79a375dbc7f323e2f551490a35f44ec36bed877c
Author: George Wu <geo at flood.OCF.Berkeley.EDU>
Date: Mon Dec 17 10:55:36 2007 +1000
r600: might as well fix VT for R600
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 16d758b..ac307ab 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -5647,11 +5647,18 @@ void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->tmds2.source_select = INREG(AVIVO_LVTMA_SOURCE_SELECT);
state->tmds2.bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
state->tmds2.data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION);
- state->tmds2.transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE);
- state->tmds2.transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL);
- state->lvtma_pwrseq_cntl = INREG(AVIVO_LVTMA_PWRSEQ_CNTL);
- state->lvtma_pwrseq_state = INREG(AVIVO_LVTMA_PWRSEQ_STATE);
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ state->tmds2.transmitter_enable = INREG(R600_LVTMA_TRANSMITTER_ENABLE);
+ state->tmds2.transmitter_cntl = INREG(R600_LVTMA_TRANSMITTER_CONTROL);
+ state->lvtma_pwrseq_cntl = INREG(R600_LVTMA_PWRSEQ_CNTL);
+ state->lvtma_pwrseq_state = INREG(R600_LVTMA_PWRSEQ_STATE);
+ } else {
+ state->tmds2.transmitter_enable = INREG(R500_LVTMA_TRANSMITTER_ENABLE);
+ state->tmds2.transmitter_cntl = INREG(R500_LVTMA_TRANSMITTER_CONTROL);
+ state->lvtma_pwrseq_cntl = INREG(R500_LVTMA_PWRSEQ_CNTL);
+ state->lvtma_pwrseq_state = INREG(R500_LVTMA_PWRSEQ_STATE);
+ }
if (state->crtc1.control & AVIVO_CRTC_EN)
info->crtc_on = TRUE;
@@ -5792,12 +5799,19 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_LVTMA_CNTL, state->tmds2.cntl);
OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2.bit_depth_cntl);
OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2.data_sync);
- OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
- OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
OUTREG(AVIVO_LVTMA_SOURCE_SELECT, state->tmds2.source_select);
-
- OUTREG(AVIVO_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
- OUTREG(AVIVO_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
+
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ OUTREG(R600_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
+ OUTREG(R600_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
+ OUTREG(R600_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
+ OUTREG(R600_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
+ } else {
+ OUTREG(R500_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
+ OUTREG(R500_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
+ OUTREG(R500_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
+ OUTREG(R500_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
+ }
OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index e7ef932..56eb7e9 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3606,9 +3606,11 @@
#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
-#define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00
+#define R500_LVTMA_CLOCK_ENABLE 0x7b00
+#define R600_LVTMA_CLOCK_ENABLE 0x7b04
-#define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04
+#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
+#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
@@ -3621,7 +3623,8 @@
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
-#define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10
+#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
+#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
@@ -3637,7 +3640,8 @@
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
-#define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0
+#define R500_LVTMA_PWRSEQ_CNTL 0x7af0
+#define R600_LVTMA_PWRSEQ_CNTL 0x7af4
# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
@@ -3652,7 +3656,8 @@
# define AVIVO_LVTMA_BLON_OVRD (1 << 25)
# define AVIVO_LVTMA_BLON_POL (1 << 26)
-#define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4
+#define R500_LVTMA_PWRSEQ_STATE 0x7af4
+#define R600_LVTMA_PWRSEQ_STATE 0x7af8
# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
commit bc213ee723a45f2c396b4ed211a50f7642349973
Author: Alex Deucher <alex at samba.(none)>
Date: Sun Dec 16 14:54:00 2007 -0500
RADEON: fix sclock printout
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 9798247..6c7828b 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -186,7 +186,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
"crtc(%d) Clock: mode %d, PLL %u\n",
- radeon_crtc->crtc_id, mode->Clock, sclock);
+ radeon_crtc->crtc_id, mode->Clock, sclock * 10);
xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
"crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n",
radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
commit a9817b2cf436a536dbc43ad77abc3bdcc53d346d
Author: Alex Deucher <alex at samba.(none)>
Date: Sat Dec 15 20:51:53 2007 -0500
RADEON: clean up units in PLL calculation
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 2297316..9798247 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -156,8 +156,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
unsigned char *RADEONMMIO = info->MMIO;
int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
CARD32 sclock = mode->Clock;
- uint16_t ref_div = 0, fb_div = 0;
- uint8_t post_div = 0;
+ CARD32 ref_div = 0, fb_div = 0, post_div = 0;
int major, minor;
SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
void *ptr;
@@ -167,29 +166,29 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
if (IS_AVIVO_VARIANT) {
CARD32 temp;
- RADEONComputePLL(&info->pll, mode->Clock * 1000, &sclock, &fb_div, &ref_div, &post_div);
- sclock /= 1000;
+ RADEONComputePLL(&info->pll, mode->Clock * 1000, &temp, &fb_div, &ref_div, &post_div);
+ sclock = temp / 10000;
/* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
if (radeon_crtc->crtc_id == 0) {
- temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
- OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
- } else {
- temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
- OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
- }
+ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ } else {
+ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ }
} else {
- sclock = save->dot_clock_freq * 10;
+ sclock = save->dot_clock_freq;
fb_div = save->feedback_div;
post_div = save->post_div;
ref_div = save->ppll_ref_div;
}
xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
- "crtc(%d) Clock: mode %d, PLL %d\n",
+ "crtc(%d) Clock: mode %d, PLL %u\n",
radeon_crtc->crtc_id, mode->Clock, sclock);
xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
- "crtc(%d) PLL : refdiv %d, fbdiv 0x%X(%d), pdiv %d\n",
+ "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n",
radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
@@ -200,7 +199,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
switch(minor) {
case 1:
case 2: {
- spc_param.sPCLKInput.usPixelClock = sclock / 10;
+ spc_param.sPCLKInput.usPixelClock = sclock;
spc_param.sPCLKInput.usRefDiv = ref_div;
spc_param.sPCLKInput.usFbDiv = fb_div;
spc_param.sPCLKInput.ucPostDiv = post_div;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 45eb1ac..611c9ab 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -690,10 +690,10 @@ RADEONComputePLL(RADEONPLLPtr pll,
}
}
- ErrorF("best_freq: %d\n", best_freq);
- ErrorF("best_feedback_div: %d\n", best_feedback_div);
- ErrorF("best_ref_div: %d\n", best_ref_div);
- ErrorF("best_post_div: %d\n", best_post_div);
+ ErrorF("best_freq: %u\n", best_freq);
+ ErrorF("best_feedback_div: %u\n", best_feedback_div);
+ ErrorF("best_ref_div: %u\n", best_ref_div);
+ ErrorF("best_post_div: %u\n", best_post_div);
*chosen_dot_clock_freq = best_freq;
*chosen_feedback_div = best_feedback_div;
commit b3eed3d87f76779b5a62a3115f99a31484dc38e0
Author: Alex Deucher <alex at samba.(none)>
Date: Fri Dec 14 00:20:10 2007 -0500
RADEON: fix typo in previous cursor fix
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 842668b..6133b2c 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -326,7 +326,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
cursor_offset = RADEON_ALIGN((fbarea->box.x1 +
fbarea->box.y1 * width) *
info->CurrentLayout.pixel_bytes,
- 256);
+ align);
for (c = 0; c < xf86_config->num_crtc; c++) {
xf86CrtcPtr crtc = xf86_config->crtc[c];
commit 814c6c48aebba2e45ce257289b922cd7e92caf2a
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Dec 13 18:45:09 2007 -0500
RADEON: rework PLL calculation
- Take into account the limits from the bios tables
- Unify the PLL calculation between legacy and avivo chips
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 5b09107..2297316 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -148,82 +148,6 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_
return ATOM_NOT_IMPLEMENTED;
}
-/*
- * Calculate the PLL parameters for a given dotclock.
- */
-#define RADEON_PLL_DEFAULT_PLLOUT_MIN 64800 /* experimental. - taken from rhd divided by 10 */
-
-static Bool
-PLLCalculate(ScrnInfoPtr pScrn, CARD32 PixelClock,
- CARD16 *RefDivider, CARD16 *FBDivider, CARD8 *PostDivider)
-{
-/* limited by the number of bits available */
-#define FB_DIV_LIMIT 1024 /* rv6x0 doesn't like 2048 */
-#define REF_DIV_LIMIT 1024
-#define POST_DIV_LIMIT 128
- RADEONInfoPtr info = RADEONPTR (pScrn);
- RADEONPLLPtr pll = &info->pll;
- CARD32 FBDiv, RefDiv, PostDiv, BestDiff = 0xFFFFFFFF;
- float Ratio;
-
- Ratio = ((float) PixelClock) / ((float) pll->reference_freq * 10);
-
- if (pll->min_pll_freq == 0)
- pll->min_pll_freq = RADEON_PLL_DEFAULT_PLLOUT_MIN;
- for (PostDiv = 2; PostDiv < POST_DIV_LIMIT; PostDiv++) {
- CARD32 VCOOut = PixelClock * PostDiv;
-
- /* we are conservative and avoid the limits */
- if (VCOOut <= pll->min_pll_freq * 10)
- continue;
- if (VCOOut >= pll->max_pll_freq * 10)
- break;
-
- for (RefDiv = 1; RefDiv <= REF_DIV_LIMIT; RefDiv++)
- {
- CARD32 Diff;
-
- FBDiv = (CARD32) ((Ratio * PostDiv * RefDiv) + 0.5);
-
- if (FBDiv >= FB_DIV_LIMIT)
- break;
-
- if (FBDiv > (500 + (13 * RefDiv))) /* rv6x0 limit */
- break;
-
- Diff = abs( PixelClock - (FBDiv * pll->reference_freq * 10) / (PostDiv * RefDiv) );
-
- if (Diff < BestDiff) {
- *FBDivider = FBDiv;
- *RefDivider = RefDiv;
- *PostDivider = PostDiv;
- BestDiff = Diff;
- }
-
- if (BestDiff == 0)
- break;
- }
- if (BestDiff == 0)
- break;
- }
-
- if (BestDiff != 0xFFFFFFFF) {
- ErrorF("PLL Calculation: %dkHz = "
- "(((0x%X / 0x%X) * 0x%X) / 0x%X) (%dkHz off)\n",
- (int) PixelClock, (unsigned int) pll->reference_freq * 10, *RefDivider,
- *FBDivider, *PostDivider, (int) BestDiff);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PLL for %dkHz uses %dkHz internally.\n",
- (int) PixelClock,
- (int) (pll->reference_freq * 10 * *FBDivider) / *RefDivider);
- return TRUE;
- } else { /* Should never happen */
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "%s: Failed to get a valid PLL setting for %dkHz\n",
- __func__, (int) PixelClock);
- return FALSE;
- }
-}
-
void
atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
{
@@ -231,7 +155,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
unsigned char *RADEONMMIO = info->MMIO;
int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
- int sclock = mode->Clock;
+ CARD32 sclock = mode->Clock;
uint16_t ref_div = 0, fb_div = 0;
uint8_t post_div = 0;
int major, minor;
@@ -240,10 +164,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
AtomBiosArgRec data;
unsigned char *space;
RADEONSavePtr save = info->ModeReg;
-
+
if (IS_AVIVO_VARIANT) {
- CARD32 temp;
- PLLCalculate(crtc->scrn, sclock, &ref_div, &fb_div, &post_div);
+ CARD32 temp;
+ RADEONComputePLL(&info->pll, mode->Clock * 1000, &sclock, &fb_div, &ref_div, &post_div);
+ sclock /= 1000;
/* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
if (radeon_crtc->crtc_id == 0) {
@@ -268,7 +193,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
-
+
ErrorF("table is %d %d\n", major, minor);
switch(major) {
case 1:
@@ -304,7 +229,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
ErrorF("Set CRTC PLL success\n");
return;
}
-
+
ErrorF("Set CRTC PLL failed\n");
return;
}
diff --git a/src/radeon.h b/src/radeon.h
index 038fcc7..6c38826 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -203,16 +203,18 @@ typedef struct {
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
- CARD32 min_pll_freq;
- CARD32 max_pll_freq;
+ CARD32 pll_in_min;
+ CARD32 pll_in_max;
+ CARD32 pll_out_min;
+ CARD32 pll_out_max;
CARD16 xclk;
CARD32 min_ref_div;
CARD32 max_ref_div;
+ CARD32 min_post_div;
+ CARD32 max_post_div;
CARD32 min_feedback_div;
CARD32 max_feedback_div;
- CARD32 pll_in_min;
- CARD32 pll_in_max;
CARD32 best_vco;
} RADEONPLLRec, *RADEONPLLPtr;
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 7b4eafb..9730119 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -611,8 +611,19 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn)
or use a new algorithm to calculate
from min_input and max_input
*/
- pll->min_pll_freq = RADEON_BIOS16 (pll_info_block + 78);
- pll->max_pll_freq = RADEON_BIOS32 (pll_info_block + 32);
+ pll->pll_out_min = RADEON_BIOS16 (pll_info_block + 78);
+ pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 32);
+
+ if (pll->pll_out_min == 0) {
+ if (IS_AVIVO_VARIANT)
+ pll->pll_out_min = 64800;
+ else
+ pll->pll_out_min = 20000;
+ }
+
+ pll->pll_in_min = RADEON_BIOS16 (pll_info_block + 74);
+ pll->pll_in_max = RADEON_BIOS16 (pll_info_block + 76);
+
pll->xclk = RADEON_BIOS16 (pll_info_block + 72);
info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0;
@@ -622,8 +633,13 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn)
pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e);
pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10);
- pll->min_pll_freq = RADEON_BIOS32 (pll_info_block + 0x12);
- pll->max_pll_freq = RADEON_BIOS32 (pll_info_block + 0x16);
+ pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12);
+ pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16);
+
+ /* not available in the bios */
+ pll->pll_in_min = 40;
+ pll->pll_in_max = 100;
+
pll->xclk = RADEON_BIOS16 (pll_info_block + 0x08);
info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0;
@@ -636,8 +652,8 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, "
"max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n",
- pll->reference_freq, (unsigned)pll->min_pll_freq,
- (unsigned)pll->max_pll_freq, pll->xclk, info->sclk,
+ pll->reference_freq, (unsigned)pll->pll_out_min,
+ (unsigned)pll->pll_out_max, pll->xclk, info->sclk,
info->mclk);
return TRUE;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index cf78e2c..45eb1ac 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -631,7 +631,7 @@ static CARD32 RADEONDiv64(CARD64 n, CARD32 d)
return (n + (d / 2)) / d;
}
-static void
+void
RADEONComputePLL(RADEONPLLPtr pll,
unsigned long freq,
CARD32 *chosen_dot_clock_freq,
@@ -639,10 +639,6 @@ RADEONComputePLL(RADEONPLLPtr pll,
CARD32 *chosen_reference_div,
CARD32 *chosen_post_div)
{
- int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0};
-
- int i;
-
CARD32 best_vco = pll->best_vco;
CARD32 best_post_div = 1;
CARD32 best_ref_div = 1;
@@ -650,15 +646,15 @@ RADEONComputePLL(RADEONPLLPtr pll,
CARD32 best_freq = 1;
CARD32 best_error = 0xffffffff;
CARD32 best_vco_diff = 1;
+ CARD32 post_div;
ErrorF("freq: %lu\n", freq);
- for (i = 0; post_divs[i]; i++) {
- int post_div = post_divs[i];
+ for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
CARD32 ref_div;
CARD32 vco = (freq / 10000) * post_div;
- if (vco < pll->min_pll_freq || vco > pll->max_pll_freq)
+ if (vco < pll->pll_out_min || vco > pll->pll_out_max)
continue;
for (ref_div = pll->min_ref_div; ref_div <= pll->max_ref_div; ++ref_div) {
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 2c5e64f..16d758b 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1162,22 +1162,25 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
if (pll->reference_div < 2) pll->reference_div = 12;
}
-
} else {
xf86DrvMsg (pScrn->scrnIndex, X_WARNING,
"Video BIOS not detected, using default clock settings!\n");
/* Default min/max PLL values */
if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) {
- pll->min_pll_freq = 20000;
- pll->max_pll_freq = 50000;
+ pll->pll_in_min = 100;
+ pll->pll_in_max = 1350;
+ pll->pll_out_min = 20000;
+ pll->pll_out_max = 50000;
} else {
- pll->min_pll_freq = 12500;
- pll->max_pll_freq = 35000;
+ pll->pll_in_min = 40;
+ pll->pll_in_max = 100;
+ pll->pll_out_min = 12500;
+ pll->pll_out_max = 35000;
}
if (RADEONProbePLLParameters(pScrn))
- return;
+ return;
if (info->IsIGP)
pll->reference_freq = 1432;
@@ -1198,25 +1201,30 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
* Empirical value changed to 24 to raise pixel clock limit and
* allow higher resolution modes on capable monitors
*/
- pll->max_pll_freq = min(pll->max_pll_freq,
+ pll->pll_out_max = min(pll->pll_out_max,
24 * info->mclk * 100 / pScrn->bitsPerPixel *
info->RamWidth / 16);
}
/* card limits for computing PLLs */
+ if (IS_AVIVO_VARIANT) {
+ pll->min_post_div = 2;
+ pll->max_post_div = 0x7f;
+ } else {
+ pll->min_post_div = 2;
+ pll->max_post_div = 12; //16 on crtc0
+ }
pll->min_ref_div = 2;
pll->max_ref_div = 0x3ff;
pll->min_feedback_div = 4;
pll->max_feedback_div = 0x7ff;
- pll->pll_in_min = 40;
- pll->pll_in_max = 100;
pll->best_vco = 0;
xf86DrvMsg (pScrn->scrnIndex, X_INFO,
"PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n",
pll->reference_freq,
pll->reference_div,
- (unsigned)pll->min_pll_freq, (unsigned)pll->max_pll_freq,
+ (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max,
pll->xclk);
/* (Some?) Radeon BIOSes seem too lie about their minimum dot
@@ -1225,7 +1233,7 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
*/
if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK,
OPTUNITS_MHZ, &min_dotclock)) {
- if (min_dotclock < 12 || min_dotclock*100 >= pll->max_pll_freq) {
+ if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Illegal minimum dotclock specified %.2f MHz "
"(option ignored)\n",
@@ -1234,8 +1242,8 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Forced minimum dotclock to %.2f MHz "
"(instead of detected %.2f MHz)\n",
- min_dotclock, ((double)pll->min_pll_freq/1000));
- pll->min_pll_freq = min_dotclock * 1000;
+ min_dotclock, ((double)pll->pll_out_min/1000));
+ pll->pll_out_min = min_dotclock * 1000;
}
}
}
commit f5ac34983411e4c4f41ab1817dce582830f398fd
Merge: f2b2e08... 6ccf5b3...
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Dec 12 22:37:44 2007 -0500
Merge branch 'master' of git+ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
merge and fix conflicts
diff --cc src/radeon_cursor.c
index 00913c8,9dd6eb8..842668b
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@@ -89,25 -89,6 +89,25 @@@
#endif
+static void
+avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 0);
+
+ if (enable) {
+ OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
- info->fbLocation + info->cursor_offset);
++ info->fbLocation + radeon_crtc->cursor_offset);
+ OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
+ ((CURSOR_WIDTH - 1) << 16) | (CURSOR_HEIGHT - 1));
+ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
+ AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
+ }
+}
+
void
radeon_crtc_show_cursor (xf86CrtcPtr crtc)
{
@@@ -191,38 -158,30 +191,38 @@@ radeon_crtc_set_cursor_position (xf86Cr
else if (mode->Flags & V_DBLSCAN)
y *= 2;
- if (crtc_id == 0) {
- OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK
- | (xorigin << 16)
- | yorigin));
- OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK
- | ((xorigin ? 0 : x) << 16)
- | (yorigin ? 0 : y)));
- RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
- OUTREG(RADEON_CUR_OFFSET,
- radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
- } else if (crtc_id == 1) {
- OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK
- | (xorigin << 16)
- | yorigin));
- OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK
- | ((xorigin ? 0 : x) << 16)
- | (yorigin ? 0 : y)));
- RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
- OUTREG(RADEON_CUR2_OFFSET,
- radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
+ if (IS_AVIVO_VARIANT) {
+ /* avivo cursor spans the full fb width */
+ x += crtc->x;
+ y += crtc->y;
+ OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16)
+ | (yorigin ? 0 : y));
+ OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
+ } else {
+ if (crtc_id == 0) {
+ OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK
+ | (xorigin << 16)
+ | yorigin));
+ OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK
+ | ((xorigin ? 0 : x) << 16)
+ | (yorigin ? 0 : y)));
+ RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
+ OUTREG(RADEON_CUR_OFFSET,
- info->cursor_offset + pScrn->fbOffset + yorigin * stride);
++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
+ } else if (crtc_id == 1) {
+ OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK
+ | (xorigin << 16)
+ | yorigin));
+ OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK
+ | ((xorigin ? 0 : x) << 16)
+ | (yorigin ? 0 : y)));
+ RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
+ OUTREG(RADEON_CUR2_OFFSET,
- info->cursor_offset + pScrn->fbOffset + yorigin * stride);
++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
+ }
}
-
}
void
@@@ -310,10 -272,10 +314,10 @@@ Bool RADEONCursorInit(ScreenPtr pScreen
FBAreaPtr fbarea;
fbarea = xf86AllocateOffscreenArea(pScreen, width, height,
- 256, NULL, NULL, NULL);
+ align, NULL, NULL, NULL);
if (!fbarea) {
- info->cursor_offset = 0;
+ cursor_offset = 0;
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Hardware cursor disabled"
" due to insufficient offscreen memory\n");
diff --cc src/radeon_probe.h
index df07149,7f8ce45..a25d635
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@@ -165,17 -166,9 +165,17 @@@ typedef struct _RADEONCrtcPrivateRec
#endif
int crtc_id;
int binding;
+ CARD32 cursor_offset;
/* Lookup table values to be set when the CRTC is enabled */
CARD8 lut_r[256], lut_g[256], lut_b[256];
+
+ uint32_t crtc_offset;
+ int h_total, h_blank, h_sync_wid, h_sync_pol;
+ int v_total, v_blank, v_sync_wid, v_sync_pol;
+ int fb_format, fb_length;
+ int fb_pitch, fb_width, fb_height;
+ INT16 cursor_x;
+ INT16 cursor_y;
- unsigned long cursor_offset;
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct {
commit f2b2e0804183b52d9d3f56ad85b3552ece76c544
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Dec 12 22:18:37 2007 -0500
RADEON: fix rotation on avivo chips
There are still some issues, but this is better than before.
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 3c61ef7..5b09107 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -238,7 +238,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
void *ptr;
AtomBiosArgRec data;
- unsigned char *space;
+ unsigned char *space;
RADEONSavePtr save = info->ModeReg;
if (IS_AVIVO_VARIANT) {
@@ -383,7 +383,8 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
default:
FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
}
- if (info->tilingEnabled) {
+
+ if (info->tilingEnabled && (crtc->rotatedData == NULL)) {
radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
}
@@ -394,24 +395,47 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
/* setup fb format and location
*/
- OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
- OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
- (mode->HDisplay << 16) | mode->VDisplay);
+ if (crtc->rotatedData != NULL) {
+ /* x/y offset is already included */
+ x = 0;
+ y = 0;
+ fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB;
+ }
+
+ /* lock the grph regs */
+ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK);
OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset,
radeon_crtc->fb_format);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset,
crtc->scrn->virtualX);
OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset,
crtc->scrn->virtualY);
OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
crtc->scrn->displayWidth);
-
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+ /* unlock the grph regs */
+ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0);
+
+ /* lock the mode regs */
+ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK);
+
+ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualY);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
+ (mode->HDisplay << 16) | mode->VDisplay);
+ /* unlock the mode regs */
+ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0);
+
}
atombios_crtc_set_pll(crtc, adjusted_mode);
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index fa2aba0..caf7369 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -1268,7 +1268,7 @@ radeon_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
if (!data)
data = radeon_crtc_shadow_allocate(crtc, width, height);
-
+
rotate_pitch = pScrn->displayWidth * cpp;
rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 8737d2e..e7ef932 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3390,6 +3390,7 @@
#define AVIVO_D1GRPH_X_END 0x6134
#define AVIVO_D1GRPH_Y_END 0x6138
#define AVIVO_D1GRPH_UPDATE 0x6144
+# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16)
#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
#define AVIVO_D1CUR_CONTROL 0x6400
@@ -3421,12 +3422,15 @@
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
+#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
+#define AVIVO_D1SCL_UPDATE 0x65cc
+# define AVIVO_D1SCL_UPDATE_LOCK (1<<16)
/* second crtc */
#define AVIVO_D2CRTC_H_TOTAL 0x6800
commit 372bf41818fdafc6a9d2914aee3a8e359f668f02
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Dec 11 14:04:58 2007 -0500
RADEON: handle HMDI properly (untested) and fix some merge leftovers
diff --git a/src/radeon_output.c b/src/radeon_output.c
index d872205..4dc47ce 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -290,6 +290,8 @@ avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
MonType = MT_LCD;
else if (radeon_output->type == OUTPUT_DVI_D)
MonType = MT_DFP;
+ else if (radeon_output->type == OUTPUT_HDMI)
+ MonType = MT_DFP;
else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */
MonType = MT_DFP;
else
@@ -388,6 +390,8 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output)
MonType = MT_LCD;
else if (radeon_output->type == OUTPUT_DVI_D)
MonType = MT_DFP;
+ else if (radeon_output->type == OUTPUT_HDMI)
+ MonType = MT_DFP;
else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */
MonType = MT_DFP;
else
@@ -655,11 +659,18 @@ legacy_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
RADEONMonitorType found = MT_NONE;
if (OUTPUT_IS_TV) {
- if (info->InternalTVOut) {
- if (radeon_output->load_detection)
- found = radeon_detect_tv(pScrn);
+ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) {
+ if (radeon_output->type == OUTPUT_STV)
+ radeon_output->MonType = MT_STV;
else
- found = MT_NONE;
+ radeon_output->MonType = MT_CTV;
+ } else {
+ if (info->InternalTVOut) {
+ if (radeon_output->load_detection)
+ radeon_output->MonType = radeon_detect_tv(pScrn);
+ else
+ radeon_output->MonType = MT_NONE;
+ }
}
} else {
if (radeon_output->DACType == DAC_PRIMARY) {
@@ -693,24 +704,16 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (!radeon_output->MonType) {
if (radeon_output->type == OUTPUT_LVDS)
radeon_output->MonType = MT_LCD;
- else if (OUTPUT_IS_TV)
- radeon_output->MonType = MT_NONE;
- else
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
- }
- } else if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) {
- if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) {
- if (radeon_output->type == OUTPUT_STV)
- radeon_output->MonType = MT_STV;
- else
- radeon_output->MonType = MT_CTV;
- } else {
- if (info->InternalTVOut) {
- if (radeon_output->load_detection)
- radeon_output->MonType = radeon_detect_tv(pScrn);
- else
+ else if (OUTPUT_IS_TV) {
+ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) {
+ if (radeon_output->type == OUTPUT_STV)
+ radeon_output->MonType = MT_STV;
+ else
+ radeon_output->MonType = MT_CTV;
+ } else
radeon_output->MonType = MT_NONE;
- }
+ } else
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
}
} else {
radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output);
@@ -1735,11 +1738,11 @@ radeon_detect(xf86OutputPtr output)
radeon_output->MonType = MT_CV;
else if (radeon_output->type == OUTPUT_DVI_D)
radeon_output->MonType = MT_DFP;
+ else if (radeon_output->type == OUTPUT_HDMI)
+ radeon_output->MonType = MT_DFP;
else if (radeon_output->type == OUTPUT_DVI_A)
radeon_output->MonType = MT_CRT;
else if (radeon_output->type == OUTPUT_DVI_I) {
- if (radeon_output->MonType == MT_NONE)
- connected = FALSE;
if (radeon_output->DVIType == DVI_ANALOG)
radeon_output->MonType = MT_CRT;
else if (radeon_output->DVIType == DVI_DIGITAL)
@@ -2296,6 +2299,9 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output
output = OUTPUT_CTV; break;
case CONNECTOR_LVDS:
output = OUTPUT_LVDS; break;
+ case CONNECTOR_HDMI_TYPE_A:
+ case CONNECTOR_HDMI_TYPE_B:
+ output = OUTPUT_HDMI; break;
case CONNECTOR_DIGITAL:
case CONNECTOR_NONE:
case CONNECTOR_UNSUPPORTED:
@@ -3236,6 +3242,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
int i = 0;
int num_vga = 0;
int num_dvi = 0;
+ int num_hdmi = 0;
/* We first get the information about all connectors from BIOS.
* This is how the card is phyiscally wired up.
@@ -3342,6 +3349,9 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
num_dvi++;
} else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) {
num_vga++;
+ } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) ||
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) {
+ num_hdmi++;
}
}
}
@@ -3385,6 +3395,14 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
} else {
output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0");
}
+ } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) ||
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) {
+ if (num_hdmi > 1) {
+ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-1");
+ num_hdmi--;
+ } else {
+ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-0");
+ }
} else
output = xf86OutputCreate(pScrn, &radeon_output_funcs, OutputType[radeon_output->type]);
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index c0b2694..df07149 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -63,7 +63,7 @@ typedef enum
MT_CTV = 4,
MT_STV = 5,
MT_CV = 6,
- MT_HDMI = 7,
+ MT_HDMI = 7, // this should really just be MT_DFP
MT_DP = 8
} RADEONMonitorType;
commit 3c22ad977c25d5ca2811821fcac6bb8ecd79994a
Merge: c9a0cee... f3d2ec3...
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Dec 11 13:11:15 2007 -0500
Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
fix conflicts
diff --cc src/radeon_crtc.c
index 1ea6d2b,8984428..fa2aba0
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@@ -699,11 -767,11 +781,10 @@@ RADEONInitPLLRegisters(ScrnInfoPtr pScr
#endif
save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
- save->htotal_cntl = 0;
+ save->htotal_cntl = mode->HTotal & 0x7;
- save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl &
- ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
-
+ save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl &
+ ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
-
}
/* Define PLL2 registers for requested video mode */
@@@ -764,17 -826,20 +839,19 @@@ RADEONInitPLL2Registers(ScrnInfoPtr pSc
(unsigned)save->dot_clock_freq_2,
(unsigned)save->pll_output_freq_2,
save->feedback_div_2,
+ save->reference_div_2,
save->post_div_2);
- save->p2pll_ref_div = pll->reference_div;
+ save->p2pll_ref_div = save->reference_div_2;
+
save->p2pll_div_0 = (save->feedback_div_2 |
(post_div->bitvalue << 16));
- save->htotal_cntl2 = 0;
- save->pixclks_cntl = ((info->SavedReg->pixclks_cntl &
- ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
- RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
+ save->htotal_cntl2 = mode->HTotal & 0x7;
- save->pixclks_cntl = ((info->SavedReg.pixclks_cntl &
++ save->pixclks_cntl = ((info->SavedReg->pixclks_cntl &
+ ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
+ RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
-
}
static void
@@@ -849,27 -914,27 +926,27 @@@ legacy_crtc_mode_set(xf86CrtcPtr crtc,
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("init crtc1\n");
- RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode);
- RADEONInitCrtcBase(crtc, &info->ModeReg, x, y);
+ RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode);
+ RADEONInitCrtcBase(crtc, info->ModeReg, x, y);
- dot_clock = adjusted_mode->Clock / 1000.0;
- if (dot_clock) {
+ dot_clock = adjusted_mode->Clock / 1000.0;
+ if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, info, info->ModeReg, &info->pll, dot_clock);
- } else {
- info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
- info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
- info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl;
- }
- RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode);
++ RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode);
+ } else {
- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
++ info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
++ info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
++ info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl;
+ }
break;
case 1:
ErrorF("init crtc2\n");
- RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode);
- RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode);
- RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y);
++ RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode);
+ RADEONInitCrtc2Base(crtc, info->ModeReg, x, y);
- dot_clock = adjusted_mode->Clock / 1000.0;
- if (dot_clock) {
+ dot_clock = adjusted_mode->Clock / 1000.0;
+ if (dot_clock) {
ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, dot_clock, no_odd_post_div);
- }
- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode);
++ RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, adjusted_mode);
+ }
break;
}
diff --cc src/radeon_probe.h
index a7d873e,66ece94..c0b2694
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@@ -232,287 -221,10 +232,289 @@@ typedef struct _RADEONOutputPrivateRec
int SupportedTVStds;
Bool tv_on;
int load_detection;
+
+ char *name;
+ int output_id;
+ int devices;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
+struct avivo_pll_state {
+ CARD32 ref_div_src;
+ CARD32 ref_div;
+ CARD32 fb_div;
+ CARD32 post_div_src;
+ CARD32 post_div;
+ CARD32 ext_ppll_cntl;
+ CARD32 pll_cntl;
+ CARD32 int_ss_cntl;
+};
+
+
+struct avivo_crtc_state {
+ CARD32 pll_source;
+ CARD32 h_total;
+ CARD32 h_blank_start_end;
+ CARD32 h_sync_a;
+ CARD32 h_sync_a_cntl;
+ CARD32 h_sync_b;
+ CARD32 h_sync_b_cntl;
+ CARD32 v_total;
+ CARD32 v_blank_start_end;
+ CARD32 v_sync_a;
+ CARD32 v_sync_a_cntl;
+ CARD32 v_sync_b;
+ CARD32 v_sync_b_cntl;
+ CARD32 control;
+ CARD32 blank_control;
+ CARD32 interlace_control;
+ CARD32 stereo_control;
+ CARD32 cursor_control;
+};
+
+struct avivo_grph_state {
+ CARD32 enable;
+ CARD32 control;
+ CARD32 prim_surf_addr;
+ CARD32 sec_surf_addr;
+ CARD32 pitch;
+ CARD32 x_offset;
+ CARD32 y_offset;
+ CARD32 x_start;
+ CARD32 y_start;
+ CARD32 x_end;
+ CARD32 y_end;
+
+ CARD32 viewport_start;
+ CARD32 viewport_size;
+ CARD32 scl_enable;
+};
+
+struct avivo_dac_state {
+ CARD32 enable;
+ CARD32 source_select;
+ CARD32 force_output_cntl;
+ CARD32 powerdown;
+};
+
+struct avivo_dig_state {
+ CARD32 cntl;
+ CARD32 bit_depth_cntl;
+ CARD32 data_sync;
+ CARD32 transmitter_enable;
+ CARD32 transmitter_cntl;
+ CARD32 source_select;
+};
+
+struct avivo_state
+{
+ CARD32 hdp_fb_location;
+ CARD32 mc_memory_map;
+ CARD32 vga_memory_base;
+ CARD32 vga_fb_start;
+
+ CARD32 vga1_cntl;
+ CARD32 vga2_cntl;
+
+ CARD32 crtc_master_en;
+ CARD32 crtc_tv_control;
+
+ CARD32 lvtma_pwrseq_cntl;
+ CARD32 lvtma_pwrseq_state;
+
+ struct avivo_pll_state pll1;
+ struct avivo_pll_state pll2;
+
+ struct avivo_crtc_state crtc1;
+ struct avivo_crtc_state crtc2;
+
+ struct avivo_grph_state grph1;
+ struct avivo_grph_state grph2;
+
+ struct avivo_dac_state daca;
+ struct avivo_dac_state dacb;
+
+ struct avivo_dig_state tmds1;
+ struct avivo_dig_state tmds2;
+
+};
+
+/*
+ * Maximum length of horizontal/vertical code timing tables for state storage
+ */
+#define MAX_H_CODE_TIMING_LEN 32
+#define MAX_V_CODE_TIMING_LEN 32
+
+typedef struct {
+ struct avivo_state avivo;
+
+ /* Common registers */
+ CARD32 ovr_clr;
+ CARD32 ovr_wid_left_right;
+ CARD32 ovr_wid_top_bottom;
+ CARD32 ov0_scale_cntl;
+ CARD32 mpp_tb_config;
+ CARD32 mpp_gp_config;
+ CARD32 subpic_cntl;
+ CARD32 viph_control;
+ CARD32 i2c_cntl_1;
+ CARD32 gen_int_cntl;
+ CARD32 cap0_trig_cntl;
+ CARD32 cap1_trig_cntl;
+ CARD32 bus_cntl;
+ CARD32 bios_4_scratch;
+ CARD32 bios_5_scratch;
+ CARD32 bios_6_scratch;
+ CARD32 surface_cntl;
+ CARD32 surfaces[8][3];
+ CARD32 mc_agp_location;
+ CARD32 mc_agp_location_hi;
+ CARD32 mc_fb_location;
+ CARD32 display_base_addr;
+ CARD32 display2_base_addr;
+ CARD32 ov0_base_addr;
+
+ /* Other registers to save for VT switches */
+ CARD32 dp_datatype;
+ CARD32 rbbm_soft_reset;
+ CARD32 clock_cntl_index;
+ CARD32 amcgpio_en_reg;
+ CARD32 amcgpio_mask;
+
+ /* CRTC registers */
+ CARD32 crtc_gen_cntl;
+ CARD32 crtc_ext_cntl;
+ CARD32 dac_cntl;
+ CARD32 crtc_h_total_disp;
+ CARD32 crtc_h_sync_strt_wid;
+ CARD32 crtc_v_total_disp;
+ CARD32 crtc_v_sync_strt_wid;
+ CARD32 crtc_offset;
+ CARD32 crtc_offset_cntl;
+ CARD32 crtc_pitch;
+ CARD32 disp_merge_cntl;
+ CARD32 grph_buffer_cntl;
+ CARD32 crtc_more_cntl;
+ CARD32 crtc_tile_x0_y0;
+
+ /* CRTC2 registers */
+ CARD32 crtc2_gen_cntl;
+ CARD32 dac_macro_cntl;
+ CARD32 dac2_cntl;
+ CARD32 disp_output_cntl;
+ CARD32 disp_tv_out_cntl;
+ CARD32 disp_hw_debug;
+ CARD32 disp2_merge_cntl;
+ CARD32 grph2_buffer_cntl;
+ CARD32 crtc2_h_total_disp;
+ CARD32 crtc2_h_sync_strt_wid;
+ CARD32 crtc2_v_total_disp;
+ CARD32 crtc2_v_sync_strt_wid;
+ CARD32 crtc2_offset;
+ CARD32 crtc2_offset_cntl;
+ CARD32 crtc2_pitch;
+ CARD32 crtc2_tile_x0_y0;
+
+ /* Flat panel registers */
+ CARD32 fp_crtc_h_total_disp;
+ CARD32 fp_crtc_v_total_disp;
+ CARD32 fp_gen_cntl;
+ CARD32 fp2_gen_cntl;
+ CARD32 fp_h_sync_strt_wid;
+ CARD32 fp_h2_sync_strt_wid;
+ CARD32 fp_horz_stretch;
+ CARD32 fp_panel_cntl;
+ CARD32 fp_v_sync_strt_wid;
+ CARD32 fp_v2_sync_strt_wid;
+ CARD32 fp_vert_stretch;
+ CARD32 lvds_gen_cntl;
+ CARD32 lvds_pll_cntl;
+ CARD32 tmds_pll_cntl;
+ CARD32 tmds_transmitter_cntl;
+
+ /* Computed values for PLL */
+ CARD32 dot_clock_freq;
+ CARD32 pll_output_freq;
+ int feedback_div;
++ int reference_div;
+ int post_div;
+
+ /* PLL registers */
+ unsigned ppll_ref_div;
+ unsigned ppll_div_3;
+ CARD32 htotal_cntl;
+ CARD32 vclk_ecp_cntl;
+
+ /* Computed values for PLL2 */
+ CARD32 dot_clock_freq_2;
+ CARD32 pll_output_freq_2;
+ int feedback_div_2;
++ int reference_div_2;
+ int post_div_2;
+
+ /* PLL2 registers */
+ CARD32 p2pll_ref_div;
+ CARD32 p2pll_div_0;
+ CARD32 htotal_cntl2;
+ CARD32 pixclks_cntl;
+
+ /* Pallet */
+ Bool palette_valid;
+ CARD32 palette[256];
+ CARD32 palette2[256];
+
+ CARD32 rs480_unk_e30;
+ CARD32 rs480_unk_e34;
+ CARD32 rs480_unk_e38;
+ CARD32 rs480_unk_e3c;
+
+ /* TV out registers */
+ CARD32 tv_master_cntl;
+ CARD32 tv_htotal;
+ CARD32 tv_hsize;
+ CARD32 tv_hdisp;
+ CARD32 tv_hstart;
+ CARD32 tv_vtotal;
+ CARD32 tv_vdisp;
+ CARD32 tv_timing_cntl;
+ CARD32 tv_vscaler_cntl1;
+ CARD32 tv_vscaler_cntl2;
+ CARD32 tv_sync_size;
+ CARD32 tv_vrestart;
+ CARD32 tv_hrestart;
+ CARD32 tv_frestart;
+ CARD32 tv_ftotal;
+ CARD32 tv_clock_sel_cntl;
+ CARD32 tv_clkout_cntl;
+ CARD32 tv_data_delay_a;
+ CARD32 tv_data_delay_b;
+ CARD32 tv_dac_cntl;
+ CARD32 tv_pll_cntl;
+ CARD32 tv_pll_cntl1;
+ CARD32 tv_pll_fine_cntl;
+ CARD32 tv_modulator_cntl1;
+ CARD32 tv_modulator_cntl2;
+ CARD32 tv_frame_lock_cntl;
+ CARD32 tv_pre_dac_mux_cntl;
+ CARD32 tv_rgb_cntl;
+ CARD32 tv_y_saw_tooth_cntl;
+ CARD32 tv_y_rise_cntl;
+ CARD32 tv_y_fall_cntl;
+ CARD32 tv_uv_adr;
+ CARD32 tv_upsamp_and_gain_cntl;
+ CARD32 tv_gain_limit_settings;
+ CARD32 tv_linear_gain_settings;
+ CARD32 tv_crc_cntl;
+ CARD32 tv_sync_cntl;
+ CARD32 gpiopad_a;
+ CARD32 pll_test_cntl;
+
+ CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
+ CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
+
+} RADEONSaveRec, *RADEONSavePtr;
+
#define RADEON_MAX_CRTC 2
-#define RADEON_MAX_BIOS_CONNECTOR 8
+#define RADEON_MAX_BIOS_CONNECTOR 16
typedef struct
{
commit c9a0cee97ca69e8fe1e1937c7670fa903214cded
Author: Dave Airlie <airlied at linux.ie>
Date: Tue Dec 11 06:03:46 2007 +1000
more zaphod fixes - some other work maybe needed
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 4afbee1..8ade8b1 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2549,11 +2549,11 @@ static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn)
int i;
if (info->IsPrimary) {
+ xf86OutputDestroy(config->output[0]);
while(config->num_output > 1) {
xf86OutputDestroy(config->output[1]);
}
} else {
- xf86OutputDestroy(config->output[0]);
while(config->num_output > 1) {
xf86OutputDestroy(config->output[1]);
}
@@ -2597,6 +2597,10 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
output->status = (*output->funcs->detect) (output);
ErrorF("finished output detect: %d\n", i);
+ if (info->IsPrimary || info->IsSecondary) {
+ if (output->status != XF86OutputStatusConnected)
+ return FALSE;
+ }
}
ErrorF("finished all detect\n");
return TRUE;
commit 731830297f2fc4a416882aacfb0d9b5f8ed32520
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:50:38 2007 +1000
fixup some warnings
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 9d17e47..a04598d 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1443,7 +1443,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
ErrorF("record type %d\n", Record->ucRecordType);
switch (Record->ucRecordType) {
case ATOM_I2C_RECORD_TYPE:
- rhdAtomParseI2CRecord(&info->atomBIOS,
+ rhdAtomParseI2CRecord(info->atomBIOS,
(ATOM_I2C_RECORD *)Record,
&info->BiosConnector[i].ddc_line);
break;
@@ -2604,7 +2604,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data)
void
atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor)
{
- ATOM_MASTER_COMMAND_TABLE *cmd_table = atomBIOS->BIOSBase + atomBIOS->cmd_offset;
+ ATOM_MASTER_COMMAND_TABLE *cmd_table = (void *)(atomBIOS->BIOSBase + atomBIOS->cmd_offset);
ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start;
ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr;
@@ -2615,7 +2615,7 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m
offset = *(((unsigned short *)table_start) + index);
- table_hdr = atomBIOS->BIOSBase + offset;
+ table_hdr = (ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)(atomBIOS->BIOSBase + offset);
*major = table_hdr->CommonHeader.ucTableFormatRevision;
*minor = table_hdr->CommonHeader.ucTableContentRevision;
commit 2818e2b02ca90c9dfa50905b5311b2ae83ac3b0c
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:43:52 2007 +1000
add more to configure.ac for using out-of-tree mode src
diff --git a/configure.ac b/configure.ac
index 71e5e45..b5c694c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -62,6 +62,11 @@ AC_ARG_ENABLE(exa,
[EXA="$enableval"],
[EXA=yes])
+AC_ARG_WITH(xserver-source,AC_HELP_STRING([--with-xserver-source=XSERVER_SOURCE],
+ [Path to X server source tree]),
+ [ XSERVER_SOURCE="$withval" ],
+ [ XSERVER_SOURCE="" ])
+
# Checks for extensions
XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto)
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
@@ -116,22 +121,6 @@ CFLAGS="$XORG_CFLAGS"
AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"])
CFLAGS="$save_CFLAGS"
-AM_CONDITIONAL(XMODES, test "x$XMODES" = xno)
-if test "x$XMODES" = xyes; then
- AC_MSG_NOTICE([X server has new mode code])
- AC_DEFINE(XMODES, 1,[X server has built-in mode code])
- XMODES_CFLAGS=
-else
- if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then
- AC_MSG_NOTICE([X server is missing new mode code, using local copy])
- else
- AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source])
- fi
- XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser'
-fi
-
-AC_SUBST([XMODES_CFLAGS])
-
# Note that this is sort of inverted from drivers/ati/Imakefile in
# the monolith. We test for foo, not for !foo (i.e. ATMISC_CPIO, not
# ATIMISC_AVOID_CPIO), but the defines are negative. So beware. Oh yeah,
@@ -228,6 +217,48 @@ AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
[#include "xorg-server.h"])
+AM_CONDITIONAL(XMODES, test "x$XMODES" = xno)
+
+if test "x$XSERVER_SOURCE" = x; then
+ if test -d ../../xserver; then
+ XSERVER_SOURCE="`cd ../../xserver && pwd`"
+ fi
+fi
+
+if test -d "$XSERVER_SOURCE"; then
+ case "$XSERVER_SOURCE" in
+ /*)
+ ;;
+ *)
+ XSERVER_SOURCE="`cd $XSERVER_SOURCE && pwd`"
+ esac
+ if test -f src/modes/xf86Modes.h; then
+ :
+ else
+ ln -sf $XSERVER_SOURCE/hw/xfree86/modes src/modes
+ fi
+
+ if test -f src/parser/xf86Parser.h; then
+ :
+ else
+ ln -sf $XSERVER_SOURCE/hw/xfree86/parser src/parser
+ fi
+fi
+if test "x$XMODES" = xyes; then
+ AC_MSG_NOTICE([X server has new mode code])
+ AC_DEFINE(XMODES, 1,[X server has built-in mode code])
+ XMODES_CFLAGS=
+else
+ if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then
+ AC_MSG_NOTICE([X server is missing new mode code, using local copy])
+ else
+ AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source])
+ fi
+ XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser'
+fi
+
+AC_SUBST([XMODES_CFLAGS])
+
CPPFLAGS="$SAVE_CPPFLAGS"
AM_CONDITIONAL(USE_EXA, test "x$USE_EXA" = xyes)
commit cc3c36100986f9d8060bc2d433373d4806f8e730
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:25:56 2007 +1000
add support for building against legacy servers similiar to Intel codepaths
diff --git a/configure.ac b/configure.ac
index b3d46a5..71e5e45 100644
--- a/configure.ac
+++ b/configure.ac
@@ -71,7 +71,7 @@ XORG_DRIVER_CHECK_EXT(XF86MISC, xf86miscproto)
XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
# Checks for pkg-config packages
-PKG_CHECK_MODULES(XORG, [xorg-server >= 1.3 xproto fontsproto $REQUIRED_MODULES])
+PKG_CHECK_MODULES(XORG, [xorg-server xproto fontsproto $REQUIRED_MODULES])
sdkdir=$(pkg-config --variable=sdkdir xorg-server)
# Checks for libraries.
@@ -112,6 +112,26 @@ if test "$DRI" = yes; then
fi
fi
+CFLAGS="$XORG_CFLAGS"
+AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"])
+CFLAGS="$save_CFLAGS"
+
+AM_CONDITIONAL(XMODES, test "x$XMODES" = xno)
+if test "x$XMODES" = xyes; then
+ AC_MSG_NOTICE([X server has new mode code])
+ AC_DEFINE(XMODES, 1,[X server has built-in mode code])
+ XMODES_CFLAGS=
+else
+ if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then
+ AC_MSG_NOTICE([X server is missing new mode code, using local copy])
+ else
+ AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source])
+ fi
+ XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser'
+fi
+
+AC_SUBST([XMODES_CFLAGS])
+
# Note that this is sort of inverted from drivers/ati/Imakefile in
# the monolith. We test for foo, not for !foo (i.e. ATMISC_CPIO, not
# ATIMISC_AVOID_CPIO), but the defines are negative. So beware. Oh yeah,
diff --git a/src/Makefile.am b/src/Makefile.am
index fd870c4..3e0352b 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -47,6 +47,22 @@ RADEON_ATOMBIOS_SOURCES = \
AtomBios/includes/ObjectID.h \
AtomBios/includes/regsdef.h
+XMODE_SRCS=\
+ local_xf86Rename.h \
+ parser/xf86Parser.h \
+ parser/xf86Optrec.h \
+ modes/xf86Modes.h \
+ modes/xf86Modes.c \
+ modes/xf86cvt.c \
+ modes/xf86Crtc.h \
+ modes/xf86Crtc.c \
+ modes/xf86Cursors.c \
+ modes/xf86EdidModes.c \
+ modes/xf86RandR12.c \
+ modes/xf86RandR12.h \
+ modes/xf86Rename.h \
+ modes/xf86Rotate.c \
+ modes/xf86DiDGA.c
if ATIMISC_CPIO
ATIMISC_CPIO_SOURCES = ativga.c ativgaio.c atibank.c atiwonder.c atiwonderio.c
@@ -61,7 +77,7 @@ ATIMISC_EXA_SOURCES = atimach64exa.c
RADEON_EXA_SOURCES = radeon_exa.c
endif
-AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER
+AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER
INCLUDES = -I$(srcdir)/AtomBios/includes
ati_drv_la_LTLIBRARIES = ati_drv.la
@@ -105,6 +121,11 @@ radeon_drv_la_SOURCES = \
$(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \
$(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c
+if XMODES
+radeon_drv_la_SOURCES += \
+ $(XMODE_SRCS)
+endif
+
theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la
theatre_detect_drv_la_LDFLAGS = -module -avoid-version
theatre_detect_drv_ladir = @moduledir@/multimedia
@@ -127,6 +148,7 @@ theatre200_drv_la_SOURCES = \
theatre200.c theatre200_module.c
EXTRA_DIST = \
+ $(XMODE_SRCS) \
atimach64render.c \
radeon_render.c \
radeon_accelfuncs.c \
commit 9c278cb7fa7f18d13bde053fd75221cfba9da377
Merge: 6451ea2... cc167b9...
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:18:03 2007 +1000
Merge branch 'zaphod-lolz' of git://git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
Conflicts:
src/radeon.h
src/radeon_crtc.c
src/radeon_driver.c
src/radeon_output.c
diff --cc src/atombios_crtc.c
index 5c2d261,0000000..3c61ef7
mode 100644,000000..100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@@ -1,433 -1,0 +1,433 @@@
+ /*
+ * Copyright © 2007 Red Hat, Inc.
+ *
+ * PLL code is:
+ * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+ * Copyright 2007 Matthias Hopf <mhopf at novell.com>
+ * Copyright 2007 Egbert Eich <eich at novell.com>
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Dave Airlie <airlied at redhat.com>
+ *
+ */
+/*
+ * avivo crtc handling functions.
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+/* DPMS */
+#define DPMS_SERVER
+#include <X11/extensions/dpms.h>
+
+#include "radeon.h"
+#include "radeon_reg.h"
+#include "radeon_macros.h"
+#include "radeon_atombios.h"
+
+#ifdef XF86DRI
+#define _XF86DRI_SERVER_
+#include "radeon_dri.h"
+#include "radeon_sarea.h"
+#include "sarea.h"
+#endif
+
+AtomBiosResult
+atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
+{
+ ENABLE_CRTC_PS_ALLOCATION crtc_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucEnable = state;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Enable":"Disable", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Enable CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+AtomBiosResult
+atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
+{
+ BLANK_CRTC_PS_ALLOCATION crtc_data;
+ unsigned char *space;
+ AtomBiosArgRec data;
+
+ memset(&crtc_data, 0, sizeof(crtc_data));
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucBlanking = state;
+
+ data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Blank":"Unblank", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Blank CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+static void
+atombios_crtc_enable(xf86CrtcPtr crtc, int enable)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable);
+
+ //TODOavivo_wait_idle(avivo);
+}
+
+void
+atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ switch (mode) {
+ case DPMSModeOn:
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ case DPMSModeOff:
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ }
+}
+
+static AtomBiosResult
+atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
+{
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = crtc_param;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC Timing success\n");
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Set CRTC Timing failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+/*
+ * Calculate the PLL parameters for a given dotclock.
+ */
+#define RADEON_PLL_DEFAULT_PLLOUT_MIN 64800 /* experimental. - taken from rhd divided by 10 */
+
+static Bool
+PLLCalculate(ScrnInfoPtr pScrn, CARD32 PixelClock,
+ CARD16 *RefDivider, CARD16 *FBDivider, CARD8 *PostDivider)
+{
+/* limited by the number of bits available */
+#define FB_DIV_LIMIT 1024 /* rv6x0 doesn't like 2048 */
+#define REF_DIV_LIMIT 1024
+#define POST_DIV_LIMIT 128
+ RADEONInfoPtr info = RADEONPTR (pScrn);
+ RADEONPLLPtr pll = &info->pll;
+ CARD32 FBDiv, RefDiv, PostDiv, BestDiff = 0xFFFFFFFF;
+ float Ratio;
+
+ Ratio = ((float) PixelClock) / ((float) pll->reference_freq * 10);
+
+ if (pll->min_pll_freq == 0)
+ pll->min_pll_freq = RADEON_PLL_DEFAULT_PLLOUT_MIN;
+ for (PostDiv = 2; PostDiv < POST_DIV_LIMIT; PostDiv++) {
+ CARD32 VCOOut = PixelClock * PostDiv;
+
+ /* we are conservative and avoid the limits */
+ if (VCOOut <= pll->min_pll_freq * 10)
+ continue;
+ if (VCOOut >= pll->max_pll_freq * 10)
+ break;
+
+ for (RefDiv = 1; RefDiv <= REF_DIV_LIMIT; RefDiv++)
+ {
+ CARD32 Diff;
+
+ FBDiv = (CARD32) ((Ratio * PostDiv * RefDiv) + 0.5);
+
+ if (FBDiv >= FB_DIV_LIMIT)
+ break;
+
+ if (FBDiv > (500 + (13 * RefDiv))) /* rv6x0 limit */
+ break;
+
+ Diff = abs( PixelClock - (FBDiv * pll->reference_freq * 10) / (PostDiv * RefDiv) );
+
+ if (Diff < BestDiff) {
+ *FBDivider = FBDiv;
+ *RefDivider = RefDiv;
+ *PostDivider = PostDiv;
+ BestDiff = Diff;
+ }
+
+ if (BestDiff == 0)
+ break;
+ }
+ if (BestDiff == 0)
+ break;
+ }
+
+ if (BestDiff != 0xFFFFFFFF) {
+ ErrorF("PLL Calculation: %dkHz = "
+ "(((0x%X / 0x%X) * 0x%X) / 0x%X) (%dkHz off)\n",
+ (int) PixelClock, (unsigned int) pll->reference_freq * 10, *RefDivider,
+ *FBDivider, *PostDivider, (int) BestDiff);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PLL for %dkHz uses %dkHz internally.\n",
+ (int) PixelClock,
+ (int) (pll->reference_freq * 10 * *FBDivider) / *RefDivider);
+ return TRUE;
+ } else { /* Should never happen */
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "%s: Failed to get a valid PLL setting for %dkHz\n",
+ __func__, (int) PixelClock);
+ return FALSE;
+ }
+}
+
+void
+atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ int sclock = mode->Clock;
+ uint16_t ref_div = 0, fb_div = 0;
+ uint8_t post_div = 0;
+ int major, minor;
+ SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
+ void *ptr;
+ AtomBiosArgRec data;
+ unsigned char *space;
- RADEONSavePtr save = &info->ModeReg;
++ RADEONSavePtr save = info->ModeReg;
+
+ if (IS_AVIVO_VARIANT) {
+ CARD32 temp;
+ PLLCalculate(crtc->scrn, sclock, &ref_div, &fb_div, &post_div);
+
+ /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
+ if (radeon_crtc->crtc_id == 0) {
+ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ } else {
+ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ }
+ } else {
+ sclock = save->dot_clock_freq * 10;
+ fb_div = save->feedback_div;
+ post_div = save->post_div;
+ ref_div = save->ppll_ref_div;
+ }
+
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) Clock: mode %d, PLL %d\n",
+ radeon_crtc->crtc_id, mode->Clock, sclock);
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) PLL : refdiv %d, fbdiv 0x%X(%d), pdiv %d\n",
+ radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ ErrorF("table is %d %d\n", major, minor);
+ switch(major) {
+ case 1:
+ switch(minor) {
+ case 1:
+ case 2: {
+ spc_param.sPCLKInput.usPixelClock = sclock / 10;
+ spc_param.sPCLKInput.usRefDiv = ref_div;
+ spc_param.sPCLKInput.usFbDiv = fb_div;
+ spc_param.sPCLKInput.ucPostDiv = post_div;
+ spc_param.sPCLKInput.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+ spc_param.sPCLKInput.ucCRTC = radeon_crtc->crtc_id;
+ spc_param.sPCLKInput.ucRefDivSrc = 1;
+
+ ptr = &spc_param;
+ break;
+ }
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = ptr;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC PLL success\n");
+ return;
+ }
+
+ ErrorF("Set CRTC PLL failed\n");
+ return;
+}
+
+void
+atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode,
+ int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
+ Bool tilingOld = info->tilingEnabled;
+
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
+
+ memset(&crtc_timing, 0, sizeof(crtc_timing));
+
+ if (info->allowColorTiling) {
+ info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
+#ifdef XF86DRI
+ if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
+ RADEONSAREAPrivPtr pSAREAPriv;
+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "[drm] failed changing tiling status\n");
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
+ info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
+ }
+#endif
+ }
+
+ crtc_timing.ucCRTC = radeon_crtc->crtc_id;
+ crtc_timing.usH_Total = adjusted_mode->CrtcHTotal;
+ crtc_timing.usH_Disp = adjusted_mode->CrtcHDisplay;
+ crtc_timing.usH_SyncStart = adjusted_mode->CrtcHSyncStart;
+ crtc_timing.usH_SyncWidth = adjusted_mode->CrtcHSyncEnd - adjusted_mode->CrtcHSyncStart;
+
+ crtc_timing.usV_Total = adjusted_mode->CrtcVTotal;
+ crtc_timing.usV_Disp = adjusted_mode->CrtcVDisplay;
+ crtc_timing.usV_SyncStart = adjusted_mode->CrtcVSyncStart;
+ crtc_timing.usV_SyncWidth = adjusted_mode->CrtcVSyncEnd - adjusted_mode->CrtcVSyncStart;
+
+ if (adjusted_mode->Flags & V_NVSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
+
+ if (adjusted_mode->Flags & V_NHSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
+
+ ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
+ adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
+
- RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info);
- RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg);
++ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
++ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+
+ if (IS_AVIVO_VARIANT) {
+ radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_height = pScrn->virtualY;
+ radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4;
+ switch (crtc->scrn->bitsPerPixel) {
+ case 15:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
+ break;
+ case 16:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
+ break;
+ case 24:
+ case 32:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
+ break;
+ default:
+ FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
+ }
+ if (info->tilingEnabled) {
+ radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
+ }
+
+ if (radeon_crtc->crtc_id == 0)
+ OUTREG(AVIVO_D1VGA_CONTROL, 0);
+ else
+ OUTREG(AVIVO_D2VGA_CONTROL, 0);
+
+ /* setup fb format and location
+ */
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
+ (mode->HDisplay << 16) | mode->VDisplay);
+
+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset,
+ radeon_crtc->fb_format);
+
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualX);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualY);
+ OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
+ crtc->scrn->displayWidth);
+
+ OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+
+ }
+
+ atombios_crtc_set_pll(crtc, adjusted_mode);
+
+ atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
+
+ if (info->tilingEnabled != tilingOld) {
+ /* need to redraw front buffer, I guess this can be considered a hack ? */
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE);
+ RADEONChangeSurfaces(pScrn);
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE);
+ /* xf86SetRootClip would do, but can't access that here */
+ }
+
+}
+
diff --cc src/radeon.h
index 2870ef5,5c3bf86..10ecd09
--- a/src/radeon.h
+++ b/src/radeon.h
@@@ -200,271 -200,8 +200,6 @@@ typedef struct
CARD16 rr4_offset;
} RADEONBIOSInitTable;
- struct avivo_pll_state {
- CARD32 ref_div_src;
- CARD32 ref_div;
- CARD32 fb_div;
- CARD32 post_div_src;
- CARD32 post_div;
- CARD32 ext_ppll_cntl;
- CARD32 pll_cntl;
- CARD32 int_ss_cntl;
- };
--
- struct avivo_crtc_state {
- CARD32 pll_source;
- CARD32 h_total;
- CARD32 h_blank_start_end;
- CARD32 h_sync_a;
- CARD32 h_sync_a_cntl;
- CARD32 h_sync_b;
- CARD32 h_sync_b_cntl;
- CARD32 v_total;
- CARD32 v_blank_start_end;
- CARD32 v_sync_a;
- CARD32 v_sync_a_cntl;
- CARD32 v_sync_b;
- CARD32 v_sync_b_cntl;
- CARD32 control;
- CARD32 blank_control;
- CARD32 interlace_control;
- CARD32 stereo_control;
- CARD32 cursor_control;
- };
--
- struct avivo_grph_state {
- CARD32 enable;
- CARD32 control;
- CARD32 prim_surf_addr;
- CARD32 sec_surf_addr;
- CARD32 pitch;
- CARD32 x_offset;
- CARD32 y_offset;
- CARD32 x_start;
- CARD32 y_start;
- CARD32 x_end;
- CARD32 y_end;
-
- CARD32 viewport_start;
- CARD32 viewport_size;
- CARD32 scl_enable;
- };
-
- struct avivo_dac_state {
- CARD32 enable;
- CARD32 source_select;
- CARD32 force_output_cntl;
- CARD32 powerdown;
- };
-
- struct avivo_dig_state {
- CARD32 cntl;
- CARD32 bit_depth_cntl;
- CARD32 data_sync;
- CARD32 transmitter_enable;
- CARD32 transmitter_cntl;
- CARD32 source_select;
- };
-
- struct avivo_state
- {
- CARD32 hdp_fb_location;
- CARD32 mc_memory_map;
- CARD32 vga_memory_base;
- CARD32 vga_fb_start;
-
- CARD32 vga1_cntl;
- CARD32 vga2_cntl;
-
- CARD32 crtc_master_en;
- CARD32 crtc_tv_control;
-
- CARD32 lvtma_pwrseq_cntl;
- CARD32 lvtma_pwrseq_state;
-
- struct avivo_pll_state pll1;
- struct avivo_pll_state pll2;
-
- struct avivo_crtc_state crtc1;
- struct avivo_crtc_state crtc2;
-
- struct avivo_grph_state grph1;
- struct avivo_grph_state grph2;
-
- struct avivo_dac_state daca;
- struct avivo_dac_state dacb;
-
- struct avivo_dig_state tmds1;
- struct avivo_dig_state tmds2;
-
- };
-
- typedef struct {
- struct avivo_state avivo;
- /* Common registers */
- CARD32 ovr_clr;
- CARD32 ovr_wid_left_right;
- CARD32 ovr_wid_top_bottom;
- CARD32 ov0_scale_cntl;
- CARD32 mpp_tb_config;
- CARD32 mpp_gp_config;
- CARD32 subpic_cntl;
- CARD32 viph_control;
- CARD32 i2c_cntl_1;
- CARD32 gen_int_cntl;
- CARD32 cap0_trig_cntl;
- CARD32 cap1_trig_cntl;
- CARD32 bus_cntl;
- CARD32 bios_4_scratch;
- CARD32 bios_5_scratch;
- CARD32 bios_6_scratch;
- CARD32 surface_cntl;
- CARD32 surfaces[8][3];
- CARD32 mc_agp_location;
- CARD32 mc_agp_location_hi;
- CARD32 mc_fb_location;
- CARD32 display_base_addr;
- CARD32 display2_base_addr;
- CARD32 ov0_base_addr;
-
- /* Other registers to save for VT switches */
- CARD32 dp_datatype;
- CARD32 rbbm_soft_reset;
- CARD32 clock_cntl_index;
- CARD32 amcgpio_en_reg;
- CARD32 amcgpio_mask;
-
- /* CRTC registers */
- CARD32 crtc_gen_cntl;
- CARD32 crtc_ext_cntl;
- CARD32 dac_cntl;
- CARD32 crtc_h_total_disp;
- CARD32 crtc_h_sync_strt_wid;
- CARD32 crtc_v_total_disp;
- CARD32 crtc_v_sync_strt_wid;
- CARD32 crtc_offset;
- CARD32 crtc_offset_cntl;
- CARD32 crtc_pitch;
- CARD32 disp_merge_cntl;
- CARD32 grph_buffer_cntl;
- CARD32 crtc_more_cntl;
- CARD32 crtc_tile_x0_y0;
-
- /* CRTC2 registers */
- CARD32 crtc2_gen_cntl;
- CARD32 dac_macro_cntl;
- CARD32 dac2_cntl;
- CARD32 disp_output_cntl;
- CARD32 disp_tv_out_cntl;
- CARD32 disp_hw_debug;
- CARD32 disp2_merge_cntl;
- CARD32 grph2_buffer_cntl;
- CARD32 crtc2_h_total_disp;
- CARD32 crtc2_h_sync_strt_wid;
- CARD32 crtc2_v_total_disp;
- CARD32 crtc2_v_sync_strt_wid;
- CARD32 crtc2_offset;
- CARD32 crtc2_offset_cntl;
- CARD32 crtc2_pitch;
- CARD32 crtc2_tile_x0_y0;
-
- /* Flat panel registers */
- CARD32 fp_crtc_h_total_disp;
- CARD32 fp_crtc_v_total_disp;
- CARD32 fp_gen_cntl;
- CARD32 fp2_gen_cntl;
- CARD32 fp_h_sync_strt_wid;
- CARD32 fp_h2_sync_strt_wid;
- CARD32 fp_horz_stretch;
- CARD32 fp_panel_cntl;
- CARD32 fp_v_sync_strt_wid;
- CARD32 fp_v2_sync_strt_wid;
- CARD32 fp_vert_stretch;
- CARD32 lvds_gen_cntl;
- CARD32 lvds_pll_cntl;
- CARD32 tmds_pll_cntl;
- CARD32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- CARD32 dot_clock_freq;
- CARD32 pll_output_freq;
- int feedback_div;
- int post_div;
-
- /* PLL registers */
- unsigned ppll_ref_div;
- unsigned ppll_div_3;
- CARD32 htotal_cntl;
- CARD32 vclk_ecp_cntl;
-
- /* Computed values for PLL2 */
- CARD32 dot_clock_freq_2;
- CARD32 pll_output_freq_2;
- int feedback_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- CARD32 p2pll_ref_div;
- CARD32 p2pll_div_0;
- CARD32 htotal_cntl2;
- CARD32 pixclks_cntl;
-
- /* Pallet */
- Bool palette_valid;
- CARD32 palette[256];
- CARD32 palette2[256];
-
- CARD32 rs480_unk_e30;
- CARD32 rs480_unk_e34;
- CARD32 rs480_unk_e38;
- CARD32 rs480_unk_e3c;
-
- /* TV out registers */
- CARD32 tv_master_cntl;
- CARD32 tv_htotal;
- CARD32 tv_hsize;
- CARD32 tv_hdisp;
- CARD32 tv_hstart;
- CARD32 tv_vtotal;
- CARD32 tv_vdisp;
- CARD32 tv_timing_cntl;
- CARD32 tv_vscaler_cntl1;
- CARD32 tv_vscaler_cntl2;
- CARD32 tv_sync_size;
- CARD32 tv_vrestart;
- CARD32 tv_hrestart;
- CARD32 tv_frestart;
- CARD32 tv_ftotal;
- CARD32 tv_clock_sel_cntl;
- CARD32 tv_clkout_cntl;
- CARD32 tv_data_delay_a;
- CARD32 tv_data_delay_b;
- CARD32 tv_dac_cntl;
- CARD32 tv_pll_cntl;
- CARD32 tv_pll_cntl1;
- CARD32 tv_pll_fine_cntl;
- CARD32 tv_modulator_cntl1;
- CARD32 tv_modulator_cntl2;
- CARD32 tv_frame_lock_cntl;
- CARD32 tv_pre_dac_mux_cntl;
- CARD32 tv_rgb_cntl;
- CARD32 tv_y_saw_tooth_cntl;
- CARD32 tv_y_rise_cntl;
- CARD32 tv_y_fall_cntl;
- CARD32 tv_uv_adr;
- CARD32 tv_upsamp_and_gain_cntl;
- CARD32 tv_gain_limit_settings;
- CARD32 tv_linear_gain_settings;
- CARD32 tv_crc_cntl;
- CARD32 tv_sync_cntl;
- CARD32 gpiopad_a;
- CARD32 pll_test_cntl;
-
- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
-
- } RADEONSaveRec, *RADEONSavePtr;
-
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
diff --cc src/radeon_crtc.c
index e288352,f28bdf7..1ea6d2b
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@@ -905,21 -891,15 +905,21 @@@ legacy_crtc_mode_set(xf86CrtcPtr crtc,
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("restore crtc1\n");
- RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreCrtcRegisters(pScrn, info->ModeReg);
ErrorF("restore pll1\n");
- RADEONRestorePLLRegisters(pScrn, info->ModeReg);
+ /*if (info->IsAtomBios)
+ atombios_crtc_set_pll(crtc, adjusted_mode);
+ else*/
- RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
++ RADEONRestorePLLRegisters(pScrn, info->ModeReg);
break;
case 1:
ErrorF("restore crtc2\n");
- RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg);
+ RADEONRestoreCrtc2Registers(pScrn, info->ModeReg);
ErrorF("restore pll2\n");
- RADEONRestorePLL2Registers(pScrn, info->ModeReg);
+ /*if (info->IsAtomBios)
- atombios_crtc_set_pll(crtc, adjusted_mode);
++ atombios_crtc_set_pll(crtc, adjusted_mode);
+ else*/
- RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
++ RADEONRestorePLL2Registers(pScrn, info->ModeReg);
break;
}
@@@ -1261,39 -1207,41 +1261,43 @@@ Bool RADEONAllocateControllers(ScrnInfo
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- if (pRADEONEnt->Controller[0])
- return TRUE;
-
- pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[0])
- return FALSE;
-
- pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[0])
- return FALSE;
-
- pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
- pRADEONEnt->Controller[0]->crtc_id = 0;
- pRADEONEnt->Controller[0]->crtc_offset = 0;
-
- if (!pRADEONEnt->HasCRTC2)
- return TRUE;
+ if (mask & 1) {
+ if (pRADEONEnt->Controller[0])
+ return TRUE;
+
+ pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
+ if (!pRADEONEnt->pCrtc[0])
+ return FALSE;
+
+ pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
+ if (!pRADEONEnt->Controller[0])
+ return FALSE;
+
+ pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
+ pRADEONEnt->Controller[0]->crtc_id = 0;
-
++ pRADEONEnt->Controller[0]->crtc_offset = 0;
+ }
- pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[1])
- return FALSE;
+ if (mask & 2) {
+ if (!pRADEONEnt->HasCRTC2)
+ return TRUE;
+
+ pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
+ if (!pRADEONEnt->pCrtc[1])
+ return FALSE;
+
+ pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
+ if (!pRADEONEnt->Controller[1])
+ {
+ xfree(pRADEONEnt->Controller[0]);
+ return FALSE;
+ }
- pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[1])
- {
- xfree(pRADEONEnt->Controller[0]);
- return FALSE;
+ pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
+ pRADEONEnt->Controller[1]->crtc_id = 1;
++ pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
}
+
- pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
- pRADEONEnt->Controller[1]->crtc_id = 1;
- pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
-
return TRUE;
}
diff --cc src/radeon_driver.c
index 74dd2a6,35b9a47..4afbee1
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@@ -2287,9 -2118,10 +2314,13 @@@ static void RADEONPreInitColorTiling(Sc
if (!info->allowColorTiling)
return;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ info->allowColorTiling = FALSE;
+
+ /* for zaphod disable tiling for now */
+ if (info->IsPrimary || info->IsSecondary)
+ info->allowColorTiling = FALSE;
+
#ifdef XF86DRI
if (info->directRenderingEnabled &&
info->pKernelDRMVersion->version_minor < 14) {
@@@ -3813,11 -3710,9 +3912,13 @@@ void RADEONRestoreMemMapRegisters(ScrnI
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
int timeout;
+ CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi;
+
+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc,
+ &mc_agp_loc, &mc_agp_loc_hi);
+ if (info->IsSecondary)
+ return;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONRestoreMemMapRegisters() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@@ -4024,36 -3863,36 +4125,39 @@@
static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 fb, agp;
+ CARD32 fb, agp, agp_hi;
+ int changed;
+ if (info->IsSecondary)
+ return;
+
- fb = INREG(RADEON_MC_FB_LOCATION);
- agp = INREG(RADEON_MC_AGP_LOCATION);
-
- if (fb != info->mc_fb_location || agp != info->mc_agp_location) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "DRI init changed memory map, adjusting ...\n");
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_FB_LOCATION was: 0x%08x is: 0x%08x\n",
- (unsigned)info->mc_fb_location, (unsigned)fb);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_AGP_LOCATION was: 0x%08x is: 0x%08x\n",
- (unsigned)info->mc_agp_location, (unsigned)agp);
- info->mc_fb_location = fb;
- info->mc_agp_location = agp;
- info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
- info->dst_pitch_offset =
- (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
- << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
-
+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi);
+
+ if (fb != info->mc_fb_location || agp != info->mc_agp_location ||
+ agp_hi || info->mc_agp_location_hi)
+ changed = 1;
- RADEONInitMemMapRegisters(pScrn, save, info);
+ if (changed) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "DRI init changed memory map, adjusting ...\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
+ info->mc_fb_location, fb);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
+ info->mc_agp_location, agp);
+ info->mc_fb_location = fb;
+ info->mc_agp_location = agp;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
+ else
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
- /* Adjust the various offsets */
- RADEONRestoreMemMapRegisters(pScrn, save);
+ info->dst_pitch_offset =
+ (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
+ << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
+ RADEONInitMemMapRegisters(pScrn, save, info);
+ RADEONRestoreMemMapRegisters(pScrn, save);
}
#ifdef USE_EXA
@@@ -5769,17 -5302,14 +5876,18 @@@ void RADEONRestore(ScrnInfoPtr pScrn
RADEONBlank(pScrn);
- OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
- RADEONPllErrataAfterIndex(info);
- OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
- OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
- OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
- OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
+ if (IS_AVIVO_VARIANT) {
+ RADEONRestoreMemMapRegisters(pScrn, restore);
+ avivo_restore(pScrn, restore);
+ } else {
+ OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
+ RADEONPllErrataAfterIndex(info);
+ OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
+ OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
+ OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
+ OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
+ if (!info->IsSecondary) {
RADEONRestoreMemMapRegisters(pScrn, restore);
RADEONRestoreCommonRegisters(pScrn, restore);
@@@ -5798,10 -5328,9 +5906,10 @@@
if (info->InternalTVOut)
RADEONRestoreTVRegisters(pScrn, restore);
-
+ }
- RADEONRestoreSurfaces(pScrn, restore);
+ RADEONRestoreSurfaces(pScrn, restore);
+ }
#if 1
/* Temp fix to "solve" VT switch problems. When switching VTs on
diff --cc src/radeon_output.c
index 15b4ddf,ecff799..85f1156
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@@ -1249,14 -1188,11 +1249,14 @@@ legacy_mode_set(xf86OutputPtr output, D
case MT_DFP:
if (radeon_output->TMDSType == TMDS_INT) {
ErrorF("restore FP\n");
- RADEONRestoreFPRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreFPRegisters(pScrn, info->ModeReg);
} else {
ErrorF("restore FP2\n");
- RADEONRestoreDVOChip(pScrn, output);
+ if (info->IsAtomBios)
+ atombios_external_tmds_setup(output, mode);
+ else
+ RADEONRestoreDVOChip(pScrn, output);
- RADEONRestoreFP2Registers(pScrn, &info->ModeReg);
+ RADEONRestoreFP2Registers(pScrn, info->ModeReg);
}
break;
case MT_STV:
diff --cc src/radeon_probe.h
index d01fd8b,d1096fb..a7d873e
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@@ -232,14 -221,181 +232,287 @@@ typedef struct _RADEONOutputPrivateRec
int SupportedTVStds;
Bool tv_on;
int load_detection;
+
+ char *name;
+ int output_id;
+ int devices;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
++struct avivo_pll_state {
++ CARD32 ref_div_src;
++ CARD32 ref_div;
++ CARD32 fb_div;
++ CARD32 post_div_src;
++ CARD32 post_div;
++ CARD32 ext_ppll_cntl;
++ CARD32 pll_cntl;
++ CARD32 int_ss_cntl;
++};
++
++
++struct avivo_crtc_state {
++ CARD32 pll_source;
++ CARD32 h_total;
++ CARD32 h_blank_start_end;
++ CARD32 h_sync_a;
++ CARD32 h_sync_a_cntl;
++ CARD32 h_sync_b;
++ CARD32 h_sync_b_cntl;
++ CARD32 v_total;
++ CARD32 v_blank_start_end;
++ CARD32 v_sync_a;
++ CARD32 v_sync_a_cntl;
++ CARD32 v_sync_b;
++ CARD32 v_sync_b_cntl;
++ CARD32 control;
++ CARD32 blank_control;
++ CARD32 interlace_control;
++ CARD32 stereo_control;
++ CARD32 cursor_control;
++};
++
++struct avivo_grph_state {
++ CARD32 enable;
++ CARD32 control;
++ CARD32 prim_surf_addr;
++ CARD32 sec_surf_addr;
++ CARD32 pitch;
++ CARD32 x_offset;
++ CARD32 y_offset;
++ CARD32 x_start;
++ CARD32 y_start;
++ CARD32 x_end;
++ CARD32 y_end;
++
++ CARD32 viewport_start;
++ CARD32 viewport_size;
++ CARD32 scl_enable;
++};
++
++struct avivo_dac_state {
++ CARD32 enable;
++ CARD32 source_select;
++ CARD32 force_output_cntl;
++ CARD32 powerdown;
++};
++
++struct avivo_dig_state {
++ CARD32 cntl;
++ CARD32 bit_depth_cntl;
++ CARD32 data_sync;
++ CARD32 transmitter_enable;
++ CARD32 transmitter_cntl;
++ CARD32 source_select;
++};
++
++struct avivo_state
++{
++ CARD32 hdp_fb_location;
++ CARD32 mc_memory_map;
++ CARD32 vga_memory_base;
++ CARD32 vga_fb_start;
++
++ CARD32 vga1_cntl;
++ CARD32 vga2_cntl;
++
++ CARD32 crtc_master_en;
++ CARD32 crtc_tv_control;
++
++ CARD32 lvtma_pwrseq_cntl;
++ CARD32 lvtma_pwrseq_state;
++
++ struct avivo_pll_state pll1;
++ struct avivo_pll_state pll2;
++
++ struct avivo_crtc_state crtc1;
++ struct avivo_crtc_state crtc2;
++
++ struct avivo_grph_state grph1;
++ struct avivo_grph_state grph2;
++
++ struct avivo_dac_state daca;
++ struct avivo_dac_state dacb;
++
++ struct avivo_dig_state tmds1;
++ struct avivo_dig_state tmds2;
++
++};
+
+ /*
+ * Maximum length of horizontal/vertical code timing tables for state storage
+ */
+ #define MAX_H_CODE_TIMING_LEN 32
+ #define MAX_V_CODE_TIMING_LEN 32
+
+ typedef struct {
++ struct avivo_state avivo;
++
+ /* Common registers */
+ CARD32 ovr_clr;
+ CARD32 ovr_wid_left_right;
+ CARD32 ovr_wid_top_bottom;
+ CARD32 ov0_scale_cntl;
+ CARD32 mpp_tb_config;
+ CARD32 mpp_gp_config;
+ CARD32 subpic_cntl;
+ CARD32 viph_control;
+ CARD32 i2c_cntl_1;
+ CARD32 gen_int_cntl;
+ CARD32 cap0_trig_cntl;
+ CARD32 cap1_trig_cntl;
+ CARD32 bus_cntl;
+ CARD32 bios_4_scratch;
+ CARD32 bios_5_scratch;
+ CARD32 bios_6_scratch;
+ CARD32 surface_cntl;
+ CARD32 surfaces[8][3];
+ CARD32 mc_agp_location;
++ CARD32 mc_agp_location_hi;
+ CARD32 mc_fb_location;
+ CARD32 display_base_addr;
+ CARD32 display2_base_addr;
+ CARD32 ov0_base_addr;
+
+ /* Other registers to save for VT switches */
+ CARD32 dp_datatype;
+ CARD32 rbbm_soft_reset;
+ CARD32 clock_cntl_index;
+ CARD32 amcgpio_en_reg;
+ CARD32 amcgpio_mask;
+
+ /* CRTC registers */
+ CARD32 crtc_gen_cntl;
+ CARD32 crtc_ext_cntl;
+ CARD32 dac_cntl;
+ CARD32 crtc_h_total_disp;
+ CARD32 crtc_h_sync_strt_wid;
+ CARD32 crtc_v_total_disp;
+ CARD32 crtc_v_sync_strt_wid;
+ CARD32 crtc_offset;
+ CARD32 crtc_offset_cntl;
+ CARD32 crtc_pitch;
+ CARD32 disp_merge_cntl;
+ CARD32 grph_buffer_cntl;
+ CARD32 crtc_more_cntl;
+ CARD32 crtc_tile_x0_y0;
+
+ /* CRTC2 registers */
+ CARD32 crtc2_gen_cntl;
+ CARD32 dac_macro_cntl;
+ CARD32 dac2_cntl;
+ CARD32 disp_output_cntl;
+ CARD32 disp_tv_out_cntl;
+ CARD32 disp_hw_debug;
+ CARD32 disp2_merge_cntl;
+ CARD32 grph2_buffer_cntl;
+ CARD32 crtc2_h_total_disp;
+ CARD32 crtc2_h_sync_strt_wid;
+ CARD32 crtc2_v_total_disp;
+ CARD32 crtc2_v_sync_strt_wid;
+ CARD32 crtc2_offset;
+ CARD32 crtc2_offset_cntl;
+ CARD32 crtc2_pitch;
+ CARD32 crtc2_tile_x0_y0;
+
+ /* Flat panel registers */
+ CARD32 fp_crtc_h_total_disp;
+ CARD32 fp_crtc_v_total_disp;
+ CARD32 fp_gen_cntl;
+ CARD32 fp2_gen_cntl;
+ CARD32 fp_h_sync_strt_wid;
+ CARD32 fp_h2_sync_strt_wid;
+ CARD32 fp_horz_stretch;
+ CARD32 fp_panel_cntl;
+ CARD32 fp_v_sync_strt_wid;
+ CARD32 fp_v2_sync_strt_wid;
+ CARD32 fp_vert_stretch;
+ CARD32 lvds_gen_cntl;
+ CARD32 lvds_pll_cntl;
+ CARD32 tmds_pll_cntl;
+ CARD32 tmds_transmitter_cntl;
+
+ /* Computed values for PLL */
+ CARD32 dot_clock_freq;
+ CARD32 pll_output_freq;
+ int feedback_div;
+ int post_div;
+
+ /* PLL registers */
+ unsigned ppll_ref_div;
+ unsigned ppll_div_3;
+ CARD32 htotal_cntl;
+ CARD32 vclk_ecp_cntl;
+
+ /* Computed values for PLL2 */
+ CARD32 dot_clock_freq_2;
+ CARD32 pll_output_freq_2;
+ int feedback_div_2;
+ int post_div_2;
+
+ /* PLL2 registers */
+ CARD32 p2pll_ref_div;
+ CARD32 p2pll_div_0;
+ CARD32 htotal_cntl2;
+ CARD32 pixclks_cntl;
+
+ /* Pallet */
+ Bool palette_valid;
+ CARD32 palette[256];
+ CARD32 palette2[256];
+
+ CARD32 rs480_unk_e30;
+ CARD32 rs480_unk_e34;
+ CARD32 rs480_unk_e38;
+ CARD32 rs480_unk_e3c;
+
+ /* TV out registers */
+ CARD32 tv_master_cntl;
+ CARD32 tv_htotal;
+ CARD32 tv_hsize;
+ CARD32 tv_hdisp;
+ CARD32 tv_hstart;
+ CARD32 tv_vtotal;
+ CARD32 tv_vdisp;
+ CARD32 tv_timing_cntl;
+ CARD32 tv_vscaler_cntl1;
+ CARD32 tv_vscaler_cntl2;
+ CARD32 tv_sync_size;
+ CARD32 tv_vrestart;
+ CARD32 tv_hrestart;
+ CARD32 tv_frestart;
+ CARD32 tv_ftotal;
+ CARD32 tv_clock_sel_cntl;
+ CARD32 tv_clkout_cntl;
+ CARD32 tv_data_delay_a;
+ CARD32 tv_data_delay_b;
+ CARD32 tv_dac_cntl;
+ CARD32 tv_pll_cntl;
+ CARD32 tv_pll_cntl1;
+ CARD32 tv_pll_fine_cntl;
+ CARD32 tv_modulator_cntl1;
+ CARD32 tv_modulator_cntl2;
+ CARD32 tv_frame_lock_cntl;
+ CARD32 tv_pre_dac_mux_cntl;
+ CARD32 tv_rgb_cntl;
+ CARD32 tv_y_saw_tooth_cntl;
+ CARD32 tv_y_rise_cntl;
+ CARD32 tv_y_fall_cntl;
+ CARD32 tv_uv_adr;
+ CARD32 tv_upsamp_and_gain_cntl;
+ CARD32 tv_gain_limit_settings;
+ CARD32 tv_linear_gain_settings;
+ CARD32 tv_crc_cntl;
+ CARD32 tv_sync_cntl;
+ CARD32 gpiopad_a;
+ CARD32 pll_test_cntl;
+
+ CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
+ CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
+
+ } RADEONSaveRec, *RADEONSavePtr;
+
#define RADEON_MAX_CRTC 2
-#define RADEON_MAX_BIOS_CONNECTOR 8
+#define RADEON_MAX_BIOS_CONNECTOR 16
typedef struct
{
commit 6451ea2dcc4fac762442f699935864f4a8d445f7
Merge: 0d89556... 5896ca4...
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:08:42 2007 +1000
Merge branch 'master' into atombios-support
commit cc167b9bb7f1c3b8579e51e7bc2fca2f8eba6bd1
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Dec 7 15:41:36 2007 +1000
disable tiling for zaphod heads
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 0632fd3..35b9a47 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2118,6 +2118,10 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn)
if (!info->allowColorTiling)
return;
+ /* for zaphod disable tiling for now */
+ if (info->IsPrimary || info->IsSecondary)
+ info->allowColorTiling = FALSE;
+
#ifdef XF86DRI
if (info->directRenderingEnabled &&
info->pKernelDRMVersion->version_minor < 14) {
commit 2ce8d192533a8c795714c5a9fb308ec74db40287
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Dec 7 15:35:21 2007 +1000
don't add fboffset to info->FB it already is mapped at the offset
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index b8cfffd..5004b64 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -189,7 +189,7 @@ radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
+ CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset);
int pixel, i;
CURSOR_SWAPPING_DECL_MMIO
@@ -231,7 +231,7 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
+ CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset);
RADEONCTRACE(("RADEONLoadCursorARGB\n"));
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 6db1d96..0632fd3 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -3474,7 +3474,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
"Initializing fb layer\n");
/* Init fb layer */
- if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset,
+ if (!fbScreenInit(pScreen, info->FB,
pScrn->virtualX, pScrn->virtualY,
pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
pScrn->bitsPerPixel))
commit 0dcd926d3092100854b3e362d6659d4950508aeb
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Dec 7 14:45:04 2007 +1000
radeon: bring back zaphod all is forgiven.
You've whined, you've cried, you've nagged, and you're guilt trippin has
made me do it... It actually wasn't as hard as I thought it would be.
Still not perfect, couple of things to fix yet
diff --git a/src/radeon.h b/src/radeon.h
index 529374e..5c3bf86 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -681,6 +681,10 @@ typedef struct {
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
+
+
+ Bool IsSecondary;
+ Bool IsPrimary;
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
@@ -801,7 +805,7 @@ extern void RADEONBlank(ScrnInfoPtr pScrn);
extern void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
int PowerManagementMode,
int flags);
-extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn);
+extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn);
extern int RADEONValidateMergeModes(ScrnInfoPtr pScrn);
extern int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName,
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 718073c..f28bdf7 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -1203,40 +1203,45 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = {
.destroy = NULL, /* XXX */
};
-Bool RADEONAllocateControllers(ScrnInfoPtr pScrn)
+Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- if (pRADEONEnt->Controller[0])
- return TRUE;
+ if (mask & 1) {
+ if (pRADEONEnt->Controller[0])
+ return TRUE;
+
+ pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
+ if (!pRADEONEnt->pCrtc[0])
+ return FALSE;
- pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[0])
- return FALSE;
+ pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
+ if (!pRADEONEnt->Controller[0])
+ return FALSE;
- pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[0])
- return FALSE;
+ pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
+ pRADEONEnt->Controller[0]->crtc_id = 0;
- pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
- pRADEONEnt->Controller[0]->crtc_id = 0;
-
- if (!pRADEONEnt->HasCRTC2)
- return TRUE;
+ }
- pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[1])
- return FALSE;
+ if (mask & 2) {
+ if (!pRADEONEnt->HasCRTC2)
+ return TRUE;
+
+ pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
+ if (!pRADEONEnt->pCrtc[1])
+ return FALSE;
+
+ pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
+ if (!pRADEONEnt->Controller[1])
+ {
+ xfree(pRADEONEnt->Controller[0]);
+ return FALSE;
+ }
- pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[1])
- {
- xfree(pRADEONEnt->Controller[0]);
- return FALSE;
+ pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
+ pRADEONEnt->Controller[1]->crtc_id = 1;
}
-
- pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
- pRADEONEnt->Controller[1]->crtc_id = 1;
return TRUE;
}
diff --git a/src/radeon_display.c b/src/radeon_display.c
index f678dda..07d633f 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -318,7 +318,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
{
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONSavePtr save = &info->ModeReg;
+ RADEONSavePtr save = info->ModeReg;
unsigned char * RADEONMMIO = info->MMIO;
unsigned long tmp;
RADEONOutputPrivatePtr radeon_output;
@@ -773,7 +773,10 @@ void RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
DisplayModePtr mode1, mode2;
int pixel_bytes2 = 0;
- mode1 = info->CurrentLayout.mode;
+ if (info->IsPrimary || info->IsSecondary)
+ mode1 = &xf86_config->crtc[0]->mode;
+ else
+ mode1 = info->CurrentLayout.mode;
mode2 = NULL;
pixel_bytes2 = info->CurrentLayout.pixel_bytes;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index f01c9aa..6db1d96 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1446,6 +1446,21 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, from,
"Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR");
+ if (info->IsPrimary) {
+ pScrn->videoRam /= 2;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Using %dk of videoram for primary head\n",
+ pScrn->videoRam);
+ }
+
+ if (info->IsSecondary) {
+ pScrn->videoRam /= 2;
+ info->LinearAddr += pScrn->videoRam * 1024;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Using %dk of videoram for secondary head\n",
+ pScrn->videoRam);
+ }
+
pScrn->videoRam &= ~1023;
info->FbMapSize = pScrn->videoRam * 1024;
@@ -1881,6 +1896,18 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->pLibDRMVersion = NULL;
info->pKernelDRMVersion = NULL;
+ if (xf86IsEntityShared(info->pEnt->index)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Direct Rendering Disabled -- "
+ "Dual-head configuration is not working with "
+ "DRI at present.\n"
+ "Please use the radeon MergedFB option if you "
+ "want Dual-head with DRI.\n");
+ return FALSE;
+ }
+ if (info->IsSecondary)
+ return FALSE;
+
if (info->Chipset == PCI_CHIP_RN50_515E ||
info->Chipset == PCI_CHIP_RN50_5969 ||
info->Chipset == PCI_CHIP_RC410_5A61 ||
@@ -2311,12 +2338,41 @@ static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
#endif
}
+static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn)
+{
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
+ int i;
+
+ if (info->IsPrimary) {
+ while(config->num_output > 1) {
+ xf86OutputDestroy(config->output[1]);
+ }
+ } else {
+ xf86OutputDestroy(config->output[0]);
+ while(config->num_output > 1) {
+ xf86OutputDestroy(config->output[1]);
+ }
+ }
+}
+
static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
{
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ RADEONInfoPtr info = RADEONPTR(pScrn);
int i;
+ int mask;
- if (!RADEONAllocateControllers(pScrn))
+ if (!info->IsPrimary && !info->IsSecondary)
+ mask = 3;
+ else if (info->IsPrimary)
+ mask = 1;
+ else
+ mask = 2;
+
+ if (!RADEONAllocateControllers(pScrn, mask))
return FALSE;
RADEONGetClockInfo(pScrn);
@@ -2324,6 +2380,11 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
if (!RADEONSetupConnectors(pScrn)) {
return FALSE;
}
+
+ if (info->IsPrimary || info->IsSecondary) {
+ /* fixup outputs for zaphod */
+ RADEONFixZaphodOutputs(pScrn);
+ }
RADEONPrintPortMap(pScrn);
@@ -2382,6 +2443,9 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info = RADEONPTR(pScrn);
info->MMIO = NULL;
+ info->IsSecondary = FALSE;
+ info->IsPrimary = FALSE;
+
info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
if (info->pEnt->location.type != BUS_PCI) goto fail;
@@ -2389,8 +2453,28 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
getRADEONEntityIndex());
pRADEONEnt = pPriv->ptr;
- info->SavedReg = &pRADEONEnt->SavedReg;
- info->ModeReg = &pRADEONEnt->ModeReg;
+ if(xf86IsEntityShared(pScrn->entityList[0]))
+ {
+ if(xf86IsPrimInitDone(pScrn->entityList[0]))
+ {
+ info->IsSecondary = TRUE;
+ pRADEONEnt->pSecondaryScrn = pScrn;
+ info->SavedReg = &pRADEONEnt->SavedReg;
+ info->ModeReg = &pRADEONEnt->ModeReg;
+ }
+ else
+ {
+ info->IsPrimary = TRUE;
+ xf86SetPrimInitDone(pScrn->entityList[0]);
+ pRADEONEnt->pPrimaryScrn = pScrn;
+ pRADEONEnt->HasSecondary = FALSE;
+ info->SavedReg = &pRADEONEnt->SavedReg;
+ info->ModeReg = &pRADEONEnt->ModeReg;
+ }
+ } else {
+ info->SavedReg = &pRADEONEnt->SavedReg;
+ info->ModeReg = &pRADEONEnt->ModeReg;
+ }
info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo),
@@ -2739,10 +2823,11 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
/* Make the change through RandR */
#ifdef RANDR_12_INTERFACE
- RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b);
-#else
- crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256);
+ if (crtc->randr_crtc)
+ RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b);
+ else
#endif
+ crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256);
}
}
@@ -3153,15 +3238,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
char* s;
#endif
-#ifdef XF86DRI
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONScreenInit %lx %ld %d\n",
- pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset);
-#else
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONScreenInit %lx %ld\n",
- pScrn->memPhysBase, pScrn->fbOffset);
-#endif
info->accelOn = FALSE;
#ifdef USE_XAA
@@ -3171,6 +3247,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
pScrn->fbOffset = info->frontOffset;
#endif
+ if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024;
+#ifdef XF86DRI
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "RADEONScreenInit %lx %ld %d\n",
+ pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset);
+#else
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONScreenInit %lx %ld\n",
+ pScrn->memPhysBase, pScrn->fbOffset);
+#endif
if (!RADEONMapMem(pScrn)) return FALSE;
#ifdef XF86DRI
@@ -3621,6 +3707,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
unsigned char *RADEONMMIO = info->MMIO;
int timeout;
+ if (info->IsSecondary)
+ return;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONRestoreMemMapRegisters() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -3774,6 +3862,9 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
unsigned char *RADEONMMIO = info->MMIO;
CARD32 fb, agp;
+ if (info->IsSecondary)
+ return;
+
fb = INREG(RADEON_MC_FB_LOCATION);
agp = INREG(RADEON_MC_AGP_LOCATION);
@@ -3832,6 +3923,9 @@ void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
+ if (info->IsSecondary)
+ return;
+
OUTREG(RADEON_OVR_CLR, restore->ovr_clr);
OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
@@ -5211,26 +5305,28 @@ void RADEONRestore(ScrnInfoPtr pScrn)
OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
- RADEONRestoreMemMapRegisters(pScrn, restore);
- RADEONRestoreCommonRegisters(pScrn, restore);
+ if (!info->IsSecondary) {
+ RADEONRestoreMemMapRegisters(pScrn, restore);
+ RADEONRestoreCommonRegisters(pScrn, restore);
- if (pRADEONEnt->HasCRTC2) {
- RADEONRestoreCrtc2Registers(pScrn, restore);
- RADEONRestorePLL2Registers(pScrn, restore);
- }
+ if (pRADEONEnt->HasCRTC2) {
+ RADEONRestoreCrtc2Registers(pScrn, restore);
+ RADEONRestorePLL2Registers(pScrn, restore);
+ }
- RADEONRestoreBIOSRegisters(pScrn, restore);
- RADEONRestoreCrtcRegisters(pScrn, restore);
- RADEONRestorePLLRegisters(pScrn, restore);
- RADEONRestoreRMXRegisters(pScrn, restore);
- RADEONRestoreFPRegisters(pScrn, restore);
- RADEONRestoreFP2Registers(pScrn, restore);
- RADEONRestoreLVDSRegisters(pScrn, restore);
+ RADEONRestoreBIOSRegisters(pScrn, restore);
+ RADEONRestoreCrtcRegisters(pScrn, restore);
+ RADEONRestorePLLRegisters(pScrn, restore);
+ RADEONRestoreRMXRegisters(pScrn, restore);
+ RADEONRestoreFPRegisters(pScrn, restore);
+ RADEONRestoreFP2Registers(pScrn, restore);
+ RADEONRestoreLVDSRegisters(pScrn, restore);
- if (info->InternalTVOut)
- RADEONRestoreTVRegisters(pScrn, restore);
+ if (info->InternalTVOut)
+ RADEONRestoreTVRegisters(pScrn, restore);
- RADEONRestoreSurfaces(pScrn, restore);
+ RADEONRestoreSurfaces(pScrn, restore);
+ }
#if 1
/* Temp fix to "solve" VT switch problems. When switching VTs on
@@ -5258,8 +5354,8 @@ void RADEONRestore(ScrnInfoPtr pScrn)
#endif
/* need to make sure we don't enable a crtc by accident or we may get a hang */
- if (pRADEONEnt->HasCRTC2) {
- if (info->crtc2_on) {
+ if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) {
+ if (info->crtc2_on && xf86_config->num_crtc > 1) {
crtc = xf86_config->crtc[1];
crtc->funcs->dpms(crtc, DPMSModeOn);
}
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index baea47c..e0a77e6 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -175,7 +175,7 @@ RADEONProbe(DriverPtr drv, int flags)
DevUnion *pPriv;
RADEONEntPtr pRADEONEnt;
- /*xf86SetEntitySharable(usedChips[i]);*/
+ xf86SetEntitySharable(usedChips[i]);
if (gRADEONEntityIndex == -1)
gRADEONEntityIndex = xf86AllocateEntityPrivateIndex();
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index cdefdf5..d1096fb 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -413,6 +413,9 @@ typedef struct
xf86CrtcPtr pCrtc[RADEON_MAX_CRTC];
RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC];
+ ScrnInfoPtr pSecondaryScrn;
+ ScrnInfoPtr pPrimaryScrn;
+
RADEONSaveRec ModeReg; /* Current mode */
RADEONSaveRec SavedReg; /* Original (text) mode */
commit bb5ede557bf32a42eef158ff0fbcfe1c6ede098a
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Dec 7 14:30:32 2007 +1000
radeon: move savedreg/modereg into entity instead of info
diff --git a/src/radeon.h b/src/radeon.h
index fe491e8..529374e 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -200,169 +200,7 @@ typedef struct {
CARD16 rr4_offset;
} RADEONBIOSInitTable;
-typedef struct {
- /* Common registers */
- CARD32 ovr_clr;
- CARD32 ovr_wid_left_right;
- CARD32 ovr_wid_top_bottom;
- CARD32 ov0_scale_cntl;
- CARD32 mpp_tb_config;
- CARD32 mpp_gp_config;
- CARD32 subpic_cntl;
- CARD32 viph_control;
- CARD32 i2c_cntl_1;
- CARD32 gen_int_cntl;
- CARD32 cap0_trig_cntl;
- CARD32 cap1_trig_cntl;
- CARD32 bus_cntl;
- CARD32 bios_4_scratch;
- CARD32 bios_5_scratch;
- CARD32 bios_6_scratch;
- CARD32 surface_cntl;
- CARD32 surfaces[8][3];
- CARD32 mc_agp_location;
- CARD32 mc_fb_location;
- CARD32 display_base_addr;
- CARD32 display2_base_addr;
- CARD32 ov0_base_addr;
-
- /* Other registers to save for VT switches */
- CARD32 dp_datatype;
- CARD32 rbbm_soft_reset;
- CARD32 clock_cntl_index;
- CARD32 amcgpio_en_reg;
- CARD32 amcgpio_mask;
-
- /* CRTC registers */
- CARD32 crtc_gen_cntl;
- CARD32 crtc_ext_cntl;
- CARD32 dac_cntl;
- CARD32 crtc_h_total_disp;
- CARD32 crtc_h_sync_strt_wid;
- CARD32 crtc_v_total_disp;
- CARD32 crtc_v_sync_strt_wid;
- CARD32 crtc_offset;
- CARD32 crtc_offset_cntl;
- CARD32 crtc_pitch;
- CARD32 disp_merge_cntl;
- CARD32 grph_buffer_cntl;
- CARD32 crtc_more_cntl;
- CARD32 crtc_tile_x0_y0;
-
- /* CRTC2 registers */
- CARD32 crtc2_gen_cntl;
- CARD32 dac_macro_cntl;
- CARD32 dac2_cntl;
- CARD32 disp_output_cntl;
- CARD32 disp_tv_out_cntl;
- CARD32 disp_hw_debug;
- CARD32 disp2_merge_cntl;
- CARD32 grph2_buffer_cntl;
- CARD32 crtc2_h_total_disp;
- CARD32 crtc2_h_sync_strt_wid;
- CARD32 crtc2_v_total_disp;
- CARD32 crtc2_v_sync_strt_wid;
- CARD32 crtc2_offset;
- CARD32 crtc2_offset_cntl;
- CARD32 crtc2_pitch;
- CARD32 crtc2_tile_x0_y0;
-
- /* Flat panel registers */
- CARD32 fp_crtc_h_total_disp;
- CARD32 fp_crtc_v_total_disp;
- CARD32 fp_gen_cntl;
- CARD32 fp2_gen_cntl;
- CARD32 fp_h_sync_strt_wid;
- CARD32 fp_h2_sync_strt_wid;
- CARD32 fp_horz_stretch;
- CARD32 fp_panel_cntl;
- CARD32 fp_v_sync_strt_wid;
- CARD32 fp_v2_sync_strt_wid;
- CARD32 fp_vert_stretch;
- CARD32 lvds_gen_cntl;
- CARD32 lvds_pll_cntl;
- CARD32 tmds_pll_cntl;
- CARD32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- CARD32 dot_clock_freq;
- CARD32 pll_output_freq;
- int feedback_div;
- int post_div;
-
- /* PLL registers */
- unsigned ppll_ref_div;
- unsigned ppll_div_3;
- CARD32 htotal_cntl;
- CARD32 vclk_ecp_cntl;
-
- /* Computed values for PLL2 */
- CARD32 dot_clock_freq_2;
- CARD32 pll_output_freq_2;
- int feedback_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- CARD32 p2pll_ref_div;
- CARD32 p2pll_div_0;
- CARD32 htotal_cntl2;
- CARD32 pixclks_cntl;
-
- /* Pallet */
- Bool palette_valid;
- CARD32 palette[256];
- CARD32 palette2[256];
-
- CARD32 rs480_unk_e30;
- CARD32 rs480_unk_e34;
- CARD32 rs480_unk_e38;
- CARD32 rs480_unk_e3c;
-
- /* TV out registers */
- CARD32 tv_master_cntl;
- CARD32 tv_htotal;
- CARD32 tv_hsize;
- CARD32 tv_hdisp;
- CARD32 tv_hstart;
- CARD32 tv_vtotal;
- CARD32 tv_vdisp;
- CARD32 tv_timing_cntl;
- CARD32 tv_vscaler_cntl1;
- CARD32 tv_vscaler_cntl2;
- CARD32 tv_sync_size;
- CARD32 tv_vrestart;
- CARD32 tv_hrestart;
- CARD32 tv_frestart;
- CARD32 tv_ftotal;
- CARD32 tv_clock_sel_cntl;
- CARD32 tv_clkout_cntl;
- CARD32 tv_data_delay_a;
- CARD32 tv_data_delay_b;
- CARD32 tv_dac_cntl;
- CARD32 tv_pll_cntl;
- CARD32 tv_pll_cntl1;
- CARD32 tv_pll_fine_cntl;
- CARD32 tv_modulator_cntl1;
- CARD32 tv_modulator_cntl2;
- CARD32 tv_frame_lock_cntl;
- CARD32 tv_pre_dac_mux_cntl;
- CARD32 tv_rgb_cntl;
- CARD32 tv_y_saw_tooth_cntl;
- CARD32 tv_y_rise_cntl;
- CARD32 tv_y_fall_cntl;
- CARD32 tv_uv_adr;
- CARD32 tv_upsamp_and_gain_cntl;
- CARD32 tv_gain_limit_settings;
- CARD32 tv_linear_gain_settings;
- CARD32 tv_crc_cntl;
- CARD32 tv_sync_cntl;
- CARD32 gpiopad_a;
- CARD32 pll_test_cntl;
-
- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
-
-} RADEONSaveRec, *RADEONSavePtr;
+
typedef struct {
CARD16 reference_freq;
@@ -522,8 +360,8 @@ typedef struct {
Bool IsDDR;
int DispPriority;
- RADEONSaveRec SavedReg; /* Original (text) mode */
- RADEONSaveRec ModeReg; /* Current mode */
+ RADEONSavePtr SavedReg; /* Original (text) mode */
+ RADEONSavePtr ModeReg; /* Current mode */
Bool (*CloseScreen)(int, ScreenPtr);
void (*BlockHandler)(int, pointer, pointer, pointer);
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 6028aff..7f05578 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -322,7 +322,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn)
#endif
/* Restore SURFACE_CNTL */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
RADEONWaitForFifo(pScrn, 1);
OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index b1d216d..718073c 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -311,7 +311,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
return FALSE;
}
- /*save->bios_4_scratch = info->SavedReg.bios_4_scratch;*/
+ /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/
save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
| RADEON_CRTC_EN
| (format << 8)
@@ -330,7 +330,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
RADEON_CRTC_HSYNC_DIS |
RADEON_CRTC_DISPLAY_DIS);
- save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
+ save->disp_merge_cntl = info->SavedReg->disp_merge_cntl;
save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
save->crtc_more_cntl = 0;
@@ -380,10 +380,10 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
if (info->IsDellServer) {
- save->dac2_cntl = info->SavedReg.dac2_cntl;
- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl;
- save->crtc2_gen_cntl = info->SavedReg.crtc2_gen_cntl;
- save->disp_hw_debug = info->SavedReg.disp_hw_debug;
+ save->dac2_cntl = info->SavedReg->dac2_cntl;
+ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl;
+ save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl;
+ save->disp_hw_debug = info->SavedReg->disp_hw_debug;
save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
@@ -589,7 +589,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
? RADEON_CRTC2_INTERLACE_EN
: 0));
- save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl;
+ save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl;
save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
@@ -687,7 +687,7 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
save->htotal_cntl = 0;
- save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl &
+ save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl &
~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
}
@@ -757,7 +757,7 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
(post_div->bitvalue << 16));
save->htotal_cntl2 = 0;
- save->pixclks_cntl = ((info->SavedReg.pixclks_cntl &
+ save->pixclks_cntl = ((info->SavedReg->pixclks_cntl &
~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
@@ -770,8 +770,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
/* tell the bios not to muck with the hardware on events */
save->bios_4_scratch = 0x4; /* 0x4 needed for backlight */
- save->bios_5_scratch = (info->SavedReg.bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */
- save->bios_6_scratch = info->SavedReg.bios_6_scratch | 0x40000000;
+ save->bios_5_scratch = (info->SavedReg->bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */
+ save->bios_6_scratch = info->SavedReg->bios_6_scratch | 0x40000000;
}
@@ -823,38 +823,38 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
}
if (info->IsMobility)
- RADEONInitBIOSRegisters(pScrn, &info->ModeReg);
+ RADEONInitBIOSRegisters(pScrn, info->ModeReg);
ErrorF("init memmap\n");
- RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info);
+ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
ErrorF("init common\n");
- RADEONInitCommonRegisters(&info->ModeReg, info);
+ RADEONInitCommonRegisters(info->ModeReg, info);
- RADEONInitSurfaceCntl(crtc, &info->ModeReg);
+ RADEONInitSurfaceCntl(crtc, info->ModeReg);
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("init crtc1\n");
- RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode);
- RADEONInitCrtcBase(crtc, &info->ModeReg, x, y);
+ RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode);
+ RADEONInitCrtcBase(crtc, info->ModeReg, x, y);
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, info, &info->ModeReg, &info->pll, dot_clock);
+ RADEONInitPLLRegisters(pScrn, info, info->ModeReg, &info->pll, dot_clock);
} else {
- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
+ info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
+ info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
+ info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl;
}
break;
case 1:
ErrorF("init crtc2\n");
- RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode);
- RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y);
+ RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode);
+ RADEONInitCrtc2Base(crtc, info->ModeReg, x, y);
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, dot_clock, no_odd_post_div);
+ RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, dot_clock, no_odd_post_div);
}
break;
}
@@ -867,13 +867,13 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
switch (radeon_crtc->crtc_id) {
case 0:
- RADEONAdjustCrtcRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
- RADEONAdjustPLLRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
+ RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
+ RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
update_tv_routing = TRUE;
break;
case 1:
- RADEONAdjustCrtc2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
- RADEONAdjustPLL2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
+ RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
+ RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
break;
}
}
@@ -881,31 +881,31 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
}
if (info->IsMobility)
- RADEONRestoreBIOSRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreBIOSRegisters(pScrn, info->ModeReg);
ErrorF("restore memmap\n");
- RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
ErrorF("restore common\n");
- RADEONRestoreCommonRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreCommonRegisters(pScrn, info->ModeReg);
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("restore crtc1\n");
- RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreCrtcRegisters(pScrn, info->ModeReg);
ErrorF("restore pll1\n");
- RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
+ RADEONRestorePLLRegisters(pScrn, info->ModeReg);
break;
case 1:
ErrorF("restore crtc2\n");
- RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg);
+ RADEONRestoreCrtc2Registers(pScrn, info->ModeReg);
ErrorF("restore pll2\n");
- RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
+ RADEONRestorePLL2Registers(pScrn, info->ModeReg);
break;
}
/* pixclks_cntl handles tv-out clock routing */
if (update_tv_routing)
- radeon_update_tv_routing(pScrn, &info->ModeReg);
+ radeon_update_tv_routing(pScrn, info->ModeReg);
if (info->DispPriority)
RADEONInitDispBandwidth(pScrn);
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 5c4fbfa..f678dda 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -689,7 +689,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
critical_point = 0x10;
}
- temp = info->SavedReg.grph_buffer_cntl;
+ temp = info->SavedReg->grph_buffer_cntl;
temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
temp &= ~(RADEON_GRPH_START_REQ_MASK);
@@ -711,7 +711,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg.grph_buffer_cntl,
+ (unsigned int)info->SavedReg->grph_buffer_cntl,
INREG(RADEON_GRPH_BUFFER_CNTL));
if (mode2) {
@@ -719,7 +719,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
if (stop_req > max_stop_req) stop_req = max_stop_req;
- temp = info->SavedReg.grph2_buffer_cntl;
+ temp = info->SavedReg->grph2_buffer_cntl;
temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
temp &= ~(RADEON_GRPH_START_REQ_MASK);
@@ -761,7 +761,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH2_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg.grph2_buffer_cntl,
+ (unsigned int)info->SavedReg->grph2_buffer_cntl,
INREG(RADEON_GRPH2_BUFFER_CNTL));
}
}
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 7136e4e..dbfa8d9 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -1197,7 +1197,7 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
info->irq = 0;
} else {
unsigned char *RADEONMMIO = info->MMIO;
- info->ModeReg.gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
+ info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
}
}
@@ -1774,7 +1774,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
RADEONDRISetVBlankInterrupt (pScrn, FALSE);
drmCtlUninstHandler(info->drmFD);
info->irq = 0;
- info->ModeReg.gen_int_cntl = 0;
+ info->ModeReg->gen_int_cntl = 0;
}
/* De-allocate vertex buffers */
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 3422b66..f01c9aa 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2370,6 +2370,8 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
void *int10_save = NULL;
const char *s;
int crtc_max_X, crtc_max_Y;
+ RADEONEntPtr pRADEONEnt;
+ DevUnion* pPriv;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONPreInit\n");
@@ -2383,6 +2385,13 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
if (info->pEnt->location.type != BUS_PCI) goto fail;
+ pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
+ getRADEONEntityIndex());
+ pRADEONEnt = pPriv->ptr;
+
+ info->SavedReg = &pRADEONEnt->SavedReg;
+ info->ModeReg = &pRADEONEnt->ModeReg;
+
info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo),
PCI_DEV_DEV(info->PciInfo),
@@ -3469,7 +3478,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
* our local image to make sure we restore them properly on mode
* changes or VT switches
*/
- RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg);
+ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {
/* we need to re-calculate bandwidth because of AGPMode difference. */
@@ -4801,7 +4810,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
}
/* Update surface images */
- RADEONSaveSurfaces(pScrn, &info->ModeReg);
+ RADEONSaveSurfaces(pScrn, info->ModeReg);
}
/* Read memory map */
@@ -5129,7 +5138,7 @@ static void RADEONSave(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr save = &info->SavedReg;
+ RADEONSavePtr save = info->SavedReg;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONSave\n");
@@ -5181,7 +5190,7 @@ void RADEONRestore(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr restore = &info->SavedReg;
+ RADEONSavePtr restore = info->SavedReg;
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
xf86CrtcPtr crtc;
@@ -5585,7 +5594,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
}
- RADEONRestoreSurfaces(pScrn, &info->ModeReg);
+ RADEONRestoreSurfaces(pScrn, info->ModeReg);
#ifdef XF86DRI
if (info->directRenderingEnabled) {
if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize)
@@ -5597,7 +5606,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
/* get the DRI back into shape after resume */
RADEONDRISetVBlankInterrupt (pScrn, TRUE);
RADEONDRIResume(pScrn->pScreen);
- RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg);
+ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
}
#endif
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 11a2a8a..ecff799 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -837,7 +837,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
int i;
- CARD32 tmp = info->SavedReg.tmds_pll_cntl & 0xfffff;
+ CARD32 tmp = info->SavedReg->tmds_pll_cntl & 0xfffff;
for (i=0; i<4; i++) {
if (radeon_output->tmds_pll[i].freq == 0) break;
@@ -851,12 +851,12 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
if (tmp & 0xfff00000)
save->tmds_pll_cntl = tmp;
else {
- save->tmds_pll_cntl = info->SavedReg.tmds_pll_cntl & 0xfff00000;
+ save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000;
save->tmds_pll_cntl |= tmp;
}
} else save->tmds_pll_cntl = tmp;
- save->tmds_transmitter_cntl = info->SavedReg.tmds_transmitter_cntl &
+ save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl &
~(RADEON_TMDS_TRANSMITTER_PLLRST);
if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !pRADEONEnt->HasCRTC2)
@@ -864,7 +864,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
else /* weird, RV chips got this bit reversed? */
save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
- save->fp_gen_cntl = info->SavedReg.fp_gen_cntl |
+ save->fp_gen_cntl = info->SavedReg->fp_gen_cntl |
(RADEON_FP_CRTC_DONT_SHADOW_VPAR |
RADEON_FP_CRTC_DONT_SHADOW_HEND );
@@ -903,10 +903,10 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
if (pScrn->rgbBits == 8)
- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl |
+ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl |
RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
else
- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl &
+ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
save->fp2_gen_cntl &= ~(RADEON_FP2_ON |
@@ -948,12 +948,12 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save,
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- save->lvds_pll_cntl = (info->SavedReg.lvds_pll_cntl |
+ save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl |
RADEON_LVDS_PLL_EN);
save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
- save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl;
+ save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl;
save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
@@ -985,9 +985,9 @@ static void RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save,
int yres = mode->VDisplay;
float Hratio, Vratio;
- save->fp_vert_stretch = info->SavedReg.fp_vert_stretch &
+ save->fp_vert_stretch = info->SavedReg->fp_vert_stretch &
RADEON_VERT_STRETCH_RESERVED;
- save->fp_horz_stretch = info->SavedReg.fp_horz_stretch &
+ save->fp_horz_stretch = info->SavedReg->fp_horz_stretch &
(RADEON_HORZ_FP_LOOP_STRETCH |
RADEON_HORZ_AUTO_RATIO_INC);
@@ -1036,25 +1036,25 @@ static void RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save,
if (IsPrimary) {
if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg.disp_output_cntl &
+ save->disp_output_cntl = info->SavedReg->disp_output_cntl &
~RADEON_DISP_DAC_SOURCE_MASK;
} else {
- save->dac2_cntl = info->SavedReg.dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL);
+ save->dac2_cntl = info->SavedReg->dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL);
}
} else {
if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg.disp_output_cntl &
+ save->disp_output_cntl = info->SavedReg->disp_output_cntl &
~RADEON_DISP_DAC_SOURCE_MASK;
save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
} else {
- save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC_CLK_SEL;
+ save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC_CLK_SEL;
}
}
save->dac_cntl = (RADEON_DAC_MASK_ALL
| RADEON_DAC_VGA_ADR_EN
| (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN));
- save->dac_macro_cntl = info->SavedReg.dac_macro_cntl;
+ save->dac_macro_cntl = info->SavedReg->dac_macro_cntl;
}
static void
@@ -1066,7 +1066,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save)
if (info->ChipFamily == CHIP_FAMILY_R420 ||
info->ChipFamily == CHIP_FAMILY_RV410) {
- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl &
+ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl &
~(RADEON_TV_DAC_STD_MASK |
RADEON_TV_DAC_BGADJ_MASK |
R420_TV_DAC_DACADJ_MASK |
@@ -1075,7 +1075,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save)
R420_TV_DAC_GDACPD |
R420_TV_DAC_TVENABLE);
} else {
- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl &
+ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl &
~(RADEON_TV_DAC_STD_MASK |
RADEON_TV_DAC_BGADJ_MASK |
RADEON_TV_DAC_DACADJ_MASK |
@@ -1101,34 +1101,34 @@ static void RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save,
RADEONInitTvDacCntl(output, save);
if (IS_R300_VARIANT)
- save->gpiopad_a = info->SavedReg.gpiopad_a | 1;
+ save->gpiopad_a = info->SavedReg->gpiopad_a | 1;
- save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL;
+ save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL;
if (IsPrimary) {
if (IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg.disp_output_cntl &
+ save->disp_output_cntl = info->SavedReg->disp_output_cntl &
~RADEON_DISP_TVDAC_SOURCE_MASK;
save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
} else if (info->ChipFamily == CHIP_FAMILY_R200) {
- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl &
+ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
~(R200_FP2_SOURCE_SEL_MASK |
RADEON_FP2_DVO_RATE_SEL_SDR);
} else {
- save->disp_hw_debug = info->SavedReg.disp_hw_debug | RADEON_CRT2_DISP1_SEL;
+ save->disp_hw_debug = info->SavedReg->disp_hw_debug | RADEON_CRT2_DISP1_SEL;
}
} else {
if (IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg.disp_output_cntl &
+ save->disp_output_cntl = info->SavedReg->disp_output_cntl &
~RADEON_DISP_TVDAC_SOURCE_MASK;
save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
} else if (info->ChipFamily == CHIP_FAMILY_R200) {
- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl &
+ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
~(R200_FP2_SOURCE_SEL_MASK |
RADEON_FP2_DVO_RATE_SEL_SDR);
save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
} else {
- save->disp_hw_debug = info->SavedReg.disp_hw_debug &
+ save->disp_hw_debug = info->SavedReg->disp_hw_debug &
~RADEON_CRT2_DISP1_SEL;
}
}
@@ -1175,35 +1175,35 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
xf86CrtcPtr crtc = output->crtc;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInitOutputRegisters(pScrn, &info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id);
+ RADEONInitOutputRegisters(pScrn, info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id);
if (radeon_crtc->crtc_id == 0)
- RADEONRestoreRMXRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreRMXRegisters(pScrn, info->ModeReg);
switch(radeon_output->MonType) {
case MT_LCD:
ErrorF("restore LVDS\n");
- RADEONRestoreLVDSRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreLVDSRegisters(pScrn, info->ModeReg);
break;
case MT_DFP:
if (radeon_output->TMDSType == TMDS_INT) {
ErrorF("restore FP\n");
- RADEONRestoreFPRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreFPRegisters(pScrn, info->ModeReg);
} else {
ErrorF("restore FP2\n");
RADEONRestoreDVOChip(pScrn, output);
- RADEONRestoreFP2Registers(pScrn, &info->ModeReg);
+ RADEONRestoreFP2Registers(pScrn, info->ModeReg);
}
break;
case MT_STV:
case MT_CTV:
ErrorF("restore tv\n");
- RADEONRestoreDACRegisters(pScrn, &info->ModeReg);
- RADEONRestoreTVRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreDACRegisters(pScrn, info->ModeReg);
+ RADEONRestoreTVRegisters(pScrn, info->ModeReg);
break;
default:
ErrorF("restore dac\n");
- RADEONRestoreDACRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreDACRegisters(pScrn, info->ModeReg);
}
}
@@ -1781,7 +1781,7 @@ radeon_create_resources(xf86OutputPtr output)
"RRConfigureOutputProperty error, %d\n", err);
}
/* Set the current value of the backlight property */
- //data = (info->SavedReg.lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT;
+ //data = (info->SavedReg->lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT;
data = RADEON_MAX_BACKLIGHT_LEVEL;
err = RRChangeOutputProperty(output->randr_output, backlight_atom,
XA_INTEGER, 32, PropModeReplace, 1, &data,
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 66ece94..cdefdf5 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -223,6 +223,177 @@ typedef struct _RADEONOutputPrivateRec {
int load_detection;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
+
+/*
+ * Maximum length of horizontal/vertical code timing tables for state storage
+ */
+#define MAX_H_CODE_TIMING_LEN 32
+#define MAX_V_CODE_TIMING_LEN 32
+
+typedef struct {
+ /* Common registers */
+ CARD32 ovr_clr;
+ CARD32 ovr_wid_left_right;
+ CARD32 ovr_wid_top_bottom;
+ CARD32 ov0_scale_cntl;
+ CARD32 mpp_tb_config;
+ CARD32 mpp_gp_config;
+ CARD32 subpic_cntl;
+ CARD32 viph_control;
+ CARD32 i2c_cntl_1;
+ CARD32 gen_int_cntl;
+ CARD32 cap0_trig_cntl;
+ CARD32 cap1_trig_cntl;
+ CARD32 bus_cntl;
+ CARD32 bios_4_scratch;
+ CARD32 bios_5_scratch;
+ CARD32 bios_6_scratch;
+ CARD32 surface_cntl;
+ CARD32 surfaces[8][3];
+ CARD32 mc_agp_location;
+ CARD32 mc_fb_location;
+ CARD32 display_base_addr;
+ CARD32 display2_base_addr;
+ CARD32 ov0_base_addr;
+
+ /* Other registers to save for VT switches */
+ CARD32 dp_datatype;
+ CARD32 rbbm_soft_reset;
+ CARD32 clock_cntl_index;
+ CARD32 amcgpio_en_reg;
+ CARD32 amcgpio_mask;
+
+ /* CRTC registers */
+ CARD32 crtc_gen_cntl;
+ CARD32 crtc_ext_cntl;
+ CARD32 dac_cntl;
+ CARD32 crtc_h_total_disp;
+ CARD32 crtc_h_sync_strt_wid;
+ CARD32 crtc_v_total_disp;
+ CARD32 crtc_v_sync_strt_wid;
+ CARD32 crtc_offset;
+ CARD32 crtc_offset_cntl;
+ CARD32 crtc_pitch;
+ CARD32 disp_merge_cntl;
+ CARD32 grph_buffer_cntl;
+ CARD32 crtc_more_cntl;
+ CARD32 crtc_tile_x0_y0;
+
+ /* CRTC2 registers */
+ CARD32 crtc2_gen_cntl;
+ CARD32 dac_macro_cntl;
+ CARD32 dac2_cntl;
+ CARD32 disp_output_cntl;
+ CARD32 disp_tv_out_cntl;
+ CARD32 disp_hw_debug;
+ CARD32 disp2_merge_cntl;
+ CARD32 grph2_buffer_cntl;
+ CARD32 crtc2_h_total_disp;
+ CARD32 crtc2_h_sync_strt_wid;
+ CARD32 crtc2_v_total_disp;
+ CARD32 crtc2_v_sync_strt_wid;
+ CARD32 crtc2_offset;
+ CARD32 crtc2_offset_cntl;
+ CARD32 crtc2_pitch;
+ CARD32 crtc2_tile_x0_y0;
+
+ /* Flat panel registers */
+ CARD32 fp_crtc_h_total_disp;
+ CARD32 fp_crtc_v_total_disp;
+ CARD32 fp_gen_cntl;
+ CARD32 fp2_gen_cntl;
+ CARD32 fp_h_sync_strt_wid;
+ CARD32 fp_h2_sync_strt_wid;
+ CARD32 fp_horz_stretch;
+ CARD32 fp_panel_cntl;
+ CARD32 fp_v_sync_strt_wid;
+ CARD32 fp_v2_sync_strt_wid;
+ CARD32 fp_vert_stretch;
+ CARD32 lvds_gen_cntl;
+ CARD32 lvds_pll_cntl;
+ CARD32 tmds_pll_cntl;
+ CARD32 tmds_transmitter_cntl;
+
+ /* Computed values for PLL */
+ CARD32 dot_clock_freq;
+ CARD32 pll_output_freq;
+ int feedback_div;
+ int post_div;
+
+ /* PLL registers */
+ unsigned ppll_ref_div;
+ unsigned ppll_div_3;
+ CARD32 htotal_cntl;
+ CARD32 vclk_ecp_cntl;
+
+ /* Computed values for PLL2 */
+ CARD32 dot_clock_freq_2;
+ CARD32 pll_output_freq_2;
+ int feedback_div_2;
+ int post_div_2;
+
+ /* PLL2 registers */
+ CARD32 p2pll_ref_div;
+ CARD32 p2pll_div_0;
+ CARD32 htotal_cntl2;
+ CARD32 pixclks_cntl;
+
+ /* Pallet */
+ Bool palette_valid;
+ CARD32 palette[256];
+ CARD32 palette2[256];
+
+ CARD32 rs480_unk_e30;
+ CARD32 rs480_unk_e34;
+ CARD32 rs480_unk_e38;
+ CARD32 rs480_unk_e3c;
+
+ /* TV out registers */
+ CARD32 tv_master_cntl;
+ CARD32 tv_htotal;
+ CARD32 tv_hsize;
+ CARD32 tv_hdisp;
+ CARD32 tv_hstart;
+ CARD32 tv_vtotal;
+ CARD32 tv_vdisp;
+ CARD32 tv_timing_cntl;
+ CARD32 tv_vscaler_cntl1;
+ CARD32 tv_vscaler_cntl2;
+ CARD32 tv_sync_size;
+ CARD32 tv_vrestart;
+ CARD32 tv_hrestart;
+ CARD32 tv_frestart;
+ CARD32 tv_ftotal;
+ CARD32 tv_clock_sel_cntl;
+ CARD32 tv_clkout_cntl;
+ CARD32 tv_data_delay_a;
+ CARD32 tv_data_delay_b;
+ CARD32 tv_dac_cntl;
+ CARD32 tv_pll_cntl;
+ CARD32 tv_pll_cntl1;
+ CARD32 tv_pll_fine_cntl;
+ CARD32 tv_modulator_cntl1;
+ CARD32 tv_modulator_cntl2;
+ CARD32 tv_frame_lock_cntl;
+ CARD32 tv_pre_dac_mux_cntl;
+ CARD32 tv_rgb_cntl;
+ CARD32 tv_y_saw_tooth_cntl;
+ CARD32 tv_y_rise_cntl;
+ CARD32 tv_y_fall_cntl;
+ CARD32 tv_uv_adr;
+ CARD32 tv_upsamp_and_gain_cntl;
+ CARD32 tv_gain_limit_settings;
+ CARD32 tv_linear_gain_settings;
+ CARD32 tv_crc_cntl;
+ CARD32 tv_sync_cntl;
+ CARD32 gpiopad_a;
+ CARD32 pll_test_cntl;
+
+ CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
+ CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
+
+} RADEONSaveRec, *RADEONSavePtr;
+
#define RADEON_MAX_CRTC 2
#define RADEON_MAX_BIOS_CONNECTOR 8
@@ -242,6 +413,9 @@ typedef struct
xf86CrtcPtr pCrtc[RADEON_MAX_CRTC];
RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC];
+ RADEONSaveRec ModeReg; /* Current mode */
+ RADEONSaveRec SavedReg; /* Original (text) mode */
+
} RADEONEntRec, *RADEONEntPtr;
/* radeon_probe.c */
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 2a8873c..5e9a9c8 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -540,7 +540,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->dac_cntl &= ~RADEON_DAC_TVO_EN;
if (IS_R300_VARIANT)
- save->gpiopad_a = info->SavedReg.gpiopad_a & ~1;
+ save->gpiopad_a = info->SavedReg->gpiopad_a & ~1;
if (IsPrimary) {
save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
@@ -571,7 +571,7 @@ void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
Bool reloadTable;
- RADEONSavePtr restore = &info->ModeReg;
+ RADEONSavePtr restore = info->ModeReg;
reloadTable = RADEONInitTVRestarts(output, restore, mode);
diff --git a/src/radeon_tv.h b/src/radeon_tv.h
index 5c8c8c9..c4b7838 100644
--- a/src/radeon_tv.h
+++ b/src/radeon_tv.h
@@ -3,11 +3,6 @@
* Federico Ulivi <fulivi at lycos.com>
*/
-/*
- * Maximum length of horizontal/vertical code timing tables for state storage
- */
-#define MAX_H_CODE_TIMING_LEN 32
-#define MAX_V_CODE_TIMING_LEN 32
/*
* Limits of h/v positions (hPos & vPos)
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 3f0209e..99b74eb 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -1430,7 +1430,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
* 0 for PIXCLK < 175Mhz, and 1 (divide by 2)
* for higher clocks, sure makes life nicer
*/
- dot_clock = info->ModeReg.dot_clock_freq;
+ dot_clock = info->ModeReg->dot_clock_freq;
if (dot_clock < 17500)
info->ecp_div = 0;
@@ -2552,9 +2552,9 @@ RADEONDisplayVideo(
/* Figure out which head we are on for dot clock */
if (radeon_crtc->crtc_id == 1)
- dot_clock = info->ModeReg.dot_clock_freq_2;
+ dot_clock = info->ModeReg->dot_clock_freq_2;
else
- dot_clock = info->ModeReg.dot_clock_freq;
+ dot_clock = info->ModeReg->dot_clock_freq;
if (dot_clock < 17500)
ecp_div = 0;
commit 0d89556bfa41a3acbd6afe85b062e3a21f2ca057
Author: Dave Airlie <airlied at ppcg5.localdomain>
Date: Thu Dec 6 19:23:06 2007 +1100
powerpc: build fixes from last merge
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 19107be..15b4ddf 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2893,7 +2893,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
info->BiosConnector[0].valid = TRUE;
info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
@@ -2935,22 +2935,22 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[1].valid = TRUE;
return TRUE;
case RADEON_MAC_IMAC_G5_ISIGHT:
- info->BiosConnector[0].DDCType = DDC_MONID;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_MONID;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_INT;
info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_D;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].DDCType = DDC_DVI;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[1].DACType = DAC_TVDAC;
info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
info->BiosConnector[1].valid = TRUE;
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].ddc_line = 0;
info->BiosConnector[2].valid = TRUE;
return TRUE;
default:
commit dbe3d2608ecc9896db9c23b3a347b50748c51e13
Merge: 48e31cd... 21ed435...
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Dec 6 14:22:03 2007 +1000
Merge branch 'master' into atombios-support
Conflicts:
src/radeon_output.c
diff --cc src/radeon_output.c
index a325add,11a2a8a..19107be
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@@ -688,15 -633,19 +688,29 @@@ void RADEONConnectorFindMonitor(ScrnInf
RADEONOutputPrivatePtr radeon_output = output->driver_private;
if (radeon_output->MonType == MT_UNKNOWN) {
- if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) {
- if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) {
+ if (IS_AVIVO_VARIANT) {
+ radeon_output->MonType = avivo_display_ddc_connected(pScrn, output);
+ if (!radeon_output->MonType) {
+ if (radeon_output->type == OUTPUT_LVDS)
+ radeon_output->MonType = MT_LCD;
+ else if (OUTPUT_IS_TV)
+ radeon_output->MonType = MT_NONE;
+ else
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
++ }
++ } else if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) {
++ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) {
+ if (radeon_output->type == OUTPUT_STV)
+ radeon_output->MonType = MT_STV;
+ else
+ radeon_output->MonType = MT_CTV;
+ } else {
+ if (info->InternalTVOut) {
+ if (radeon_output->load_detection)
+ radeon_output->MonType = radeon_detect_tv(pScrn);
+ else
+ radeon_output->MonType = MT_NONE;
+ }
}
} else {
radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output);
@@@ -2896,9 -2786,28 +2931,28 @@@ static Bool RADEONSetupAppleConnectors(
info->BiosConnector[1].ConnectorType = CONNECTOR_STV;
info->BiosConnector[1].DACType = DAC_TVDAC;
info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[1].ddc_line = 0;
info->BiosConnector[1].valid = TRUE;
return TRUE;
+ case RADEON_MAC_IMAC_G5_ISIGHT:
+ info->BiosConnector[0].DDCType = DDC_MONID;
+ info->BiosConnector[0].DACType = DAC_NONE;
+ info->BiosConnector[0].TMDSType = TMDS_INT;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_D;
+ info->BiosConnector[0].valid = TRUE;
+
+ info->BiosConnector[1].DDCType = DDC_DVI;
+ info->BiosConnector[1].DACType = DAC_TVDAC;
+ info->BiosConnector[1].TMDSType = TMDS_NONE;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[1].valid = TRUE;
+
+ info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
+ info->BiosConnector[2].DACType = DAC_TVDAC;
+ info->BiosConnector[2].TMDSType = TMDS_NONE;
+ info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].valid = TRUE;
+ return TRUE;
default:
return FALSE;
}
commit 48e31cdaa0caa21573879af5b9267773fe89176a
Author: George Wu <geo at ocf.berkeley.edu>
Date: Sun Dec 2 15:25:09 2007 +1000
RADEON/R600: small code cleanup
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 6e98913..ba4c111 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1349,15 +1349,13 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
/* We shouldn't use info->videoRam here which might have been clipped
* but the real video RAM instead
*/
- if (info->ChipFamily >= CHIP_FAMILY_R600)
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
mem_size = INREG(R600_CONFIG_MEMSIZE);
- else
- mem_size = INREG(RADEON_CONFIG_MEMSIZE);
-
- if (info->ChipFamily >= CHIP_FAMILY_R600)
aper_size = INREG(R600_CONFIG_APER_SIZE);
- else
+ } else {
+ mem_size = INREG(RADEON_CONFIG_MEMSIZE);
aper_size = INREG(RADEON_CONFIG_APER_SIZE);
+ }
if (mem_size == 0)
mem_size = 0x800000;
commit 1e029fef5fe264f2ced445b80bf6070abcb84b82
Author: Alex Deucher <alex at samba.(none)>
Date: Sat Dec 1 00:58:51 2007 -0500
RADEON: move GPIO lookup to a separate function
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index aa25ed3..9d17e47 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1326,11 +1326,38 @@ rhdAtomParseI2CRecord(atomBiosHandlePtr handle,
}
}
+static CARD32
+RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, CARD8 id)
+{
+ RADEONInfoPtr info = RADEONPTR (pScrn);
+ atomDataTablesPtr atomDataPtr;
+ ATOM_GPIO_I2C_ASSIGMENT gpio;
+ CARD32 ret = 0;
+ CARD8 crev, frev;
+
+ atomDataPtr = info->atomBIOS->atomDataPtr;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ &(atomDataPtr->GPIO_I2C_Info->sHeader),
+ &crev,&frev,NULL)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Info Table found!\n");
+ return ret;
+ }
+
+ /* note clk and data regs can be different!
+ * gpio.usClkMaskRegisterIndex and gpio.usDataMaskRegisterIndex
+ */
+
+ gpio = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[id];
+ ret = gpio.usClkMaskRegisterIndex * 4;
+
+ return ret;
+}
+
Bool
RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
- int ret;
CARD8 crev, frev;
unsigned short size;
atomDataTablesPtr atomDataPtr;
@@ -1445,13 +1472,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
atomDataPtr = info->atomBIOS->atomDataPtr;
if (!rhdAtomGetTableRevisionAndSize(
- &(atomDataPtr->GPIO_I2C_Info->sHeader),
- &crev,&frev,NULL)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Info Table found!\n");
- return FALSE;
- }
-
- if (!rhdAtomGetTableRevisionAndSize(
&(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader),
&crev,&frev,NULL)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Device Info Table found!\n");
@@ -1481,26 +1501,18 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC - 1;
if (ci.sucI2cId.sbfAccess.bfHW_Capable) {
- ATOM_GPIO_I2C_ASSIGMENT gpio
- = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[ci.sucI2cId.sbfAccess.bfI2C_LineMux];
-
- /* note clk and data regs can be different!
- * gpio.usClkMaskRegisterIndex and gpio.usDataMaskRegisterIndex
- */
-
/* don't assign a gpio for tv */
if ((i == ATOM_DEVICE_TV1_INDEX) ||
(i == ATOM_DEVICE_TV2_INDEX) ||
(i == ATOM_DEVICE_CV_INDEX))
info->BiosConnector[i].ddc_line = 0;
else
- info->BiosConnector[i].ddc_line = gpio.usClkMaskRegisterIndex * 4;
+ info->BiosConnector[i].ddc_line =
+ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
} else if (ci.sucI2cId.sbfAccess.bfI2C_LineMux) {
- ATOM_GPIO_I2C_ASSIGMENT gpio
- = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[ci.sucI2cId.sbfAccess.bfI2C_LineMux];
-
/* add support for GPIO line */
- ErrorF("Unsupported SW GPIO - device %d: gpio line: 0x%x\n", i, gpio.usClkMaskRegisterIndex * 4);
+ ErrorF("Unsupported SW GPIO - device %d: gpio line: 0x%x\n",
+ i, RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux));
info->BiosConnector[i].ddc_line = 0;
} else {
info->BiosConnector[i].ddc_line = 0;
commit dcbef1ba9dfcf35c28e058832a55adf00afb472e
Author: Alex Deucher <alex at samba.(none)>
Date: Sat Dec 1 00:35:25 2007 -0500
RADEON: fix typo in previous commit
check gpio table revision before connector table revision
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 1670020..aa25ed3 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1445,16 +1445,16 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
atomDataPtr = info->atomBIOS->atomDataPtr;
if (!rhdAtomGetTableRevisionAndSize(
- &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader),
+ &(atomDataPtr->GPIO_I2C_Info->sHeader),
&crev,&frev,NULL)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Device Info Table found!\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Info Table found!\n");
return FALSE;
}
if (!rhdAtomGetTableRevisionAndSize(
- &(atomDataPtr->GPIO_I2C_Info->sHeader),
+ &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader),
&crev,&frev,NULL)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Info Table found!\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Device Info Table found!\n");
return FALSE;
}
commit fdce0598a2228c48c84deae1d7bebb2d7b3e979b
Author: Alex Deucher <alex at samba.(none)>
Date: Sat Dec 1 00:15:34 2007 -0500
RADEON: convert atombios connector table parsing to use ATOM structs
convert and add hpd info
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index fc816b2..1670020 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1326,7 +1326,8 @@ rhdAtomParseI2CRecord(atomBiosHandlePtr handle,
}
}
-Bool RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+Bool
+RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
int ret;
@@ -1432,6 +1433,161 @@ Bool RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
return TRUE;
}
+
+Bool
+RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR (pScrn);
+ atomDataTablesPtr atomDataPtr;
+ CARD8 crev, frev;
+ int i, j;
+
+ atomDataPtr = info->atomBIOS->atomDataPtr;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader),
+ &crev,&frev,NULL)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Device Info Table found!\n");
+ return FALSE;
+ }
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ &(atomDataPtr->GPIO_I2C_Info->sHeader),
+ &crev,&frev,NULL)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Info Table found!\n");
+ return FALSE;
+ }
+
+ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+ ATOM_CONNECTOR_INFO_I2C ci
+ = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[i];
+
+ if (!(atomDataPtr->SupportedDevicesInfo
+ .SupportedDevicesInfo->usDeviceSupport & (1 << i))) {
+ info->BiosConnector[i].valid = FALSE;
+ continue;
+ }
+
+ if (i == ATOM_DEVICE_CV_INDEX) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping Component Video\n");
+ info->BiosConnector[i].valid = FALSE;
+ continue;
+ }
+
+ info->BiosConnector[i].valid = TRUE;
+ info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
+ info->BiosConnector[i].devices = (1 << i);
+ info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType;
+ info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC - 1;
+
+ if (ci.sucI2cId.sbfAccess.bfHW_Capable) {
+ ATOM_GPIO_I2C_ASSIGMENT gpio
+ = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[ci.sucI2cId.sbfAccess.bfI2C_LineMux];
+
+ /* note clk and data regs can be different!
+ * gpio.usClkMaskRegisterIndex and gpio.usDataMaskRegisterIndex
+ */
+
+ /* don't assign a gpio for tv */
+ if ((i == ATOM_DEVICE_TV1_INDEX) ||
+ (i == ATOM_DEVICE_TV2_INDEX) ||
+ (i == ATOM_DEVICE_CV_INDEX))
+ info->BiosConnector[i].ddc_line = 0;
+ else
+ info->BiosConnector[i].ddc_line = gpio.usClkMaskRegisterIndex * 4;
+ } else if (ci.sucI2cId.sbfAccess.bfI2C_LineMux) {
+ ATOM_GPIO_I2C_ASSIGMENT gpio
+ = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[ci.sucI2cId.sbfAccess.bfI2C_LineMux];
+
+ /* add support for GPIO line */
+ ErrorF("Unsupported SW GPIO - device %d: gpio line: 0x%x\n", i, gpio.usClkMaskRegisterIndex * 4);
+ info->BiosConnector[i].ddc_line = 0;
+ } else {
+ info->BiosConnector[i].ddc_line = 0;
+ }
+
+ if (i == ATOM_DEVICE_DFP1_INDEX)
+ info->BiosConnector[i].TMDSType = TMDS_INT;
+ else if (i == ATOM_DEVICE_DFP2_INDEX)
+ info->BiosConnector[i].TMDSType = TMDS_EXT;
+ else if (i == ATOM_DEVICE_DFP3_INDEX)
+ info->BiosConnector[i].TMDSType = TMDS_EXT;
+ else
+ info->BiosConnector[i].TMDSType = TMDS_UNKNOWN;
+
+ /* Always set the connector type to VGA for CRT1/CRT2. if they are
+ * shared with a DVI port, we'll pick up the DVI connector below when we
+ * merge the outputs
+ */
+ if ((i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) &&
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I ||
+ info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D ||
+ info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) {
+ info->BiosConnector[i].ConnectorType = CONNECTOR_VGA;
+ }
+
+ if (crev > 1) {
+ ATOM_CONNECTOR_INC_SRC_BITMAP isb
+ = atomDataPtr->SupportedDevicesInfo
+ .SupportedDevicesInfo_HD->asIntSrcInfo[i];
+
+ switch (isb.ucIntSrcBitmap) {
+ case 0x4:
+ info->BiosConnector[i].hpd_mask = 0x00000001;
+ break;
+ case 0xa:
+ info->BiosConnector[i].hpd_mask = 0x00000100;
+ break;
+ default:
+ info->BiosConnector[i].hpd_mask = 0;
+ break;
+ }
+ } else {
+ info->BiosConnector[i].hpd_mask = 0;
+ }
+ }
+
+ /* CRTs/DFPs may share a port */
+ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+ if (info->BiosConnector[i].valid) {
+ for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
+ if (info->BiosConnector[j].valid && (i != j) ) {
+ if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) {
+ if (((i == ATOM_DEVICE_DFP1_INDEX) ||
+ (i == ATOM_DEVICE_DFP2_INDEX) ||
+ (i == ATOM_DEVICE_DFP3_INDEX)) &&
+ ((j == ATOM_DEVICE_CRT1_INDEX) || (j == ATOM_DEVICE_CRT2_INDEX))) {
+ info->BiosConnector[i].DACType = info->BiosConnector[j].DACType;
+ info->BiosConnector[i].devices |= info->BiosConnector[j].devices;
+ info->BiosConnector[j].valid = FALSE;
+ } else if (((j == ATOM_DEVICE_DFP1_INDEX) ||
+ (j == ATOM_DEVICE_DFP2_INDEX) ||
+ (j == ATOM_DEVICE_DFP3_INDEX)) &&
+ ((i == ATOM_DEVICE_CRT1_INDEX) || (i == ATOM_DEVICE_CRT2_INDEX))) {
+ info->BiosConnector[j].DACType = info->BiosConnector[i].DACType;
+ info->BiosConnector[j].devices |= info->BiosConnector[i].devices;
+ info->BiosConnector[i].valid = FALSE;
+ }
+ /* other possible combos? */
+ }
+ }
+ }
+ }
+ }
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n");
+ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+ if (info->BiosConnector[i].valid) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x, DACType-%d, TMDSType-%d, ConnectorType-%d, hpd_mask-0x%x\n",
+ i, info->BiosConnector[i].ddc_line, info->BiosConnector[i].DACType,
+ info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType,
+ info->BiosConnector[i].hpd_mask);
+ }
+ }
+
+ return TRUE;
+}
+
#if 0
#define RHD_CONNECTORS_MAX 4
#define MAX_OUTPUTS_PER_CONNECTOR 2
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 293172b..3043de6 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -210,6 +210,9 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn))
return TRUE;
+ if (RADEONGetATOMConnectorInfoFromBIOSConnectorTable(pScrn))
+ return TRUE;
+
offset = RADEON_BIOS16(info->MasterDataStart + 22);
if (offset) {
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 0b4bf55..d01fd8b 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -186,6 +186,7 @@ typedef struct {
Bool valid;
int output_id;
int devices;
+ int hpd_mask;
} RADEONBIOSConnector;
typedef struct _RADEONOutputPrivateRec {
commit e3d7de9cc956aec5f940ad6db09e826b3a69523a
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 30 20:14:42 2007 -0500
RADEON: remove unused cruft from last atom import
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 0e325a6..0b4bf55 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -86,18 +86,6 @@ typedef enum
CONNECTOR_UNSUPPORTED
} RADEONConnectorType;
-typedef enum {
- OUTPUT_NONE_ATOM,
- OUTPUT_DAC_EXTERNAL_ATOM,
- OUTPUT_DACA_ATOM,
- OUTPUT_DACB_ATOM,
- OUTPUT_TMDSA_ATOM,
- OUTPUT_LVTMA_ATOM,
- OUTPUT_TMDSB_ATOM,
- OUTPUT_LVDS_ATOM,
- OUTPUT_LVTMB_ATOM
-} RADEONOutputTypeATOM;
-
typedef enum
{
DAC_UNKNOWN = -1,
commit d5d83411e8a884154d671aad440524507cce313e
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 30 20:11:42 2007 -0500
RADEON: save/restore avivo crtc cursor control
this should prevent the cursor from showing up on in text
mode or vesafb etc. after running the driver.
diff --git a/src/radeon.h b/src/radeon.h
index 586a1fc..76dcec7 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -227,6 +227,7 @@ struct avivo_crtc_state {
CARD32 blank_control;
CARD32 interlace_control;
CARD32 stereo_control;
+ CARD32 cursor_control;
};
struct avivo_grph_state {
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 73e192a..6e98913 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -5445,6 +5445,8 @@ void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL);
state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL);
+ state->crtc1.cursor_control = INREG(AVIVO_D1CUR_CONTROL);
+
state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE);
state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL);
state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL);
@@ -5483,6 +5485,8 @@ void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL);
state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL);
+ state->crtc2.cursor_control = INREG(AVIVO_D2CUR_CONTROL);
+
state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE);
state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL);
state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL);
@@ -5588,6 +5592,8 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control);
OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control);
+ OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control);
+
OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable);
OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control);
OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr);
@@ -5625,6 +5631,8 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control);
OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control);
+ OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control);
+
OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable);
OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control);
OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr);
commit af0196f7bf0d1d5d211391149c18935d64ed2b06
Merge: d9858a2... 0175b79...
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 30 16:40:28 2007 -0500
Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
merge master and fix conflicts
diff --cc src/radeon.h
index b814b10,f9bf343..586a1fc
--- a/src/radeon.h
+++ b/src/radeon.h
@@@ -943,11 -833,8 +950,12 @@@ typedef struct
#if defined(__powerpc__)
RADEONMacModel MacModel;
#endif
+ RADEONExtTMDSChip ext_tmds_chip;
+ atomBiosHandlePtr atomBIOS;
+ unsigned long FbFreeStart, FbFreeSize;
+ unsigned char* BIOSCopy;
+
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
diff --cc src/radeon_output.c
index d8ded6d,efe093f..a325add
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@@ -1741,11 -1683,13 +1752,13 @@@ radeon_detect(xf86OutputPtr output
/* default to unknown for flaky chips/connectors
* so we can get something on the screen
*/
- if (((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) &&
- radeon_output->DACType == DAC_TVDAC)) {
- if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI) &&
++ if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) &&
+ (radeon_output->DACType == DAC_TVDAC) &&
+ (info->ChipFamily == CHIP_FAMILY_RS400)) {
radeon_output->MonType = MT_CRT;
return XF86OutputStatusUnknown;
- } else if (info->IsIGP && radeon_output->type == OUTPUT_DVI_D) {
+ } else if ((info->ChipFamily == CHIP_FAMILY_RS400) &&
- radeon_output->type == OUTPUT_DVI) {
++ radeon_output->type == OUTPUT_DVI_D) {
radeon_output->MonType = MT_DFP; /* MT_LCD ??? */
return XF86OutputStatusUnknown;
}
@@@ -2799,17 -2675,17 +2812,17 @@@ static Bool RADEONSetupAppleConnectors(
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].ddc_line = 0;
info->BiosConnector[2].valid = TRUE;
return TRUE;
- case RADEON_MAC_POWERBOOK_DL:
+ case RADEON_MAC_POWERBOOK_EXTERNAL:
- info->BiosConnector[0].DDCType = DDC_DVI;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_PRIMARY;
info->BiosConnector[1].TMDSType = TMDS_EXT;
info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
@@@ -2818,17 -2694,17 +2831,18 @@@
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].ddc_line = 0;
info->BiosConnector[2].valid = TRUE;
return TRUE;
- case RADEON_MAC_POWERBOOK:
++
+ case RADEON_MAC_POWERBOOK_INTERNAL:
- info->BiosConnector[0].DDCType = DDC_DVI;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_PRIMARY;
info->BiosConnector[1].TMDSType = TMDS_INT;
info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
@@@ -2837,11 -2713,30 +2851,30 @@@
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].ddc_line = 0;
info->BiosConnector[2].valid = TRUE;
return TRUE;
- case RADEON_MAC_MINI:
+ case RADEON_MAC_POWERBOOK_VGA:
- info->BiosConnector[0].DDCType = DDC_DVI;
++ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
+ info->BiosConnector[0].DACType = DAC_NONE;
+ info->BiosConnector[0].TMDSType = TMDS_NONE;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[0].valid = TRUE;
+
- info->BiosConnector[1].DDCType = DDC_VGA;
++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].DACType = DAC_PRIMARY;
+ info->BiosConnector[1].TMDSType = TMDS_INT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[1].valid = TRUE;
+
+ info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
+ info->BiosConnector[2].DACType = DAC_TVDAC;
+ info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
++ info->BiosConnector[2].ddc_line = 0;
+ info->BiosConnector[2].valid = TRUE;
+ return TRUE;
+ case RADEON_MAC_MINI_EXTERNAL:
- info->BiosConnector[0].DDCType = DDC_CRT2;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC;
info->BiosConnector[0].DACType = DAC_TVDAC;
info->BiosConnector[0].TMDSType = TMDS_EXT;
info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
@@@ -2850,9 -2745,22 +2883,22 @@@
info->BiosConnector[1].ConnectorType = CONNECTOR_STV;
info->BiosConnector[1].DACType = DAC_TVDAC;
info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[1].ddc_line = 0;
info->BiosConnector[1].valid = TRUE;
return TRUE;
+ case RADEON_MAC_MINI_INTERNAL:
- info->BiosConnector[0].DDCType = DDC_CRT2;
++ info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC;
+ info->BiosConnector[0].DACType = DAC_TVDAC;
+ info->BiosConnector[0].TMDSType = TMDS_INT;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[0].valid = TRUE;
+
+ info->BiosConnector[1].ConnectorType = CONNECTOR_STV;
+ info->BiosConnector[1].DACType = DAC_TVDAC;
+ info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].DDCType = DDC_NONE_DETECTED;
++ info->BiosConnector[1].ddc_line = 0;
+ info->BiosConnector[1].valid = TRUE;
+ return TRUE;
default:
return FALSE;
}
@@@ -2909,96 -2864,19 +2955,104 @@@ static void RADEONSetupGenericConnector
- if (info->InternalTVOut) {
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].ddc_line = 0;
+ info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT;
info->BiosConnector[2].valid = TRUE;
- }
+ } else {
+ if (info->IsMobility) {
+ /* Below is the most common setting, but may not be true */
+ if (info->IsIGP) {
+ info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK;
+ info->BiosConnector[0].DACType = DAC_UNKNOWN;
+ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
+ info->BiosConnector[0].valid = TRUE;
+
+ /* IGP only has TVDAC */
+ if (info->ChipFamily == CHIP_FAMILY_RS400)
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_CRT2_DDC;
+ else
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].DACType = DAC_TVDAC;
+ info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[1].valid = TRUE;
+ } else {
+#if defined(__powerpc__)
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
+#else
+ info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK;
+#endif
+ info->BiosConnector[0].DACType = DAC_UNKNOWN;
+ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
+ info->BiosConnector[0].valid = TRUE;
+
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].DACType = DAC_PRIMARY;
+ info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[1].valid = TRUE;
+ }
+ } else {
+ /* Below is the most common setting, but may not be true */
+ if (info->IsIGP) {
+ if (info->ChipFamily == CHIP_FAMILY_RS400)
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC;
+ else
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[0].DACType = DAC_TVDAC;
+ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[0].valid = TRUE;
+
+ /* not sure what a good default DDCType for DVI on
+ * IGP desktop chips is
+ */
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_MONID; /* DDC_DVI? */
+ info->BiosConnector[1].DACType = DAC_UNKNOWN;
+ info->BiosConnector[1].TMDSType = TMDS_EXT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_D;
+ info->BiosConnector[1].valid = TRUE;
+ } else {
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
+ info->BiosConnector[0].DACType = DAC_TVDAC;
+ info->BiosConnector[0].TMDSType = TMDS_INT;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[0].valid = TRUE;
- /* Some cards have the DDC lines swapped and we have no way to
- * detect it yet (Mac cards)
- */
- if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
- info->BiosConnector[0].DDCType = DDC_VGA;
- info->BiosConnector[1].DDCType = DDC_DVI;
- }
++#if defined(__powerpc__)
++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
++ info->BiosConnector[1].DACType = DAC_PRIMARY;
++ info->BiosConnector[1].TMDSType = TMDS_EXT;
++ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
++ info->BiosConnector[1].valid = TRUE;
++#else
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].DACType = DAC_PRIMARY;
+ info->BiosConnector[1].TMDSType = TMDS_EXT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[1].valid = TRUE;
++#endif
+ }
+ }
+
+ if (info->InternalTVOut) {
+ info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
+ info->BiosConnector[2].DACType = DAC_TVDAC;
+ info->BiosConnector[2].TMDSType = TMDS_NONE;
+ info->BiosConnector[2].ddc_line = 0;
+ info->BiosConnector[2].valid = TRUE;
+ }
+ /* Some cards have the DDC lines swapped and we have no way to
+ * detect it yet (Mac cards)
+ */
+ if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_DVI_DDC;
+ }
+ }
}
#if defined(__powerpc__)
commit d9858a2b3744b99003cfb9f31b743a2d31b322e9
Author: Dave Airlie <airlied at linux.ie>
Date: Sat Dec 1 06:49:59 2007 +1000
radeon: add in pll spread spectrum workaround
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index a2f0291..5c2d261 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -229,6 +229,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
int sclock = mode->Clock;
uint16_t ref_div = 0, fb_div = 0;
@@ -241,7 +242,17 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
RADEONSavePtr save = &info->ModeReg;
if (IS_AVIVO_VARIANT) {
+ CARD32 temp;
PLLCalculate(crtc->scrn, sclock, &ref_div, &fb_div, &post_div);
+
+ /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
+ if (radeon_crtc->crtc_id == 0) {
+ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ } else {
+ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ }
} else {
sclock = save->dot_clock_freq * 10;
fb_div = save->feedback_div;
commit e1945f1f25a34310bd58ce128c8ff27ecc985618
Merge: b368b0f... df7777b...
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 30 14:30:55 2007 -0500
Merge branch 'atombios-support' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
commit b368b0f22cd1d7ef9b4c65d82929c76f3b82d573
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 30 14:29:27 2007 -0500
RADEON: disable atom pll set for r4xx cards
the clocks do not get set correctly in all cases. this needs
further investigation.
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index c4a5d11..57fad39 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -907,18 +907,18 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
ErrorF("restore crtc1\n");
RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
ErrorF("restore pll1\n");
- if (info->IsAtomBios)
+ /*if (info->IsAtomBios)
atombios_crtc_set_pll(crtc, adjusted_mode);
- else
+ else*/
RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
break;
case 1:
ErrorF("restore crtc2\n");
RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg);
ErrorF("restore pll2\n");
- if (info->IsAtomBios)
+ /*if (info->IsAtomBios)
atombios_crtc_set_pll(crtc, adjusted_mode);
- else
+ else*/
RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
break;
}
commit 5af15739571c09260750bcfd3620e16fd7fec862
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 30 14:24:30 2007 -0500
RADEON: small cleanup of pll code
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 0609bb5..a2f0291 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -240,10 +240,10 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
unsigned char *space;
RADEONSavePtr save = &info->ModeReg;
- sclock = mode->Clock;
if (IS_AVIVO_VARIANT) {
- PLLCalculate(crtc->scrn, mode->Clock, &ref_div, &fb_div, &post_div);
+ PLLCalculate(crtc->scrn, sclock, &ref_div, &fb_div, &post_div);
} else {
+ sclock = save->dot_clock_freq * 10;
fb_div = save->feedback_div;
post_div = save->post_div;
ref_div = save->ppll_ref_div;
commit df7777bff40c1feabcc12d2148ad6ac5213efbb3
Author: George Wu <geo at ocf.berkeley.edu>
Date: Fri Nov 30 17:49:33 2007 +1000
Add LVTMA PWRSEQ registers to fix VT switching for LVDS
diff --git a/src/radeon.h b/src/radeon.h
index ed99be7..b814b10 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -276,6 +276,9 @@ struct avivo_state
CARD32 crtc_master_en;
CARD32 crtc_tv_control;
+ CARD32 lvtma_pwrseq_cntl;
+ CARD32 lvtma_pwrseq_state;
+
struct avivo_pll_state pll1;
struct avivo_pll_state pll2;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 2e49d81..507b700 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -5520,6 +5520,9 @@ void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->tmds2.transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE);
state->tmds2.transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL);
+ state->lvtma_pwrseq_cntl = INREG(AVIVO_LVTMA_PWRSEQ_CNTL);
+ state->lvtma_pwrseq_state = INREG(AVIVO_LVTMA_PWRSEQ_STATE);
+
if (state->crtc1.control & AVIVO_CRTC_EN)
info->crtc_on = TRUE;
@@ -5658,6 +5661,9 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
OUTREG(AVIVO_LVTMA_SOURCE_SELECT, state->tmds2.source_select);
+
+ OUTREG(AVIVO_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
+ OUTREG(AVIVO_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
commit 017c939cf0a2b12fbdc1681cc70c28b23ae3b397
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Nov 29 02:52:14 2007 -0500
RADEON: implement CLUT adjust support
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 9192a9e..c4a5d11 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -980,8 +980,25 @@ void radeon_crtc_load_lut(xf86CrtcPtr crtc)
if (!crtc->enabled)
return;
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
+
+ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
+
+ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff);
+ }
+
PAL_SELECT(radeon_crtc->crtc_id);
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_DC_LUT_RW_MODE, 0);
+ OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
+ }
+
for (i = 0; i < 256; i++) {
OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]);
}
@@ -995,13 +1012,8 @@ radeon_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green,
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
int i, j;
- // fix me
- if (IS_AVIVO_VARIANT)
- return;
-
if (pScrn->depth == 16) {
for (i = 0; i < 64; i++) {
if (i <= 31) {
diff --git a/src/radeon_macros.h b/src/radeon_macros.h
index 4359eb8..7f532a8 100644
--- a/src/radeon_macros.h
+++ b/src/radeon_macros.h
@@ -92,12 +92,20 @@ do { \
#define OUTPAL_START(idx) \
do { \
- OUTREG8(RADEON_PALETTE_INDEX, (idx)); \
+ if (IS_AVIVO_VARIANT) { \
+ OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \
+ } else { \
+ OUTREG8(RADEON_PALETTE_INDEX, (idx)); \
+ } \
} while (0)
#define OUTPAL_NEXT(r, g, b) \
do { \
- OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
+ if (IS_AVIVO_VARIANT) { \
+ OUTREG(AVIVO_DC_LUT_30_COLOR, ((r) << 22) | ((g) << 12) | ((b) << 2)); \
+ } else { \
+ OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
+ } \
} while (0)
#define OUTPAL_NEXT_CARD32(v) \
@@ -113,20 +121,39 @@ do { \
#define INPAL_START(idx) \
do { \
- OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \
+ if (IS_AVIVO_VARIANT) { \
+ OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \
+ } else { \
+ OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \
+ } \
} while (0)
-#define INPAL_NEXT() INREG(RADEON_PALETTE_DATA)
+#define INPAL_NEXT() \
+do { \
+ if (IS_AVIVO_VARIANT) { \
+ INREG(AVIVO_DC_LUT_30_COLOR); \
+ } else { \
+ INREG(RADEON_PALETTE_DATA); \
+ } \
+} while (0)
#define PAL_SELECT(idx) \
do { \
- if (!idx) { \
- OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \
- (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \
- } else { \
- OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \
- RADEON_DAC2_PALETTE_ACC_CTL); \
- } \
+ if (IS_AVIVO_VARIANT) { \
+ if (!idx) { \
+ OUTREG(AVIVO_DC_LUT_RW_SELECT, 0); \
+ } else { \
+ OUTREG(AVIVO_DC_LUT_RW_SELECT, 1); \
+ } \
+ } else { \
+ if (!idx) { \
+ OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \
+ (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \
+ } else { \
+ OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \
+ RADEON_DAC2_PALETTE_ACC_CTL); \
+ } \
+ } \
} while (0)
#define INMC(pScrn, addr) RADEONINMC(pScrn, addr)
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 1860fa4..8737d2e 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3402,6 +3402,25 @@
#define AVIVO_D1CUR_POSITION 0x6414
#define AVIVO_D1CUR_HOT_SPOT 0x6418
+#define AVIVO_DC_LUT_RW_SELECT 0x6480
+#define AVIVO_DC_LUT_RW_MODE 0x6484
+#define AVIVO_DC_LUT_RW_INDEX 0x6488
+#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
+#define AVIVO_DC_LUT_PWL_DATA 0x6490
+#define AVIVO_DC_LUT_30_COLOR 0x6494
+#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
+#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
+#define AVIVO_DC_LUT_AUTOFILL 0x64a0
+
+#define AVIVO_DC_LUTA_CONTROL 0x64c0
+#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
+#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
+#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
+#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
+#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
+#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
+
+
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
commit 9963b0fe01feb6dd0cb555b874a48f6fa3b255cb
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Nov 29 00:46:23 2007 -0500
RADEON: fix cursor offset on avivo chips
diff --git a/src/radeon.h b/src/radeon.h
index ab6c0b3..ed99be7 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -945,12 +945,6 @@ typedef struct {
unsigned long FbFreeStart, FbFreeSize;
unsigned char* BIOSCopy;
- int cursor_width;
- int cursor_height;
- int cursor_format;
- int cursor_x;
- int cursor_y;
-
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index a2cec55..282ffd8 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -102,7 +102,7 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable)
OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
info->fbLocation + info->cursor_offset);
OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
- ((info->cursor_width -1) << 16) | (info->cursor_height-1));
+ ((CURSOR_WIDTH - 1) << 16) | (CURSOR_HEIGHT - 1));
OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
}
@@ -192,17 +192,12 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
y *= 2;
if (IS_AVIVO_VARIANT) {
- if (x < 0)
- x = 0;
- if (y < 0)
- y = 0;
-
/* avivo cursor spans the full fb width */
x += crtc->x;
y += crtc->y;
- OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
- radeon_crtc->cursor_x = x;
- radeon_crtc->cursor_y = y;
+ OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16)
+ | (yorigin ? 0 : y));
+ OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
} else {
if (crtc_id == 0) {
OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index d3c4e52..1860fa4 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3400,6 +3400,7 @@
#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
#define AVIVO_D1CUR_SIZE 0x6410
#define AVIVO_D1CUR_POSITION 0x6414
+#define AVIVO_D1CUR_HOT_SPOT 0x6418
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
commit 6c56e3d7655b17e93e8823aefe34b05291104695
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 27 15:27:36 2007 -0500
RADEON: switch r4xx to atombios load detection
works great
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 6e0d0d0..d8ded6d 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -678,33 +678,25 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (radeon_output->MonType == MT_UNKNOWN) {
if (IS_AVIVO_VARIANT) {
- if (OUTPUT_IS_TV)
- radeon_output->MonType = MT_NONE;
- else {
- radeon_output->MonType = avivo_display_ddc_connected(pScrn, output);
- if (!radeon_output->MonType) {
- if (radeon_output->type == OUTPUT_LVDS)
- radeon_output->MonType = MT_LCD;
- else
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
- }
+ radeon_output->MonType = avivo_display_ddc_connected(pScrn, output);
+ if (!radeon_output->MonType) {
+ if (radeon_output->type == OUTPUT_LVDS)
+ radeon_output->MonType = MT_LCD;
+ else if (OUTPUT_IS_TV)
+ radeon_output->MonType = MT_NONE;
+ else
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
}
} else {
- if (OUTPUT_IS_TV) {
- if (info->InternalTVOut) {
- if (radeon_output->load_detection)
- radeon_output->MonType = legacy_dac_detect(pScrn, output);
- else
- radeon_output->MonType = MT_NONE;
- }
- } else {
- radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output);
+ radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output);
+ if (!radeon_output->MonType) {
+ if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI)
+ radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output);
if (!radeon_output->MonType) {
- if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI)
- radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output);
- if (!radeon_output->MonType) {
+ if (info->IsAtomBios)
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
+ else
radeon_output->MonType = legacy_dac_detect(pScrn, output);
- }
}
}
}
commit 7561242e5b79bc2798ca3aace2b79e1a36949488
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 27 14:50:36 2007 -0500
RADEON: re-org load detection for legacy chips
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 16aa1b8..6e0d0d0 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -636,6 +636,38 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
}
#endif
+static RADEONMonitorType
+legacy_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONMonitorType found = MT_NONE;
+
+ if (OUTPUT_IS_TV) {
+ if (info->InternalTVOut) {
+ if (radeon_output->load_detection)
+ found = radeon_detect_tv(pScrn);
+ else
+ found = MT_NONE;
+ }
+ } else {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ if (radeon_output->load_detection)
+ found = radeon_detect_primary_dac(pScrn, TRUE);
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ if (radeon_output->load_detection) {
+ if (info->ChipFamily == CHIP_FAMILY_R200)
+ found = radeon_detect_ext_dac(pScrn);
+ else
+ found = radeon_detect_tv_dac(pScrn, TRUE);
+ } else
+ found = MT_NONE;
+ }
+ }
+
+ return found;
+}
+
/* Primary Head (DVI or Laptop Int. panel)*/
/* A ddc capable display connected on DVI port */
/* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/
@@ -661,7 +693,7 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (OUTPUT_IS_TV) {
if (info->InternalTVOut) {
if (radeon_output->load_detection)
- radeon_output->MonType = radeon_detect_tv(pScrn);
+ radeon_output->MonType = legacy_dac_detect(pScrn, output);
else
radeon_output->MonType = MT_NONE;
}
@@ -671,18 +703,7 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI)
radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output);
if (!radeon_output->MonType) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- if (radeon_output->load_detection)
- radeon_output->MonType = radeon_detect_primary_dac(pScrn, TRUE);
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (radeon_output->load_detection) {
- if (info->ChipFamily == CHIP_FAMILY_R200)
- radeon_output->MonType = radeon_detect_ext_dac(pScrn);
- else
- radeon_output->MonType = radeon_detect_tv_dac(pScrn, TRUE);
- } else
- radeon_output->MonType = MT_NONE;
- }
+ radeon_output->MonType = legacy_dac_detect(pScrn, output);
}
}
}
@@ -1216,7 +1237,7 @@ legacy_mode_set(xf86OutputPtr output, DisplayModePtr mode,
ErrorF("restore FP2\n");
if (info->IsAtomBios)
atombios_external_tmds_setup(output, mode);
- else
+ else
RADEONRestoreDVOChip(pScrn, output);
RADEONRestoreFP2Registers(pScrn, &info->ModeReg);
}
commit febdcc2dccd42acbcd68ae630b7811cae5c58e8a
Author: Dave Airlie <airlied at linux.ie>
Date: Wed Nov 28 05:10:57 2007 +1000
legacy: fix fb/agp read/writes
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index cb77283..2e49d81 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -817,8 +817,10 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc,
OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc);
(void)INMC(pScrn, R520_MC_FB_LOCATION);
} else {
- OUTREG(RADEON_MC_FB_LOCATION, fb_loc);
- OUTREG(RADEON_MC_AGP_LOCATION, agp_loc);
+ if (mask & LOC_FB)
+ OUTREG(RADEON_MC_FB_LOCATION, fb_loc);
+ if (mask & LOC_AGP)
+ OUTREG(RADEON_MC_AGP_LOCATION, agp_loc);
}
}
@@ -849,8 +851,10 @@ void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc,
*agp_loc_hi = 0;
}
} else {
- *fb_loc = INREG(RADEON_MC_FB_LOCATION);
- *agp_loc = INREG(RADEON_MC_AGP_LOCATION);
+ if (mask & LOC_FB)
+ *fb_loc = INREG(RADEON_MC_FB_LOCATION);
+ if (mask & LOC_AGP)
+ *agp_loc = INREG(RADEON_MC_AGP_LOCATION);
}
}
commit bb8545146959b748994be055d5b3de66ec66c8b2
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Nov 26 17:34:51 2007 -0500
RADEON: first pass at TV/Component video
Untested and not likely to work just yet.
diff --git a/src/atombios_output.c b/src/atombios_output.c
index ecbfbdb..f84afd0 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -23,6 +23,7 @@
*
* Authors:
* Dave Airlie <airlied at redhat.com>
+ * Alex Deucher <alexdeucher at gmail.com>
*
*/
@@ -45,23 +46,48 @@
static int
atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode)
{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
AtomBiosArgRec data;
unsigned char *space;
disp_data.ucAction = 1;
- disp_data.ucDacStandard = 1;
+
+ if (radeon_output->MonType == MT_CRT)
+ disp_data.ucDacStandard = ATOM_DAC1_PS2;
+ else if (radeon_output->MonType == MT_CV)
+ disp_data.ucDacStandard = ATOM_DAC1_CV;
+ else if (OUTPUT_IS_TV) {
+ switch (radeon_output->tvStd) {
+ case TV_STD_NTSC:
+ case TV_STD_NTSC_J:
+ case TV_STD_PAL_60:
+ disp_data.ucDacStandard = ATOM_DAC1_NTSC;
+ break;
+ case TV_STD_PAL:
+ case TV_STD_PAL_M:
+ case TV_STD_SCART_PAL:
+ case TV_STD_SECAM:
+ case TV_STD_PAL_CN:
+ disp_data.ucDacStandard = ATOM_DAC1_PAL;
+ break;
+ default:
+ disp_data.ucDacStandard = ATOM_DAC1_NTSC;
+ break;
+ }
+ }
+
disp_data.usPixelClock = mode->Clock / 10;
data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
-
+
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Output DAC1 setup success\n");
return ATOM_SUCCESS;
}
-
+
ErrorF("Output DAC1 setup failed\n");
return ATOM_NOT_IMPLEMENTED;
@@ -70,28 +96,113 @@ atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode)
static int
atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode)
{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
AtomBiosArgRec data;
unsigned char *space;
disp_data.ucAction = 1;
- disp_data.ucDacStandard = 1;
+
+ if (radeon_output->MonType == MT_CRT)
+ disp_data.ucDacStandard = ATOM_DAC2_PS2;
+ else if (radeon_output->MonType == MT_CV)
+ disp_data.ucDacStandard = ATOM_DAC2_CV;
+ else if (OUTPUT_IS_TV) {
+ switch (radeon_output->tvStd) {
+ case TV_STD_NTSC:
+ case TV_STD_NTSC_J:
+ case TV_STD_PAL_60:
+ disp_data.ucDacStandard = ATOM_DAC2_NTSC;
+ break;
+ case TV_STD_PAL:
+ case TV_STD_PAL_M:
+ case TV_STD_SCART_PAL:
+ case TV_STD_SECAM:
+ case TV_STD_PAL_CN:
+ disp_data.ucDacStandard = ATOM_DAC2_PAL;
+ break;
+ default:
+ disp_data.ucDacStandard = ATOM_DAC2_NTSC;
+ break;
+ }
+ }
+
disp_data.usPixelClock = mode->Clock / 10;
data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
-
+
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Output DAC2 setup success\n");
return ATOM_SUCCESS;
}
-
+
ErrorF("Output DAC2 setup failed\n");
return ATOM_NOT_IMPLEMENTED;
}
+static int
+atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ TV_ENCODER_CONTROL_PS_ALLOCATION disp_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ disp_data.sTVEncoder.ucAction = 1;
+
+ if (radeon_output->MonType == MT_CV)
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_CV;
+ else {
+ switch (radeon_output->tvStd) {
+ case TV_STD_NTSC:
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
+ break;
+ case TV_STD_PAL:
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
+ break;
+ case TV_STD_PAL_M:
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
+ break;
+ case TV_STD_PAL_60:
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
+ break;
+ case TV_STD_NTSC_J:
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
+ break;
+ case TV_STD_SCART_PAL:
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
+ break;
+ case TV_STD_SECAM:
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
+ break;
+ case TV_STD_PAL_CN:
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
+ break;
+ default:
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
+ break;
+ }
+ }
+
+ disp_data.sTVEncoder.usPixelClock = mode->Clock / 10;
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output TV1 setup success\n");
+ return ATOM_SUCCESS;
+ }
+
+ ErrorF("Output TV1 setup failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+
+}
+
int
atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
{
@@ -251,6 +362,12 @@ atombios_device_dpms(xf86OutputPtr output, int device, int mode)
case ATOM_DEVICE_LCD1_SUPPORT:
index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
break;
+ case ATOM_DEVICE_TV1_SUPPORT:
+ index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
+ break;
+ case ATOM_DEVICE_CV_SUPPORT:
+ index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
+ break;
default:
return;
}
@@ -411,31 +528,51 @@ atombios_output_mode_set(xf86OutputPtr output,
} else if (radeon_output->MonType == MT_LCD) {
if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
atombios_output_lvds_setup(output, adjusted_mode);
+ } else if (OUTPUT_IS_TV || (radeon_output->MonType == MT_CV)) {
+ atombios_output_dac2_setup(output, adjusted_mode);
+ atombios_output_tv1_setup(output, adjusted_mode);
}
+
}
static AtomBiosResult
-atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, int dac)
+atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output)
{
- DAC_LOAD_DETECTION_PS_ALLOCATION dac_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- dac_data.sDacload.usDeviceID = 0;
- dac_data.sDacload.ucDacType = 0;
- dac_data.sDacload.ucMisc = 0;
-
- data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &dac_data;
-
- if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
-
- ErrorF("Dac detection success\n");
- return ATOM_SUCCESS ;
- }
-
- ErrorF("DAC detection failed\n");
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ DAC_LOAD_DETECTION_PS_ALLOCATION dac_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) {
+ dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT1_SUPPORT;
+ dac_data.sDacload.ucDacType = ATOM_DAC_A;
+ } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
+ dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT2_SUPPORT;
+ dac_data.sDacload.ucDacType = ATOM_DAC_B;
+ } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) {
+ dac_data.sDacload.usDeviceID = ATOM_DEVICE_CV_SUPPORT;
+ dac_data.sDacload.ucDacType = ATOM_DAC_B;
+ } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) {
+ dac_data.sDacload.usDeviceID = ATOM_DEVICE_TV1_SUPPORT;
+ dac_data.sDacload.ucDacType = ATOM_DAC_B;
+ } else {
+ ErrorF("invalid output device for dac detection\n");
+ return ATOM_NOT_IMPLEMENTED;
+ }
+
+ dac_data.sDacload.ucMisc = 0;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &dac_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+
+ ErrorF("Dac detection success\n");
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("DAC detection failed\n");
return ATOM_NOT_IMPLEMENTED;
}
@@ -449,19 +586,28 @@ atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
AtomBiosResult ret;
uint32_t bios_0_scratch;
- ret = atom_bios_dac_load_detect(info->atomBIOS, radeon_output->DACType);
+ ret = atom_bios_dac_load_detect(info->atomBIOS, output);
if (ret == ATOM_SUCCESS) {
- ErrorF("DAC connect %08X\n", (unsigned int)INREG(RADEON_BIOS_0_SCRATCH));
bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH);
-
+ ErrorF("DAC connect %08X\n", (unsigned int)bios_0_scratch);
+
if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) {
- if (bios_0_scratch & ATOM_S0_CRT1_COLOR)
+ if (bios_0_scratch & ATOM_S0_CRT1_MASK)
MonType = MT_CRT;
} else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
- if (bios_0_scratch & ATOM_S0_CRT2_COLOR)
+ if (bios_0_scratch & ATOM_S0_CRT2_MASK)
MonType = MT_CRT;
+ } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) {
+ if (bios_0_scratch & (ATOM_S0_CV_MASK | ATOM_S0_CV_MASK_A))
+ MonType = MT_CV;
+ } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) {
+ if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
+ MonType = MT_CTV;
+ else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
+ MonType = MT_STV;
}
}
+
return MonType;
}
diff --git a/src/radeon_output.c b/src/radeon_output.c
index faf3dc9..16aa1b8 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2187,6 +2187,12 @@ radeon_set_property(xf86OutputPtr output, Atom property,
} else if (value->size == strlen("scart-pal") && !strncmp("scart-pal", s, strlen("scart-pal"))) {
radeon_output->tvStd = TV_STD_SCART_PAL;
return TRUE;
+ } else if (value->size == strlen("pal-cn") && !strncmp("pal-cn", s, strlen("pal-cn"))) {
+ radeon_output->tvStd = TV_STD_PAL_CN;
+ return TRUE;
+ } else if (value->size == strlen("secam") && !strncmp("secam", s, strlen("secam"))) {
+ radeon_output->tvStd = TV_STD_SECAM;
+ return TRUE;
}
return FALSE;
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index c1a7913..0e325a6 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -164,6 +164,8 @@ typedef enum
TV_STD_PAL_60 = 8,
TV_STD_NTSC_J = 16,
TV_STD_SCART_PAL = 32,
+ TV_STD_SECAM = 64,
+ TV_STD_PAL_CN = 128,
} TVStd;
typedef struct _RADEONCrtcPrivateRec {
commit e2bde646b864dca9056d9ecfe23a0d905647ea9a
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Nov 26 14:35:57 2007 -0500
RADEON: move crtc output source selection into atombios_output.c
The function fits better as an output function and should now
work with clones as well.
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index dbb8b69..0609bb5 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -298,79 +298,6 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
return;
}
-static void
-atombios_set_crtc_source(xf86CrtcPtr crtc)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- AtomBiosArgRec data;
- unsigned char *space;
- SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
- int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
- int major, minor, i;
-
- atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
-
- ErrorF("select crtc source table is %d %d\n", major, minor);
-
- crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
- crtc_src_param.ucDevice = 0;
-
- for (i = 0; i < xf86_config->num_output; i++) {
- xf86OutputPtr output = xf86_config->output[i];
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- /* doesn't seem to support cloning via atom */
- if (output->crtc == crtc) {
- switch(major) {
- case 1: {
- switch(minor) {
- case 0:
- case 1:
- default:
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_CRT1_INDEX;
- else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_CRT2_INDEX;
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_DFP1_INDEX;
- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_DFP2_INDEX;
- else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_DFP3_INDEX;
- } else if (radeon_output->MonType == MT_LCD) {
- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_LCD1_INDEX;
- }
- break;
- }
- break;
- }
- default:
- break;
- }
- }
- }
-
- ErrorF("device sourced: 0x%x\n", crtc_src_param.ucDevice);
-
- data.exec.index = index;
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &crtc_src_param;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Set CRTC %d Source success\n", radeon_crtc->crtc_id);
- return;
- }
-
- ErrorF("Set CRTC Source failed\n");
- return;
-}
-
void
atombios_crtc_mode_set(xf86CrtcPtr crtc,
DisplayModePtr mode,
@@ -480,8 +407,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
- atombios_set_crtc_source(crtc);
-
if (info->tilingEnabled != tilingOld) {
/* need to redraw front buffer, I guess this can be considered a hack ? */
/* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
diff --git a/src/atombios_output.c b/src/atombios_output.c
index a6b4277..ecbfbdb 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -323,6 +323,70 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
#endif
}
+static void
+atombios_set_output_crtc_source(xf86OutputPtr output)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ AtomBiosArgRec data;
+ unsigned char *space;
+ SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
+ int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
+ int major, minor;
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ ErrorF("select crtc source table is %d %d\n", major, minor);
+
+ crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
+ crtc_src_param.ucDevice = 0;
+
+ switch(major) {
+ case 1: {
+ switch(minor) {
+ case 0:
+ case 1:
+ default:
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_CRT1_INDEX;
+ else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_CRT2_INDEX;
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_DFP1_INDEX;
+ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_DFP2_INDEX;
+ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_DFP3_INDEX;
+ } else if (radeon_output->MonType == MT_LCD) {
+ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_LCD1_INDEX;
+ }
+ break;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ ErrorF("device sourced: 0x%x\n", crtc_src_param.ucDevice);
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_src_param;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC %d Source success\n", radeon_crtc->crtc_id);
+ return;
+ }
+
+ ErrorF("Set CRTC Source failed\n");
+ return;
+}
+
void
atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr mode,
@@ -330,6 +394,8 @@ atombios_output_mode_set(xf86OutputPtr output,
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ atombios_set_output_crtc_source(output);
+
if (radeon_output->MonType == MT_CRT) {
if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
atombios_output_dac1_setup(output, adjusted_mode);
commit 16c9be4107678a2a58d3418b7f1cc94d695ca8d6
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Nov 26 14:20:54 2007 -0500
RADEON: add default connector table for avivo chips
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 678e4d7..faf3dc9 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -46,7 +46,7 @@
#include "radeon_probe.h"
#include "radeon_version.h"
#include "radeon_tv.h"
-
+#include "radeon_atombios.h"
const char *MonTypeName[7] = {
"AUTO",
@@ -2856,92 +2856,130 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
return;
}
- if (info->IsMobility) {
- /* Below is the most common setting, but may not be true */
- if (info->IsIGP) {
- info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK;
- info->BiosConnector[0].DACType = DAC_UNKNOWN;
- info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
- info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
- info->BiosConnector[0].valid = TRUE;
-
- /* IGP only has TVDAC */
- if (info->ChipFamily == CHIP_FAMILY_RS400)
- info->BiosConnector[1].ddc_line = RADEON_GPIO_CRT2_DDC;
- else
- info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
- info->BiosConnector[1].DACType = DAC_TVDAC;
- info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
- info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[1].valid = TRUE;
- } else {
-#if defined(__powerpc__)
- info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
-#else
- info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK;
-#endif
- info->BiosConnector[0].DACType = DAC_UNKNOWN;
- info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
+ if (IS_AVIVO_VARIANT) {
+ if (info->IsMobility) {
+ info->BiosConnector[0].ddc_line = 0x7e60;
+ info->BiosConnector[0].DACType = DAC_NONE;
+ info->BiosConnector[0].TMDSType = TMDS_NONE;
info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
+ info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].ddc_line = 0x7e40;
info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[1].TMDSType = TMDS_NONE;
info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[1].valid = TRUE;
- }
- } else {
- /* Below is the most common setting, but may not be true */
- if (info->IsIGP) {
- if (info->ChipFamily == CHIP_FAMILY_RS400)
- info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC;
- else
- info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
- info->BiosConnector[0].DACType = DAC_TVDAC;
- info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
- info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[0].valid = TRUE;
-
- /* not sure what a good default DDCType for DVI on
- * IGP desktop chips is
- */
- info->BiosConnector[1].ddc_line = RADEON_GPIO_MONID; /* DDC_DVI? */
- info->BiosConnector[1].DACType = DAC_UNKNOWN;
- info->BiosConnector[1].TMDSType = TMDS_EXT;
- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_D;
+ info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT;
info->BiosConnector[1].valid = TRUE;
} else {
- info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
+ info->BiosConnector[0].ddc_line = 0x7e50;
info->BiosConnector[0].DACType = DAC_TVDAC;
info->BiosConnector[0].TMDSType = TMDS_INT;
info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].ddc_line = 0x7e40;
info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_EXT;
+ info->BiosConnector[1].TMDSType = TMDS_NONE;
info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT;
info->BiosConnector[1].valid = TRUE;
}
- }
- if (info->InternalTVOut) {
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
info->BiosConnector[2].ddc_line = 0;
+ info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT;
info->BiosConnector[2].valid = TRUE;
- }
+ } else {
+ if (info->IsMobility) {
+ /* Below is the most common setting, but may not be true */
+ if (info->IsIGP) {
+ info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK;
+ info->BiosConnector[0].DACType = DAC_UNKNOWN;
+ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
+ info->BiosConnector[0].valid = TRUE;
+
+ /* IGP only has TVDAC */
+ if (info->ChipFamily == CHIP_FAMILY_RS400)
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_CRT2_DDC;
+ else
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].DACType = DAC_TVDAC;
+ info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[1].valid = TRUE;
+ } else {
+#if defined(__powerpc__)
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
+#else
+ info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK;
+#endif
+ info->BiosConnector[0].DACType = DAC_UNKNOWN;
+ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
+ info->BiosConnector[0].valid = TRUE;
- /* Some cards have the DDC lines swapped and we have no way to
- * detect it yet (Mac cards)
- */
- if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
- info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
- info->BiosConnector[1].ddc_line = RADEON_GPIO_DVI_DDC;
- }
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].DACType = DAC_PRIMARY;
+ info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[1].valid = TRUE;
+ }
+ } else {
+ /* Below is the most common setting, but may not be true */
+ if (info->IsIGP) {
+ if (info->ChipFamily == CHIP_FAMILY_RS400)
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC;
+ else
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[0].DACType = DAC_TVDAC;
+ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[0].valid = TRUE;
+
+ /* not sure what a good default DDCType for DVI on
+ * IGP desktop chips is
+ */
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_MONID; /* DDC_DVI? */
+ info->BiosConnector[1].DACType = DAC_UNKNOWN;
+ info->BiosConnector[1].TMDSType = TMDS_EXT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_D;
+ info->BiosConnector[1].valid = TRUE;
+ } else {
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
+ info->BiosConnector[0].DACType = DAC_TVDAC;
+ info->BiosConnector[0].TMDSType = TMDS_INT;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[0].valid = TRUE;
+
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].DACType = DAC_PRIMARY;
+ info->BiosConnector[1].TMDSType = TMDS_EXT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[1].valid = TRUE;
+ }
+ }
+ if (info->InternalTVOut) {
+ info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
+ info->BiosConnector[2].DACType = DAC_TVDAC;
+ info->BiosConnector[2].TMDSType = TMDS_NONE;
+ info->BiosConnector[2].ddc_line = 0;
+ info->BiosConnector[2].valid = TRUE;
+ }
+
+ /* Some cards have the DDC lines swapped and we have no way to
+ * detect it yet (Mac cards)
+ */
+ if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_DVI_DDC;
+ }
+ }
}
#if defined(__powerpc__)
commit 4e792db655dc92d2864db36b4d8f6714908de8e8
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Nov 23 15:44:44 2007 +1000
r500: set default minimum pll freq
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 732eab1..dbb8b69 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -151,6 +151,8 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_
/*
* Calculate the PLL parameters for a given dotclock.
*/
+#define RADEON_PLL_DEFAULT_PLLOUT_MIN 64800 /* experimental. - taken from rhd divided by 10 */
+
static Bool
PLLCalculate(ScrnInfoPtr pScrn, CARD32 PixelClock,
CARD16 *RefDivider, CARD16 *FBDivider, CARD8 *PostDivider)
@@ -166,6 +168,8 @@ PLLCalculate(ScrnInfoPtr pScrn, CARD32 PixelClock,
Ratio = ((float) PixelClock) / ((float) pll->reference_freq * 10);
+ if (pll->min_pll_freq == 0)
+ pll->min_pll_freq = RADEON_PLL_DEFAULT_PLLOUT_MIN;
for (PostDiv = 2; PostDiv < POST_DIV_LIMIT; PostDiv++) {
CARD32 VCOOut = PixelClock * PostDiv;
commit a13b4c69c105c096dd05e6de2c5c154c9a8bcc71
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Nov 23 15:25:06 2007 +1000
r5xx: cleanup pll code..
Clean the PLL code to use the radeon pll structs.
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 2bd4902..732eab1 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -148,62 +148,31 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_
return ATOM_NOT_IMPLEMENTED;
}
-#define USE_RADEONHD_CODE_FOR_PLL 1
-#if USE_RADEONHD_CODE_FOR_PLL
-
-struct rhdPLL {
- int scrnIndex;
-
-/* also used as an index to rhdPtr->PLLs */
-#define PLL_ID_PLL1 0
-#define PLL_ID_PLL2 1
-#define PLL_ID_NONE -1
- int Id;
-
- CARD32 CurrentClock;
- Bool Active;
-
- /* from defaults or from atom */
- CARD32 RefClock;
- CARD32 InMin;
- CARD32 InMax;
- CARD32 OutMin;
- CARD32 OutMax;
- CARD32 PixMin;
- CARD32 PixMax;
-};
-
-static struct rhdPLL mypll = {
- 0, 0, 0, 0,
- 27000,
- 1000, 13500,
- 600000, 1100000,
- 16000, 400000
-};
/*
* Calculate the PLL parameters for a given dotclock.
*/
static Bool
-PLLCalculate(CARD32 PixelClock,
+PLLCalculate(ScrnInfoPtr pScrn, CARD32 PixelClock,
CARD16 *RefDivider, CARD16 *FBDivider, CARD8 *PostDivider)
{
/* limited by the number of bits available */
#define FB_DIV_LIMIT 1024 /* rv6x0 doesn't like 2048 */
#define REF_DIV_LIMIT 1024
#define POST_DIV_LIMIT 128
- struct rhdPLL *PLL = &mypll;
+ RADEONInfoPtr info = RADEONPTR (pScrn);
+ RADEONPLLPtr pll = &info->pll;
CARD32 FBDiv, RefDiv, PostDiv, BestDiff = 0xFFFFFFFF;
float Ratio;
- Ratio = ((float) PixelClock) / ((float) PLL->RefClock);
+ Ratio = ((float) PixelClock) / ((float) pll->reference_freq * 10);
for (PostDiv = 2; PostDiv < POST_DIV_LIMIT; PostDiv++) {
CARD32 VCOOut = PixelClock * PostDiv;
/* we are conservative and avoid the limits */
- if (VCOOut <= PLL->OutMin)
+ if (VCOOut <= pll->min_pll_freq * 10)
continue;
- if (VCOOut >= PLL->OutMax)
+ if (VCOOut >= pll->max_pll_freq * 10)
break;
for (RefDiv = 1; RefDiv <= REF_DIV_LIMIT; RefDiv++)
@@ -218,7 +187,7 @@ PLLCalculate(CARD32 PixelClock,
if (FBDiv > (500 + (13 * RefDiv))) /* rv6x0 limit */
break;
- Diff = abs( PixelClock - (FBDiv * PLL->RefClock) / (PostDiv * RefDiv) );
+ Diff = abs( PixelClock - (FBDiv * pll->reference_freq * 10) / (PostDiv * RefDiv) );
if (Diff < BestDiff) {
*FBDivider = FBDiv;
@@ -237,23 +206,19 @@ PLLCalculate(CARD32 PixelClock,
if (BestDiff != 0xFFFFFFFF) {
ErrorF("PLL Calculation: %dkHz = "
"(((0x%X / 0x%X) * 0x%X) / 0x%X) (%dkHz off)\n",
- (int) PixelClock, (unsigned int) PLL->RefClock, *RefDivider,
+ (int) PixelClock, (unsigned int) pll->reference_freq * 10, *RefDivider,
*FBDivider, *PostDivider, (int) BestDiff);
- xf86DrvMsg(PLL->scrnIndex, X_INFO, "PLL for %dkHz uses %dkHz internally.\n",
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PLL for %dkHz uses %dkHz internally.\n",
(int) PixelClock,
- (int) (PLL->RefClock * *FBDivider) / *RefDivider);
+ (int) (pll->reference_freq * 10 * *FBDivider) / *RefDivider);
return TRUE;
} else { /* Should never happen */
- xf86DrvMsg(PLL->scrnIndex, X_ERROR,
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"%s: Failed to get a valid PLL setting for %dkHz\n",
__func__, (int) PixelClock);
return FALSE;
}
}
-#else // avivo code
-
-
-#endif
void
atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
@@ -273,7 +238,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
sclock = mode->Clock;
if (IS_AVIVO_VARIANT) {
- PLLCalculate(mode->Clock, &ref_div, &fb_div, &post_div);
+ PLLCalculate(crtc->scrn, mode->Clock, &ref_div, &fb_div, &post_div);
} else {
fb_div = save->feedback_div;
post_div = save->post_div;
commit 5d792b5673bbf4784eb0ec059221e9b57232a122
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Nov 23 15:03:13 2007 +1000
radeon: fix up memory mapping issues for vt switch
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 9615b20..2bd4902 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -454,8 +454,10 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
+ RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info);
+ RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg);
+
if (IS_AVIVO_VARIANT) {
- RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg);
radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay;
radeon_crtc->fb_height = pScrn->virtualY;
radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay;
@@ -481,7 +483,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
if (radeon_crtc->crtc_id == 0)
OUTREG(AVIVO_D1VGA_CONTROL, 0);
else
- OUTREG(AVIVO_D1VGA_CONTROL, 0);
+ OUTREG(AVIVO_D2VGA_CONTROL, 0);
/* setup fb format and location
*/
@@ -502,6 +504,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
crtc->scrn->displayWidth);
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+
}
atombios_crtc_set_pll(crtc, adjusted_mode);
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 51d41b9..cb77283 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -790,6 +790,70 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
}
}
+#define LOC_FB 0x1
+#define LOC_AGP 0x2
+void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, CARD32 agp_loc, CARD32 agp_loc_hi)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (mask & LOC_FB)
+ OUTREG(R600_MC_VM_FB_LOCATION, fb_loc);
+ if (mask & LOC_AGP) {
+ OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
+ OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
+ }
+ } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ if (mask & LOC_FB)
+ OUTMC(pScrn, RV515_MC_FB_LOCATION, fb_loc);
+ if (mask & LOC_AGP)
+ OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc);
+ (void)INMC(pScrn, RV515_MC_AGP_LOCATION);
+ } else if (info->ChipFamily >= CHIP_FAMILY_R520) {
+ if (mask & LOC_FB)
+ OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc);
+ if (mask & LOC_AGP)
+ OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc);
+ (void)INMC(pScrn, R520_MC_FB_LOCATION);
+ } else {
+ OUTREG(RADEON_MC_FB_LOCATION, fb_loc);
+ OUTREG(RADEON_MC_AGP_LOCATION, agp_loc);
+ }
+}
+
+void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, CARD32 *agp_loc, CARD32 *agp_loc_hi)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (mask & LOC_FB)
+ *fb_loc = INREG(R600_MC_VM_FB_LOCATION);
+ if (mask & LOC_AGP) {
+ *agp_loc = INREG(R600_MC_VM_AGP_BOT);
+ *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
+ }
+ } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ if (mask & LOC_FB)
+ *fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION);
+ if (mask & LOC_AGP) {
+ *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION);
+ *agp_loc_hi = 0;
+ }
+ } else if (info->ChipFamily >= CHIP_FAMILY_R520) {
+ if (mask & LOC_FB)
+ *fb_loc = INMC(pScrn, R520_MC_FB_LOCATION);
+ if (mask & LOC_AGP) {
+ *agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION);
+ *agp_loc_hi = 0;
+ }
+ } else {
+ *fb_loc = INREG(RADEON_MC_FB_LOCATION);
+ *agp_loc = INREG(RADEON_MC_AGP_LOCATION);
+ }
+}
+
#if 0
/* Read PAL information (only used for debugging) */
static int RADEONINPAL(int idx)
@@ -1256,12 +1320,12 @@ static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
RADEONInfoPtr info)
{
+ save->mc_fb_location = info->mc_fb_location;
+ save->mc_agp_location = info->mc_agp_location;
+
if (IS_AVIVO_VARIANT) {
- save->mc_fb_location = info->mc_fb_location;
- save->mc_agp_location = info->mc_agp_location;
+ save->mc_agp_location_hi = info->mc_agp_location_hi;
} else {
- save->mc_fb_location = info->mc_fb_location;
- save->mc_agp_location = info->mc_agp_location;
save->display_base_addr = info->fbLocation;
save->display2_base_addr = info->fbLocation;
save->ov0_base_addr = info->fbLocation;
@@ -1275,22 +1339,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
CARD32 mem_size;
CARD32 aper_size;
- if (IS_AVIVO_VARIANT) {
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- info->mc_fb_location = INREG(R600_MC_VM_FB_LOCATION);
- info->mc_agp_location = 0xffffffc0;
- } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
- info->mc_fb_location = INMC(pScrn, RV515_MC_FB_LOCATION);
- info->mc_agp_location = INMC(pScrn, RV515_MC_AGP_LOCATION);
- } else {
- info->mc_fb_location = INMC(pScrn, R520_MC_FB_LOCATION);
- info->mc_agp_location = INMC(pScrn, R520_MC_AGP_LOCATION);
- }
- } else {
- /* Default to existing values */
- info->mc_fb_location = INREG(RADEON_MC_FB_LOCATION);
- info->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION);
- }
+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location,
+ &info->mc_agp_location, &info->mc_agp_location_hi);
/* We shouldn't use info->videoRam here which might have been clipped
* but the real video RAM instead
@@ -1374,11 +1424,12 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
/* Just disable the damn AGP apertures for now, it may be
* re-enabled later by the DRM
*/
- info->mc_agp_location = 0xffffffc0;
if (IS_AVIVO_VARIANT) {
OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
- }
+ info->mc_agp_location = 0x003f0000;
+ } else
+ info->mc_agp_location = 0xffffffc0;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONInitMemoryMap() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -3759,40 +3810,31 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
int timeout;
+ CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi;
+
+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc,
+ &mc_agp_loc, &mc_agp_loc_hi);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONRestoreMemMapRegisters() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_FB_LOCATION : 0x%08x\n",
- (unsigned)info->mc_fb_location);
+ " MC_FB_LOCATION : 0x%08x 0x%08x\n",
+ (unsigned)restore->mc_fb_location, mc_fb_loc);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
" MC_AGP_LOCATION : 0x%08x\n",
(unsigned)restore->mc_agp_location);
if (IS_AVIVO_VARIANT) {
- CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi = 0;
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- mc_fb_loc = INREG(R600_MC_VM_FB_LOCATION);
- mc_agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
- mc_agp_loc = INREG(R600_MC_VM_AGP_BOT);
- } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
- mc_fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION);
- mc_agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION);
- } else {
- mc_fb_loc = INMC(pScrn, R520_MC_FB_LOCATION);
- mc_agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION);
- }
-#if 1
- /* disable VGA CTRL */
- OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
- OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
-#endif
- if (mc_fb_loc != info->mc_fb_location ||
- mc_agp_loc != info->mc_agp_location) {
+
+ if (mc_fb_loc != restore->mc_fb_location ||
+ mc_agp_loc != restore->mc_agp_location) {
CARD32 tmp;
RADEONWaitForIdleMMIO(pScrn);
+ OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+ OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+
/* Stop display & memory access */
tmp = INREG(AVIVO_D1CRTC_CONTROL);
OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
@@ -3820,19 +3862,13 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
usleep(10);
}
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_MC_VM_FB_LOCATION, info->mc_fb_location);
- } else {
- if (info->ChipFamily == CHIP_FAMILY_RV515) {
- OUTMC(pScrn, RV515_MC_FB_LOCATION, info->mc_fb_location);
- OUTMC(pScrn, RV515_MC_AGP_LOCATION, 0x003f0000);
- (void)INMC(pScrn, RV515_MC_AGP_LOCATION);
- } else {
- OUTMC(pScrn, R520_MC_FB_LOCATION, info->mc_fb_location);
- OUTMC(pScrn, R520_MC_AGP_LOCATION, 0x003f0000);
- (void)INMC(pScrn, R520_MC_FB_LOCATION);
- }
- OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
+ radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP,
+ restore->mc_fb_location,
+ restore->mc_agp_location,
+ restore->mc_agp_location_hi);
+
+ if (info->ChipFamily < CHIP_FAMILY_R600) {
+ OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location);
}
/* Reset the engine and HDP */
@@ -3844,8 +3880,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
* since we must ensure no access is done while they are
* reprogrammed
*/
- if (INREG(RADEON_MC_FB_LOCATION) != restore->mc_fb_location ||
- INREG(RADEON_MC_AGP_LOCATION) != restore->mc_agp_location) {
+ if (mc_fb_loc != restore->mc_fb_location ||
+ mc_agp_loc != restore->mc_agp_location) {
CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl;
CARD32 old_mc_status, status_idle;
@@ -3918,8 +3954,11 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
*/
OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc);
OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location);
+ radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location,
+ 0xfffffffc, 0);
igp_no_mcfb:
- OUTREG(RADEON_MC_AGP_LOCATION, restore->mc_agp_location);
+ radeon_write_mc_fb_agp_location(pScrn, LOC_AGP, 0,
+ restore->mc_agp_location, 0);
/* Make sure map fully reached the chip */
(void)INREG(RADEON_MC_FB_LOCATION);
@@ -3982,75 +4021,36 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 fb, agp;
- int fb_loc_changed;
-
- if (IS_AVIVO_VARIANT) {
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- fb = INREG(R600_MC_VM_FB_LOCATION);
- agp = 0xffffffc0;
- } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
- fb = INMC(pScrn, RV515_MC_FB_LOCATION);
- agp = INMC(pScrn, RV515_MC_AGP_LOCATION);
- } else {
- fb = INMC(pScrn, R520_MC_FB_LOCATION);
- agp = INMC(pScrn, R520_MC_AGP_LOCATION);
- }
- fb_loc_changed = (fb != info->mc_fb_location);
-
- if (fb_loc_changed || agp != info->mc_agp_location) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "DRI init changed memory map, adjusting ...\n");
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
- info->mc_fb_location, fb);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
- info->mc_agp_location, agp);
- info->mc_fb_location = fb;
- info->mc_agp_location = agp;
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
- else
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
-
- info->dst_pitch_offset =
- (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
- << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
- RADEONInitMemMapRegisters(pScrn, save, info);
-
- /* If MC_FB_LOCATION was changed, adjust the various offsets */
- if (fb_loc_changed)
- RADEONRestoreMemMapRegisters(pScrn, save);
- }
- } else {
-
- fb = INREG(RADEON_MC_FB_LOCATION);
- agp = INREG(RADEON_MC_AGP_LOCATION);
-
- if (fb != info->mc_fb_location || agp != info->mc_agp_location) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "DRI init changed memory map, adjusting ...\n");
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_FB_LOCATION was: 0x%08x is: 0x%08x\n",
- (unsigned)info->mc_fb_location, (unsigned)fb);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_AGP_LOCATION was: 0x%08x is: 0x%08x\n",
- (unsigned)info->mc_agp_location, (unsigned)agp);
- info->mc_fb_location = fb;
- info->mc_agp_location = agp;
- info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
- info->dst_pitch_offset =
- (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
- << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
+ CARD32 fb, agp, agp_hi;
+ int changed;
+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi);
+
+ if (fb != info->mc_fb_location || agp != info->mc_agp_location ||
+ agp_hi || info->mc_agp_location_hi)
+ changed = 1;
- RADEONInitMemMapRegisters(pScrn, save, info);
+ if (changed) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "DRI init changed memory map, adjusting ...\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
+ info->mc_fb_location, fb);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
+ info->mc_agp_location, agp);
+ info->mc_fb_location = fb;
+ info->mc_agp_location = agp;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
+ else
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
- /* Adjust the various offsets */
- RADEONRestoreMemMapRegisters(pScrn, save);
- }
+ info->dst_pitch_offset =
+ (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
+ << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
+ RADEONInitMemMapRegisters(pScrn, save, info);
+ RADEONRestoreMemMapRegisters(pScrn, save);
}
#ifdef USE_EXA
@@ -5068,11 +5068,14 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- save->mc_fb_location = INREG(RADEON_MC_FB_LOCATION);
- save->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION);
- save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR);
- save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR);
- save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR);
+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location,
+ &save->mc_agp_location, &save->mc_agp_location_hi);
+
+ if (!IS_AVIVO_VARIANT) {
+ save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR);
+ save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR);
+ save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR);
+ }
}
/* Read common registers */
@@ -5654,7 +5657,6 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
- RADEONRestoreMemMapRegisters(pScrn, restore);
}
void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore)
@@ -5699,6 +5701,7 @@ static void RADEONSave(ScrnInfoPtr pScrn)
#endif
if (IS_AVIVO_VARIANT) {
+ RADEONSaveMemMapRegisters(pScrn, save);
avivo_save(pScrn, save);
} else {
save->dp_datatype = INREG(RADEON_DP_DATATYPE);
@@ -5746,6 +5749,7 @@ void RADEONRestore(ScrnInfoPtr pScrn)
RADEONBlank(pScrn);
if (IS_AVIVO_VARIANT) {
+ RADEONRestoreMemMapRegisters(pScrn, restore);
avivo_restore(pScrn, restore);
} else {
OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
commit 558a2ef266c1ca517c7fb464b0ccfef83238c913
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Nov 23 14:39:32 2007 +1000
fix silly spaces
diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h
index 3eb5f77..e58e302 100644
--- a/src/AtomBios/includes/atombios.h
+++ b/src/AtomBios/includes/atombios.h
@@ -1557,7 +1557,7 @@ ulCPUCapInfo: TBD
#define ATOM_DEVICE_TV2_INDEX 0x00000006
#define ATOM_DEVICE_DFP2_INDEX 0x00000007
#define ATOM_DEVICE_CV_INDEX 0x00000008
-#define ATOM_DEVICE_DFP3_INDEX 0x00000009
+#define ATOM_DEVICE_DFP3_INDEX 0x00000009
#define ATOM_DEVICE_RESERVEDA_INDEX 0x0000000A
#define ATOM_DEVICE_RESERVEDB_INDEX 0x0000000B
#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
commit 1bda4424a7031de437acfca9c41d4b3668e36051
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Nov 23 14:39:19 2007 +1000
r600: add hi agp address for mc
diff --git a/src/radeon.h b/src/radeon.h
index fcfa8b5..ab6c0b3 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -315,6 +315,7 @@ typedef struct {
CARD32 surface_cntl;
CARD32 surfaces[8][3];
CARD32 mc_agp_location;
+ CARD32 mc_agp_location_hi;
CARD32 mc_fb_location;
CARD32 display_base_addr;
CARD32 display2_base_addr;
commit 133234c31a294f24a3968a576aad2bb8b89d0f6a
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Nov 23 14:15:18 2007 +1000
atombios: use values from object header
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 8cac15d..fc816b2 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1366,6 +1366,7 @@ Bool RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
ErrorF("object id %04x %02x\n", obj_id, SrcDstTable->ucNumberOfSrc);
info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id];
info->BiosConnector[i].valid = TRUE;
+ info->BiosConnector[i].devices = 0;
for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) {
CARD8 sobj_id;
@@ -1374,23 +1375,32 @@ Bool RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
ErrorF("src object id %04x %d\n", SrcDstTable->usSrcObjectID[j], sobj_id);
switch(sobj_id) {
- case 2:
+ case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX);
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX);
info->BiosConnector[i].TMDSType = TMDS_INT;
break;
- case 3:
- case 15:
+ case ENCODER_OBJECT_ID_INTERNAL_TMDS2:
+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX);
+ info->BiosConnector[i].TMDSType = TMDS_EXT;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP3_INDEX);
info->BiosConnector[i].TMDSType = TMDS_EXT;
break;
- case 4:
- case 21:
+ case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT1_INDEX);
info->BiosConnector[i].DACType = DAC_PRIMARY;
break;
- case 5:
- case 22:
+ case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT2_INDEX);
info->BiosConnector[i].DACType = DAC_TVDAC;
break;
}
-
}
Record = (ATOM_COMMON_RECORD_HEADER *)
commit dbf6eae7e7a4bd1bc60fefdc7ab6276ed3f097c4
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Nov 23 11:55:05 2007 +1000
atombios: add initial object header parsing for r600 cards
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 46ceea8..8cac15d 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -565,7 +565,7 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2,
if (!(BIOSImageSize = RHDReadPCIBios(info, &ptr)))
return ATOM_FAILED;
} else*/ {
- int read_len;
+ int read_len;
unsigned char tmp[32];
xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from legacy VBIOS location\n");
if (xf86ReadBIOS(legacyBIOSLocation, 0, tmp, 32) < 0) {
@@ -1270,6 +1270,158 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle,
return ATOM_SUCCESS;
}
+const int object_connector_convert[] =
+ { CONNECTOR_NONE,
+ CONNECTOR_DVI_I,
+ CONNECTOR_DVI_I,
+ CONNECTOR_DVI_D,
+ CONNECTOR_DVI_D,
+ CONNECTOR_VGA,
+ CONNECTOR_CTV,
+ CONNECTOR_STV,
+ CONNECTOR_NONE,
+ CONNECTOR_DIN,
+ CONNECTOR_SCART,
+ CONNECTOR_HDMI_TYPE_A,
+ CONNECTOR_HDMI_TYPE_B,
+ CONNECTOR_HDMI_TYPE_B,
+ CONNECTOR_LVDS,
+ CONNECTOR_DIN,
+ CONNECTOR_NONE,
+ CONNECTOR_NONE,
+ CONNECTOR_NONE,
+ CONNECTOR_NONE,
+ };
+
+static void
+rhdAtomParseI2CRecord(atomBiosHandlePtr handle,
+ ATOM_I2C_RECORD *Record, CARD32 *ddc_line)
+{
+ ErrorF(" %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n",
+ __func__,
+ Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID",
+ Record->sucI2cId.bfI2C_LineMux,
+ Record->sucI2cId.bfHW_EngineID,
+ Record->ucI2CAddr);
+
+ if (!*(unsigned char *)&(Record->sucI2cId))
+ *ddc_line = 0;
+ else {
+
+ if (Record->ucI2CAddr != 0)
+ return;
+
+ if (Record->sucI2cId.bfHW_Capable) {
+ switch(Record->sucI2cId.bfI2C_LineMux) {
+ case 0: *ddc_line = 0x7e40; break;
+ case 1: *ddc_line = 0x7e50; break;
+ case 2: *ddc_line = 0x7e30; break;
+ default: break;
+ }
+ return;
+
+ } else {
+ /* add GPIO pin parsing */
+ }
+ }
+}
+
+Bool RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR (pScrn);
+ int ret;
+ CARD8 crev, frev;
+ unsigned short size;
+ atomDataTablesPtr atomDataPtr;
+ ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
+ int i, j;
+
+ atomDataPtr = info->atomBIOS->atomDataPtr;
+ if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->Object_Header), &crev, &frev, &size))
+ return FALSE;
+
+ if (crev < 2)
+ return FALSE;
+
+ con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
+ ((char *)&atomDataPtr->Object_Header->sHeader +
+ atomDataPtr->Object_Header->usConnectorObjectTableOffset);
+
+ for (i = 0; i < con_obj->ucNumberOfObjects; i++) {
+ ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable;
+ ATOM_COMMON_RECORD_HEADER *Record;
+ CARD8 obj_id, num, obj_type;
+ int record_base;
+
+ obj_id = (con_obj->asObjects[i].usObjectID & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+ num = (con_obj->asObjects[i].usObjectID & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
+ obj_type = (con_obj->asObjects[i].usObjectID & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+ if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR)
+ continue;
+
+ SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
+ ((char *)&atomDataPtr->Object_Header->sHeader
+ + con_obj->asObjects[i].usSrcDstTableOffset);
+
+ ErrorF("object id %04x %02x\n", obj_id, SrcDstTable->ucNumberOfSrc);
+ info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id];
+ info->BiosConnector[i].valid = TRUE;
+
+ for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) {
+ CARD8 sobj_id;
+
+ sobj_id = (SrcDstTable->usSrcObjectID[j] & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+ ErrorF("src object id %04x %d\n", SrcDstTable->usSrcObjectID[j], sobj_id);
+
+ switch(sobj_id) {
+ case 2:
+ info->BiosConnector[i].TMDSType = TMDS_INT;
+ break;
+ case 3:
+ case 15:
+ info->BiosConnector[i].TMDSType = TMDS_EXT;
+ break;
+ case 4:
+ case 21:
+ info->BiosConnector[i].DACType = DAC_PRIMARY;
+ break;
+ case 5:
+ case 22:
+ info->BiosConnector[i].DACType = DAC_TVDAC;
+ break;
+ }
+
+ }
+
+ Record = (ATOM_COMMON_RECORD_HEADER *)
+ ((char *)&atomDataPtr->Object_Header->sHeader
+ + con_obj->asObjects[i].usRecordOffset);
+
+ record_base = con_obj->asObjects[i].usRecordOffset;
+
+ while (Record->ucRecordType > 0
+ && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) {
+
+ ErrorF("record type %d\n", Record->ucRecordType);
+ switch (Record->ucRecordType) {
+ case ATOM_I2C_RECORD_TYPE:
+ rhdAtomParseI2CRecord(&info->atomBIOS,
+ (ATOM_I2C_RECORD *)Record,
+ &info->BiosConnector[i].ddc_line);
+ break;
+ case ATOM_HPD_INT_RECORD_TYPE:
+ break;
+ case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE:
+ break;
+ }
+
+ Record = (ATOM_COMMON_RECORD_HEADER*)
+ ((char *)Record + Record->ucRecordSize);
+ }
+ }
+ return TRUE;
+}
+
#if 0
#define RHD_CONNECTORS_MAX 4
#define MAX_OUTPUTS_PER_CONNECTOR 2
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 373659a..293172b 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -206,6 +206,9 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
int offset, i, j, tmp, tmp0, id, portinfo, gpio;
if (!info->VBIOS) return FALSE;
+
+ if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn))
+ return TRUE;
offset = RADEON_BIOS16(info->MasterDataStart + 22);
commit 6b103915c11fc79d2efc43c44fc2a00c3bc64ede
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Nov 23 09:24:20 2007 +1000
r500: make vt switch work again for me
diff --git a/src/atombios_output.c b/src/atombios_output.c
index d94f2f3..a6b4277 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -295,7 +295,7 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
OUTREG(0x0028, tmp | 0x100);
#endif
- ErrorF("AGD: output dpms\n");
+ ErrorF("AGD: output dpms %d\n", mode);
if (radeon_output->MonType == MT_LCD) {
if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
diff --git a/src/radeon.h b/src/radeon.h
index c37e134..fcfa8b5 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -260,6 +260,7 @@ struct avivo_dig_state {
CARD32 data_sync;
CARD32 transmitter_enable;
CARD32 transmitter_cntl;
+ CARD32 source_select;
};
struct avivo_state
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 013c28f..51d41b9 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -5500,17 +5500,25 @@ void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->dacb.powerdown = INREG(AVIVO_DACB_POWERDOWN);
state->tmds1.cntl = INREG(AVIVO_TMDSA_CNTL);
+ state->tmds1.source_select = INREG(AVIVO_TMDSA_SOURCE_SELECT);
state->tmds1.bit_depth_cntl = INREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL);
state->tmds1.data_sync = INREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION);
state->tmds1.transmitter_enable = INREG(AVIVO_TMDSA_TRANSMITTER_ENABLE);
state->tmds1.transmitter_cntl = INREG(AVIVO_TMDSA_TRANSMITTER_CONTROL);
state->tmds2.cntl = INREG(AVIVO_LVTMA_CNTL);
+ state->tmds2.source_select = INREG(AVIVO_LVTMA_SOURCE_SELECT);
state->tmds2.bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
state->tmds2.data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION);
state->tmds2.transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE);
state->tmds2.transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL);
+ if (state->crtc1.control & AVIVO_CRTC_EN)
+ info->crtc_on = TRUE;
+
+ if (state->crtc2.control & AVIVO_CRTC_EN)
+ info->crtc2_on = TRUE;
+
}
void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
@@ -5523,8 +5531,6 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
// OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base);
// OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start);
- OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
- OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en);
OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control);
@@ -5558,15 +5564,7 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total);
OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end);
- /*
- * Weird we shouldn't restore sync width when going back to text
- * mode, it must not be a 0 value, i guess a deeper look in cold
- * text mode register value would help to understand what is
- * truely needed to do.
- */
-#if 0
- OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1_v_sync_a);
-#endif
+ OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1.v_sync_a);
OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl);
OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b);
OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl);
@@ -5603,15 +5601,7 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total);
OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end);
- /*
- * Weird we shouldn't restore sync width when going back to text
- * mode, it must not be a 0 value, i guess a deeper look in cold
- * text mode register value would help to understand what is
- * truely needed to do.
- */
-#if 0
- OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2_v_sync_a);
-#endif
+ OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2.v_sync_a);
OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl);
OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b);
OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl);
@@ -5648,6 +5638,7 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION, state->tmds1.data_sync);
OUTREG(AVIVO_TMDSA_TRANSMITTER_ENABLE, state->tmds1.transmitter_enable);
OUTREG(AVIVO_TMDSA_TRANSMITTER_CONTROL, state->tmds1.transmitter_cntl);
+ OUTREG(AVIVO_TMDSA_SOURCE_SELECT, state->tmds1.source_select);
OUTREG(AVIVO_DACB_ENABLE, state->dacb.enable);
OUTREG(AVIVO_DACB_SOURCE_SELECT, state->dacb.source_select);
@@ -5659,10 +5650,23 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2.data_sync);
OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
+ OUTREG(AVIVO_LVTMA_SOURCE_SELECT, state->tmds2.source_select);
+ OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
+ OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
RADEONRestoreMemMapRegisters(pScrn, restore);
}
+void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ struct avivo_state *state = &restore->avivo;
+
+ OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
+ OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
+}
+
/* Save everything needed to restore the original VC state */
static void RADEONSave(ScrnInfoPtr pScrn)
{
@@ -5813,6 +5817,8 @@ void RADEONRestore(ScrnInfoPtr pScrn)
/* to restore console mode, DAC registers should be set after every other registers are set,
* otherwise,we may get blank screen
*/
+ if (IS_AVIVO_VARIANT)
+ avivo_restore_vga_regs(pScrn, restore);
RADEONRestoreDACRegisters(pScrn, restore);
#if 0
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 22f5268..d3c4e52 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3499,7 +3499,7 @@
# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
-#define AVIVO_TMDSA_CRTC_SOURCE 0x7884
+#define AVIVO_TMDSA_SOURCE_SELECT 0x7884
/* 78a8 appears to be some kind of (reasonably tolerant) clock?
* 78d0 definitely hits the transmitter, definitely clock. */
/* MYSTERY1 This appears to control dithering? */
commit d24208276aad7669feeed527dced60c76d39eae6
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Nov 23 08:50:25 2007 +1000
avivo: fix typo in register saving
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 8a79831..013c28f 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -5390,7 +5390,7 @@ void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
// state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE);
// state->vga_fb_start = INREG(AVIVO_VGA_FB_START);
state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL);
- state->vga2_cntl = INREG(AVIVO_D1VGA_CONTROL);
+ state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL);
state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN);
state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL);
commit 0cc7e94849c1525750fabd04cf58f2dee88372e0
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 21 17:06:17 2007 -0500
RADEON: reorder crtc/pll setup
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 0bd6c80..9615b20 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -504,11 +504,11 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
}
- atombios_set_crtc_source(crtc);
+ atombios_crtc_set_pll(crtc, adjusted_mode);
atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
- atombios_crtc_set_pll(crtc, adjusted_mode);
+ atombios_set_crtc_source(crtc);
if (info->tilingEnabled != tilingOld) {
/* need to redraw front buffer, I guess this can be considered a hack ? */
commit d56bde98efceaa8344e62f8e98db90c4bb642331
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 21 17:03:39 2007 -0500
RADEON: fix crtc to output routing
Thanks to AMD for the information
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 5188ec3..0bd6c80 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -353,6 +353,7 @@ atombios_set_crtc_source(xf86CrtcPtr crtc)
xf86OutputPtr output = xf86_config->output[i];
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ /* doesn't seem to support cloning via atom */
if (output->crtc == crtc) {
switch(major) {
case 1: {
@@ -360,7 +361,22 @@ atombios_set_crtc_source(xf86CrtcPtr crtc)
case 0:
case 1:
default:
- crtc_src_param.ucDevice = radeon_output->output_id;
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_CRT1_INDEX;
+ else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_CRT2_INDEX;
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_DFP1_INDEX;
+ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_DFP2_INDEX;
+ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_DFP3_INDEX;
+ } else if (radeon_output->MonType == MT_LCD) {
+ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_LCD1_INDEX;
+ }
break;
}
break;
@@ -371,7 +387,7 @@ atombios_set_crtc_source(xf86CrtcPtr crtc)
}
}
- ErrorF("devices sourced: 0x%x\n", crtc_src_param.ucDevice);
+ ErrorF("device sourced: 0x%x\n", crtc_src_param.ucDevice);
data.exec.index = index;
data.exec.dataSpace = (void *)&space;
commit a12390c832abe423def60e39cd5a9118e5910339
Merge: d531792... e74dca1...
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 21 02:24:48 2007 -0500
Merge branch 'atombios-support' of git://git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
commit d5317922f29a57b6c4127826a2fc126c5fd7c117
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 21 02:23:37 2007 -0500
RADEON: attempt to fix crtc to output routing
The output routing seems to be based on the output ids from the bios
connector tables and the connected status in the bios scratch regs.
I don't fully understand this yet, but this seems to work
for the most part, however changing modes can sometimes
lead to a blanked head. This can be remedied by forcing
a dpms off cycle.
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 1ab2f6d..5188ec3 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -353,37 +353,26 @@ atombios_set_crtc_source(xf86CrtcPtr crtc)
xf86OutputPtr output = xf86_config->output[i];
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- switch(major) {
- case 1: {
- switch(minor) {
- case 0:
- case 1:
+ if (output->crtc == crtc) {
+ switch(major) {
+ case 1: {
+ switch(minor) {
+ case 0:
+ case 1:
+ default:
+ crtc_src_param.ucDevice = radeon_output->output_id;
+ break;
+ }
+ break;
+ }
default:
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY)
- crtc_src_param.ucDevice |= ATOM_DEVICE_CRT1_SUPPORT;
- else
- crtc_src_param.ucDevice |= ATOM_DEVICE_CRT2_SUPPORT;
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT)
- crtc_src_param.ucDevice |= ATOM_DEVICE_DFP1_SUPPORT;
- else
- crtc_src_param.ucDevice |= ATOM_DEVICE_DFP2_SUPPORT;
- } else if (radeon_output->MonType == MT_LCD)
- crtc_src_param.ucDevice |= ATOM_DEVICE_LCD1_SUPPORT;
- else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV)
- crtc_src_param.ucDevice |= ATOM_DEVICE_TV1_SUPPORT;
- else if (radeon_output->MonType == MT_CV)
- crtc_src_param.ucDevice |= ATOM_DEVICE_CV_SUPPORT;
break;
}
- break;
- }
- default:
- break;
}
}
+ ErrorF("devices sourced: 0x%x\n", crtc_src_param.ucDevice);
+
data.exec.index = index;
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &crtc_src_param;
commit 81ce299bffd75540925b4c8234adf11226147165
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 21 01:35:44 2007 -0500
RADEON: provide clearer debugging info
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index e2f3a0b..1ab2f6d 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -389,7 +389,7 @@ atombios_set_crtc_source(xf86CrtcPtr crtc)
data.exec.pspace = &crtc_src_param;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Set CRTC Source success\n");
+ ErrorF("Set CRTC %d Source success\n", radeon_crtc->crtc_id);
return;
}
diff --git a/src/atombios_output.c b/src/atombios_output.c
index ed3a250..d94f2f3 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -58,11 +58,11 @@ atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.pspace = &disp_data;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output DAC1 enable success\n");
+ ErrorF("Output DAC1 setup success\n");
return ATOM_SUCCESS;
}
- ErrorF("Output DAC1 enable failed\n");
+ ErrorF("Output DAC1 setup failed\n");
return ATOM_NOT_IMPLEMENTED;
}
@@ -83,11 +83,11 @@ atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.pspace = &disp_data;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output DAC2 enable success\n");
+ ErrorF("Output DAC2 setup success\n");
return ATOM_SUCCESS;
}
- ErrorF("Output DAC2 enable failed\n");
+ ErrorF("Output DAC2 setup failed\n");
return ATOM_NOT_IMPLEMENTED;
}
@@ -115,11 +115,11 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.pspace = &disp_data;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("External TMDS enable success\n");
+ ErrorF("External TMDS setup success\n");
return ATOM_SUCCESS;
}
- ErrorF("External TMDS enable failed\n");
+ ErrorF("External TMDS setup failed\n");
return ATOM_NOT_IMPLEMENTED;
}
@@ -142,11 +142,11 @@ atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.pspace = &disp_data;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output TMDS1 enable success\n");
+ ErrorF("Output TMDS1 setup success\n");
return ATOM_SUCCESS;
}
- ErrorF("Output TMDS1 enable failed\n");
+ ErrorF("Output TMDS1 setup failed\n");
return ATOM_NOT_IMPLEMENTED;
}
@@ -170,11 +170,11 @@ atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.pspace = &disp_data;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output TMDS2 enable success\n");
+ ErrorF("Output TMDS2 setup success\n");
return ATOM_SUCCESS;
}
- ErrorF("Output TMDS2 enable failed\n");
+ ErrorF("Output TMDS2 setup failed\n");
return ATOM_NOT_IMPLEMENTED;
}
@@ -197,11 +197,11 @@ atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.pspace = &disp_data;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output LVDS enable success\n");
+ ErrorF("Output LVDS setup success\n");
return ATOM_SUCCESS;
}
- ErrorF("Output LVDS enable failed\n");
+ ErrorF("Output LVDS setup failed\n");
return ATOM_NOT_IMPLEMENTED;
}
@@ -218,11 +218,11 @@ atombios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool sta
data.exec.pspace = &disp_data;
if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output %d enable success\n", device);
+ ErrorF("Output %d %s success\n", device, state? "enable":"disable");
return ATOM_SUCCESS;
}
- ErrorF("Output %d enable failed\n", device);
+ ErrorF("Output %d %s failed\n", device, state? "enable":"disable");
return ATOM_NOT_IMPLEMENTED;
}
commit e74dca19416b13f97db9d1fc06299b988057d6a4
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Nov 21 16:24:25 2007 +1000
re-enable mobility chips
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index b8da989..8a79831 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1683,21 +1683,11 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
if (info->ChipFamily >= CHIP_FAMILY_R600) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"R600 support is mostly incomplete and very experimental\n");
- if (info->IsMobility) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "R600 mobility support is incomplete. You need to force enable it in the code for testing until developers are sure about it.\n");
- return FALSE;
- }
}
if ((info->ChipFamily >= CHIP_FAMILY_RV515) && (info->ChipFamily < CHIP_FAMILY_R600)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"R500 support is under development. Please report any issues to xorg-driver-ati at lists.x.org\n");
- if (info->IsMobility) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "R500 mobility support is incomplete. You need to force enable it in the code for testing until developers are sure about it.\n");
- return FALSE;
- }
}
from = X_PROBED;
commit 9c5b813dd6b3492cbc9833bc59792a5cec457e51
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 21 01:22:42 2007 -0500
RADEON: major re-org and clean up of atom output control
- use radeon_output->devices to determine output
- clean up and simplify dpms and mode set
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 441f7d6..ed3a250 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -42,43 +42,34 @@
#include "radeon_macros.h"
#include "radeon_atombios.h"
-static AtomBiosResult
-atombios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state)
+static int
+atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode)
{
- DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
AtomBiosArgRec data;
unsigned char *space;
- disp_data.ucAction = state;
- data.exec.index = device;
+ disp_data.ucAction = 1;
+ disp_data.ucDacStandard = 1;
+ disp_data.usPixelClock = mode->Clock / 10;
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
- if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output %d enable success\n", device);
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output DAC1 enable success\n");
return ATOM_SUCCESS;
}
- ErrorF("Output %d enable failed\n", device);
+ ErrorF("Output DAC1 enable failed\n");
return ATOM_NOT_IMPLEMENTED;
-}
-
-static void
-atombios_enable_crt(atomBiosHandlePtr atomBIOS, int dac, Bool state)
-{
- int output;
- if (dac == DAC_PRIMARY)
- output = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
- else
- output = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
- atombios_display_device_control(atomBIOS, output, state);
}
static int
-atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
+atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode)
{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
AtomBiosArgRec data;
@@ -87,19 +78,16 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
disp_data.ucAction = 1;
disp_data.ucDacStandard = 1;
disp_data.usPixelClock = mode->Clock / 10;
- if (radeon_output->DACType == DAC_PRIMARY)
- data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
- else
- data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output DAC %d enable success\n", radeon_output->DACType);
+ ErrorF("Output DAC2 enable success\n");
return ATOM_SUCCESS;
}
- ErrorF("Output DAC %d enable failed\n", radeon_output->DACType);
+ ErrorF("Output DAC2 enable failed\n");
return ATOM_NOT_IMPLEMENTED;
}
@@ -122,7 +110,7 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
if (!info->dac6bits)
disp_data.sXTmdsEncoder.ucMisc |= (1 << 1);
- data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableExternalTMDS_Encoder);
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
@@ -217,77 +205,64 @@ atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode)
return ATOM_NOT_IMPLEMENTED;
}
-static void
-atombios_output_dac_dpms(xf86OutputPtr output, int mode)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
-
- switch(mode) {
- case DPMSModeOn:
- atombios_enable_crt(info->atomBIOS, radeon_output->DACType, ATOM_ENABLE);
- break;
- case DPMSModeStandby:
- case DPMSModeSuspend:
- case DPMSModeOff:
- atombios_enable_crt(info->atomBIOS, radeon_output->DACType, ATOM_DISABLE);
- break;
- }
-}
-
-static void
-atombios_output_tmds1_dpms(xf86OutputPtr output, int mode)
+static AtomBiosResult
+atombios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state)
{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
+ DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
- switch(mode) {
- case DPMSModeOn:
- /* TODO */
- atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl), ATOM_ENABLE);
+ disp_data.ucAction = state;
+ data.exec.index = device;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
- break;
- case DPMSModeStandby:
- case DPMSModeSuspend:
- case DPMSModeOff:
- /* TODO */
- atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl), ATOM_DISABLE);
- break;
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output %d enable success\n", device);
+ return ATOM_SUCCESS;
}
+
+ ErrorF("Output %d enable failed\n", device);
+ return ATOM_NOT_IMPLEMENTED;
}
static void
-atombios_output_tmds2_dpms(xf86OutputPtr output, int mode)
+atombios_device_dpms(xf86OutputPtr output, int device, int mode)
{
RADEONInfoPtr info = RADEONPTR(output->scrn);
+ int index;
- switch(mode) {
- case DPMSModeOn:
- atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl), ATOM_ENABLE);
- /* TODO */
- break;
- case DPMSModeStandby:
- case DPMSModeSuspend:
- case DPMSModeOff:
- atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl), ATOM_DISABLE);
- /* TODO */
- break;
+ switch (device) {
+ case ATOM_DEVICE_CRT1_SUPPORT:
+ index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
+ break;
+ case ATOM_DEVICE_CRT2_SUPPORT:
+ index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
+ break;
+ case ATOM_DEVICE_DFP1_SUPPORT:
+ index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
+ break;
+ case ATOM_DEVICE_DFP2_SUPPORT:
+ index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
+ break;
+ case ATOM_DEVICE_DFP3_SUPPORT:
+ index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
+ break;
+ case ATOM_DEVICE_LCD1_SUPPORT:
+ index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
+ break;
+ default:
+ return;
}
-}
-static void
-atombios_output_lvds_dpms(xf86OutputPtr output, int mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
-
- switch(mode) {
+ switch (mode) {
case DPMSModeOn:
- atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LCD1OutputControl), ATOM_ENABLE);
-
+ atombios_display_device_control(info->atomBIOS, index, ATOM_ENABLE);
break;
case DPMSModeStandby:
case DPMSModeSuspend:
case DPMSModeOff:
- atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LCD1OutputControl), ATOM_DISABLE);
+ atombios_display_device_control(info->atomBIOS, index, ATOM_DISABLE);
break;
}
}
@@ -323,16 +298,22 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
ErrorF("AGD: output dpms\n");
if (radeon_output->MonType == MT_LCD) {
- atombios_output_lvds_dpms(output, mode);
+ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
+ atombios_device_dpms(output, ATOM_DEVICE_LCD1_SUPPORT, mode);
} else if (radeon_output->MonType == MT_DFP) {
ErrorF("AGD: tmds dpms\n");
- if (radeon_output->TMDSType == TMDS_INT)
- atombios_output_tmds1_dpms(output, mode);
- else
- atombios_output_tmds2_dpms(output, mode);
+ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
+ atombios_device_dpms(output, ATOM_DEVICE_DFP1_SUPPORT, mode);
+ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
+ atombios_device_dpms(output, ATOM_DEVICE_DFP2_SUPPORT, mode);
+ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
+ atombios_device_dpms(output, ATOM_DEVICE_DFP3_SUPPORT, mode);
} else if (radeon_output->MonType == MT_CRT) {
ErrorF("AGD: dac dpms\n");
- atombios_output_dac_dpms(output, mode);
+ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
+ atombios_device_dpms(output, ATOM_DEVICE_CRT1_SUPPORT, mode);
+ else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT)
+ atombios_device_dpms(output, ATOM_DEVICE_CRT2_SUPPORT, mode);
}
#if 1
@@ -350,14 +331,20 @@ atombios_output_mode_set(xf86OutputPtr output,
RADEONOutputPrivatePtr radeon_output = output->driver_private;
if (radeon_output->MonType == MT_CRT) {
- atombios_output_dac_setup(output, adjusted_mode);
+ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
+ atombios_output_dac1_setup(output, adjusted_mode);
+ else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT)
+ atombios_output_dac2_setup(output, adjusted_mode);
} else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT)
- atombios_output_tmds1_setup(output, adjusted_mode);
- else
- atombios_output_tmds2_setup(output, adjusted_mode);
+ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
+ atombios_output_tmds1_setup(output, adjusted_mode);
+ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
+ atombios_external_tmds_setup(output, adjusted_mode);
+ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
+ atombios_output_tmds2_setup(output, adjusted_mode);
} else if (radeon_output->MonType == MT_LCD) {
- atombios_output_lvds_setup(output, adjusted_mode);
+ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
+ atombios_output_lvds_setup(output, adjusted_mode);
}
}
@@ -398,13 +385,13 @@ atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
ret = atom_bios_dac_load_detect(info->atomBIOS, radeon_output->DACType);
if (ret == ATOM_SUCCESS) {
- ErrorF("DAC connect %08X\n", (unsigned int)INREG(0x10));
+ ErrorF("DAC connect %08X\n", (unsigned int)INREG(RADEON_BIOS_0_SCRATCH));
bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH);
- if (radeon_output->DACType == DAC_PRIMARY) {
+ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) {
if (bios_0_scratch & ATOM_S0_CRT1_COLOR)
MonType = MT_CRT;
- } else {
+ } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
if (bios_0_scratch & ATOM_S0_CRT2_COLOR)
MonType = MT_CRT;
}
commit 7634cb6b96f938bc6615eb2c49ae75aaefd04cce
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 21 00:10:14 2007 -0500
RADEON: make naming consistent and remove some cruft
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 71112f6..441f7d6 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -43,7 +43,7 @@
#include "radeon_atombios.h"
static AtomBiosResult
-atom_bios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state)
+atombios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state)
{
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data;
AtomBiosArgRec data;
@@ -64,7 +64,7 @@ atom_bios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool st
}
static void
-atom_bios_enable_crt(atomBiosHandlePtr atomBIOS, int dac, Bool state)
+atombios_enable_crt(atomBiosHandlePtr atomBIOS, int dac, Bool state)
{
int output;
if (dac == DAC_PRIMARY)
@@ -72,7 +72,7 @@ atom_bios_enable_crt(atomBiosHandlePtr atomBIOS, int dac, Bool state)
else
output = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
- atom_bios_display_device_control(atomBIOS, output, state);
+ atombios_display_device_control(atomBIOS, output, state);
}
static int
@@ -102,12 +102,6 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
ErrorF("Output DAC %d enable failed\n", radeon_output->DACType);
return ATOM_NOT_IMPLEMENTED;
-#if 0
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, CRT1OutputControl), ATOM_TRANSMITTER_ACTION_INIT);
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, CRT1OutputControl), ATOM_TRANSMITTER_ACTION_SETUP);
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, CRT1OutputControl), ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT);
- return ATOM_SUCCESS;
-#endif
}
int
@@ -167,12 +161,6 @@ atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
ErrorF("Output TMDS1 enable failed\n");
return ATOM_NOT_IMPLEMENTED;
-#if 0
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, DFP1OutputControl), ATOM_TRANSMITTER_ACTION_INIT);
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, DFP1OutputControl), ATOM_TRANSMITTER_ACTION_SETUP);
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, DFP1OutputControl), ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT);
- return ATOM_SUCCESS;
-#endif
}
static int
@@ -237,12 +225,12 @@ atombios_output_dac_dpms(xf86OutputPtr output, int mode)
switch(mode) {
case DPMSModeOn:
- atom_bios_enable_crt(info->atomBIOS, radeon_output->DACType, ATOM_ENABLE);
+ atombios_enable_crt(info->atomBIOS, radeon_output->DACType, ATOM_ENABLE);
break;
case DPMSModeStandby:
case DPMSModeSuspend:
case DPMSModeOff:
- atom_bios_enable_crt(info->atomBIOS, radeon_output->DACType, ATOM_DISABLE);
+ atombios_enable_crt(info->atomBIOS, radeon_output->DACType, ATOM_DISABLE);
break;
}
}
@@ -255,14 +243,14 @@ atombios_output_tmds1_dpms(xf86OutputPtr output, int mode)
switch(mode) {
case DPMSModeOn:
/* TODO */
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl), ATOM_ENABLE);
+ atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl), ATOM_ENABLE);
break;
case DPMSModeStandby:
case DPMSModeSuspend:
case DPMSModeOff:
/* TODO */
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl), ATOM_DISABLE);
+ atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl), ATOM_DISABLE);
break;
}
}
@@ -274,13 +262,13 @@ atombios_output_tmds2_dpms(xf86OutputPtr output, int mode)
switch(mode) {
case DPMSModeOn:
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl), ATOM_ENABLE);
+ atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl), ATOM_ENABLE);
/* TODO */
break;
case DPMSModeStandby:
case DPMSModeSuspend:
case DPMSModeOff:
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl), ATOM_DISABLE);
+ atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl), ATOM_DISABLE);
/* TODO */
break;
}
@@ -293,13 +281,13 @@ atombios_output_lvds_dpms(xf86OutputPtr output, int mode)
switch(mode) {
case DPMSModeOn:
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LCD1OutputControl), ATOM_ENABLE);
+ atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LCD1OutputControl), ATOM_ENABLE);
break;
case DPMSModeStandby:
case DPMSModeSuspend:
case DPMSModeOff:
- atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LCD1OutputControl), ATOM_DISABLE);
+ atombios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LCD1OutputControl), ATOM_DISABLE);
break;
}
}
commit 908748343fc9a6cdc38af0fc028c63a82766da3f
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 21 00:05:42 2007 -0500
RADEON: store devices ids from bios for each driver output
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index ac2495f..373659a 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -236,6 +236,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
info->BiosConnector[i].ddc_line = gpio;
info->BiosConnector[i].output_id = id;
+ info->BiosConnector[i].devices = (1 << i);
if (i == ATOM_DEVICE_DFP1_INDEX)
info->BiosConnector[i].TMDSType = TMDS_INT;
@@ -277,12 +278,14 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
(i == ATOM_DEVICE_DFP3_INDEX)) &&
((j == ATOM_DEVICE_CRT1_INDEX) || (j == ATOM_DEVICE_CRT2_INDEX))) {
info->BiosConnector[i].DACType = info->BiosConnector[j].DACType;
+ info->BiosConnector[i].devices |= info->BiosConnector[j].devices;
info->BiosConnector[j].valid = FALSE;
} else if (((j == ATOM_DEVICE_DFP1_INDEX) ||
(j == ATOM_DEVICE_DFP2_INDEX) ||
(j == ATOM_DEVICE_DFP3_INDEX)) &&
((i == ATOM_DEVICE_CRT1_INDEX) || (i == ATOM_DEVICE_CRT2_INDEX))) {
info->BiosConnector[j].DACType = info->BiosConnector[i].DACType;
+ info->BiosConnector[j].devices |= info->BiosConnector[i].devices;
info->BiosConnector[i].valid = FALSE;
}
/* other possible combos? */
diff --git a/src/radeon_output.c b/src/radeon_output.c
index a824e5b..678e4d7 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -3134,7 +3134,9 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
radeon_output->MonType = MT_UNKNOWN;
radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType;
radeon_output->ddc_line = info->BiosConnector[i].ddc_line;
+ radeon_output->devices = info->BiosConnector[i].devices;
radeon_output->output_id = info->BiosConnector[i].output_id;
+
if (radeon_output->ConnectorType == CONNECTOR_DVI_D)
radeon_output->DACType = DAC_NONE;
else
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index bfc352f..c1a7913 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -195,6 +195,7 @@ typedef struct {
RADEONConnectorType ConnectorType;
Bool valid;
int output_id;
+ int devices;
} RADEONBIOSConnector;
typedef struct _RADEONOutputPrivateRec {
@@ -243,6 +244,7 @@ typedef struct _RADEONOutputPrivateRec {
char *name;
int output_id;
+ int devices;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
#define RADEON_MAX_CRTC 2
commit 3975da2ea8cb628f7f66c3f26c5dfa181cd1c532
Merge: e283aa3... 295ce27...
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 20 23:52:29 2007 -0500
Merge branch 'atombios-support' of git://git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
commit e283aa332adf0134243a4fa3d14263719cd8a3fd
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 20 23:35:46 2007 -0500
RADEON: add LVDS atom support
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 9018a7e..71112f6 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -202,6 +202,33 @@ atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode)
return ATOM_NOT_IMPLEMENTED;
}
+static int
+atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode)
+{
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ LVDS_ENCODER_CONTROL_PS_ALLOCATION disp_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ disp_data.ucAction = 1;
+ if (mode->Clock > 165000)
+ disp_data.ucMisc = 1;
+ else
+ disp_data.ucMisc = 0;
+ disp_data.usPixelClock = mode->Clock / 10;
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output LVDS enable success\n");
+ return ATOM_SUCCESS;
+ }
+
+ ErrorF("Output LVDS enable failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
static void
atombios_output_dac_dpms(xf86OutputPtr output, int mode)
{
@@ -262,7 +289,19 @@ atombios_output_tmds2_dpms(xf86OutputPtr output, int mode)
static void
atombios_output_lvds_dpms(xf86OutputPtr output, int mode)
{
- atombios_output_tmds2_dpms(output, mode);
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+
+ switch(mode) {
+ case DPMSModeOn:
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LCD1OutputControl), ATOM_ENABLE);
+
+ break;
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ case DPMSModeOff:
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LCD1OutputControl), ATOM_DISABLE);
+ break;
+ }
}
void
@@ -296,7 +335,7 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
ErrorF("AGD: output dpms\n");
if (radeon_output->MonType == MT_LCD) {
- atombios_output_tmds2_dpms(output, mode);
+ atombios_output_lvds_dpms(output, mode);
} else if (radeon_output->MonType == MT_DFP) {
ErrorF("AGD: tmds dpms\n");
if (radeon_output->TMDSType == TMDS_INT)
@@ -330,7 +369,7 @@ atombios_output_mode_set(xf86OutputPtr output,
else
atombios_output_tmds2_setup(output, adjusted_mode);
} else if (radeon_output->MonType == MT_LCD) {
- atombios_output_tmds2_setup(output, adjusted_mode);
+ atombios_output_lvds_setup(output, adjusted_mode);
}
}
commit e4bc3e1e7bb45571367d41b5328ff2590810b0f9
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 20 18:09:29 2007 -0500
RADEON: enable/disable the right TMDS controller
diff --git a/src/atombios_output.c b/src/atombios_output.c
index d0f7339..9018a7e 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -299,7 +299,10 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
atombios_output_tmds2_dpms(output, mode);
} else if (radeon_output->MonType == MT_DFP) {
ErrorF("AGD: tmds dpms\n");
- atombios_output_tmds1_dpms(output, mode);
+ if (radeon_output->TMDSType == TMDS_INT)
+ atombios_output_tmds1_dpms(output, mode);
+ else
+ atombios_output_tmds2_dpms(output, mode);
} else if (radeon_output->MonType == MT_CRT) {
ErrorF("AGD: dac dpms\n");
atombios_output_dac_dpms(output, mode);
commit 3e47683ffaa44a89cda9bcddf530643befb27efa
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 20 18:01:15 2007 -0500
RADEON: fixup for bios tables with wrong connector types
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index f7fb419..ac2495f 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -246,6 +246,17 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
else
info->BiosConnector[i].TMDSType = TMDS_UNKNOWN;
+ /* Always set the connector type to VGA for CRT1/CRT2. if they are
+ * shared with a DVI port, we'll pick up the DVI connector below when we
+ * merge the outputs
+ */
+ if ((i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) &&
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I ||
+ info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D ||
+ info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) {
+ info->BiosConnector[i].ConnectorType = CONNECTOR_VGA;
+ }
+
} else {
info->BiosConnector[i].valid = FALSE;
}
commit 7412952eb1d1e9857cdab8417f7305f676900827
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 20 18:00:12 2007 -0500
RADEON: switch to using ATOM defines for bios device table
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 5e33d98..f7fb419 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -214,7 +214,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (tmp & (1 << i)) {
- if (i == DEVICE_CV) {
+ if (i == ATOM_DEVICE_CV_INDEX) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping Component Video\n");
info->BiosConnector[i].valid = FALSE;
continue;
@@ -228,17 +228,20 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
tmp0 = RADEON_BIOS16(info->MasterDataStart + 24);
gpio = RADEON_BIOS16(tmp0 + 4 + 27 * id) * 4;
/* don't assign a gpio for tv */
- if ((i == DEVICE_TV1) || (i == DEVICE_TV2) || (i == DEVICE_CV))
+ if ((i == ATOM_DEVICE_TV1_INDEX) ||
+ (i == ATOM_DEVICE_TV2_INDEX) ||
+ (i == ATOM_DEVICE_CV_INDEX))
info->BiosConnector[i].ddc_line = 0;
else
info->BiosConnector[i].ddc_line = gpio;
+
info->BiosConnector[i].output_id = id;
- if (i == DEVICE_DFP1)
+ if (i == ATOM_DEVICE_DFP1_INDEX)
info->BiosConnector[i].TMDSType = TMDS_INT;
- else if (i == DEVICE_DFP2)
+ else if (i == ATOM_DEVICE_DFP2_INDEX)
info->BiosConnector[i].TMDSType = TMDS_EXT;
- else if (i == DEVICE_DFP3)
+ else if (i == ATOM_DEVICE_DFP3_INDEX)
info->BiosConnector[i].TMDSType = TMDS_EXT;
else
info->BiosConnector[i].TMDSType = TMDS_UNKNOWN;
@@ -258,12 +261,16 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
for (j = 0; j < RADEON_MAX_BIOS_CONNECTOR; j++) {
if (info->BiosConnector[j].valid && (i != j) ) {
if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) {
- if (((i == DEVICE_DFP1) || (i == DEVICE_DFP2) || (i == DEVICE_DFP3)) &&
- ((j == DEVICE_CRT1) || (j == DEVICE_CRT2))) {
+ if (((i == ATOM_DEVICE_DFP1_INDEX) ||
+ (i == ATOM_DEVICE_DFP2_INDEX) ||
+ (i == ATOM_DEVICE_DFP3_INDEX)) &&
+ ((j == ATOM_DEVICE_CRT1_INDEX) || (j == ATOM_DEVICE_CRT2_INDEX))) {
info->BiosConnector[i].DACType = info->BiosConnector[j].DACType;
info->BiosConnector[j].valid = FALSE;
- } else if (((j == DEVICE_DFP1) || (j == DEVICE_DFP2) || (j == DEVICE_DFP3)) &&
- ((i == DEVICE_CRT1) || (i == DEVICE_CRT2))) {
+ } else if (((j == ATOM_DEVICE_DFP1_INDEX) ||
+ (j == ATOM_DEVICE_DFP2_INDEX) ||
+ (j == ATOM_DEVICE_DFP3_INDEX)) &&
+ ((i == ATOM_DEVICE_CRT1_INDEX) || (i == ATOM_DEVICE_CRT2_INDEX))) {
info->BiosConnector[j].DACType = info->BiosConnector[i].DACType;
info->BiosConnector[i].valid = FALSE;
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index d19be93..bfc352f 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -67,21 +67,6 @@ typedef enum
MT_DP = 8
} RADEONMonitorType;
-/* ATOM bios output devices table */
-typedef enum
-{
- DEVICE_CRT1 = 0,
- DEVICE_LCD1 = 1,
- DEVICE_TV1 = 2,
- DEVICE_DFP1 = 3,
- DEVICE_CRT2 = 4,
- DEVICE_LCD2 = 5,
- DEVICE_TV2 = 6,
- DEVICE_DFP2 = 7,
- DEVICE_CV = 8,
- DEVICE_DFP3 = 9
-} RADEONDeviceType;
-
typedef enum
{
CONNECTOR_NONE,
commit 295ce277bb0a44b9539b3dba575e7aff279dc2d0
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Nov 21 08:56:40 2007 +1000
add missing files for make dist
noted by ndim on #radeonhd
diff --git a/src/Makefile.am b/src/Makefile.am
index 938c5fd..fd870c4 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -215,4 +215,5 @@ EXTRA_DIST = \
radeon_chipset_gen.h \
radeon_pci_chipset_gen.h \
pcidb/ati_pciids.csv \
- pcidb/parse_pci_ids.pl
+ pcidb/parse_pci_ids.pl \
+ radeon_atombios.h
commit 20083b0695987b25e442ecbdec24f3cb6f1ac2ae
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Nov 21 08:53:44 2007 +1000
LVDS on r500/r600 needs some work disable mobile chips for now
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 8a79831..b8da989 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1683,11 +1683,21 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
if (info->ChipFamily >= CHIP_FAMILY_R600) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"R600 support is mostly incomplete and very experimental\n");
+ if (info->IsMobility) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "R600 mobility support is incomplete. You need to force enable it in the code for testing until developers are sure about it.\n");
+ return FALSE;
+ }
}
if ((info->ChipFamily >= CHIP_FAMILY_RV515) && (info->ChipFamily < CHIP_FAMILY_R600)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"R500 support is under development. Please report any issues to xorg-driver-ati at lists.x.org\n");
+ if (info->IsMobility) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "R500 mobility support is incomplete. You need to force enable it in the code for testing until developers are sure about it.\n");
+ return FALSE;
+ }
}
from = X_PROBED;
commit e4b8a4479ddea9b083b3a763dc0b9302e7b9a82a
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Nov 21 08:06:12 2007 +1000
r600: add memory controller regs from AMD
diff --git a/src/radeon.h b/src/radeon.h
index 5e2782c..c37e134 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -579,6 +579,7 @@ typedef struct {
CARD32 gartLocation;
CARD32 mc_fb_location;
CARD32 mc_agp_location;
+ CARD32 mc_agp_location_hi;
void *MMIO; /* Map of MMIO region */
void *FB; /* Map of frame buffer */
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 8d9382b..8a79831 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1277,7 +1277,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
if (IS_AVIVO_VARIANT) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- info->mc_fb_location = INREG(R600_MC_FB_LOCATION);
+ info->mc_fb_location = INREG(R600_MC_VM_FB_LOCATION);
info->mc_agp_location = 0xffffffc0;
} else if (info->ChipFamily == CHIP_FAMILY_RV515) {
info->mc_fb_location = INMC(pScrn, RV515_MC_FB_LOCATION);
@@ -1440,9 +1440,14 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- CARD32 aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
+ CARD32 aper_size;
unsigned char byte;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
+ else
+ aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
+
#ifdef XF86DRI
/* If we use the DRI, we need to check if it's a version that has the
* bug of always cropping MC_FB_LOCATION to one aperture, in which case
@@ -3765,10 +3770,11 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
(unsigned)restore->mc_agp_location);
if (IS_AVIVO_VARIANT) {
- CARD32 mc_fb_loc, mc_agp_loc;
+ CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi = 0;
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- mc_fb_loc = INREG(R600_MC_FB_LOCATION);
- mc_agp_loc = 0xffffffc0;
+ mc_fb_loc = INREG(R600_MC_VM_FB_LOCATION);
+ mc_agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
+ mc_agp_loc = INREG(R600_MC_VM_AGP_BOT);
} else if (info->ChipFamily == CHIP_FAMILY_RV515) {
mc_fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION);
mc_agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION);
@@ -3815,7 +3821,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
}
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_MC_FB_LOCATION, info->mc_fb_location);
+ OUTREG(R600_MC_VM_FB_LOCATION, info->mc_fb_location);
} else {
if (info->ChipFamily == CHIP_FAMILY_RV515) {
OUTMC(pScrn, RV515_MC_FB_LOCATION, info->mc_fb_location);
@@ -3982,7 +3988,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
if (IS_AVIVO_VARIANT) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- fb = INREG(R600_MC_FB_LOCATION);
+ fb = INREG(R600_MC_VM_FB_LOCATION);
agp = 0xffffffc0;
} else if (info->ChipFamily == CHIP_FAMILY_RV515) {
fb = INMC(pScrn, RV515_MC_FB_LOCATION);
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 4b895ce..22f5268 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3689,7 +3689,14 @@
# define AVIVO_I2C_EN (1 << 0)
# define AVIVO_I2C_RESET (1 << 8)
-#define R600_MC_FB_LOCATION 0x2180
+#define R600_MC_VM_FB_LOCATION 0x2180
+#define R600_MC_VM_AGP_TOP 0x2184
+#define R600_MC_VM_AGP_BOT 0x2188
+#define R600_MC_VM_AGP_BASE 0x218c
+#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
+#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
+#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
+
#define R600_BUS_CNTL 0x5420
#define R600_CONFIG_CNTL 0x5424
#define R600_CONFIG_MEMSIZE 0x5428
commit aa88da974b97ea1e9bbb47b3494543575c09d912
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Nov 21 08:01:35 2007 +1000
rs690 is !> r600
diff --git a/src/radeon.h b/src/radeon.h
index f776394..5e2782c 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -500,11 +500,11 @@ typedef enum {
CHIP_FAMILY_R580, /* r580 */
CHIP_FAMILY_RV560, /* rv560 */
CHIP_FAMILY_RV570, /* rv570 */
+ CHIP_FAMILY_RS690,
CHIP_FAMILY_R600, /* r60 */
CHIP_FAMILY_R630,
CHIP_FAMILY_RV610,
CHIP_FAMILY_RV630,
- CHIP_FAMILY_RS690,
CHIP_FAMILY_RS740,
CHIP_FAMILY_LAST
} RADEONChipFamily;
commit a5b34c2f1f7d5346c4489cb30e07291d1217026c
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 16:37:29 2007 +1000
r600: use standard memory controller setup paths
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 205e21e..8d9382b 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -774,7 +774,10 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ /* no idea where this is on r600 yet */
+ return TRUE;
+ } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
return TRUE;
else
@@ -1272,18 +1275,11 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
CARD32 mem_size;
CARD32 aper_size;
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- mem_size = INREG(RADEON_CONFIG_MEMSIZE);
- aper_size = INREG(RADEON_CONFIG_APER_SIZE);
- info->mc_fb_location = 0xcfffc000;
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
- info->mc_agp_location = 0xffffffc0;
- return;
- }
-
if (IS_AVIVO_VARIANT) {
-
- if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ info->mc_fb_location = INREG(R600_MC_FB_LOCATION);
+ info->mc_agp_location = 0xffffffc0;
+ } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
info->mc_fb_location = INMC(pScrn, RV515_MC_FB_LOCATION);
info->mc_agp_location = INMC(pScrn, RV515_MC_AGP_LOCATION);
} else {
@@ -1299,8 +1295,16 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
/* We shouldn't use info->videoRam here which might have been clipped
* but the real video RAM instead
*/
- mem_size = INREG(RADEON_CONFIG_MEMSIZE);
- aper_size = INREG(RADEON_CONFIG_APER_SIZE);
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ mem_size = INREG(R600_CONFIG_MEMSIZE);
+ else
+ mem_size = INREG(RADEON_CONFIG_MEMSIZE);
+
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ aper_size = INREG(R600_CONFIG_APER_SIZE);
+ else
+ aper_size = INREG(RADEON_CONFIG_APER_SIZE);
+
if (mem_size == 0)
mem_size = 0x800000;
@@ -1329,7 +1333,13 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
else
#endif
{
- CARD32 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
+ CARD32 aper0_base;
+
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ aper0_base = INREG(R600_CONFIG_F0_BASE);
+ } else {
+ aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
+ }
/* Recent chips have an "issue" with the memory controller, the
* location must be aligned to the size. We just align it down,
@@ -1346,12 +1356,21 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
info->ChipFamily == CHIP_FAMILY_RV410)
aper0_base &= ~(mem_size - 1);
- info->mc_fb_location = (aper0_base >> 16) |
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ info->mc_fb_location = (aper0_base >> 24) |
+ (((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
+ ErrorF("mc fb loc is %08x\n", info->mc_fb_location);
+ } else {
+ info->mc_fb_location = (aper0_base >> 16) |
((aper0_base + mem_size - 1) & 0xffff0000U);
+ }
}
}
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
-
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
+ } else {
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
+ }
/* Just disable the damn AGP apertures for now, it may be
* re-enabled later by the DRM
*/
@@ -3736,21 +3755,21 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
unsigned char *RADEONMMIO = info->MMIO;
int timeout;
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- return;
-
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONRestoreMemMapRegisters() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
" MC_FB_LOCATION : 0x%08x\n",
- (unsigned)restore->mc_fb_location);
+ (unsigned)info->mc_fb_location);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
" MC_AGP_LOCATION : 0x%08x\n",
(unsigned)restore->mc_agp_location);
if (IS_AVIVO_VARIANT) {
CARD32 mc_fb_loc, mc_agp_loc;
- if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ mc_fb_loc = INREG(R600_MC_FB_LOCATION);
+ mc_agp_loc = 0xffffffc0;
+ } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
mc_fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION);
mc_agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION);
} else {
@@ -3795,16 +3814,20 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
usleep(10);
}
- if (info->ChipFamily == CHIP_FAMILY_RV515) {
- OUTMC(pScrn, RV515_MC_FB_LOCATION, info->mc_fb_location);
- OUTMC(pScrn, RV515_MC_AGP_LOCATION, 0x003f0000);
- (void)INMC(pScrn, RV515_MC_AGP_LOCATION);
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ OUTREG(R600_MC_FB_LOCATION, info->mc_fb_location);
} else {
- OUTMC(pScrn, R520_MC_FB_LOCATION, info->mc_fb_location);
- OUTMC(pScrn, R520_MC_AGP_LOCATION, 0x003f0000);
- (void)INMC(pScrn, R520_MC_FB_LOCATION);
+ if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ OUTMC(pScrn, RV515_MC_FB_LOCATION, info->mc_fb_location);
+ OUTMC(pScrn, RV515_MC_AGP_LOCATION, 0x003f0000);
+ (void)INMC(pScrn, RV515_MC_AGP_LOCATION);
+ } else {
+ OUTMC(pScrn, R520_MC_FB_LOCATION, info->mc_fb_location);
+ OUTMC(pScrn, R520_MC_AGP_LOCATION, 0x003f0000);
+ (void)INMC(pScrn, R520_MC_FB_LOCATION);
+ }
+ OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
}
- OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
/* Reset the engine and HDP */
RADEONEngineReset(pScrn);
@@ -3958,7 +3981,10 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
int fb_loc_changed;
if (IS_AVIVO_VARIANT) {
- if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ fb = INREG(R600_MC_FB_LOCATION);
+ agp = 0xffffffc0;
+ } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
fb = INMC(pScrn, RV515_MC_FB_LOCATION);
agp = INMC(pScrn, RV515_MC_AGP_LOCATION);
} else {
@@ -3978,7 +4004,11 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
info->mc_agp_location, agp);
info->mc_fb_location = fb;
info->mc_agp_location = agp;
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
+ else
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
+
info->dst_pitch_offset =
(((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
<< 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 424ec19..4b895ce 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3689,8 +3689,10 @@
# define AVIVO_I2C_EN (1 << 0)
# define AVIVO_I2C_RESET (1 << 8)
+#define R600_MC_FB_LOCATION 0x2180
#define R600_BUS_CNTL 0x5420
#define R600_CONFIG_CNTL 0x5424
#define R600_CONFIG_MEMSIZE 0x5428
+#define R600_CONFIG_F0_BASE 0x542C
#define R600_CONFIG_APER_SIZE 0x5430
#endif
commit 4a523da5221d53f2efa49da2326500e9b0b9f14d
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 15:31:11 2007 +1000
r600: get r600 to work non-accelerated.
DDC still not working yet
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 9bcde2d..205e21e 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1272,7 +1272,17 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
CARD32 mem_size;
CARD32 aper_size;
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ mem_size = INREG(RADEON_CONFIG_MEMSIZE);
+ aper_size = INREG(RADEON_CONFIG_APER_SIZE);
+ info->mc_fb_location = 0xcfffc000;
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
+ info->mc_agp_location = 0xffffffc0;
+ return;
+ }
+
if (IS_AVIVO_VARIANT) {
+
if (info->ChipFamily == CHIP_FAMILY_RV515) {
info->mc_fb_location = INMC(pScrn, RV515_MC_FB_LOCATION);
info->mc_agp_location = INMC(pScrn, RV515_MC_AGP_LOCATION);
@@ -1489,13 +1499,18 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024);
} else {
- /* Read VRAM size from card */
- pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
-
- /* Some production boards of m6 will return 0 if it's 8 MB */
- if (pScrn->videoRam == 0) {
- pScrn->videoRam = 8192;
- OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
+
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
+ else {
+ /* Read VRAM size from card */
+ pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
+
+ /* Some production boards of m6 will return 0 if it's 8 MB */
+ if (pScrn->videoRam == 0) {
+ pScrn->videoRam = 8192;
+ OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
+ }
}
}
@@ -1643,7 +1658,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
if (info->ChipFamily >= CHIP_FAMILY_R600) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "R600 support is mostly incomplete and very experimental\n"); return FALSE;
+ "R600 support is mostly incomplete and very experimental\n");
}
if ((info->ChipFamily >= CHIP_FAMILY_RV515) && (info->ChipFamily < CHIP_FAMILY_R600)) {
@@ -2194,6 +2209,9 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn)
if (!info->allowColorTiling)
return;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ info->allowColorTiling = FALSE;
+
#ifdef XF86DRI
if (info->directRenderingEnabled &&
info->pKernelDRMVersion->version_minor < 14) {
@@ -3718,6 +3736,9 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
unsigned char *RADEONMMIO = info->MMIO;
int timeout;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ return;
+
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONRestoreMemMapRegisters() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 3aedb4c..424ec19 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3689,4 +3689,8 @@
# define AVIVO_I2C_EN (1 << 0)
# define AVIVO_I2C_RESET (1 << 8)
+#define R600_BUS_CNTL 0x5420
+#define R600_CONFIG_CNTL 0x5424
+#define R600_CONFIG_MEMSIZE 0x5428
+#define R600_CONFIG_APER_SIZE 0x5430
#endif
commit 80023441ba46882bc810ff3790c7148059f155f5
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 14:10:23 2007 +1000
r600: block r600 startup due to lack of memory controller info
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index eb833fb..4ce76cb 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -853,6 +853,9 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ return FALSE;
+
#ifdef USE_EXA
if (info->useEXA) {
# ifdef XF86DRI
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 17f9b81..9bcde2d 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1643,7 +1643,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
if (info->ChipFamily >= CHIP_FAMILY_R600) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "R600 support is mostly incomplete and very experimental\n");
+ "R600 support is mostly incomplete and very experimental\n"); return FALSE;
}
if ((info->ChipFamily >= CHIP_FAMILY_RV515) && (info->ChipFamily < CHIP_FAMILY_R600)) {
@@ -1865,6 +1865,12 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
info->useEXA = FALSE;
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT,
+ "No acceleration support available on R600 yet.\n");
+ return TRUE;
+ }
+
if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
int errmaj = 0, errmin = 0;
@@ -1981,15 +1987,16 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->Chipset == PCI_CHIP_RN50_5969 ||
info->Chipset == PCI_CHIP_RC410_5A61 ||
info->Chipset == PCI_CHIP_RC410_5A62 ||
- info->Chipset == PCI_CHIP_RS485_5975) {
+ info->Chipset == PCI_CHIP_RS485_5975 ||
+ info->ChipFamily >= CHIP_FAMILY_R600) {
if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Direct rendering for RN50/RC410/RS485 forced on -- "
+ "Direct rendering for RN50/RC410/RS485/R600 forced on -- "
"This is NOT officially supported at the hardware level "
"and may cause instability or lockups\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Direct rendering not officially supported on RN50/RC410\n");
+ "Direct rendering not officially supported on RN50/RC410/R600\n");
return FALSE;
}
}
commit f6fbbacc17bf9b1073d3e993b225987fd9173182
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 13:41:55 2007 +1000
atombios: add warnings for r500 and r600
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 90b1fe5..17f9b81 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1641,6 +1641,15 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
break;
}
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "R600 support is mostly incomplete and very experimental\n");
+ }
+
+ if ((info->ChipFamily >= CHIP_FAMILY_RV515) && (info->ChipFamily < CHIP_FAMILY_R600)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "R500 support is under development. Please report any issues to xorg-driver-ati at lists.x.org\n");
+ }
from = X_PROBED;
info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL;
commit 45a8b083c123b820c008f04ab857a64a8facec14
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 13:37:00 2007 +1000
atombios: add all r5xx and r6xx pci ids
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index ad54f64..53ae24c 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -215,5 +215,137 @@
#define PCI_CHIP_RV410_5E4C 0x5E4C
#define PCI_CHIP_RV410_5E4D 0x5E4D
#define PCI_CHIP_RV410_5E4F 0x5E4F
+#define PCI_CHIP_R520_7100 0x7100
+#define PCI_CHIP_R520_7101 0x7101
+#define PCI_CHIP_R520_7102 0x7102
+#define PCI_CHIP_R520_7103 0x7103
+#define PCI_CHIP_R520_7104 0x7104
+#define PCI_CHIP_R520_7105 0x7105
+#define PCI_CHIP_R520_7106 0x7106
+#define PCI_CHIP_R520_7108 0x7108
+#define PCI_CHIP_R520_7109 0x7109
+#define PCI_CHIP_R520_710A 0x710A
+#define PCI_CHIP_R520_710B 0x710B
+#define PCI_CHIP_R520_710C 0x710C
+#define PCI_CHIP_R520_710E 0x710E
+#define PCI_CHIP_R520_710F 0x710F
+#define PCI_CHIP_RV515_7140 0x7140
+#define PCI_CHIP_RV515_7141 0x7141
+#define PCI_CHIP_RV515_7142 0x7142
+#define PCI_CHIP_RV515_7143 0x7143
+#define PCI_CHIP_RV515_7144 0x7144
+#define PCI_CHIP_RV515_7145 0x7145
+#define PCI_CHIP_RV515_7146 0x7146
+#define PCI_CHIP_RV515_7147 0x7147
+#define PCI_CHIP_RV515_7149 0x7149
+#define PCI_CHIP_RV515_714A 0x714A
+#define PCI_CHIP_RV515_714B 0x714B
+#define PCI_CHIP_RV515_714C 0x714C
+#define PCI_CHIP_RV515_714D 0x714D
+#define PCI_CHIP_RV515_714E 0x714E
+#define PCI_CHIP_RV515_714F 0x714F
+#define PCI_CHIP_RV515_7151 0x7151
+#define PCI_CHIP_RV515_7152 0x7152
+#define PCI_CHIP_RV515_7153 0x7153
+#define PCI_CHIP_RV515_715E 0x715E
+#define PCI_CHIP_RV515_715F 0x715F
+#define PCI_CHIP_RV515_7180 0x7180
+#define PCI_CHIP_RV515_7181 0x7181
+#define PCI_CHIP_RV515_7183 0x7183
+#define PCI_CHIP_RV515_7186 0x7186
+#define PCI_CHIP_RV515_7187 0x7187
+#define PCI_CHIP_RV515_7188 0x7188
+#define PCI_CHIP_RV515_718A 0x718A
+#define PCI_CHIP_RV515_718B 0x718B
+#define PCI_CHIP_RV515_718C 0x718C
+#define PCI_CHIP_RV515_718D 0x718D
+#define PCI_CHIP_RV515_718F 0x718F
+#define PCI_CHIP_RV515_7193 0x7193
+#define PCI_CHIP_RV515_7196 0x7196
+#define PCI_CHIP_RV515_719B 0x719B
+#define PCI_CHIP_RV515_719F 0x719F
+#define PCI_CHIP_RV530_71C0 0x71C0
+#define PCI_CHIP_RV530_71C1 0x71C1
+#define PCI_CHIP_RV530_71C2 0x71C2
+#define PCI_CHIP_RV530_71C3 0x71C3
+#define PCI_CHIP_RV530_71C4 0x71C4
+#define PCI_CHIP_RV530_71C5 0x71C5
+#define PCI_CHIP_RV530_71C6 0x71C6
+#define PCI_CHIP_RV530_71C7 0x71C7
+#define PCI_CHIP_RV530_71CD 0x71CD
+#define PCI_CHIP_RV530_71CE 0x71CE
+#define PCI_CHIP_RV530_71D2 0x71D2
+#define PCI_CHIP_RV530_71D4 0x71D4
+#define PCI_CHIP_RV530_71D5 0x71D5
+#define PCI_CHIP_RV530_71D6 0x71D6
+#define PCI_CHIP_RV530_71DA 0x71DA
+#define PCI_CHIP_RV530_71DE 0x71DE
+#define PCI_CHIP_RV530_7200 0x7200
+#define PCI_CHIP_RV530_7210 0x7210
+#define PCI_CHIP_RV530_7211 0x7211
+#define PCI_CHIP_R580_7240 0x7240
+#define PCI_CHIP_R580_7243 0x7243
+#define PCI_CHIP_R580_7244 0x7244
+#define PCI_CHIP_R580_7245 0x7245
+#define PCI_CHIP_R580_7246 0x7246
+#define PCI_CHIP_R580_7247 0x7247
+#define PCI_CHIP_R580_7248 0x7248
+#define PCI_CHIP_R580_7249 0x7249
+#define PCI_CHIP_R580_724A 0x724A
+#define PCI_CHIP_R580_724B 0x724B
+#define PCI_CHIP_R580_724C 0x724C
+#define PCI_CHIP_R580_724D 0x724D
+#define PCI_CHIP_R580_724E 0x724E
+#define PCI_CHIP_R580_724F 0x724F
+#define PCI_CHIP_RV570_7280 0x7280
+#define PCI_CHIP_RV560_7281 0x7281
+#define PCI_CHIP_RV560_7283 0x7283
+#define PCI_CHIP_R580_7284 0x7284
+#define PCI_CHIP_RV560_7287 0x7287
+#define PCI_CHIP_RV570_7288 0x7288
+#define PCI_CHIP_RV570_7289 0x7289
+#define PCI_CHIP_RV570_728B 0x728B
+#define PCI_CHIP_RV570_728C 0x728C
+#define PCI_CHIP_RV560_7290 0x7290
+#define PCI_CHIP_RV560_7291 0x7291
+#define PCI_CHIP_RV560_7293 0x7293
+#define PCI_CHIP_RV560_7297 0x7297
#define PCI_CHIP_RS350_7834 0x7834
#define PCI_CHIP_RS350_7835 0x7835
+#define PCI_CHIP_RS690_791E 0x791E
+#define PCI_CHIP_RS690_791F 0x791F
+#define PCI_CHIP_RS740_796C 0x796C
+#define PCI_CHIP_RS740_796D 0x796D
+#define PCI_CHIP_RS740_796E 0x796E
+#define PCI_CHIP_RS740_796F 0x796F
+#define PCI_CHIP_R600_9400 0x9400
+#define PCI_CHIP_R600_9401 0x9401
+#define PCI_CHIP_R600_9402 0x9402
+#define PCI_CHIP_R600_9403 0x9403
+#define PCI_CHIP_R600_9405 0x9405
+#define PCI_CHIP_R600_940A 0x940A
+#define PCI_CHIP_R600_940B 0x940B
+#define PCI_CHIP_R600_940F 0x940F
+#define PCI_CHIP_RV610_94C0 0x94C0
+#define PCI_CHIP_RV610_94C1 0x94C1
+#define PCI_CHIP_RV610_94C3 0x94C3
+#define PCI_CHIP_RV610_94C4 0x94C4
+#define PCI_CHIP_RV610_94C5 0x94C5
+#define PCI_CHIP_RV610_94C6 0x94C6
+#define PCI_CHIP_RV610_94C7 0x94C7
+#define PCI_CHIP_RV610_94C8 0x94C8
+#define PCI_CHIP_RV610_94C9 0x94C9
+#define PCI_CHIP_RV610_94CB 0x94CB
+#define PCI_CHIP_RV610_94CC 0x94CC
+#define PCI_CHIP_RV630_9580 0x9580
+#define PCI_CHIP_RV630_9581 0x9581
+#define PCI_CHIP_RV630_9583 0x9583
+#define PCI_CHIP_RV630_9586 0x9586
+#define PCI_CHIP_RV630_9587 0x9587
+#define PCI_CHIP_RV630_9588 0x9588
+#define PCI_CHIP_RV630_9589 0x9589
+#define PCI_CHIP_RV630_958A 0x958A
+#define PCI_CHIP_RV630_958B 0x958B
+#define PCI_CHIP_RV630_958C 0x958C
+#define PCI_CHIP_RV630_958D 0x958D
+#define PCI_CHIP_RV630_958E 0x958E
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index f201cc4..a62e8a5 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -216,5 +216,137 @@
"0x5E4C","RV410_5E4C","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)"
"0x5E4D","RV410_5E4D","RV410",,,,,,"ATI Radeon X700 (RV410) (PCIE)"
"0x5E4F","RV410_5E4F","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)"
+"0x7100","R520_7100","R520",,,,,,"ATI Radeon X1800"
+"0x7101","R520_7101","R520",1,,,,,"ATI Mobility Radeon X1800 XT"
+"0x7102","R520_7102","R520",1,,,,,"ATI Mobility Radeon X1800"
+"0x7103","R520_7103","R520",1,,,,,"ATI Mobility FireGL V7200"
+"0x7104","R520_7104","R520",,,,,,"ATI FireGL V7200"
+"0x7105","R520_7105","R520",,,,,,"ATI FireGL V5300"
+"0x7106","R520_7106","R520",1,,,,,"ATI Mobility FireGL V7100"
+"0x7108","R520_7108","R520",,,,,,"ATI Radeon X1800"
+"0x7109","R520_7109","R520",,,,,,"ATI Radeon X1800"
+"0x710A","R520_710A","R520",,,,,,"ATI Radeon X1800"
+"0x710B","R520_710B","R520",,,,,,"ATI Radeon X1800"
+"0x710C","R520_710C","R520",,,,,,"ATI Radeon X1800"
+"0x710E","R520_710E","R520",,,,,,"ATI FireGL V7300"
+"0x710F","R520_710F","R520",,,,,,"ATI FireGL V7350"
+"0x7140","RV515_7140","RV515",,,,,,"ATI Radeon X1600"
+"0x7141","RV515_7141","RV515",,,,,,"ATI RV505"
+"0x7142","RV515_7142","RV515",,,,,,"ATI Radeon X1300/X1550"
+"0x7143","RV515_7143","RV515",,,,,,"ATI Radeon X1550"
+"0x7144","RV515_7144","RV515",1,,,,,"ATI M54-GL"
+"0x7145","RV515_7145","RV515",1,,,,,"ATI Mobility Radeon X1400"
+"0x7146","RV515_7146","RV515",,,,,,"ATI Radeon X1300/X1550"
+"0x7147","RV515_7147","RV515",,,,,,"ATI Radeon X1550 64-bit"
+"0x7149","RV515_7149","RV515",1,,,,,"ATI Mobility Radeon X1300"
+"0x714A","RV515_714A","RV515",1,,,,,"ATI Mobility Radeon X1300"
+"0x714B","RV515_714B","RV515",1,,,,,"ATI Mobility Radeon X1300"
+"0x714C","RV515_714C","RV515",1,,,,,"ATI Mobility Radeon X1300"
+"0x714D","RV515_714D","RV515",,,,,,"ATI Radeon X1300"
+"0x714E","RV515_714E","RV515",,,,,,"ATI Radeon X1300"
+"0x714F","RV515_714F","RV515",,,,,,"ATI RV505"
+"0x7151","RV515_7151","RV515",,,,,,"ATI RV505"
+"0x7152","RV515_7152","RV515",,,,,,"ATI FireGL V3300"
+"0x7153","RV515_7153","RV515",,,,,,"ATI FireGL V3350"
+"0x715E","RV515_715E","RV515",,,,,,"ATI Radeon X1300"
+"0x715F","RV515_715F","RV515",,,,,,"ATI Radeon X1550 64-bit"
+"0x7180","RV515_7180","RV515",,,,,,"ATI Radeon X1300/X1550"
+"0x7181","RV515_7181","RV515",,,,,,"ATI Radeon X1600"
+"0x7183","RV515_7183","RV515",,,,,,"ATI Radeon X1300/X1550"
+"0x7186","RV515_7186","RV515",1,,,,,"ATI Mobility Radeon X1450"
+"0x7187","RV515_7187","RV515",,,,,,"ATI Radeon X1300/X1550"
+"0x7188","RV515_7188","RV515",1,,,,,"ATI Mobility Radeon X2300"
+"0x718A","RV515_718A","RV515",1,,,,,"ATI Mobility Radeon X2300"
+"0x718B","RV515_718B","RV515",1,,,,,"ATI Mobility Radeon X1350"
+"0x718C","RV515_718C","RV515",1,,,,,"ATI Mobility Radeon X1350"
+"0x718D","RV515_718D","RV515",1,,,,,"ATI Mobility Radeon X1450"
+"0x718F","RV515_718F","RV515",,,,,,"ATI Radeon X1300"
+"0x7193","RV515_7193","RV515",,,,,,"ATI Radeon X1550"
+"0x7196","RV515_7196","RV515",1,,,,,"ATI Mobility Radeon X1350"
+"0x719B","RV515_719B","RV515",,,,,,"ATI FireMV 2250"
+"0x719F","RV515_719F","RV515",,,,,,"ATI Radeon X1550 64-bit"
+"0x71C0","RV530_71C0","RV530",,,,,,"ATI Radeon X1600"
+"0x71C1","RV530_71C1","RV530",,,,,,"ATI Radeon X1650"
+"0x71C2","RV530_71C2","RV530",,,,,,"ATI Radeon X1600"
+"0x71C3","RV530_71C3","RV530",,,,,,"ATI Radeon X1600"
+"0x71C4","RV530_71C4","RV530",1,,,,,"ATI Mobility FireGL V5200"
+"0x71C5","RV530_71C5","RV530",1,,,,,"ATI Mobility Radeon X1600"
+"0x71C6","RV530_71C6","RV530",,,,,,"ATI Radeon X1650"
+"0x71C7","RV530_71C7","RV530",,,,,,"ATI Radeon X1650"
+"0x71CD","RV530_71CD","RV530",,,,,,"ATI Radeon X1600"
+"0x71CE","RV530_71CE","RV530",,,,,,"ATI Radeon X1300 XT/X1600 Pro"
+"0x71D2","RV530_71D2","RV530",,,,,,"ATI FireGL V3400"
+"0x71D4","RV530_71D4","RV530",1,,,,,"ATI Mobility FireGL V5250"
+"0x71D5","RV530_71D5","RV530",1,,,,,"ATI Mobility Radeon X1700"
+"0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT"
+"0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200"
+"0x71DE","RV530_71DE","RV530",1,,,,,"ATI Mobility Radeon X1700"
+"0x7200","RV530_7200","RV530",,,,,,"ATI Radeon X2300HD"
+"0x7210","RV530_7210","RV530",1,,,,,"ATI Mobility Radeon HD 2300"
+"0x7211","RV530_7211","RV530",1,,,,,"ATI Mobility Radeon HD 2300"
+"0x7240","R580_7240","R580",,,,,,"ATI Radeon X1950"
+"0x7243","R580_7243","R580",,,,,,"ATI Radeon X1900"
+"0x7244","R580_7244","R580",,,,,,"ATI Radeon X1950"
+"0x7245","R580_7245","R580",,,,,,"ATI Radeon X1900"
+"0x7246","R580_7246","R580",,,,,,"ATI Radeon X1900"
+"0x7247","R580_7247","R580",,,,,,"ATI Radeon X1900"
+"0x7248","R580_7248","R580",,,,,,"ATI Radeon X1900"
+"0x7249","R580_7249","R580",,,,,,"ATI Radeon X1900"
+"0x724A","R580_724A","R580",,,,,,"ATI Radeon X1900"
+"0x724B","R580_724B","R580",,,,,,"ATI Radeon X1900"
+"0x724C","R580_724C","R580",,,,,,"ATI Radeon X1900"
+"0x724D","R580_724D","R580",,,,,,"ATI Radeon X1900"
+"0x724E","R580_724E","R580",,,,,,"ATI AMD Stream Processor"
+"0x724F","R580_724F","R580",,,,,,"ATI Radeon X1900"
+"0x7280","RV570_7280","RV570",,,,,,"ATI Radeon X1950"
+"0x7281","RV560_7281","RV560",,,,,,"ATI RV560"
+"0x7283","RV560_7283","RV560",,,,,,"ATI RV560"
+"0x7284","R580_7284","R580",1,,,,,"ATI Mobility Radeon X1900"
+"0x7287","RV560_7287","RV560",,,,,,"ATI RV560"
+"0x7288","RV570_7288","RV570",,,,,,"ATI Radeon X1950 GT"
+"0x7289","RV570_7289","RV570",,,,,,"ATI RV570"
+"0x728B","RV570_728B","RV570",,,,,,"ATI RV570"
+"0x728C","RV570_728C","RV570",,,,,,"ATI ATI FireGL V7400"
+"0x7290","RV560_7290","RV560",,,,,,"ATI RV560"
+"0x7291","RV560_7291","RV560",,,,,,"ATI Radeon X1650"
+"0x7293","RV560_7293","RV560",,,,,,"ATI Radeon X1650"
+"0x7297","RV560_7297","RV560",,,,,,"ATI RV560"
"0x7834","RS350_7834","RS300",,1,,,,"ATI Radeon 9100 PRO IGP 7834"
"0x7835","RS350_7835","RS300",1,1,,,,"ATI Radeon Mobility 9200 IGP 7835"
+"0x791E","RS690_791E","RS690",,1,,,,"ATI Radeon X1200"
+"0x791F","RS690_791F","RS690",,1,,,,"ATI Radeon X1200"
+"0x796C","RS740_796C","RS740",,1,,,,"ATI RS740"
+"0x796D","RS740_796D","RS740",,1,,,,"ATI RS740M"
+"0x796E","RS740_796E","RS740",,1,,,,"ATI RS740"
+"0x796F","RS740_796F","RS740",,1,,,,"ATI RS740M"
+"0x9400","R600_9400","R600",,,,,,"ATI Radeon HD 2900 XT"
+"0x9401","R600_9401","R600",,,,,,"ATI Radeon HD 2900 XT"
+"0x9402","R600_9402","R600",,,,,,"ATI Radeon HD 2900 XT"
+"0x9403","R600_9403","R600",,,,,,"ATI Radeon HD 2900 Pro"
+"0x9405","R600_9405","R600",,,,,,"ATI Radeon HD 2900 GT"
+"0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650"
+"0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600"
+"0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600"
+"0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610"
+"0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT"
+"0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro"
+"0x94C4","RV610_94C4","RV610",,,,,,"ATI ATI Radeon HD 2400 PRO AGP"
+"0x94C5","RV610_94C5","RV610",,,,,,"ATI FireGL V4000"
+"0x94C6","RV610_94C6","RV610",,,,,,"ATI RV610"
+"0x94C7","RV610_94C7","RV610",,,,,,"ATI ATI Radeon HD 2350"
+"0x94C8","RV610_94C8","RV610",1,,,,,"ATI Mobility Radeon HD 2400 XT"
+"0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400"
+"0x94CB","RV610_94CB","RV610",1,,,,,"ATI ATI RADEON E2400"
+"0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610"
+"0x9580","RV630_9580","RV630",,,,,,"ATI RV630"
+"0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600"
+"0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT"
+"0x9586","RV630_9586","RV630",,,,,,"ATI ATI Radeon HD 2600 XT AGP"
+"0x9587","RV630_9587","RV630",,,,,,"ATI ATI Radeon HD 2600 Pro AGP"
+"0x9588","RV630_9588","RV630",,,,,,"ATI Radeon HD 2600 XT"
+"0x9589","RV630_9589","RV630",,,,,,"ATI Radeon HD 2600 Pro"
+"0x958A","RV630_958A","RV630",,,,,,"ATI Gemini RV630"
+"0x958B","RV630_958B","RV630",1,,,,,"ATI Gemini ATI Mobility Radeon HD 2600 XT"
+"0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600"
+"0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600"
+"0x958E","RV630_958E","RV630",,,,,,"ATI ATI Radeon HD 2600 LE"
diff --git a/src/radeon.h b/src/radeon.h
index d503f92..f776394 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -496,9 +496,16 @@ typedef enum {
CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */
CHIP_FAMILY_RV515, /* rv515 */
CHIP_FAMILY_R520, /* r520 */
+ CHIP_FAMILY_RV530, /* rv530 */
CHIP_FAMILY_R580, /* r580 */
+ CHIP_FAMILY_RV560, /* rv560 */
CHIP_FAMILY_RV570, /* rv570 */
CHIP_FAMILY_R600, /* r60 */
+ CHIP_FAMILY_R630,
+ CHIP_FAMILY_RV610,
+ CHIP_FAMILY_RV630,
+ CHIP_FAMILY_RS690,
+ CHIP_FAMILY_RS740,
CHIP_FAMILY_LAST
} RADEONChipFamily;
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index a12b225..cf70557 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -135,6 +135,138 @@ RADEONCardInfo RADEONCards[] = {
{ 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
{ 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
{ 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
+ { 0x7100, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x7101, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
+ { 0x7102, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
+ { 0x7103, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
+ { 0x7104, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x7105, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x7106, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
+ { 0x7108, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x7109, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x710A, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x710B, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x710C, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x710E, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x710F, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
+ { 0x7140, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7141, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7142, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7143, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7144, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x7145, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x7146, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7147, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7149, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x714A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x714B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x714C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x714D, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x714E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x714F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7151, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7152, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7153, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x715E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x715F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7180, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7181, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7183, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7186, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x7187, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7188, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x718A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x718B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x718C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x718D, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x718F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7193, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7196, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x719B, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x719F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x71C0, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71C1, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71C2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71C3, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71C4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
+ { 0x71C5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
+ { 0x71C6, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71C7, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71CD, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71CE, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71D2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71D4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
+ { 0x71D5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
+ { 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
+ { 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
+ { 0x7200, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
+ { 0x7210, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
+ { 0x7211, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
+ { 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x7245, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x7246, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x7247, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x7248, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x7249, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x724A, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x724B, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x724C, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x724D, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x724E, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x724F, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
+ { 0x7280, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
+ { 0x7281, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
+ { 0x7283, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
+ { 0x7284, CHIP_FAMILY_R580, 1, 0, 0, 0, 0 },
+ { 0x7287, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
+ { 0x7288, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
+ { 0x7289, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
+ { 0x728B, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
+ { 0x728C, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
+ { 0x7290, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
+ { 0x7291, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
+ { 0x7293, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
+ { 0x7297, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
{ 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 0 },
{ 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 0 },
+ { 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 0 },
+ { 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 0 },
+ { 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 0 },
+ { 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 0 },
+ { 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 0 },
+ { 0x796F, CHIP_FAMILY_RS740, 0, 1, 0, 0, 0 },
+ { 0x9400, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
+ { 0x9401, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
+ { 0x9402, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
+ { 0x9403, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
+ { 0x9405, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
+ { 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
+ { 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
+ { 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
+ { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x94C4, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x94C5, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x94C6, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x94C7, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x94C8, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
+ { 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
+ { 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
+ { 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
+ { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
+ { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
+ { 0x9586, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
+ { 0x9587, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
+ { 0x9588, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
+ { 0x9589, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
+ { 0x958A, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
+ { 0x958B, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
+ { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
+ { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
+ { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 0a7a9c1..9f15b3d 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -135,7 +135,139 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" },
{ PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" },
{ PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" },
+ { PCI_CHIP_R520_7100, "ATI Radeon X1800" },
+ { PCI_CHIP_R520_7101, "ATI Mobility Radeon X1800 XT" },
+ { PCI_CHIP_R520_7102, "ATI Mobility Radeon X1800" },
+ { PCI_CHIP_R520_7103, "ATI Mobility FireGL V7200" },
+ { PCI_CHIP_R520_7104, "ATI FireGL V7200" },
+ { PCI_CHIP_R520_7105, "ATI FireGL V5300" },
+ { PCI_CHIP_R520_7106, "ATI Mobility FireGL V7100" },
+ { PCI_CHIP_R520_7108, "ATI Radeon X1800" },
+ { PCI_CHIP_R520_7109, "ATI Radeon X1800" },
+ { PCI_CHIP_R520_710A, "ATI Radeon X1800" },
+ { PCI_CHIP_R520_710B, "ATI Radeon X1800" },
+ { PCI_CHIP_R520_710C, "ATI Radeon X1800" },
+ { PCI_CHIP_R520_710E, "ATI FireGL V7300" },
+ { PCI_CHIP_R520_710F, "ATI FireGL V7350" },
+ { PCI_CHIP_RV515_7140, "ATI Radeon X1600" },
+ { PCI_CHIP_RV515_7141, "ATI RV505" },
+ { PCI_CHIP_RV515_7142, "ATI Radeon X1300/X1550" },
+ { PCI_CHIP_RV515_7143, "ATI Radeon X1550" },
+ { PCI_CHIP_RV515_7144, "ATI M54-GL" },
+ { PCI_CHIP_RV515_7145, "ATI Mobility Radeon X1400" },
+ { PCI_CHIP_RV515_7146, "ATI Radeon X1300/X1550" },
+ { PCI_CHIP_RV515_7147, "ATI Radeon X1550 64-bit" },
+ { PCI_CHIP_RV515_7149, "ATI Mobility Radeon X1300" },
+ { PCI_CHIP_RV515_714A, "ATI Mobility Radeon X1300" },
+ { PCI_CHIP_RV515_714B, "ATI Mobility Radeon X1300" },
+ { PCI_CHIP_RV515_714C, "ATI Mobility Radeon X1300" },
+ { PCI_CHIP_RV515_714D, "ATI Radeon X1300" },
+ { PCI_CHIP_RV515_714E, "ATI Radeon X1300" },
+ { PCI_CHIP_RV515_714F, "ATI RV505" },
+ { PCI_CHIP_RV515_7151, "ATI RV505" },
+ { PCI_CHIP_RV515_7152, "ATI FireGL V3300" },
+ { PCI_CHIP_RV515_7153, "ATI FireGL V3350" },
+ { PCI_CHIP_RV515_715E, "ATI Radeon X1300" },
+ { PCI_CHIP_RV515_715F, "ATI Radeon X1550 64-bit" },
+ { PCI_CHIP_RV515_7180, "ATI Radeon X1300/X1550" },
+ { PCI_CHIP_RV515_7181, "ATI Radeon X1600" },
+ { PCI_CHIP_RV515_7183, "ATI Radeon X1300/X1550" },
+ { PCI_CHIP_RV515_7186, "ATI Mobility Radeon X1450" },
+ { PCI_CHIP_RV515_7187, "ATI Radeon X1300/X1550" },
+ { PCI_CHIP_RV515_7188, "ATI Mobility Radeon X2300" },
+ { PCI_CHIP_RV515_718A, "ATI Mobility Radeon X2300" },
+ { PCI_CHIP_RV515_718B, "ATI Mobility Radeon X1350" },
+ { PCI_CHIP_RV515_718C, "ATI Mobility Radeon X1350" },
+ { PCI_CHIP_RV515_718D, "ATI Mobility Radeon X1450" },
+ { PCI_CHIP_RV515_718F, "ATI Radeon X1300" },
+ { PCI_CHIP_RV515_7193, "ATI Radeon X1550" },
+ { PCI_CHIP_RV515_7196, "ATI Mobility Radeon X1350" },
+ { PCI_CHIP_RV515_719B, "ATI FireMV 2250" },
+ { PCI_CHIP_RV515_719F, "ATI Radeon X1550 64-bit" },
+ { PCI_CHIP_RV530_71C0, "ATI Radeon X1600" },
+ { PCI_CHIP_RV530_71C1, "ATI Radeon X1650" },
+ { PCI_CHIP_RV530_71C2, "ATI Radeon X1600" },
+ { PCI_CHIP_RV530_71C3, "ATI Radeon X1600" },
+ { PCI_CHIP_RV530_71C4, "ATI Mobility FireGL V5200" },
+ { PCI_CHIP_RV530_71C5, "ATI Mobility Radeon X1600" },
+ { PCI_CHIP_RV530_71C6, "ATI Radeon X1650" },
+ { PCI_CHIP_RV530_71C7, "ATI Radeon X1650" },
+ { PCI_CHIP_RV530_71CD, "ATI Radeon X1600" },
+ { PCI_CHIP_RV530_71CE, "ATI Radeon X1300 XT/X1600 Pro" },
+ { PCI_CHIP_RV530_71D2, "ATI FireGL V3400" },
+ { PCI_CHIP_RV530_71D4, "ATI Mobility FireGL V5250" },
+ { PCI_CHIP_RV530_71D5, "ATI Mobility Radeon X1700" },
+ { PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" },
+ { PCI_CHIP_RV530_71DA, "ATI FireGL V5200" },
+ { PCI_CHIP_RV530_71DE, "ATI Mobility Radeon X1700" },
+ { PCI_CHIP_RV530_7200, "ATI Radeon X2300HD" },
+ { PCI_CHIP_RV530_7210, "ATI Mobility Radeon HD 2300" },
+ { PCI_CHIP_RV530_7211, "ATI Mobility Radeon HD 2300" },
+ { PCI_CHIP_R580_7240, "ATI Radeon X1950" },
+ { PCI_CHIP_R580_7243, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_7244, "ATI Radeon X1950" },
+ { PCI_CHIP_R580_7245, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_7246, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_7247, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_7248, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_7249, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_724A, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_724B, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_724C, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_724D, "ATI Radeon X1900" },
+ { PCI_CHIP_R580_724E, "ATI AMD Stream Processor" },
+ { PCI_CHIP_R580_724F, "ATI Radeon X1900" },
+ { PCI_CHIP_RV570_7280, "ATI Radeon X1950" },
+ { PCI_CHIP_RV560_7281, "ATI RV560" },
+ { PCI_CHIP_RV560_7283, "ATI RV560" },
+ { PCI_CHIP_R580_7284, "ATI Mobility Radeon X1900" },
+ { PCI_CHIP_RV560_7287, "ATI RV560" },
+ { PCI_CHIP_RV570_7288, "ATI Radeon X1950 GT" },
+ { PCI_CHIP_RV570_7289, "ATI RV570" },
+ { PCI_CHIP_RV570_728B, "ATI RV570" },
+ { PCI_CHIP_RV570_728C, "ATI ATI FireGL V7400" },
+ { PCI_CHIP_RV560_7290, "ATI RV560" },
+ { PCI_CHIP_RV560_7291, "ATI Radeon X1650" },
+ { PCI_CHIP_RV560_7293, "ATI Radeon X1650" },
+ { PCI_CHIP_RV560_7297, "ATI RV560" },
{ PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" },
{ PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" },
+ { PCI_CHIP_RS690_791E, "ATI Radeon X1200" },
+ { PCI_CHIP_RS690_791F, "ATI Radeon X1200" },
+ { PCI_CHIP_RS740_796C, "ATI RS740" },
+ { PCI_CHIP_RS740_796D, "ATI RS740M" },
+ { PCI_CHIP_RS740_796E, "ATI RS740" },
+ { PCI_CHIP_RS740_796F, "ATI RS740M" },
+ { PCI_CHIP_R600_9400, "ATI Radeon HD 2900 XT" },
+ { PCI_CHIP_R600_9401, "ATI Radeon HD 2900 XT" },
+ { PCI_CHIP_R600_9402, "ATI Radeon HD 2900 XT" },
+ { PCI_CHIP_R600_9403, "ATI Radeon HD 2900 Pro" },
+ { PCI_CHIP_R600_9405, "ATI Radeon HD 2900 GT" },
+ { PCI_CHIP_R600_940A, "ATI FireGL V8650" },
+ { PCI_CHIP_R600_940B, "ATI FireGL V8600" },
+ { PCI_CHIP_R600_940F, "ATI FireGL V7600" },
+ { PCI_CHIP_RV610_94C0, "ATI RV610" },
+ { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" },
+ { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" },
+ { PCI_CHIP_RV610_94C4, "ATI ATI Radeon HD 2400 PRO AGP" },
+ { PCI_CHIP_RV610_94C5, "ATI FireGL V4000" },
+ { PCI_CHIP_RV610_94C6, "ATI RV610" },
+ { PCI_CHIP_RV610_94C7, "ATI ATI Radeon HD 2350" },
+ { PCI_CHIP_RV610_94C8, "ATI Mobility Radeon HD 2400 XT" },
+ { PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" },
+ { PCI_CHIP_RV610_94CB, "ATI ATI RADEON E2400" },
+ { PCI_CHIP_RV610_94CC, "ATI RV610" },
+ { PCI_CHIP_RV630_9580, "ATI RV630" },
+ { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" },
+ { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" },
+ { PCI_CHIP_RV630_9586, "ATI ATI Radeon HD 2600 XT AGP" },
+ { PCI_CHIP_RV630_9587, "ATI ATI Radeon HD 2600 Pro AGP" },
+ { PCI_CHIP_RV630_9588, "ATI Radeon HD 2600 XT" },
+ { PCI_CHIP_RV630_9589, "ATI Radeon HD 2600 Pro" },
+ { PCI_CHIP_RV630_958A, "ATI Gemini RV630" },
+ { PCI_CHIP_RV630_958B, "ATI Gemini ATI Mobility Radeon HD 2600 XT" },
+ { PCI_CHIP_RV630_958C, "ATI FireGL V5600" },
+ { PCI_CHIP_RV630_958D, "ATI FireGL V3600" },
+ { PCI_CHIP_RV630_958E, "ATI ATI Radeon HD 2600 LE" },
{ -1, NULL }
};
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 7a36242..5847d5a 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -135,7 +135,139 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA },
{ PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA },
{ PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7100, PCI_CHIP_R520_7100, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7101, PCI_CHIP_R520_7101, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7102, PCI_CHIP_R520_7102, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7103, PCI_CHIP_R520_7103, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7104, PCI_CHIP_R520_7104, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7105, PCI_CHIP_R520_7105, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7106, PCI_CHIP_R520_7106, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7108, PCI_CHIP_R520_7108, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7109, PCI_CHIP_R520_7109, RES_SHARED_VGA },
+ { PCI_CHIP_R520_710A, PCI_CHIP_R520_710A, RES_SHARED_VGA },
+ { PCI_CHIP_R520_710B, PCI_CHIP_R520_710B, RES_SHARED_VGA },
+ { PCI_CHIP_R520_710C, PCI_CHIP_R520_710C, RES_SHARED_VGA },
+ { PCI_CHIP_R520_710E, PCI_CHIP_R520_710E, RES_SHARED_VGA },
+ { PCI_CHIP_R520_710F, PCI_CHIP_R520_710F, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7140, PCI_CHIP_RV515_7140, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7141, PCI_CHIP_RV515_7141, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7143, PCI_CHIP_RV515_7143, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7144, PCI_CHIP_RV515_7144, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7145, PCI_CHIP_RV515_7145, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7146, PCI_CHIP_RV515_7146, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7147, PCI_CHIP_RV515_7147, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7149, PCI_CHIP_RV515_7149, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_714A, PCI_CHIP_RV515_714A, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_714B, PCI_CHIP_RV515_714B, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_714C, PCI_CHIP_RV515_714C, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_714D, PCI_CHIP_RV515_714D, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_714E, PCI_CHIP_RV515_714E, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_714F, PCI_CHIP_RV515_714F, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7151, PCI_CHIP_RV515_7151, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7152, PCI_CHIP_RV515_7152, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7153, PCI_CHIP_RV515_7153, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_715E, PCI_CHIP_RV515_715E, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_715F, PCI_CHIP_RV515_715F, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7180, PCI_CHIP_RV515_7180, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7181, PCI_CHIP_RV515_7181, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7186, PCI_CHIP_RV515_7186, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7187, PCI_CHIP_RV515_7187, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7188, PCI_CHIP_RV515_7188, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_718A, PCI_CHIP_RV515_718A, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_718B, PCI_CHIP_RV515_718B, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_718C, PCI_CHIP_RV515_718C, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_718D, PCI_CHIP_RV515_718D, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_718F, PCI_CHIP_RV515_718F, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7193, PCI_CHIP_RV515_7193, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7196, PCI_CHIP_RV515_7196, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_719B, PCI_CHIP_RV515_719B, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_719F, PCI_CHIP_RV515_719F, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71C0, PCI_CHIP_RV530_71C0, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71C1, PCI_CHIP_RV530_71C1, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71C2, PCI_CHIP_RV530_71C2, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71C3, PCI_CHIP_RV530_71C3, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71C4, PCI_CHIP_RV530_71C4, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71C5, PCI_CHIP_RV530_71C5, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71C6, PCI_CHIP_RV530_71C6, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71C7, PCI_CHIP_RV530_71C7, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71CD, PCI_CHIP_RV530_71CD, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71CE, PCI_CHIP_RV530_71CE, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71D2, PCI_CHIP_RV530_71D2, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71D4, PCI_CHIP_RV530_71D4, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71D5, PCI_CHIP_RV530_71D5, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71D6, PCI_CHIP_RV530_71D6, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71DA, PCI_CHIP_RV530_71DA, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71DE, PCI_CHIP_RV530_71DE, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_7200, PCI_CHIP_RV530_7200, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_7210, PCI_CHIP_RV530_7210, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_7211, PCI_CHIP_RV530_7211, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7240, PCI_CHIP_R580_7240, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7243, PCI_CHIP_R580_7243, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7244, PCI_CHIP_R580_7244, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7245, PCI_CHIP_R580_7245, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7246, PCI_CHIP_R580_7246, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7247, PCI_CHIP_R580_7247, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7248, PCI_CHIP_R580_7248, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA },
+ { PCI_CHIP_R580_724A, PCI_CHIP_R580_724A, RES_SHARED_VGA },
+ { PCI_CHIP_R580_724B, PCI_CHIP_R580_724B, RES_SHARED_VGA },
+ { PCI_CHIP_R580_724C, PCI_CHIP_R580_724C, RES_SHARED_VGA },
+ { PCI_CHIP_R580_724D, PCI_CHIP_R580_724D, RES_SHARED_VGA },
+ { PCI_CHIP_R580_724E, PCI_CHIP_R580_724E, RES_SHARED_VGA },
+ { PCI_CHIP_R580_724F, PCI_CHIP_R580_724F, RES_SHARED_VGA },
+ { PCI_CHIP_RV570_7280, PCI_CHIP_RV570_7280, RES_SHARED_VGA },
+ { PCI_CHIP_RV560_7281, PCI_CHIP_RV560_7281, RES_SHARED_VGA },
+ { PCI_CHIP_RV560_7283, PCI_CHIP_RV560_7283, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7284, PCI_CHIP_R580_7284, RES_SHARED_VGA },
+ { PCI_CHIP_RV560_7287, PCI_CHIP_RV560_7287, RES_SHARED_VGA },
+ { PCI_CHIP_RV570_7288, PCI_CHIP_RV570_7288, RES_SHARED_VGA },
+ { PCI_CHIP_RV570_7289, PCI_CHIP_RV570_7289, RES_SHARED_VGA },
+ { PCI_CHIP_RV570_728B, PCI_CHIP_RV570_728B, RES_SHARED_VGA },
+ { PCI_CHIP_RV570_728C, PCI_CHIP_RV570_728C, RES_SHARED_VGA },
+ { PCI_CHIP_RV560_7290, PCI_CHIP_RV560_7290, RES_SHARED_VGA },
+ { PCI_CHIP_RV560_7291, PCI_CHIP_RV560_7291, RES_SHARED_VGA },
+ { PCI_CHIP_RV560_7293, PCI_CHIP_RV560_7293, RES_SHARED_VGA },
+ { PCI_CHIP_RV560_7297, PCI_CHIP_RV560_7297, RES_SHARED_VGA },
{ PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA },
{ PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA },
+ { PCI_CHIP_RS690_791E, PCI_CHIP_RS690_791E, RES_SHARED_VGA },
+ { PCI_CHIP_RS690_791F, PCI_CHIP_RS690_791F, RES_SHARED_VGA },
+ { PCI_CHIP_RS740_796C, PCI_CHIP_RS740_796C, RES_SHARED_VGA },
+ { PCI_CHIP_RS740_796D, PCI_CHIP_RS740_796D, RES_SHARED_VGA },
+ { PCI_CHIP_RS740_796E, PCI_CHIP_RS740_796E, RES_SHARED_VGA },
+ { PCI_CHIP_RS740_796F, PCI_CHIP_RS740_796F, RES_SHARED_VGA },
+ { PCI_CHIP_R600_9400, PCI_CHIP_R600_9400, RES_SHARED_VGA },
+ { PCI_CHIP_R600_9401, PCI_CHIP_R600_9401, RES_SHARED_VGA },
+ { PCI_CHIP_R600_9402, PCI_CHIP_R600_9402, RES_SHARED_VGA },
+ { PCI_CHIP_R600_9403, PCI_CHIP_R600_9403, RES_SHARED_VGA },
+ { PCI_CHIP_R600_9405, PCI_CHIP_R600_9405, RES_SHARED_VGA },
+ { PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA },
+ { PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA },
+ { PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94C4, PCI_CHIP_RV610_94C4, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94C5, PCI_CHIP_RV610_94C5, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94C6, PCI_CHIP_RV610_94C6, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94C7, PCI_CHIP_RV610_94C7, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94C8, PCI_CHIP_RV610_94C8, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94C9, PCI_CHIP_RV610_94C9, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94CB, PCI_CHIP_RV610_94CB, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94CC, PCI_CHIP_RV610_94CC, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_9586, PCI_CHIP_RV630_9586, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_9587, PCI_CHIP_RV630_9587, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_9588, PCI_CHIP_RV630_9588, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_9589, PCI_CHIP_RV630_9589, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_958A, PCI_CHIP_RV630_958A, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_958B, PCI_CHIP_RV630_958B, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
commit 5d023e2c3c2ab44ea57ffadc9607025d602c376c
Merge: 0d1e0c7... c887260...
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 13:02:43 2007 +1000
Merge branch 'master' into atombios-support
Conflicts:
src/radeon_chipset.h
src/radeon_driver.c
src/radeon_probe.c
diff --cc src/atipciids.h
index 902bddc,f24f8fb..2953964
--- a/src/atipciids.h
+++ b/src/atipciids.h
@@@ -38,261 -38,8 +38,15 @@@
#define PCI_VENDOR_AMD 0x1022
#define PCI_VENDOR_DELL 0x1028
- /* ATI */
- #define PCI_CHIP_RV380_3150 0x3150
- #define PCI_CHIP_RV380_3151 0x3151
- #define PCI_CHIP_RV380_3152 0x3152
- #define PCI_CHIP_RV380_3153 0x3153
- #define PCI_CHIP_RV380_3154 0x3154
- #define PCI_CHIP_RV380_3156 0x3156
- #define PCI_CHIP_RV380_3E50 0x3E50
- #define PCI_CHIP_RV380_3E51 0x3E51
- #define PCI_CHIP_RV380_3E52 0x3E52
- #define PCI_CHIP_RV380_3E53 0x3E53
- #define PCI_CHIP_RV380_3E54 0x3E54
- #define PCI_CHIP_RV380_3E56 0x3E56
- #define PCI_CHIP_RS100_4136 0x4136
- #define PCI_CHIP_RS200_4137 0x4137
- #define PCI_CHIP_R300_AD 0x4144
- #define PCI_CHIP_R300_AE 0x4145
- #define PCI_CHIP_R300_AF 0x4146
- #define PCI_CHIP_R300_AG 0x4147
- #define PCI_CHIP_R350_AH 0x4148
- #define PCI_CHIP_R350_AI 0x4149
- #define PCI_CHIP_R350_AJ 0x414A
- #define PCI_CHIP_R350_AK 0x414B
- #define PCI_CHIP_RV350_AP 0x4150
- #define PCI_CHIP_RV350_AQ 0x4151
- #define PCI_CHIP_RV360_AR 0x4152
- #define PCI_CHIP_RV350_AS 0x4153
- #define PCI_CHIP_RV350_AT 0x4154
- #define PCI_CHIP_RV350_4155 0x4155
- #define PCI_CHIP_RV350_AV 0x4156
- #define PCI_CHIP_MACH32 0x4158
- #define PCI_CHIP_RS250_4237 0x4237
- #define PCI_CHIP_R200_BB 0x4242
- #define PCI_CHIP_R200_BC 0x4243
- #define PCI_CHIP_RS100_4336 0x4336
- #define PCI_CHIP_RS200_4337 0x4337
- #define PCI_CHIP_MACH64CT 0x4354
- #define PCI_CHIP_MACH64CX 0x4358
- #define PCI_CHIP_RS250_4437 0x4437
- #define PCI_CHIP_MACH64ET 0x4554
- #define PCI_CHIP_MACH64GB 0x4742
- #define PCI_CHIP_MACH64GD 0x4744
- #define PCI_CHIP_MACH64GI 0x4749
- #define PCI_CHIP_MACH64GL 0x474C
- #define PCI_CHIP_MACH64GM 0x474D
- #define PCI_CHIP_MACH64GN 0x474E
- #define PCI_CHIP_MACH64GO 0x474F
- #define PCI_CHIP_MACH64GP 0x4750
- #define PCI_CHIP_MACH64GQ 0x4751
- #define PCI_CHIP_MACH64GR 0x4752
- #define PCI_CHIP_MACH64GS 0x4753
- #define PCI_CHIP_MACH64GT 0x4754
- #define PCI_CHIP_MACH64GU 0x4755
- #define PCI_CHIP_MACH64GV 0x4756
- #define PCI_CHIP_MACH64GW 0x4757
- #define PCI_CHIP_MACH64GX 0x4758
- #define PCI_CHIP_MACH64GY 0x4759
- #define PCI_CHIP_MACH64GZ 0x475A
- #define PCI_CHIP_RV250_Id 0x4964
- #define PCI_CHIP_RV250_Ie 0x4965
- #define PCI_CHIP_RV250_If 0x4966
- #define PCI_CHIP_RV250_Ig 0x4967
- #define PCI_CHIP_R420_JH 0x4A48
- #define PCI_CHIP_R420_JI 0x4A49
- #define PCI_CHIP_R420_JJ 0x4A4A
- #define PCI_CHIP_R420_JK 0x4A4B
- #define PCI_CHIP_R420_JL 0x4A4C
- #define PCI_CHIP_R420_JM 0x4A4D
- #define PCI_CHIP_R420_JN 0x4A4E
- #define PCI_CHIP_R420_4A4F 0x4A4F
- #define PCI_CHIP_R420_JP 0x4A50
- #define PCI_CHIP_R420_4A54 0x4A54
- #define PCI_CHIP_R481_4B49 0x4B49
- #define PCI_CHIP_R481_4B4A 0x4B4A
- #define PCI_CHIP_R481_4B4B 0x4B4B
- #define PCI_CHIP_R481_4B4C 0x4B4C
- #define PCI_CHIP_MACH64LB 0x4C42
- #define PCI_CHIP_MACH64LD 0x4C44
- #define PCI_CHIP_RAGE128LE 0x4C45
- #define PCI_CHIP_RAGE128LF 0x4C46
- #define PCI_CHIP_MACH64LG 0x4C47
- #define PCI_CHIP_MACH64LI 0x4C49
- #define PCI_CHIP_MACH64LM 0x4C4D
- #define PCI_CHIP_MACH64LN 0x4C4E
- #define PCI_CHIP_MACH64LP 0x4C50
- #define PCI_CHIP_MACH64LQ 0x4C51
- #define PCI_CHIP_MACH64LR 0x4C52
- #define PCI_CHIP_MACH64LS 0x4C53
- #define PCI_CHIP_RADEON_LW 0x4C57
- #define PCI_CHIP_RADEON_LX 0x4C58
- #define PCI_CHIP_RADEON_LY 0x4C59
- #define PCI_CHIP_RADEON_LZ 0x4C5A
- #define PCI_CHIP_RV250_Ld 0x4C64
- #define PCI_CHIP_RV250_Le 0x4C65
- #define PCI_CHIP_RV250_Lf 0x4C66
- #define PCI_CHIP_RV250_Lg 0x4C67
- #define PCI_CHIP_RV250_Ln 0x4C6E
- #define PCI_CHIP_RAGE128MF 0x4D46
- #define PCI_CHIP_RAGE128ML 0x4D4C
- #define PCI_CHIP_R300_ND 0x4E44
- #define PCI_CHIP_R300_NE 0x4E45
- #define PCI_CHIP_R300_NF 0x4E46
- #define PCI_CHIP_R300_NG 0x4E47
- #define PCI_CHIP_R350_NH 0x4E48
- #define PCI_CHIP_R350_NI 0x4E49
- #define PCI_CHIP_R360_NJ 0x4E4A
- #define PCI_CHIP_R350_NK 0x4E4B
- #define PCI_CHIP_RV350_NP 0x4E50
- #define PCI_CHIP_RV350_NQ 0x4E51
- #define PCI_CHIP_RV350_NR 0x4E52
- #define PCI_CHIP_RV350_NS 0x4E53
- #define PCI_CHIP_RV350_NT 0x4E54
- #define PCI_CHIP_RV350_NV 0x4E56
- #define PCI_CHIP_RAGE128PA 0x5041
- #define PCI_CHIP_RAGE128PB 0x5042
- #define PCI_CHIP_RAGE128PC 0x5043
- #define PCI_CHIP_RAGE128PD 0x5044
- #define PCI_CHIP_RAGE128PE 0x5045
- #define PCI_CHIP_RAGE128PF 0x5046
- #define PCI_CHIP_RAGE128PG 0x5047
- #define PCI_CHIP_RAGE128PH 0x5048
- #define PCI_CHIP_RAGE128PI 0x5049
- #define PCI_CHIP_RAGE128PJ 0x504A
- #define PCI_CHIP_RAGE128PK 0x504B
- #define PCI_CHIP_RAGE128PL 0x504C
- #define PCI_CHIP_RAGE128PM 0x504D
- #define PCI_CHIP_RAGE128PN 0x504E
- #define PCI_CHIP_RAGE128PO 0x504F
- #define PCI_CHIP_RAGE128PP 0x5050
- #define PCI_CHIP_RAGE128PQ 0x5051
- #define PCI_CHIP_RAGE128PR 0x5052
- #define PCI_CHIP_RAGE128PS 0x5053
- #define PCI_CHIP_RAGE128PT 0x5054
- #define PCI_CHIP_RAGE128PU 0x5055
- #define PCI_CHIP_RAGE128PV 0x5056
- #define PCI_CHIP_RAGE128PW 0x5057
- #define PCI_CHIP_RAGE128PX 0x5058
- #define PCI_CHIP_RADEON_QD 0x5144
- #define PCI_CHIP_RADEON_QE 0x5145
- #define PCI_CHIP_RADEON_QF 0x5146
- #define PCI_CHIP_RADEON_QG 0x5147
- #define PCI_CHIP_R200_QH 0x5148
- #define PCI_CHIP_R200_QI 0x5149
- #define PCI_CHIP_R200_QJ 0x514A
- #define PCI_CHIP_R200_QK 0x514B
- #define PCI_CHIP_R200_QL 0x514C
- #define PCI_CHIP_R200_QM 0x514D
- #define PCI_CHIP_R200_QN 0x514E
- #define PCI_CHIP_R200_QO 0x514F
- #define PCI_CHIP_RV200_QW 0x5157
- #define PCI_CHIP_RV200_QX 0x5158
- #define PCI_CHIP_RV100_QY 0x5159
- #define PCI_CHIP_RV100_QZ 0x515A
- #define PCI_CHIP_RN50_515E 0x515E
- #define PCI_CHIP_RAGE128RE 0x5245
- #define PCI_CHIP_RAGE128RF 0x5246
- #define PCI_CHIP_RAGE128RG 0x5247
- #define PCI_CHIP_RAGE128RK 0x524B
- #define PCI_CHIP_RAGE128RL 0x524C
- #define PCI_CHIP_RAGE128SE 0x5345
- #define PCI_CHIP_RAGE128SF 0x5346
- #define PCI_CHIP_RAGE128SG 0x5347
- #define PCI_CHIP_RAGE128SH 0x5348
- #define PCI_CHIP_RAGE128SK 0x534B
- #define PCI_CHIP_RAGE128SL 0x534C
- #define PCI_CHIP_RAGE128SM 0x534D
- #define PCI_CHIP_RAGE128SN 0x534E
- #define PCI_CHIP_RAGE128TF 0x5446
- #define PCI_CHIP_RAGE128TL 0x544C
- #define PCI_CHIP_RAGE128TR 0x5452
- #define PCI_CHIP_RAGE128TS 0x5453
- #define PCI_CHIP_RAGE128TT 0x5454
- #define PCI_CHIP_RAGE128TU 0x5455
- #define PCI_CHIP_RV370_5460 0x5460
- #define PCI_CHIP_RV370_5461 0x5461
- #define PCI_CHIP_RV370_5462 0x5462
- #define PCI_CHIP_RV370_5463 0x5463
- #define PCI_CHIP_RV370_5464 0x5464
- #define PCI_CHIP_RV370_5465 0x5465
- #define PCI_CHIP_RV370_5466 0x5466
- #define PCI_CHIP_RV370_5467 0x5467
- #define PCI_CHIP_R423_UH 0x5548
- #define PCI_CHIP_R423_UI 0x5549
- #define PCI_CHIP_R423_UJ 0x554A
- #define PCI_CHIP_R423_UK 0x554B
- #define PCI_CHIP_R430_554C 0x554C
- #define PCI_CHIP_R430_554D 0x554D
- #define PCI_CHIP_R430_554E 0x554E
- #define PCI_CHIP_R430_554F 0x554F
- #define PCI_CHIP_R423_5550 0x5550
- #define PCI_CHIP_R423_UQ 0x5551
- #define PCI_CHIP_R423_UR 0x5552
- #define PCI_CHIP_R423_UT 0x5554
- #define PCI_CHIP_RV410_564A 0x564A
- #define PCI_CHIP_RV410_564B 0x564B
- #define PCI_CHIP_RV410_564F 0x564F
- #define PCI_CHIP_RV410_5652 0x5652
- #define PCI_CHIP_RV410_5653 0x5653
- #define PCI_CHIP_MACH64VT 0x5654
- #define PCI_CHIP_MACH64VU 0x5655
- #define PCI_CHIP_MACH64VV 0x5656
- #define PCI_CHIP_RS300_5834 0x5834
- #define PCI_CHIP_RS300_5835 0x5835
- #define PCI_CHIP_RS300_5836 0x5836
- #define PCI_CHIP_RS300_5837 0x5837
- #define PCI_CHIP_RS480_5954 0x5954
- #define PCI_CHIP_RS480_5955 0x5955
- #define PCI_CHIP_RV280_5960 0x5960
- #define PCI_CHIP_RV280_5961 0x5961
- #define PCI_CHIP_RV280_5962 0x5962
- #define PCI_CHIP_RV280_5964 0x5964
- #define PCI_CHIP_RV280_5965 0x5965
- #define PCI_CHIP_RN50_5969 0x5969
- #define PCI_CHIP_RS482_5974 0x5974
- #define PCI_CHIP_RS485_5975 0x5975
- #define PCI_CHIP_RS400_5A41 0x5A41
- #define PCI_CHIP_RS400_5A42 0x5A42
- #define PCI_CHIP_RC410_5A61 0x5A61
- #define PCI_CHIP_RC410_5A62 0x5A62
- #define PCI_CHIP_RV370_5B60 0x5B60
- #define PCI_CHIP_RV370_5B61 0x5B61
- #define PCI_CHIP_RV370_5B62 0x5B62
- #define PCI_CHIP_RV370_5B63 0x5B63
- #define PCI_CHIP_RV370_5B64 0x5B64
- #define PCI_CHIP_RV370_5B65 0x5B65
- #define PCI_CHIP_RV370_5B66 0x5B66
- #define PCI_CHIP_RV370_5B67 0x5B67
- #define PCI_CHIP_RV280_5C61 0x5C61
- #define PCI_CHIP_RV280_5C63 0x5C63
- #define PCI_CHIP_R430_5D48 0x5D48
- #define PCI_CHIP_R430_5D49 0x5D49
- #define PCI_CHIP_R430_5D4A 0x5D4A
- #define PCI_CHIP_R480_5D4C 0x5D4C
- #define PCI_CHIP_R480_5D4D 0x5D4D
- #define PCI_CHIP_R480_5D4E 0x5D4E
- #define PCI_CHIP_R480_5D4F 0x5D4F
- #define PCI_CHIP_R480_5D50 0x5D50
- #define PCI_CHIP_R480_5D52 0x5D52
- #define PCI_CHIP_R423_5D57 0x5D57
- #define PCI_CHIP_RV410_5E48 0x5E48
- #define PCI_CHIP_RV410_5E4A 0x5E4A
- #define PCI_CHIP_RV410_5E4B 0x5E4B
- #define PCI_CHIP_RV410_5E4C 0x5E4C
- #define PCI_CHIP_RV410_5E4D 0x5E4D
- #define PCI_CHIP_RV410_5E4F 0x5E4F
- #define PCI_CHIP_RS350_7834 0x7834
- #define PCI_CHIP_RS350_7835 0x7835
+ #include "ati_pciids_gen.h"
+#define PCI_CHIP_R520_7104 0x7104
+#define PCI_CHIP_RV515_7142 0x7142
+#define PCI_CHIP_RV515_7183 0x7183
+#define PCI_CHIP_RV530_71C5 0x71C5
+#define PCI_CHIP_R580_7249 0x7249
+#define PCI_CHIP_RV570_7280 0x7280
+
/* Misc */
#define PCI_CHIP_AMD761 0x700E
diff --cc src/radeon.h
index 8fffafe,5b91d00..d503f92
--- a/src/radeon.h
+++ b/src/radeon.h
@@@ -545,9 -443,17 +545,19 @@@ typedef enum
CARD_PCIE
} RADEONCardType;
+typedef struct _atomBiosHandle *atomBiosHandlePtr;
+
typedef struct {
+ CARD32 pci_device_id;
+ RADEONChipFamily chip_family;
+ int mobility;
+ int igp;
+ int nocrtc2;
+ int nointtvout;
+ int singledac;
+ } RADEONCardInfo;
+
+ typedef struct {
EntityInfoPtr pEnt;
pciVideoPtr PciInfo;
PCITAG PciTag;
commit 0d1e0c7805b3d8e56ccb49465e6b144afb7bdc51
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 09:08:04 2007 +1000
r5xx: add 71c5 for macbook pro
diff --git a/src/atipciids.h b/src/atipciids.h
index 7f50dfb..902bddc 100644
--- a/src/atipciids.h
+++ b/src/atipciids.h
@@ -289,6 +289,7 @@
#define PCI_CHIP_R520_7104 0x7104
#define PCI_CHIP_RV515_7142 0x7142
#define PCI_CHIP_RV515_7183 0x7183
+#define PCI_CHIP_RV530_71C5 0x71C5
#define PCI_CHIP_R580_7249 0x7249
#define PCI_CHIP_RV570_7280 0x7280
diff --git a/src/radeon_chipset.h b/src/radeon_chipset.h
index 6568fcc..892717a 100644
--- a/src/radeon_chipset.h
+++ b/src/radeon_chipset.h
@@ -139,6 +139,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" },
{ PCI_CHIP_RV515_7142, "ATI AVIVO X1300 (PCIE)"},
{ PCI_CHIP_RV515_7183, "ATI AVIVO X1550PRO (PCI/PCIE)"},
+ { PCI_CHIP_RV530_71C5, "ATI Mobility Radeon X1600" },
{ PCI_CHIP_R520_7104, "ATI FireGL V7200 (PCIE)" },
{ PCI_CHIP_R580_7249, "ATI Radeon X1900 XT"},
{ PCI_CHIP_RV570_7280, "ATI Radeon X1950 Pro (PCIE)" },
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 55f279b..0da3cfe 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1847,6 +1847,11 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->ChipFamily = CHIP_FAMILY_R520;
break;
+ case PCI_CHIP_RV530_71C5:
+ info->ChipFamily = CHIP_FAMILY_RV570;
+ info->IsMobility = TRUE;
+ break;
+
case PCI_CHIP_R580_7249:
info->ChipFamily = CHIP_FAMILY_R580;
break;
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index fe6f759..d4036f6 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -195,6 +195,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_R520_7104, PCI_CHIP_R520_7104, RES_SHARED_VGA },
{ PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA },
{ PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA },
+ { PCI_CHIP_RV530_71C5, PCI_CHIP_RV530_71C5, RES_SHARED_VGA },
{ PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA },
{ PCI_CHIP_RV570_7280, PCI_CHIP_RV570_7280, RES_SHARED_VGA },
commit d5909b30595c103bb5f42cd1704330f944bba49c
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 08:15:58 2007 +1000
r5xx: cleanups after last merge
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 8cef5d6..a2cec55 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -154,6 +154,7 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
& ~(AVIVO_D1CURSOR_EN));
avivo_setup_cursor(crtc, FALSE);
} else {
+ switch(crtc_id) {
case 0:
OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
break;
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 14abb2e..a824e5b 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -1729,11 +1729,10 @@ radeon_detect(xf86OutputPtr output)
* so we can get something on the screen
*/
if (((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) &&
- radeon_output->DACType == DAC_TVDAC) ||
- (info->IsIGP && radeon_output->type == OUTPUT_DVI_D))
+ radeon_output->DACType == DAC_TVDAC)) {
radeon_output->MonType = MT_CRT;
return XF86OutputStatusUnknown;
- } else if (info->IsIGP && radeon_output->type == OUTPUT_DVI) {
+ } else if (info->IsIGP && radeon_output->type == OUTPUT_DVI_D) {
radeon_output->MonType = MT_DFP; /* MT_LCD ??? */
return XF86OutputStatusUnknown;
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 24dceea..d19be93 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -36,6 +36,7 @@
#ifndef _RADEON_PROBE_H_
#define _RADEON_PROBE_H_ 1
+#include <stdint.h>
#include "xf86str.h"
#include "xf86DDC.h"
#include "randrstr.h"
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 290869f..3aedb4c 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3647,7 +3647,6 @@
#define AVIVO_GPIO_3 0x7e60
#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
-#define R520_PCLK_HDCP_CNTL 0x494
#define AVIVO_I2C_STATUS 0x7d30
# define AVIVO_I2C_STATUS_DONE (1 << 0)
commit fe2f7a09050fb7a345a1f52239f8f3c4f1053891
Merge: 744c8cb... 49055d8...
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 08:04:32 2007 +1000
Merge branch 'master' into agd-atom-merge
Conflicts:
src/radeon_cursor.c
src/radeon_output.c
diff --cc src/radeon_cursor.c
index bf66516,b8cfffd..8cef5d6
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@@ -117,29 -98,19 +117,26 @@@ radeon_crtc_show_cursor (xf86CrtcPtr cr
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- #ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
- #endif
-
- RADEON_SYNC(info, pScrn);
-
- switch (crtc_id) {
- case 0:
- OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
- break;
- case 1:
- OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
- break;
- default:
- return;
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
+ INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset)
+ | AVIVO_D1CURSOR_EN);
+ avivo_setup_cursor(crtc, TRUE);
+ } else {
- if (crtc_id == 0)
- OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN | 2 << 20,
- ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
- else if (crtc_id == 1)
- OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN | 2 << 20,
- ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_CUR_MODE_MASK));
++ switch (crtc_id) {
++ case 0:
++ OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
++ break;
++ case 1:
++ OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
++ break;
++ default:
++ return;
++ }
++
++ OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20,
++ ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
}
--
- #ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
- #endif
- OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20,
- ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
}
void
@@@ -151,27 -122,18 +148,24 @@@ radeon_crtc_hide_cursor (xf86CrtcPtr cr
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- #ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
- #endif
-
- RADEON_SYNC(info, pScrn);
-
- switch (crtc_id) {
- case 0:
- OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
- break;
- case 1:
- OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
- break;
- default:
- return;
- }
-
- OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_D1CUR_CONTROL+ radeon_crtc->crtc_offset,
+ INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset)
+ & ~(AVIVO_D1CURSOR_EN));
+ avivo_setup_cursor(crtc, FALSE);
+ } else {
- if (crtc_id == 0)
- OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_CUR_EN);
- else if (crtc_id == 1)
- OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN);
- }
-
- #ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
- #endif
++ case 0:
++ OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
++ break;
++ case 1:
++ OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
++ break;
++ default:
++ return;
++ }
++
++ OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
++ }
}
void
diff --cc src/radeon_output.c
index 59ed8b1,54c27cd..14abb2e
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@@ -728,10 -696,10 +730,10 @@@ static RADEONMonitorType RADEONPortChec
if (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
MonType = MT_DFP;
}
- }
+ }*/
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Detected Monitor Type: %d\n", MonType);
+ "Detected non-DDC Monitor Type: %d\n", MonType);
return MonType;
@@@ -1724,10 -1672,14 +1728,15 @@@ radeon_detect(xf86OutputPtr output
/* default to unknown for flaky chips/connectors
* so we can get something on the screen
*/
- if (((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI) &&
- radeon_output->DACType == DAC_TVDAC)) {
+ if (((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) &&
+ radeon_output->DACType == DAC_TVDAC) ||
+ (info->IsIGP && radeon_output->type == OUTPUT_DVI_D))
+ radeon_output->MonType = MT_CRT;
return XF86OutputStatusUnknown;
+ } else if (info->IsIGP && radeon_output->type == OUTPUT_DVI) {
+ radeon_output->MonType = MT_DFP; /* MT_LCD ??? */
+ return XF86OutputStatusUnknown;
+ }
}
if (connected)
@@@ -2737,8 -2626,10 +2746,9 @@@ void RADEONInitConnector(xf86OutputPtr
RADEONGetTMDSInfo(output);
}
- if (radeon_output->type == OUTPUT_STV ||
- radeon_output->type == OUTPUT_CTV) {
+ if (OUTPUT_IS_TV) {
RADEONGetTVInfo(output);
+ RADEONGetTVDacAdjInfo(output);
}
if (radeon_output->DACType == DAC_TVDAC) {
commit 744c8cb6c293fcaa687566f52901644e699baace
Merge: e258fbe... e530af7...
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Nov 20 07:56:33 2007 +1000
Merge branch 'agd-atom' of ssh://people.freedesktop.org/~agd5f/xf86-video-ati-atom into agd-atom
commit e258fbe411d255a1044b61d7ff738aee3fb5b7f4
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 16:35:05 2007 +1000
makes 2-headed cursor work
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 948ecd4..bf66516 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -202,6 +202,9 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
if (y < 0)
y = 0;
+ /* avivo cursor spans the full fb width */
+ x += crtc->x;
+ y += crtc->y;
OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
radeon_crtc->cursor_x = x;
radeon_crtc->cursor_y = y;
commit e530af79adf51b3e95a0eca676c915a34dcbf4a7
Merge: 69e197f... 52aba8d...
Author: Alex Deucher <alex at botch2.(none)>
Date: Mon Nov 19 00:59:30 2007 -0500
Merge branch 'agd-atom' of /home/alex/git/airlied/xf86-video-ati2 into agd-atom
commit 69e197f2c8002aacf2587754c8d3bd63c88f85b1
Merge: 5e8940f... 862dcab...
Author: Alex Deucher <alex at botch2.(none)>
Date: Mon Nov 19 00:57:34 2007 -0500
Merge branch 'agd-atom' of /home/alex/git/airlied/xf86-video-ati2 into agd-atom
commit fca47ad083449f4cf9063dd970cdcebea6a7f110
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 15:53:40 2007 +1000
add z3ro's pciids
diff --git a/src/atipciids.h b/src/atipciids.h
index 62b56c0..7f50dfb 100644
--- a/src/atipciids.h
+++ b/src/atipciids.h
@@ -290,6 +290,7 @@
#define PCI_CHIP_RV515_7142 0x7142
#define PCI_CHIP_RV515_7183 0x7183
#define PCI_CHIP_R580_7249 0x7249
+#define PCI_CHIP_RV570_7280 0x7280
/* Misc */
#define PCI_CHIP_AMD761 0x700E
diff --git a/src/radeon.h b/src/radeon.h
index db0f34a..8fffafe 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -497,6 +497,7 @@ typedef enum {
CHIP_FAMILY_RV515, /* rv515 */
CHIP_FAMILY_R520, /* r520 */
CHIP_FAMILY_R580, /* r580 */
+ CHIP_FAMILY_RV570, /* rv570 */
CHIP_FAMILY_R600, /* r60 */
CHIP_FAMILY_LAST
} RADEONChipFamily;
diff --git a/src/radeon_chipset.h b/src/radeon_chipset.h
index 2c26ce7..6568fcc 100644
--- a/src/radeon_chipset.h
+++ b/src/radeon_chipset.h
@@ -141,6 +141,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV515_7183, "ATI AVIVO X1550PRO (PCI/PCIE)"},
{ PCI_CHIP_R520_7104, "ATI FireGL V7200 (PCIE)" },
{ PCI_CHIP_R580_7249, "ATI Radeon X1900 XT"},
+ { PCI_CHIP_RV570_7280, "ATI Radeon X1950 Pro (PCIE)" },
{ -1, NULL }
};
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 8eb0bc3..e5b87e1 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1851,6 +1851,10 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->ChipFamily = CHIP_FAMILY_R580;
break;
+ case PCI_CHIP_RV570_7280:
+ info->ChipFamily = CHIP_FAMILY_RV570;
+ break;
+
default:
/* Original Radeon/7200 */
info->ChipFamily = CHIP_FAMILY_RADEON;
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index 9b77f33..fe6f759 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -196,6 +196,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA },
{ PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA },
{ PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA },
+ { PCI_CHIP_RV570_7280, PCI_CHIP_RV570_7280, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
commit 5e8940fa6e33d09091aa4bcf04b0f9e79596e1b8
Author: Alex Deucher <alex at botch2.(none)>
Date: Mon Nov 19 00:52:38 2007 -0500
fix logic in connector table check for TVs and switch counter to symbolic names
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index a9da889..5e33d98 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -214,7 +214,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (tmp & (1 << i)) {
- if (i == 8) {
+ if (i == DEVICE_CV) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping Component Video\n");
info->BiosConnector[i].valid = FALSE;
continue;
@@ -228,17 +228,17 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
tmp0 = RADEON_BIOS16(info->MasterDataStart + 24);
gpio = RADEON_BIOS16(tmp0 + 4 + 27 * id) * 4;
/* don't assign a gpio for tv */
- if ((i == 2) && (i == 6) && (i == 8))
+ if ((i == DEVICE_TV1) || (i == DEVICE_TV2) || (i == DEVICE_CV))
info->BiosConnector[i].ddc_line = 0;
else
info->BiosConnector[i].ddc_line = gpio;
info->BiosConnector[i].output_id = id;
- if (i == 3)
+ if (i == DEVICE_DFP1)
info->BiosConnector[i].TMDSType = TMDS_INT;
- else if (i == 7)
+ else if (i == DEVICE_DFP2)
info->BiosConnector[i].TMDSType = TMDS_EXT;
- else if (i == 9)
+ else if (i == DEVICE_DFP3)
info->BiosConnector[i].TMDSType = TMDS_EXT;
else
info->BiosConnector[i].TMDSType = TMDS_UNKNOWN;
@@ -258,12 +258,12 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
for (j = 0; j < RADEON_MAX_BIOS_CONNECTOR; j++) {
if (info->BiosConnector[j].valid && (i != j) ) {
if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) {
- if (((i == 3) || (i == 7) || (i == 9)) &&
- ((j == 0) || (j == 4))) {
+ if (((i == DEVICE_DFP1) || (i == DEVICE_DFP2) || (i == DEVICE_DFP3)) &&
+ ((j == DEVICE_CRT1) || (j == DEVICE_CRT2))) {
info->BiosConnector[i].DACType = info->BiosConnector[j].DACType;
info->BiosConnector[j].valid = FALSE;
- } else if (((j == 3) || (j == 7) || (j == 9)) &&
- ((i == 0) || (i == 4))) {
+ } else if (((j == DEVICE_DFP1) || (j == DEVICE_DFP2) || (j == DEVICE_DFP3)) &&
+ ((i == DEVICE_CRT1) || (i == DEVICE_CRT2))) {
info->BiosConnector[j].DACType = info->BiosConnector[i].DACType;
info->BiosConnector[i].valid = FALSE;
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index bac2f51..24dceea 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -66,6 +66,21 @@ typedef enum
MT_DP = 8
} RADEONMonitorType;
+/* ATOM bios output devices table */
+typedef enum
+{
+ DEVICE_CRT1 = 0,
+ DEVICE_LCD1 = 1,
+ DEVICE_TV1 = 2,
+ DEVICE_DFP1 = 3,
+ DEVICE_CRT2 = 4,
+ DEVICE_LCD2 = 5,
+ DEVICE_TV2 = 6,
+ DEVICE_DFP2 = 7,
+ DEVICE_CV = 8,
+ DEVICE_DFP3 = 9
+} RADEONDeviceType;
+
typedef enum
{
CONNECTOR_NONE,
commit c19123fd9483758eb6b286c3dffcb6d79d5b1ee5
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 15:46:58 2007 +1000
add firegl card on ajaxs machine
diff --git a/src/atipciids.h b/src/atipciids.h
index 9c45c24..62b56c0 100644
--- a/src/atipciids.h
+++ b/src/atipciids.h
@@ -286,6 +286,7 @@
#define PCI_CHIP_RS350_7834 0x7834
#define PCI_CHIP_RS350_7835 0x7835
+#define PCI_CHIP_R520_7104 0x7104
#define PCI_CHIP_RV515_7142 0x7142
#define PCI_CHIP_RV515_7183 0x7183
#define PCI_CHIP_R580_7249 0x7249
diff --git a/src/radeon_chipset.h b/src/radeon_chipset.h
index b2e20d2..2c26ce7 100644
--- a/src/radeon_chipset.h
+++ b/src/radeon_chipset.h
@@ -139,6 +139,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" },
{ PCI_CHIP_RV515_7142, "ATI AVIVO X1300 (PCIE)"},
{ PCI_CHIP_RV515_7183, "ATI AVIVO X1550PRO (PCI/PCIE)"},
+ { PCI_CHIP_R520_7104, "ATI FireGL V7200 (PCIE)" },
{ PCI_CHIP_R580_7249, "ATI Radeon X1900 XT"},
{ -1, NULL }
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index fa04413..8eb0bc3 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1843,6 +1843,10 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->ChipFamily = CHIP_FAMILY_RV515;
break;
+ case PCI_CHIP_R520_7104:
+ info->ChipFamily = CHIP_FAMILY_R520;
+ break;
+
case PCI_CHIP_R580_7249:
info->ChipFamily = CHIP_FAMILY_R580;
break;
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index c1ed105..9b77f33 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -192,6 +192,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA },
{ PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA },
{ PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA },
+ { PCI_CHIP_R520_7104, PCI_CHIP_R520_7104, RES_SHARED_VGA },
{ PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA },
{ PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA },
{ PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA },
commit f02f340e466a415b4e01648ca1e323f4ce125885
Author: Alex Deucher <alex at botch2.(none)>
Date: Mon Nov 19 00:39:19 2007 -0500
Don't assign a gpio for TV
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 4dada7c..a9da889 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -227,7 +227,11 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
id = (portinfo >> 8) & 0xf;
tmp0 = RADEON_BIOS16(info->MasterDataStart + 24);
gpio = RADEON_BIOS16(tmp0 + 4 + 27 * id) * 4;
- info->BiosConnector[i].ddc_line = gpio;
+ /* don't assign a gpio for tv */
+ if ((i == 2) && (i == 6) && (i == 8))
+ info->BiosConnector[i].ddc_line = 0;
+ else
+ info->BiosConnector[i].ddc_line = gpio;
info->BiosConnector[i].output_id = id;
if (i == 3)
commit 52aba8d73189ba959f19c0437499d5e7a8829827
Merge: 862dcab... 5e8940f...
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 15:30:46 2007 +1000
Merge branch 'agd-atom' of ssh://people.freedesktop.org/~agd5f/xf86-video-ati-atom into agd-atom
commit 862dcabfe0c10751d815e5cdd7436c10c2c2db10
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 15:30:08 2007 +1000
r520: nail i2c enable/disable issue
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 619b7e2..59ed8b1 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -143,6 +143,8 @@ static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color
static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color);
static RADEONMonitorType radeon_detect_ext_dac(ScrnInfoPtr pScrn);
static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output);
+#define AVIVO_I2C_DISABLE 0
+#define AVIVO_I2C_ENABLE 1
static Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio);
extern void atombios_output_mode_set(xf86OutputPtr output,
@@ -266,9 +268,9 @@ avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
RADEONOutputPrivatePtr radeon_output = output->driver_private;
if (radeon_output->pI2CBus) {
- AVIVOI2CDoLock(output->scrn, 1, radeon_output->ddc_line);
+ AVIVOI2CDoLock(pScrn, AVIVO_I2C_ENABLE, radeon_output->ddc_line);
MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
- AVIVOI2CDoLock(output->scrn, 0, radeon_output->ddc_line);
+ AVIVOI2CDoLock(pScrn, AVIVO_I2C_DISABLE, radeon_output->ddc_line);
}
if (MonInfo) {
if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
@@ -2249,12 +2251,12 @@ Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio_reg)
temp = INREG(gpio_reg);
if (gpio_reg == AVIVO_GPIO_0) {
- if (lock_state == 0)
+ if (lock_state == AVIVO_I2C_ENABLE)
temp |= (1 << 19) | (1 << 18);
else
temp &= ~((1 << 19) | (1 << 18));
} else {
- if (lock_state == 0)
+ if (lock_state == AVIVO_I2C_ENABLE)
temp |= (1 << 0) | (1 << 8);
else
temp &= ~((1 << 0) | (1 << 8));
commit f3dd7f413b670eeb6b8639f6677d72050ad5fe04
Author: Alex Deucher <alex at botch2.(none)>
Date: Mon Nov 19 00:19:39 2007 -0500
Don't detect TV out for now
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 310072e..619b7e2 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -644,12 +644,16 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (radeon_output->MonType == MT_UNKNOWN) {
if (IS_AVIVO_VARIANT) {
- radeon_output->MonType = avivo_display_ddc_connected(pScrn, output);
- if (!radeon_output->MonType) {
- if (radeon_output->type == OUTPUT_LVDS)
- radeon_output->MonType = MT_LCD;
- if (!radeon_output->MonType)
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
+ if (OUTPUT_IS_TV)
+ radeon_output->MonType = MT_NONE;
+ else {
+ radeon_output->MonType = avivo_display_ddc_connected(pScrn, output);
+ if (!radeon_output->MonType) {
+ if (radeon_output->type == OUTPUT_LVDS)
+ radeon_output->MonType = MT_LCD;
+ else
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
+ }
}
} else {
if (OUTPUT_IS_TV) {
commit 94de0e22d7229ca71e18e1e849d8545d9ca7bafe
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 14:47:33 2007 +1000
i2c: fix bus enable stuff
diff --git a/src/radeon_output.c b/src/radeon_output.c
index b491442..310072e 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2243,7 +2243,7 @@ Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio_reg)
unsigned char *RADEONMMIO = info->MMIO;
CARD32 temp;
- temp = INREG(gpio_reg + 4);
+ temp = INREG(gpio_reg);
if (gpio_reg == AVIVO_GPIO_0) {
if (lock_state == 0)
temp |= (1 << 19) | (1 << 18);
@@ -2255,8 +2255,8 @@ Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio_reg)
else
temp &= ~((1 << 0) | (1 << 8));
}
- OUTREG(gpio_reg + 4, temp);
- temp = INREG(gpio_reg + 4);
+ OUTREG(gpio_reg, temp);
+ temp = INREG(gpio_reg);
return TRUE;
}
commit 3f1fc7eef13ea02fa5119e9b51d499841b801f2d
Author: Alex Deucher <alex at botch2.(none)>
Date: Mon Nov 19 00:02:14 2007 -0500
CRTs/DFPs may share a DVI port, but TV and CV don't
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 8b6b075..4dada7c 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -248,15 +248,18 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
return FALSE;
}
+ /* CRTs/DFPs may share a port */
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
for (j = 0; j < RADEON_MAX_BIOS_CONNECTOR; j++) {
if (info->BiosConnector[j].valid && (i != j) ) {
if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) {
- if ((i == 3) || (i == 7) || (i == 9)) {
+ if (((i == 3) || (i == 7) || (i == 9)) &&
+ ((j == 0) || (j == 4))) {
info->BiosConnector[i].DACType = info->BiosConnector[j].DACType;
info->BiosConnector[j].valid = FALSE;
- } else if ((j == 3) || (j == 7) || (j == 9)) {
+ } else if (((j == 3) || (j == 7) || (j == 9)) &&
+ ((i == 0) || (i == 4))) {
info->BiosConnector[j].DACType = info->BiosConnector[i].DACType;
info->BiosConnector[i].valid = FALSE;
}
commit 8f84c5ad4c4af14612ea68fe6f24d0d527f00acc
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 18 23:43:06 2007 -0500
fix typo in loop
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 4d1956f..8b6b075 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -250,7 +250,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
- for (j = 0; j < 8; j++) {
+ for (j = 0; j < RADEON_MAX_BIOS_CONNECTOR; j++) {
if (info->BiosConnector[j].valid && (i != j) ) {
if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) {
if ((i == 3) || (i == 7) || (i == 9)) {
commit 384cd8f52c89d089c6559e2eedbae45641fcd14e
Merge: f3f0e4e... 234b607...
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 14:02:55 2007 +1000
Merge branch 'agd-atom' of ../xf86-video-ati into agd-atom
commit f3f0e4ec92c935c89ddb2f4241fe4335a521b439
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 18 23:14:01 2007 -0500
RADEON: unify connectortype handling
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index aaa703b..4d1956f 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -42,6 +42,29 @@
#include "radeon_atombios.h"
#include "vbe.h"
+typedef enum
+{
+ DDC_NONE_DETECTED,
+ DDC_MONID,
+ DDC_DVI,
+ DDC_VGA,
+ DDC_CRT2,
+ DDC_LCD,
+ DDC_GPIO,
+} RADEONLegacyDDCType;
+
+typedef enum
+{
+ CONNECTOR_NONE_LEGACY,
+ CONNECTOR_PROPRIETARY_LEGACY,
+ CONNECTOR_CRT_LEGACY,
+ CONNECTOR_DVI_I_LEGACY,
+ CONNECTOR_DVI_D_LEGACY,
+ CONNECTOR_CTV_LEGACY,
+ CONNECTOR_STV_LEGACY,
+ CONNECTOR_UNSUPPORTED_LEGACY
+} RADEONLegacyConnectorType;
+
/* Read the Video BIOS block and the FP registers (if applicable). */
Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
{
@@ -260,7 +283,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
int offset, i, entry, tmp, tmp0, tmp1;
- RADEONDDCType DDCType;
+ RADEONLegacyDDCType DDCType;
+ RADEONLegacyConnectorType ConnectorType;
if (!info->VBIOS) return FALSE;
@@ -275,6 +299,31 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
info->BiosConnector[i].valid = TRUE;
tmp = RADEON_BIOS16(entry);
info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf;
+ ConnectorType = (tmp >> 12) & 0xf;
+ switch (ConnectorType) {
+ case CONNECTOR_PROPRIETARY_LEGACY:
+ info->BiosConnector[i].ConnectorType = CONNECTOR_LVDS;
+ break;
+ case CONNECTOR_CRT_LEGACY:
+ info->BiosConnector[i].ConnectorType = CONNECTOR_VGA;
+ break;
+ case CONNECTOR_DVI_I_LEGACY:
+ info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_I;
+ break;
+ case CONNECTOR_DVI_D_LEGACY:
+ info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D;
+ break;
+ case CONNECTOR_CTV_LEGACY:
+ info->BiosConnector[i].ConnectorType = CONNECTOR_CTV;
+ break;
+ case CONNECTOR_STV_LEGACY:
+ info->BiosConnector[i].ConnectorType = CONNECTOR_STV;
+ break;
+ default:
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown Connector Type: %d\n", ConnectorType);
+ info->BiosConnector[i].valid = FALSE;
+ break;
+ }
DDCType = (tmp >> 8) & 0xf;
switch (DDCType) {
case DDC_MONID:
@@ -308,7 +357,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
* lets see what happens with that.
*/
if (info->ChipFamily == CHIP_FAMILY_RS400 &&
- info->BiosConnector[i].ConnectorType == CONNECTOR_CRT &&
+ info->BiosConnector[i].ConnectorType == CONNECTOR_VGA &&
info->BiosConnector[i].ddc_line == RADEON_GPIO_CRT2_DDC) {
info->BiosConnector[i].ddc_line = RADEON_GPIO_MONID;
}
@@ -317,20 +366,13 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
* DVI-D, try and do the right thing here.
*/
if ((!info->IsMobility) &&
- (info->BiosConnector[i].ConnectorType == CONNECTOR_PROPRIETARY)) {
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_LVDS)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Proprietary connector found, assuming DVI-D\n");
info->BiosConnector[i].DACType = DAC_NONE;
info->BiosConnector[i].TMDSType = TMDS_EXT;
info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D;
}
-
- if (info->BiosConnector[i].ConnectorType >= CONNECTOR_UNSUPPORTED) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown connector type: %d!\n",
- info->BiosConnector[i].ConnectorType);
- info->BiosConnector[i].valid = FALSE;
- }
-
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n");
@@ -342,7 +384,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40);
if (offset) {
info->BiosConnector[4].valid = TRUE;
- info->BiosConnector[4].ConnectorType = CONNECTOR_PROPRIETARY;
+ info->BiosConnector[4].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[4].DACType = DAC_NONE;
info->BiosConnector[4].TMDSType = TMDS_NONE;
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 990b6b9..b491442 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -82,18 +82,7 @@ const char *DACTypeName[4] = {
"None"
};
-const char *ConnectorTypeName[8] = {
- "None",
- "Proprietary/LVDS",
- "VGA",
- "DVI-I",
- "DVI-D",
- "CTV",
- "STV",
- "Unsupported"
-};
-
-const char *ConnectorTypeNameATOM[10] = {
+const char *ConnectorTypeName[15] = {
"None",
"VGA",
"DVI-I",
@@ -103,10 +92,15 @@ const char *ConnectorTypeNameATOM[10] = {
"CTV",
"LVDS",
"Digital",
+ "SCART",
+ "HDMI-A",
+ "HDMI-B",
+ "DIN",
+ "DisplayPort",
"Unsupported"
};
-const char *OutputType[16] = {
+const char *OutputType[11] = {
"None",
"VGA",
"DVI",
@@ -242,7 +236,6 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output)
void RADEONPrintPortMap(ScrnInfoPtr pScrn)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
RADEONOutputPrivatePtr radeon_output;
xf86OutputPtr output;
@@ -256,8 +249,6 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn)
"Port%d:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- 0x%x\n",
o,
MonTypeName[radeon_output->MonType+1],
- info->IsAtomBios ?
- ConnectorTypeNameATOM[radeon_output->ConnectorType]:
ConnectorTypeName[radeon_output->ConnectorType],
DACTypeName[radeon_output->DACType+1],
TMDSTypeName[radeon_output->TMDSType+1],
@@ -698,10 +689,7 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (output->MonInfo) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on connector: %s ----------------------\n",
- info->IsAtomBios ?
- ConnectorTypeNameATOM[radeon_output->ConnectorType]:
- ConnectorTypeName[radeon_output->ConnectorType]
- );
+ ConnectorTypeName[radeon_output->ConnectorType]);
xf86PrintEDID( output->MonInfo );
}
}
@@ -2210,51 +2198,28 @@ static const xf86OutputFuncsRec radeon_output_funcs = {
void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output)
{
- RADEONInfoPtr info = RADEONPTR (pScrn);
RADEONOutputType output;
- if (info->IsAtomBios) {
- switch(radeon_output->ConnectorType) {
- case CONNECTOR_VGA_ATOM:
- output = OUTPUT_VGA; break;
- case CONNECTOR_DVI_I_ATOM:
- output = OUTPUT_DVI_I; break;
- case CONNECTOR_DVI_D_ATOM:
- output = OUTPUT_DVI_D; break;
- case CONNECTOR_DVI_A_ATOM:
- output = OUTPUT_DVI_A; break;
- case CONNECTOR_STV_ATOM:
- output = OUTPUT_STV; break;
- case CONNECTOR_CTV_ATOM:
- output = OUTPUT_CTV; break;
- case CONNECTOR_LVDS_ATOM:
- case CONNECTOR_DIGITAL_ATOM:
- output = OUTPUT_LVDS; break;
- case CONNECTOR_NONE_ATOM:
- case CONNECTOR_UNSUPPORTED_ATOM:
- default:
- output = OUTPUT_NONE; break;
- }
- }
- else {
- switch(radeon_output->ConnectorType) {
- case CONNECTOR_PROPRIETARY:
- output = OUTPUT_LVDS; break;
- case CONNECTOR_CRT:
- output = OUTPUT_VGA; break;
- case CONNECTOR_DVI_I:
- output = OUTPUT_DVI_I; break;
- case CONNECTOR_DVI_D:
- output = OUTPUT_DVI_D; break;
- case CONNECTOR_CTV:
- output = OUTPUT_CTV; break;
- case CONNECTOR_STV:
- output = OUTPUT_STV; break;
- case CONNECTOR_NONE:
- case CONNECTOR_UNSUPPORTED:
- default:
- output = OUTPUT_NONE; break;
- }
+ switch(radeon_output->ConnectorType) {
+ case CONNECTOR_VGA:
+ output = OUTPUT_VGA; break;
+ case CONNECTOR_DVI_I:
+ output = OUTPUT_DVI_I; break;
+ case CONNECTOR_DVI_D:
+ output = OUTPUT_DVI_D; break;
+ case CONNECTOR_DVI_A:
+ output = OUTPUT_DVI_A; break;
+ case CONNECTOR_STV:
+ output = OUTPUT_STV; break;
+ case CONNECTOR_CTV:
+ output = OUTPUT_CTV; break;
+ case CONNECTOR_LVDS:
+ output = OUTPUT_LVDS; break;
+ case CONNECTOR_DIGITAL:
+ case CONNECTOR_NONE:
+ case CONNECTOR_UNSUPPORTED:
+ default:
+ output = OUTPUT_NONE; break;
}
radeon_output->type = output;
}
@@ -2788,13 +2753,13 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[0].valid = TRUE;
info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_TVDAC;
info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
info->BiosConnector[1].valid = TRUE;
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
@@ -2807,7 +2772,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[0].valid = TRUE;
info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
@@ -2826,7 +2791,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[0].valid = TRUE;
info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
@@ -2871,7 +2836,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[0].DACType = DAC_PRIMARY;
info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
info->BiosConnector[0].valid = TRUE;
return;
}
@@ -2882,7 +2847,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK;
info->BiosConnector[0].DACType = DAC_UNKNOWN;
info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[0].valid = TRUE;
/* IGP only has TVDAC */
@@ -2892,7 +2857,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_TVDAC;
info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
info->BiosConnector[1].valid = TRUE;
} else {
#if defined(__powerpc__)
@@ -2902,13 +2867,13 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
#endif
info->BiosConnector[0].DACType = DAC_UNKNOWN;
info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[0].valid = TRUE;
info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_PRIMARY;
info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
info->BiosConnector[1].valid = TRUE;
}
} else {
@@ -2920,7 +2885,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[0].DACType = DAC_TVDAC;
info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
- info->BiosConnector[0].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
info->BiosConnector[0].valid = TRUE;
/* not sure what a good default DDCType for DVI on
@@ -2941,7 +2906,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_PRIMARY;
info->BiosConnector[1].TMDSType = TMDS_EXT;
- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
info->BiosConnector[1].valid = TRUE;
}
}
@@ -3096,12 +3061,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
if (info->HasSingleDAC) {
/* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT)
+ if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA)
info->BiosConnector[i].DACType = DAC_TVDAC;
}
} else if (!pRADEONEnt->HasCRTC2) {
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT)
+ if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA)
info->BiosConnector[i].DACType = DAC_PRIMARY;
}
}
@@ -3135,21 +3100,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
if (info->BiosConnector[i].DACType == DAC_TVDAC)
info->tvdac_use_count++;
- if (info->IsAtomBios) {
- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D_ATOM) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I_ATOM) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A_ATOM)) {
- num_dvi++;
- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA_ATOM) {
- num_vga++;
- }
- } else {
- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I)) {
- num_dvi++;
- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT) {
- num_vga++;
- }
+ if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I) ||
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) {
+ num_dvi++;
+ } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) {
+ num_vga++;
}
}
}
@@ -3164,66 +3120,35 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType;
radeon_output->ddc_line = info->BiosConnector[i].ddc_line;
radeon_output->output_id = info->BiosConnector[i].output_id;
- if (info->IsAtomBios) {
- if (radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM)
- radeon_output->DACType = DAC_NONE;
- else
- radeon_output->DACType = info->BiosConnector[i].DACType;
-
- if (radeon_output->ConnectorType == CONNECTOR_VGA_ATOM)
- radeon_output->TMDSType = TMDS_NONE;
- else
- radeon_output->TMDSType = info->BiosConnector[i].TMDSType;
- } else {
- if (radeon_output->ConnectorType == CONNECTOR_DVI_D)
- radeon_output->DACType = DAC_NONE;
- else
- radeon_output->DACType = info->BiosConnector[i].DACType;
-
- if (radeon_output->ConnectorType == CONNECTOR_CRT)
- radeon_output->TMDSType = TMDS_NONE;
- else
- radeon_output->TMDSType = info->BiosConnector[i].TMDSType;
- }
+ if (radeon_output->ConnectorType == CONNECTOR_DVI_D)
+ radeon_output->DACType = DAC_NONE;
+ else
+ radeon_output->DACType = info->BiosConnector[i].DACType;
+
+ if (radeon_output->ConnectorType == CONNECTOR_VGA)
+ radeon_output->TMDSType = TMDS_NONE;
+ else
+ radeon_output->TMDSType = info->BiosConnector[i].TMDSType;
+
RADEONSetOutputType(pScrn, radeon_output);
- if (info->IsAtomBios) {
- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D_ATOM) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I_ATOM) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A_ATOM)) {
- if (num_dvi > 1) {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-1");
- num_dvi--;
- } else {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-0");
- }
- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA_ATOM) {
- if (num_vga > 1) {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-1");
- num_vga--;
- } else {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0");
- }
- } else
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, OutputType[radeon_output->type]);
- } else {
- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I)) {
- if (num_dvi > 1) {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-1");
- num_dvi--;
- } else {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-0");
- }
- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT) {
- if (num_vga > 1) {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-1");
- num_vga--;
- } else {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0");
- }
- } else
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, OutputType[radeon_output->type]);
- }
+ if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I) ||
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) {
+ if (num_dvi > 1) {
+ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-1");
+ num_dvi--;
+ } else {
+ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-0");
+ }
+ } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) {
+ if (num_vga > 1) {
+ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-1");
+ num_vga--;
+ } else {
+ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0");
+ }
+ } else
+ output = xf86OutputCreate(pScrn, &radeon_output_funcs, OutputType[radeon_output->type]);
if (!output) {
return FALSE;
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 7c757dc..bac2f51 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -54,17 +54,6 @@
typedef enum
{
- DDC_NONE_DETECTED,
- DDC_MONID,
- DDC_DVI,
- DDC_VGA,
- DDC_CRT2,
- DDC_LCD,
- DDC_GPIO,
-} RADEONDDCType;
-
-typedef enum
-{
MT_UNKNOWN = -1,
MT_NONE = 0,
MT_CRT = 1,
@@ -80,34 +69,22 @@ typedef enum
typedef enum
{
CONNECTOR_NONE,
- CONNECTOR_PROPRIETARY,
- CONNECTOR_CRT,
+ CONNECTOR_VGA,
CONNECTOR_DVI_I,
CONNECTOR_DVI_D,
- CONNECTOR_CTV,
+ CONNECTOR_DVI_A,
CONNECTOR_STV,
+ CONNECTOR_CTV,
+ CONNECTOR_LVDS,
+ CONNECTOR_DIGITAL,
+ CONNECTOR_SCART,
+ CONNECTOR_HDMI_TYPE_A,
+ CONNECTOR_HDMI_TYPE_B,
+ CONNECTOR_DIN,
+ CONNECTOR_DISPLAY_PORT,
CONNECTOR_UNSUPPORTED
} RADEONConnectorType;
-typedef enum
-{
- CONNECTOR_NONE_ATOM,
- CONNECTOR_VGA_ATOM,
- CONNECTOR_DVI_I_ATOM,
- CONNECTOR_DVI_D_ATOM,
- CONNECTOR_DVI_A_ATOM,
- CONNECTOR_STV_ATOM,
- CONNECTOR_CTV_ATOM,
- CONNECTOR_LVDS_ATOM,
- CONNECTOR_DIGITAL_ATOM,
- CONNECTOR_SCART_ATOM,
- CONNECTOR_HDMI_TYPE_A_ATOM,
- CONNECTOR_HDMI_TYPE_B_ATOM,
- CONNECTOR_CASE_1_ATOM,
- CONNECTOR_DISPLAY_PORT_ATOM,
- CONNECTOR_UNSUPPORTED_ATOM
-} RADEONConnectorTypeATOM;
-
typedef enum {
OUTPUT_NONE_ATOM,
OUTPUT_DAC_EXTERNAL_ATOM,
commit 234b6073054ac7630e82781683e666b94b2f12de
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 14:02:09 2007 +1000
restore avivo memory map registers at correct places
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 9305592..c30e2de 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -450,6 +450,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
if (IS_AVIVO_VARIANT) {
+ RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg);
radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay;
radeon_crtc->fb_height = pScrn->virtualY;
radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 69f8c76..fa04413 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1346,6 +1346,9 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
*/
info->mc_agp_location = 0xffffffc0;
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
+ }
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONInitMemoryMap() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -5797,6 +5800,7 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
+ RADEONRestoreMemMapRegisters(pScrn, restore);
}
/* Save everything needed to restore the original VC state */
commit 459a30ba511fe2fa8051380a9741fcfd9bb401ef
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 13:44:38 2007 +1000
fix type for r520 agp code
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index de75ee3..69f8c76 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4136,7 +4136,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
agp = INMC(pScrn, RV515_MC_AGP_LOCATION);
} else {
fb = INMC(pScrn, R520_MC_FB_LOCATION);
- agp = INMC(pScrn, RV515_MC_AGP_LOCATION);
+ agp = INMC(pScrn, R520_MC_AGP_LOCATION);
}
fb_loc_changed = (fb != info->mc_fb_location);
commit 760af92412ef0d5cc44e52e7cec11fd80c4aaaeb
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 18 22:34:59 2007 -0500
RADEON: unify DDC line handling
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 0e14d94..aaa703b 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -204,33 +204,9 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
id = (portinfo >> 8) & 0xf;
tmp0 = RADEON_BIOS16(info->MasterDataStart + 24);
gpio = RADEON_BIOS16(tmp0 + 4 + 27 * id) * 4;
- info->BiosConnector[i].gpio = gpio;
+ info->BiosConnector[i].ddc_line = gpio;
info->BiosConnector[i].output_id = id;
- switch(gpio) {
- case RADEON_GPIO_MONID:
- info->BiosConnector[i].DDCType = DDC_MONID;
- break;
- case RADEON_GPIO_DVI_DDC:
- info->BiosConnector[i].DDCType = DDC_DVI;
- break;
- case RADEON_GPIO_VGA_DDC:
- info->BiosConnector[i].DDCType = DDC_VGA;
- break;
- case RADEON_GPIO_CRT2_DDC:
- info->BiosConnector[i].DDCType = DDC_CRT2;
- break;
- case RADEON_LCD_GPIO_MASK:
- info->BiosConnector[i].DDCType = DDC_LCD;
- break;
- case RADEON_MDGPIO_EN_REG:
- info->BiosConnector[i].DDCType = DDC_GPIO;
- break;
- default:
- info->BiosConnector[i].DDCType = DDC_NONE_DETECTED;
- break;
- }
-
if (i == 3)
info->BiosConnector[i].TMDSType = TMDS_INT;
else if (i == 7)
@@ -271,8 +247,8 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n");
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-%d, DACType-%d, TMDSType-%d, ConnectorType-%d\n",
- i, info->BiosConnector[i].DDCType, info->BiosConnector[i].DACType,
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x, DACType-%d, TMDSType-%d, ConnectorType-%d\n",
+ i, info->BiosConnector[i].ddc_line, info->BiosConnector[i].DACType,
info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType);
}
}
@@ -284,6 +260,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
int offset, i, entry, tmp, tmp0, tmp1;
+ RADEONDDCType DDCType;
if (!info->VBIOS) return FALSE;
@@ -298,7 +275,30 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
info->BiosConnector[i].valid = TRUE;
tmp = RADEON_BIOS16(entry);
info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf;
- info->BiosConnector[i].DDCType = (tmp >> 8) & 0xf;
+ DDCType = (tmp >> 8) & 0xf;
+ switch (DDCType) {
+ case DDC_MONID:
+ info->BiosConnector[i].ddc_line = RADEON_GPIO_MONID;
+ break;
+ case DDC_DVI:
+ info->BiosConnector[i].ddc_line = RADEON_GPIO_DVI_DDC;
+ break;
+ case DDC_VGA:
+ info->BiosConnector[i].ddc_line = RADEON_GPIO_VGA_DDC;
+ break;
+ case DDC_CRT2:
+ info->BiosConnector[i].ddc_line = RADEON_GPIO_CRT2_DDC;
+ break;
+ case DDC_LCD:
+ info->BiosConnector[i].ddc_line = RADEON_LCD_GPIO_MASK;
+ break;
+ case DDC_GPIO:
+ info->BiosConnector[i].ddc_line = RADEON_MDGPIO_EN_REG;
+ break;
+ default:
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType);
+ break;
+ }
info->BiosConnector[i].DACType = tmp & 0x1;
info->BiosConnector[i].TMDSType = (tmp >> 4) & 0x1;
@@ -309,8 +309,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
*/
if (info->ChipFamily == CHIP_FAMILY_RS400 &&
info->BiosConnector[i].ConnectorType == CONNECTOR_CRT &&
- info->BiosConnector[i].DDCType == DDC_CRT2) {
- info->BiosConnector[i].DDCType = DDC_MONID;
+ info->BiosConnector[i].ddc_line == RADEON_GPIO_CRT2_DDC) {
+ info->BiosConnector[i].ddc_line = RADEON_GPIO_MONID;
}
/* XPRESS desktop chips seem to have a proprietary connector listed for
@@ -351,19 +351,36 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
tmp0 = RADEON_BIOS16(tmp + 0x15);
if (tmp0) {
tmp1 = RADEON_BIOS8(tmp0+2) & 0x07;
- if (tmp1) {
- info->BiosConnector[4].DDCType = tmp1;
- if (info->BiosConnector[4].DDCType > DDC_GPIO) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Unknown DDCType %d found\n",
- info->BiosConnector[4].DDCType);
- info->BiosConnector[4].DDCType = DDC_NONE_DETECTED;
+ if (tmp1) {
+ DDCType = tmp1;
+ switch (DDCType) {
+ case DDC_MONID:
+ info->BiosConnector[4].ddc_line = RADEON_GPIO_MONID;
+ break;
+ case DDC_DVI:
+ info->BiosConnector[4].ddc_line = RADEON_GPIO_DVI_DDC;
+ break;
+ case DDC_VGA:
+ info->BiosConnector[4].ddc_line = RADEON_GPIO_VGA_DDC;
+ break;
+ case DDC_CRT2:
+ info->BiosConnector[4].ddc_line = RADEON_GPIO_CRT2_DDC;
+ break;
+ case DDC_LCD:
+ info->BiosConnector[4].ddc_line = RADEON_LCD_GPIO_MASK;
+ break;
+ case DDC_GPIO:
+ info->BiosConnector[4].ddc_line = RADEON_MDGPIO_EN_REG;
+ break;
+ default:
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType);
+ break;
}
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n");
}
}
} else {
- info->BiosConnector[4].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[4].ddc_line = 0;
}
}
}
@@ -378,7 +395,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
info->BiosConnector[5].ConnectorType = CONNECTOR_STV;
info->BiosConnector[5].DACType = DAC_TVDAC;
info->BiosConnector[5].TMDSType = TMDS_NONE;
- info->BiosConnector[5].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[5].ddc_line = 0;
}
}
}
@@ -386,8 +403,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n");
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-%d, DACType-%d, TMDSType-%d, ConnectorType-%d\n",
- i, info->BiosConnector[i].DDCType, info->BiosConnector[i].DACType,
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x, DACType-%d, TMDSType-%d, ConnectorType-%d\n",
+ i, info->BiosConnector[i].ddc_line, info->BiosConnector[i].DACType,
info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType);
}
}
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 6ac3980..990b6b9 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -75,16 +75,6 @@ const char *TMDSTypeName[4] = {
"None"
};
-const char *DDCTypeName[7] = {
- "None",
- "MONID",
- "DVI_DDC",
- "VGA_DDC",
- "CRT2_DDC",
- "LCD_DDC",
- "GPIO_DDC"
-};
-
const char *DACTypeName[4] = {
"Unknown",
"Primary",
@@ -116,7 +106,7 @@ const char *ConnectorTypeNameATOM[10] = {
"Unsupported"
};
-const char *OutputType[10] = {
+const char *OutputType[16] = {
"None",
"VGA",
"DVI",
@@ -263,7 +253,7 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn)
radeon_output = output->driver_private;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Port%d:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s [0x%x]\n",
+ "Port%d:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- 0x%x\n",
o,
MonTypeName[radeon_output->MonType+1],
info->IsAtomBios ?
@@ -271,8 +261,7 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn)
ConnectorTypeName[radeon_output->ConnectorType],
DACTypeName[radeon_output->DACType+1],
TMDSTypeName[radeon_output->TMDSType+1],
- DDCTypeName[radeon_output->DDCType],
- radeon_output->gpio);
+ radeon_output->ddc_line);
}
}
@@ -281,16 +270,14 @@ static RADEONMonitorType
avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned long DDCReg;
RADEONMonitorType MonType = MT_NONE;
xf86MonPtr MonInfo = NULL;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONDDCType DDCType = radeon_output->DDCType;
if (radeon_output->pI2CBus) {
- AVIVOI2CDoLock(output->scrn, 1, radeon_output->gpio);
+ AVIVOI2CDoLock(output->scrn, 1, radeon_output->ddc_line);
MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
- AVIVOI2CDoLock(output->scrn, 0, radeon_output->gpio);
+ AVIVOI2CDoLock(output->scrn, 0, radeon_output->ddc_line);
}
if (MonInfo) {
if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
@@ -306,7 +293,7 @@ avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
} else MonType = MT_NONE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "DDC Type: %d[%04x], Detected Monitor Type: %d\n", DDCType, radeon_output->gpio, MonType);
+ "DDC Type: 0x%x, Detected Monitor Type: %d\n", radeon_output->ddc_line, MonType);
return MonType;
}
@@ -316,14 +303,13 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- unsigned long DDCReg;
+ CARD32 DDCReg;
RADEONMonitorType MonType = MT_NONE;
xf86MonPtr MonInfo = NULL;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONDDCType DDCType = radeon_output->DDCType;
int i, j;
- DDCReg = radeon_output->DDCReg;
+ DDCReg = radeon_output->ddc_line;
/* Read and output monitor info using DDC2 over I2C bus */
if (radeon_output->pI2CBus && info->ddc2 && (DDCReg != RADEON_LCD_GPIO_MASK) && (DDCReg != RADEON_MDGPIO_EN_REG)) {
@@ -405,7 +391,7 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output)
} else MonType = MT_NONE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "DDC Type: %d, Detected Monitor Type: %d\n", DDCType, MonType);
+ "DDC Type: 0x%x, Detected Monitor Type: %d\n", radeon_output->ddc_line, MonType);
return MonType;
}
@@ -2729,26 +2715,18 @@ void RADEONInitConnector(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int DDCReg = 0;
- char* name = (char*) DDCTypeName[radeon_output->DDCType];
+ char stmp[16];
+ char *name;
+ sprintf(stmp, "DDC_0x%x", radeon_output->ddc_line);
+ name = xnfalloc(strlen(stmp) + 1);
+ strcpy(name, stmp);
if (IS_AVIVO_VARIANT) {
- if (radeon_output->gpio)
- avivo_i2c_init(pScrn, &radeon_output->pI2CBus, radeon_output->gpio, name);
+ if (radeon_output->ddc_line)
+ avivo_i2c_init(pScrn, &radeon_output->pI2CBus, radeon_output->ddc_line, name);
} else {
- switch(radeon_output->DDCType) {
- case DDC_MONID: DDCReg = RADEON_GPIO_MONID; break;
- case DDC_DVI : DDCReg = RADEON_GPIO_DVI_DDC; break;
- case DDC_VGA : DDCReg = RADEON_GPIO_VGA_DDC; break;
- case DDC_CRT2 : DDCReg = RADEON_GPIO_CRT2_DDC; break;
- case DDC_LCD : DDCReg = RADEON_LCD_GPIO_MASK; break;
- case DDC_GPIO : DDCReg = RADEON_MDGPIO_EN_REG; break;
- default: break;
- }
- if (DDCReg) {
- radeon_output->DDCReg = DDCReg;
- RADEONI2CInit(pScrn, &radeon_output->pI2CBus, DDCReg, name);
- }
+ if (radeon_output->ddc_line)
+ RADEONI2CInit(pScrn, &radeon_output->pI2CBus, radeon_output->ddc_line, name);
}
if (radeon_output->DACType == DAC_PRIMARY)
@@ -2807,13 +2785,13 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
switch (info->MacModel) {
case RADEON_MAC_IBOOK:
- info->BiosConnector[0].DDCType = DDC_DVI;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_TVDAC;
info->BiosConnector[1].TMDSType = TMDS_NONE;
info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
@@ -2822,17 +2800,17 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].ddc_line = 0;
info->BiosConnector[2].valid = TRUE;
return TRUE;
case RADEON_MAC_POWERBOOK_DL:
- info->BiosConnector[0].DDCType = DDC_DVI;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_PRIMARY;
info->BiosConnector[1].TMDSType = TMDS_EXT;
info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
@@ -2841,17 +2819,17 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].ddc_line = 0;
info->BiosConnector[2].valid = TRUE;
return TRUE;
case RADEON_MAC_POWERBOOK:
- info->BiosConnector[0].DDCType = DDC_DVI;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_PRIMARY;
info->BiosConnector[1].TMDSType = TMDS_INT;
info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
@@ -2860,11 +2838,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].ddc_line = 0;
info->BiosConnector[2].valid = TRUE;
return TRUE;
case RADEON_MAC_MINI:
- info->BiosConnector[0].DDCType = DDC_CRT2;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC;
info->BiosConnector[0].DACType = DAC_TVDAC;
info->BiosConnector[0].TMDSType = TMDS_EXT;
info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
@@ -2873,7 +2851,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[1].ConnectorType = CONNECTOR_STV;
info->BiosConnector[1].DACType = DAC_TVDAC;
info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[1].ddc_line = 0;
info->BiosConnector[1].valid = TRUE;
return TRUE;
default:
@@ -2890,7 +2868,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
if (!pRADEONEnt->HasCRTC2) {
- info->BiosConnector[0].DDCType = DDC_VGA;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[0].DACType = DAC_PRIMARY;
info->BiosConnector[0].TMDSType = TMDS_NONE;
info->BiosConnector[0].ConnectorType = CONNECTOR_CRT;
@@ -2901,7 +2879,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
if (info->IsMobility) {
/* Below is the most common setting, but may not be true */
if (info->IsIGP) {
- info->BiosConnector[0].DDCType = DDC_LCD;
+ info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK;
info->BiosConnector[0].DACType = DAC_UNKNOWN;
info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
@@ -2909,25 +2887,25 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
/* IGP only has TVDAC */
if (info->ChipFamily == CHIP_FAMILY_RS400)
- info->BiosConnector[1].DDCType = DDC_CRT2;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_CRT2_DDC;
else
- info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_TVDAC;
info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
info->BiosConnector[1].valid = TRUE;
} else {
#if defined(__powerpc__)
- info->BiosConnector[0].DDCType = DDC_DVI;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
#else
- info->BiosConnector[0].DDCType = DDC_LCD;
+ info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK;
#endif
info->BiosConnector[0].DACType = DAC_UNKNOWN;
info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_PRIMARY;
info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
@@ -2937,9 +2915,9 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
/* Below is the most common setting, but may not be true */
if (info->IsIGP) {
if (info->ChipFamily == CHIP_FAMILY_RS400)
- info->BiosConnector[0].DDCType = DDC_CRT2;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC;
else
- info->BiosConnector[0].DDCType = DDC_VGA;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[0].DACType = DAC_TVDAC;
info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
info->BiosConnector[0].ConnectorType = CONNECTOR_CRT;
@@ -2948,19 +2926,19 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
/* not sure what a good default DDCType for DVI on
* IGP desktop chips is
*/
- info->BiosConnector[1].DDCType = DDC_MONID; /* DDC_DVI? */
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_MONID; /* DDC_DVI? */
info->BiosConnector[1].DACType = DAC_UNKNOWN;
info->BiosConnector[1].TMDSType = TMDS_EXT;
info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_D;
info->BiosConnector[1].valid = TRUE;
} else {
- info->BiosConnector[0].DDCType = DDC_DVI;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
info->BiosConnector[0].DACType = DAC_TVDAC;
info->BiosConnector[0].TMDSType = TMDS_INT;
info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC;
info->BiosConnector[1].DACType = DAC_PRIMARY;
info->BiosConnector[1].TMDSType = TMDS_EXT;
info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
@@ -2972,7 +2950,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
info->BiosConnector[2].DACType = DAC_TVDAC;
info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].ddc_line = 0;
info->BiosConnector[2].valid = TRUE;
}
@@ -2980,8 +2958,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
* detect it yet (Mac cards)
*/
if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
- info->BiosConnector[0].DDCType = DDC_VGA;
- info->BiosConnector[1].DDCType = DDC_DVI;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC;
+ info->BiosConnector[1].ddc_line = RADEON_GPIO_DVI_DDC;
}
}
@@ -3076,7 +3054,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
*/
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
info->BiosConnector[i].valid = FALSE;
- info->BiosConnector[i].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[i].ddc_line = 0;
info->BiosConnector[i].DACType = DAC_UNKNOWN;
info->BiosConnector[i].TMDSType = TMDS_UNKNOWN;
info->BiosConnector[i].ConnectorType = CONNECTOR_NONE;
@@ -3138,11 +3116,11 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].valid = TRUE;
info->BiosConnector[1].valid = TRUE;
if (sscanf(optstr, "%u,%d,%d,%u,%u,%d,%d,%u",
- &info->BiosConnector[0].DDCType,
+ &info->BiosConnector[0].ddc_line,
&info->BiosConnector[0].DACType,
&info->BiosConnector[0].TMDSType,
&info->BiosConnector[0].ConnectorType,
- &info->BiosConnector[1].DDCType,
+ &info->BiosConnector[1].ddc_line,
&info->BiosConnector[1].DACType,
&info->BiosConnector[1].TMDSType,
&info->BiosConnector[1].ConnectorType) != 8) {
@@ -3184,9 +3162,8 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
}
radeon_output->MonType = MT_UNKNOWN;
radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType;
- radeon_output->gpio = info->BiosConnector[i].gpio;
+ radeon_output->ddc_line = info->BiosConnector[i].ddc_line;
radeon_output->output_id = info->BiosConnector[i].output_id;
- radeon_output->DDCType = info->BiosConnector[i].DDCType;
if (info->IsAtomBios) {
if (radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM)
radeon_output->DACType = DAC_NONE;
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index ad732f6..7c757dc 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -211,12 +211,11 @@ typedef struct _RADEONCrtcPrivateRec {
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct {
- RADEONDDCType DDCType;
+ CARD32 ddc_line;
RADEONDacType DACType;
RADEONTmdsType TMDSType;
RADEONConnectorType ConnectorType;
Bool valid;
- int gpio;
int output_id;
} RADEONBIOSConnector;
@@ -224,7 +223,7 @@ typedef struct _RADEONOutputPrivateRec {
int num;
RADEONOutputType type;
void *dev_priv;
- RADEONDDCType DDCType;
+ CARD32 ddc_line;
RADEONDacType DACType;
RADEONDviType DVIType;
RADEONTmdsType TMDSType;
@@ -264,7 +263,6 @@ typedef struct _RADEONOutputPrivateRec {
Bool tv_on;
int load_detection;
- unsigned long gpio;
char *name;
int output_id;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
commit e73bf6290da20dd61798ace775999ce1cb550934
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 19 13:32:16 2007 +1000
add x1900xt support
diff --git a/src/atipciids.h b/src/atipciids.h
index 685b811..9c45c24 100644
--- a/src/atipciids.h
+++ b/src/atipciids.h
@@ -288,7 +288,7 @@
#define PCI_CHIP_RV515_7142 0x7142
#define PCI_CHIP_RV515_7183 0x7183
-
+#define PCI_CHIP_R580_7249 0x7249
/* Misc */
#define PCI_CHIP_AMD761 0x700E
diff --git a/src/radeon.h b/src/radeon.h
index 7c32693..e00b6be 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -496,6 +496,7 @@ typedef enum {
CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */
CHIP_FAMILY_RV515, /* rv515 */
CHIP_FAMILY_R520, /* r520 */
+ CHIP_FAMILY_R580, /* r580 */
CHIP_FAMILY_R600, /* r60 */
CHIP_FAMILY_LAST
} RADEONChipFamily;
diff --git a/src/radeon_chipset.h b/src/radeon_chipset.h
index d6d8bae..b2e20d2 100644
--- a/src/radeon_chipset.h
+++ b/src/radeon_chipset.h
@@ -139,6 +139,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" },
{ PCI_CHIP_RV515_7142, "ATI AVIVO X1300 (PCIE)"},
{ PCI_CHIP_RV515_7183, "ATI AVIVO X1550PRO (PCI/PCIE)"},
+ { PCI_CHIP_R580_7249, "ATI Radeon X1900 XT"},
{ -1, NULL }
};
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index cabc539..de75ee3 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1840,6 +1840,10 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->ChipFamily = CHIP_FAMILY_RV515;
break;
+ case PCI_CHIP_R580_7249:
+ info->ChipFamily = CHIP_FAMILY_R580;
+ break;
+
default:
/* Original Radeon/7200 */
info->ChipFamily = CHIP_FAMILY_RADEON;
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index 7a3c908..c1ed105 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -194,6 +194,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA },
{ PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA },
{ PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA },
+ { PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
commit 2e37937bacd624d616b91c41006c113791ebe98d
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 18 20:18:50 2007 -0500
RADEON: step one in output rework
re-organize the output type
diff --git a/src/radeon_modes.c b/src/radeon_modes.c
index 3c4badd..21fb659 100644
--- a/src/radeon_modes.c
+++ b/src/radeon_modes.c
@@ -214,7 +214,7 @@ RADEONProbeOutputModes(xf86OutputPtr output)
ErrorF("in RADEONProbeOutputModes\n");
if (output->status == XF86OutputStatusConnected) {
- if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) {
+ if (OUTPUT_IS_TV) {
modes = RADEONTVModes(output);
} else {
if (output->MonInfo)
diff --git a/src/radeon_output.c b/src/radeon_output.c
index e61b978..6ac3980 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -120,9 +120,14 @@ const char *OutputType[10] = {
"None",
"VGA",
"DVI",
+ "DVI",
+ "DVI",
"LVDS",
"S-video",
"Composite",
+ "Component",
+ "HDMI",
+ "DisplayPort",
};
static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] =
@@ -290,18 +295,14 @@ avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (MonInfo) {
if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
xf86OutputSetEDID(output, MonInfo);
- if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_LVDS_ATOM) ||
- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_PROPRIETARY)) {
+ if (radeon_output->type == OUTPUT_LVDS)
MonType = MT_LCD;
- } else if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM) ||
- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D)) {
+ else if (radeon_output->type == OUTPUT_DVI_D)
MonType = MT_DFP;
- } else if (radeon_output->type == OUTPUT_DVI &&
- (MonInfo->rawData[0x14] & 0x80)) { /* if it's digital and DVI */
+ else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */
MonType = MT_DFP;
- } else {
+ else
MonType = MT_CRT;
- }
} else MonType = MT_NONE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -393,18 +394,14 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (MonInfo) {
if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
xf86OutputSetEDID(output, MonInfo);
- if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_LVDS_ATOM) ||
- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_PROPRIETARY)) {
+ if (radeon_output->type == OUTPUT_LVDS)
MonType = MT_LCD;
- } else if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM) ||
- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D)) {
+ else if (radeon_output->type == OUTPUT_DVI_D)
MonType = MT_DFP;
- } else if (radeon_output->type == OUTPUT_DVI &&
- (MonInfo->rawData[0x14] & 0x80)) { /* if it's digital and DVI */
+ else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */
MonType = MT_DFP;
- } else {
+ else
MonType = MT_CRT;
- }
} else MonType = MT_NONE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -669,29 +666,26 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
RADEONOutputPrivatePtr radeon_output = output->driver_private;
if (radeon_output->MonType == MT_UNKNOWN) {
- if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) {
- if (info->InternalTVOut) {
- if (radeon_output->load_detection)
- radeon_output->MonType = radeon_detect_tv(pScrn);
- else
- radeon_output->MonType = MT_NONE;
+ if (IS_AVIVO_VARIANT) {
+ radeon_output->MonType = avivo_display_ddc_connected(pScrn, output);
+ if (!radeon_output->MonType) {
+ if (radeon_output->type == OUTPUT_LVDS)
+ radeon_output->MonType = MT_LCD;
+ if (!radeon_output->MonType)
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
}
} else {
- if (IS_AVIVO_VARIANT)
- radeon_output->MonType = avivo_display_ddc_connected(pScrn, output);
- else
+ if (OUTPUT_IS_TV) {
+ if (info->InternalTVOut) {
+ if (radeon_output->load_detection)
+ radeon_output->MonType = radeon_detect_tv(pScrn);
+ else
+ radeon_output->MonType = MT_NONE;
+ }
+ } else {
radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output);
- if (!radeon_output->MonType) {
- if (IS_AVIVO_VARIANT) {
- if (!radeon_output->MonType) {
- if (radeon_output->type == OUTPUT_LVDS)
- radeon_output->MonType = MT_LCD;
- if (!radeon_output->MonType) {
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
- }
- }
- } else {
- if (radeon_output->type == OUTPUT_LVDS || radeon_output->type == OUTPUT_DVI)
+ if (!radeon_output->MonType) {
+ if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI)
radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output);
if (!radeon_output->MonType) {
if (radeon_output->DACType == DAC_PRIMARY) {
@@ -746,7 +740,7 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr
} else
#endif
MonType = MT_LCD;
- } else if (radeon_output->type == OUTPUT_DVI) {
+ } else if (OUTPUT_IS_DVI) {
if (radeon_output->TMDSType == TMDS_INT) {
if (INREG(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
MonType = MT_DFP;
@@ -757,7 +751,7 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Detected Monitor Type: %d\n", MonType);
+ "Detected non-DDC Monitor Type: %d\n", MonType);
return MonType;
@@ -803,8 +797,7 @@ radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- if (radeon_output->type == OUTPUT_STV ||
- radeon_output->type == OUTPUT_CTV) {
+ if (OUTPUT_IS_TV) {
/* FIXME: Update when more modes are added */
if (pMode->HDisplay == 800 && pMode->VDisplay == 600)
return MODE_OK;
@@ -1705,19 +1698,6 @@ radeon_detect(xf86OutputPtr output)
radeon_output->MonType = MT_UNKNOWN;
RADEONConnectorFindMonitor(pScrn, output);
- /* force montype based on output property */
- if (radeon_output->type == OUTPUT_DVI) {
- if (radeon_output->MonType == MT_NONE)
- connected = FALSE;
- if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I_ATOM) ||
- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I)) {
- if (radeon_output->DVIType == DVI_ANALOG)
- radeon_output->MonType = MT_CRT;
- else if (radeon_output->DVIType == DVI_DIGITAL)
- radeon_output->MonType = MT_DFP;
- }
- }
-
/* set montype so users can force outputs on even if detection fails */
if (radeon_output->MonType == MT_NONE) {
connected = FALSE;
@@ -1729,9 +1709,20 @@ radeon_detect(xf86OutputPtr output)
radeon_output->MonType = MT_STV;
else if (radeon_output->type == OUTPUT_CTV)
radeon_output->MonType = MT_CTV;
- else if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM) ||
- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D))
+ else if (radeon_output->type == OUTPUT_CV)
+ radeon_output->MonType = MT_CV;
+ else if (radeon_output->type == OUTPUT_DVI_D)
radeon_output->MonType = MT_DFP;
+ else if (radeon_output->type == OUTPUT_DVI_A)
+ radeon_output->MonType = MT_CRT;
+ else if (radeon_output->type == OUTPUT_DVI_I) {
+ if (radeon_output->MonType == MT_NONE)
+ connected = FALSE;
+ if (radeon_output->DVIType == DVI_ANALOG)
+ radeon_output->MonType = MT_CRT;
+ else if (radeon_output->DVIType == DVI_DIGITAL)
+ radeon_output->MonType = MT_DFP;
+ }
}
if (radeon_output->MonType == MT_UNKNOWN) {
@@ -1753,9 +1744,9 @@ radeon_detect(xf86OutputPtr output)
/* default to unknown for flaky chips/connectors
* so we can get something on the screen
*/
- if (((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI) &&
+ if (((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) &&
radeon_output->DACType == DAC_TVDAC) ||
- (info->IsIGP && radeon_output->type == OUTPUT_DVI))
+ (info->IsIGP && radeon_output->type == OUTPUT_DVI_D))
return XF86OutputStatusUnknown;
}
@@ -1880,8 +1871,7 @@ radeon_create_resources(xf86OutputPtr output)
}
}
- if (radeon_output->type == OUTPUT_DVI &&
- radeon_output->TMDSType == TMDS_INT) {
+ if (OUTPUT_IS_DVI && radeon_output->TMDSType == TMDS_INT) {
tmds_pll_atom = MAKE_ATOM("tmds_pll");
err = RRConfigureOutputProperty(output->randr_output, tmds_pll_atom,
@@ -1912,8 +1902,7 @@ radeon_create_resources(xf86OutputPtr output)
/* RMX control - fullscreen, centered, keep ratio, off */
/* actually more of a crtc property as only crtc1 has rmx */
- if (radeon_output->type == OUTPUT_LVDS ||
- radeon_output->type == OUTPUT_DVI) {
+ if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI) {
rmx_atom = MAKE_ATOM("scaler");
err = RRConfigureOutputProperty(output->randr_output, rmx_atom,
@@ -1937,31 +1926,27 @@ radeon_create_resources(xf86OutputPtr output)
}
/* force auto/analog/digital for DVI-I ports */
- if (radeon_output->type == OUTPUT_DVI) {
- if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I_ATOM) ||
- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I)) {
- monitor_type_atom = MAKE_ATOM("dvi_monitor_type");
-
- err = RRConfigureOutputProperty(output->randr_output, monitor_type_atom,
- FALSE, FALSE, FALSE, 0, NULL);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
- /* Set the current value of the backlight property */
- s = "auto";
- err = RRChangeOutputProperty(output->randr_output, monitor_type_atom,
- XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s,
- FALSE, FALSE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
+ if (radeon_output->type == OUTPUT_DVI_I) {
+ monitor_type_atom = MAKE_ATOM("dvi_monitor_type");
+
+ err = RRConfigureOutputProperty(output->randr_output, monitor_type_atom,
+ FALSE, FALSE, FALSE, 0, NULL);
+ if (err != 0) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "RRConfigureOutputProperty error, %d\n", err);
+ }
+ /* Set the current value of the backlight property */
+ s = "auto";
+ err = RRChangeOutputProperty(output->randr_output, monitor_type_atom,
+ XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s,
+ FALSE, FALSE);
+ if (err != 0) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "RRChangeOutputProperty error, %d\n", err);
}
}
- if (radeon_output->type == OUTPUT_STV ||
- radeon_output->type == OUTPUT_CTV) {
+ if (OUTPUT_IS_TV) {
tv_hsize_atom = MAKE_ATOM("tv_horizontal_size");
range[0] = -MAX_H_SIZE;
@@ -1980,10 +1965,7 @@ radeon_create_resources(xf86OutputPtr output)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RRChangeOutputProperty error, %d\n", err);
}
- }
- if (radeon_output->type == OUTPUT_STV ||
- radeon_output->type == OUTPUT_CTV) {
tv_hpos_atom = MAKE_ATOM("tv_horizontal_position");
range[0] = -MAX_H_POSITION;
@@ -2002,10 +1984,7 @@ radeon_create_resources(xf86OutputPtr output)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RRChangeOutputProperty error, %d\n", err);
}
- }
- if (radeon_output->type == OUTPUT_STV ||
- radeon_output->type == OUTPUT_CTV) {
tv_vpos_atom = MAKE_ATOM("tv_vertical_position");
range[0] = -MAX_V_POSITION;
@@ -2024,10 +2003,7 @@ radeon_create_resources(xf86OutputPtr output)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RRChangeOutputProperty error, %d\n", err);
}
- }
- if (radeon_output->type == OUTPUT_STV ||
- radeon_output->type == OUTPUT_CTV) {
tv_std_atom = MAKE_ATOM("tv_standard");
err = RRConfigureOutputProperty(output->randr_output, tv_std_atom,
@@ -2256,9 +2232,11 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output
case CONNECTOR_VGA_ATOM:
output = OUTPUT_VGA; break;
case CONNECTOR_DVI_I_ATOM:
+ output = OUTPUT_DVI_I; break;
case CONNECTOR_DVI_D_ATOM:
+ output = OUTPUT_DVI_D; break;
case CONNECTOR_DVI_A_ATOM:
- output = OUTPUT_DVI; break;
+ output = OUTPUT_DVI_A; break;
case CONNECTOR_STV_ATOM:
output = OUTPUT_STV; break;
case CONNECTOR_CTV_ATOM:
@@ -2279,8 +2257,9 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output
case CONNECTOR_CRT:
output = OUTPUT_VGA; break;
case CONNECTOR_DVI_I:
+ output = OUTPUT_DVI_I; break;
case CONNECTOR_DVI_D:
- output = OUTPUT_DVI; break;
+ output = OUTPUT_DVI_D; break;
case CONNECTOR_CTV:
output = OUTPUT_CTV; break;
case CONNECTOR_STV:
@@ -2785,7 +2764,7 @@ void RADEONInitConnector(xf86OutputPtr output)
RADEONGetLVDSInfo(output);
}
- if (radeon_output->type == OUTPUT_DVI) {
+ if (OUTPUT_IS_DVI) {
I2CBusPtr pDVOBus;
radeon_output->rmx_type = RMX_OFF;
if (radeon_output->TMDSType == TMDS_EXT) {
@@ -2809,8 +2788,7 @@ void RADEONInitConnector(xf86OutputPtr output)
RADEONGetTMDSInfo(output);
}
- if (radeon_output->type == OUTPUT_STV ||
- radeon_output->type == OUTPUT_CTV) {
+ if (OUTPUT_IS_TV) {
RADEONGetTVInfo(output);
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 5f098a7..ad732f6 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -72,7 +72,9 @@ typedef enum
MT_DFP = 3,
MT_CTV = 4,
MT_STV = 5,
- MT_CV = 6
+ MT_CV = 6,
+ MT_HDMI = 7,
+ MT_DP = 8
} RADEONMonitorType;
typedef enum
@@ -158,12 +160,23 @@ typedef enum
{
OUTPUT_NONE,
OUTPUT_VGA,
- OUTPUT_DVI,
+ OUTPUT_DVI_I,
+ OUTPUT_DVI_D,
+ OUTPUT_DVI_A,
OUTPUT_LVDS,
OUTPUT_STV,
OUTPUT_CTV,
+ OUTPUT_CV,
+ OUTPUT_HDMI,
+ OUTPUT_DP
} RADEONOutputType;
+#define OUTPUT_IS_DVI ((radeon_output->type == OUTPUT_DVI_D || \
+ radeon_output->type == OUTPUT_DVI_I || \
+ radeon_output->type == OUTPUT_DVI_A))
+#define OUTPUT_IS_TV ((radeon_output->type == OUTPUT_STV || \
+ radeon_output->type == OUTPUT_CTV))
+
/* standards */
typedef enum
{
commit 679e7a2e0d1b213524b8109193483bc9840fb116
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 18 17:56:51 2007 -0500
Few fixes from the last commit.
Update parser works fine on r4xx.
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 15612fb..46ceea8 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -65,8 +65,8 @@ static AtomBiosResult rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle,
AtomBiosRequestID func, AtomBiosArgPtr data);
static AtomBiosResult rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle,
AtomBiosRequestID func, AtomBiosArgPtr data);
-static AtomBiosResult rhdAtomConnectorInfo(atomBiosHandlePtr handle,
- AtomBiosRequestID unused, AtomBiosArgPtr data);
+/*static AtomBiosResult rhdAtomConnectorInfo(atomBiosHandlePtr handle,
+ AtomBiosRequestID unused, AtomBiosArgPtr data);*/
# ifdef ATOM_BIOS_PARSER
static AtomBiosResult rhdAtomExec(atomBiosHandlePtr handle,
AtomBiosRequestID unused, AtomBiosArgPtr data);
@@ -98,8 +98,8 @@ struct atomBIOSRequests {
#endif
{ATOMBIOS_ALLOCATE_FB_SCRATCH, rhdAtomAllocateFbScratch,
"AtomBIOS Set FB Space", MSG_FORMAT_NONE},
- {ATOMBIOS_GET_CONNECTORS, rhdAtomConnectorInfo,
- "AtomBIOS Get Connectors", MSG_FORMAT_NONE},
+ /*{ATOMBIOS_GET_CONNECTORS, rhdAtomConnectorInfo,
+ "AtomBIOS Get Connectors", MSG_FORMAT_NONE},*/
{ATOMBIOS_GET_PANEL_MODE, rhdAtomLvdsGetTimings,
"AtomBIOS Get Panel Mode", MSG_FORMAT_NONE},
{ATOMBIOS_GET_PANEL_EDID, rhdAtomLvdsGetTimings,
@@ -382,7 +382,7 @@ rhdAtomGetDataTable(int scrnIndex,
__func__);
}
- if (cmd_offset + sizeof (ATOM_MASTER_COMMAND_TABLE) > BIOSImageSize) {
+ if (*cmd_offset + sizeof (ATOM_MASTER_COMMAND_TABLE) > BIOSImageSize) {
xf86DrvMsg(scrnIndex,X_ERROR,"%s: Atom command table outside of BIOS\n",
__func__);
}
@@ -2278,7 +2278,7 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m
ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start;
ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr;
- unsigned short *ptr;
+ //unsigned short *ptr;
unsigned short offset;
table_start = &cmd_table->ListOfCommandTables;
commit 1cd7cc3e6758ab1012f3ced6e958a1517f45557f
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 18 17:44:36 2007 -0500
WIP: new atom code comples.
I commented out the object parsing for the time being as
using it will require some thought as to new output
related data structures.
diff --git a/src/Makefile.am b/src/Makefile.am
index 9bad63d..46e5ca1 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -32,10 +32,11 @@ R128_DRI_SRCS = r128_dri.c
RADEON_DRI_SRCS = radeon_dri.c
endif
-RADEON_ATOMBIOS_SOURCES = AtomBios/CD_Operations.c\
- AtomBios/Decoder.c\
- AtomBios/hwserv_drv.c \
- AtomBios/includes/atombios.h \
+RADEON_ATOMBIOS_SOURCES = \
+ AtomBios/CD_Operations.c \
+ AtomBios/Decoder.c \
+ AtomBios/hwserv_drv.c \
+ AtomBios/includes/atombios.h \
AtomBios/includes/CD_binding.h \
AtomBios/includes/CD_Common_Types.h \
AtomBios/includes/CD_Definitions.h \
@@ -43,6 +44,7 @@ RADEON_ATOMBIOS_SOURCES = AtomBios/CD_Operations.c\
AtomBios/includes/CD_Opcodes.h \
AtomBios/includes/CD_Structs.h \
AtomBios/includes/Decoder.h \
+ AtomBios/includes/ObjectID.h \
AtomBios/includes/regsdef.h
@@ -202,6 +204,7 @@ EXTRA_DIST = \
radeon_version.h \
radeon_video.h \
radeon_tv.h \
+ radeon_atomwrapper.h \
theatre200.h \
theatre_detect.h \
theatre.h \
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 9305592..d0c6a06 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -53,10 +53,10 @@
#endif
AtomBiosResult
-atombios_enable_crtc(atomBIOSHandlePtr atomBIOS, int crtc, int state)
+atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
{
ENABLE_CRTC_PS_ALLOCATION crtc_data;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
crtc_data.ucCRTC = crtc;
@@ -66,7 +66,7 @@ atombios_enable_crtc(atomBIOSHandlePtr atomBIOS, int crtc, int state)
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &crtc_data;
- if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("%s CRTC %d success\n", state? "Enable":"Disable", crtc);
return ATOM_SUCCESS ;
}
@@ -76,11 +76,11 @@ atombios_enable_crtc(atomBIOSHandlePtr atomBIOS, int crtc, int state)
}
AtomBiosResult
-atombios_blank_crtc(atomBIOSHandlePtr atomBIOS, int crtc, int state)
+atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
{
BLANK_CRTC_PS_ALLOCATION crtc_data;
unsigned char *space;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
memset(&crtc_data, 0, sizeof(crtc_data));
crtc_data.ucCRTC = crtc;
@@ -90,7 +90,7 @@ atombios_blank_crtc(atomBIOSHandlePtr atomBIOS, int crtc, int state)
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &crtc_data;
- if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("%s CRTC %d success\n", state? "Blank":"Unblank", crtc);
return ATOM_SUCCESS ;
}
@@ -130,16 +130,16 @@ atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
}
static AtomBiosResult
-atombios_set_crtc_timing(atomBIOSHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
+atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
{
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = crtc_param;
- if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Set CRTC Timing success\n");
return ATOM_SUCCESS ;
}
@@ -267,7 +267,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
int major, minor;
SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
void *ptr;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
RADEONSavePtr save = &info->ModeReg;
@@ -320,7 +320,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
data.exec.dataSpace = (void *)&space;
data.exec.pspace = ptr;
- if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Set CRTC PLL success\n");
return;
}
@@ -336,7 +336,7 @@ atombios_set_crtc_source(xf86CrtcPtr crtc)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
@@ -388,7 +388,7 @@ atombios_set_crtc_source(xf86CrtcPtr crtc)
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &crtc_src_param;
- if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Set CRTC Source success\n");
return;
}
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 2893455..d0f7339 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -43,10 +43,10 @@
#include "radeon_atombios.h"
static AtomBiosResult
-atom_bios_display_device_control(atomBIOSHandlePtr atomBIOS, int device, Bool state)
+atom_bios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state)
{
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
disp_data.ucAction = state;
@@ -54,7 +54,7 @@ atom_bios_display_device_control(atomBIOSHandlePtr atomBIOS, int device, Bool st
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
- if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Output %d enable success\n", device);
return ATOM_SUCCESS;
}
@@ -64,7 +64,7 @@ atom_bios_display_device_control(atomBIOSHandlePtr atomBIOS, int device, Bool st
}
static void
-atom_bios_enable_crt(atomBIOSHandlePtr atomBIOS, int dac, Bool state)
+atom_bios_enable_crt(atomBiosHandlePtr atomBIOS, int dac, Bool state)
{
int output;
if (dac == DAC_PRIMARY)
@@ -81,7 +81,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
disp_data.ucAction = 1;
@@ -94,7 +94,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
- if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Output DAC %d enable success\n", radeon_output->DACType);
return ATOM_SUCCESS;
}
@@ -115,7 +115,7 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
{
RADEONInfoPtr info = RADEONPTR(output->scrn);
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
disp_data.sXTmdsEncoder.ucEnable = 1;
@@ -132,7 +132,7 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
- if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("External TMDS enable success\n");
return ATOM_SUCCESS;
}
@@ -146,7 +146,7 @@ atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
{
RADEONInfoPtr info = RADEONPTR(output->scrn);
TMDS1_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
disp_data.ucAction = 1;
@@ -159,7 +159,7 @@ atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
- if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Output TMDS1 enable success\n");
return ATOM_SUCCESS;
}
@@ -180,7 +180,7 @@ atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode)
{
RADEONInfoPtr info = RADEONPTR(output->scrn);
TMDS2_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
disp_data.ucAction = 1;
@@ -193,7 +193,7 @@ atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode)
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
- if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Output TMDS2 enable success\n");
return ATOM_SUCCESS;
}
@@ -332,10 +332,10 @@ atombios_output_mode_set(xf86OutputPtr output,
}
static AtomBiosResult
-atom_bios_dac_load_detect(atomBIOSHandlePtr atomBIOS, int dac)
+atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, int dac)
{
DAC_LOAD_DETECTION_PS_ALLOCATION dac_data;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
unsigned char *space;
dac_data.sDacload.usDeviceID = 0;
@@ -346,7 +346,7 @@ atom_bios_dac_load_detect(atomBIOSHandlePtr atomBIOS, int dac)
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &dac_data;
- if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Dac detection success\n");
return ATOM_SUCCESS ;
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index d12f631..15612fb 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -28,10 +28,11 @@
#endif
#include "xf86.h"
#include "xf86_OSproc.h"
-//#include "xf86_ansic.h"
#include "radeon.h"
#include "radeon_atombios.h"
+#include "radeon_atomwrapper.h"
+#include "radeon_probe.h"
#include "radeon_macros.h"
#include "xorg-server.h"
@@ -178,11 +179,34 @@ enum {
legacyBIOSMax = 0x10000
};
+#define DEBUGP(x) {x;}
+#define LOG_DEBUG 7
+
# ifdef ATOM_BIOS_PARSER
# define LOG_CAIL LOG_DEBUG + 1
static void
+RHDDebug(int scrnIndex, const char *format, ...)
+{
+ va_list ap;
+
+ va_start(ap, format);
+ xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_DEBUG, format, ap);
+ va_end(ap);
+}
+
+static void
+RHDDebugCont(const char *format, ...)
+{
+ va_list ap;
+
+ va_start(ap, format);
+ xf86VDrvMsgVerb(-1, X_NONE, LOG_DEBUG, format, ap);
+ va_end(ap);
+}
+
+static void
CailDebug(int scrnIndex, const char *format, ...)
{
va_list ap;
@@ -207,8 +231,9 @@ rhdAtomAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr)
static int
rhdAtomAnalyzeRomHdr(unsigned char *rombase,
- ATOM_ROM_HEADER *hdr,
- unsigned int *data_offset)
+ ATOM_ROM_HEADER *hdr,
+ unsigned int *data_offset,
+ unsigned int *command_offset)
{
if (!rhdAtomAnalyzeCommonHdr(&hdr->sHeader)) {
return FALSE;
@@ -221,6 +246,7 @@ rhdAtomAnalyzeRomHdr(unsigned char *rombase,
rombase + hdr->usBIOS_BootupMessageOffset);
*data_offset = hdr->usMasterDataTableOffset;
+ *command_offset = hdr->usMasterCommandTableOffset;
return TRUE;
}
@@ -242,7 +268,7 @@ rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset,
return TRUE;
}
-static Bool
+Bool
rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr,
CARD8 *contentRev,
CARD8 *formatRev,
@@ -320,10 +346,13 @@ rhdAtomAnalyzeMasterDataTable(unsigned char *base,
}
static Bool
-rhdAtomGetDataTable(int scrnIndex, unsigned char *base,
- atomDataTables *atomDataPtr, unsigned int BIOSImageSize)
+rhdAtomGetDataTable(int scrnIndex,
+ unsigned char *base,
+ atomDataTables *atomDataPtr,
+ unsigned int *cmd_offset,
+ unsigned int BIOSImageSize)
{
- unsigned int data_offset;
+ unsigned int data_offset;
unsigned int atom_romhdr_off = *(unsigned short*)
(base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER);
ATOM_ROM_HEADER *atom_rom_hdr =
@@ -343,7 +372,7 @@ rhdAtomGetDataTable(int scrnIndex, unsigned char *base,
return FALSE;
}
xf86DrvMsg(scrnIndex, X_INFO, "ATOM BIOS Rom: \n");
- if (!rhdAtomAnalyzeRomHdr(base, atom_rom_hdr, &data_offset)) {
+ if (!rhdAtomAnalyzeRomHdr(base, atom_rom_hdr, &data_offset, cmd_offset)) {
xf86DrvMsg(scrnIndex, X_ERROR, "RomHeader invalid\n");
return FALSE;
}
@@ -353,6 +382,11 @@ rhdAtomGetDataTable(int scrnIndex, unsigned char *base,
__func__);
}
+ if (cmd_offset + sizeof (ATOM_MASTER_COMMAND_TABLE) > BIOSImageSize) {
+ xf86DrvMsg(scrnIndex,X_ERROR,"%s: Atom command table outside of BIOS\n",
+ __func__);
+ }
+
if (!rhdAtomAnalyzeMasterDataTable(base, (ATOM_MASTER_DATA_TABLE *)
(base + data_offset),
atomDataPtr)) {
@@ -509,6 +543,7 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2,
RADEONInfoPtr info = RADEONPTR(xf86Screens[scrnIndex]);
unsigned char *ptr;
atomDataTablesPtr atomDataPtr;
+ unsigned int cmd_offset;
atomBiosHandlePtr handle = NULL;
unsigned int BIOSImageSize = 0;
data->atomhandle = NULL;
@@ -562,7 +597,7 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2,
"ATOM BIOS data tabes\n");
goto error;
}
- if (!rhdAtomGetDataTable(scrnIndex, ptr, atomDataPtr,BIOSImageSize))
+ if (!rhdAtomGetDataTable(scrnIndex, ptr, atomDataPtr, &cmd_offset, BIOSImageSize))
goto error1;
if (!(handle = xcalloc(1, sizeof(atomBiosHandleRec)))) {
xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory\n");
@@ -570,6 +605,7 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2,
}
handle->BIOSBase = ptr;
handle->atomDataPtr = atomDataPtr;
+ handle->cmd_offset = cmd_offset;
handle->scrnIndex = scrnIndex;
#if XSERVER_LIBPCIACCESS
handle->device = info->PciInfo;
@@ -1234,6 +1270,10 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle,
return ATOM_SUCCESS;
}
+#if 0
+#define RHD_CONNECTORS_MAX 4
+#define MAX_OUTPUTS_PER_CONNECTOR 2
+
#define Limit(n,max,name) ((n >= max) ? ( \
xf86DrvMsg(handle->scrnIndex,X_ERROR,"%s: %s %i exceeds maximum %i\n", \
__func__,name,n,max), TRUE) : FALSE)
@@ -1241,116 +1281,118 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle,
static const struct _rhd_connector_objs
{
char *name;
- rhdConnectorType con;
+ RADEONConnectorTypeATOM con;
} rhd_connector_objs[] = {
- { "NONE", RHD_CONNECTOR_NONE },
- { "SINGLE_LINK_DVI_I", RHD_CONNECTOR_DVI },
- { "DUAL_LINK_DVI_I", RHD_CONNECTOR_DVI_DUAL },
- { "SINGLE_LINK_DVI_D", RHD_CONNECTOR_DVI },
- { "DUAL_LINK_DVI_D", RHD_CONNECTOR_DVI_DUAL },
- { "VGA", RHD_CONNECTOR_VGA },
- { "COMPOSITE", RHD_CONNECTOR_TV },
- { "SVIDEO", RHD_CONNECTOR_TV, },
- { "D_CONNECTOR", RHD_CONNECTOR_NONE, },
- { "9PIN_DIN", RHD_CONNECTOR_NONE },
- { "SCART", RHD_CONNECTOR_TV },
- { "HDMI_TYPE_A", RHD_CONNECTOR_NONE },
- { "HDMI_TYPE_B", RHD_CONNECTOR_NONE },
- { "HDMI_TYPE_B", RHD_CONNECTOR_NONE },
- { "LVDS", RHD_CONNECTOR_PANEL },
- { "7PIN_DIN", RHD_CONNECTOR_TV },
- { "PCIE_CONNECTOR", RHD_CONNECTOR_NONE },
- { "CROSSFIRE", RHD_CONNECTOR_NONE },
- { "HARDCODE_DVI", RHD_CONNECTOR_NONE },
- { "DISPLAYPORT", RHD_CONNECTOR_NONE}
+ { "NONE", CONNECTOR_NONE_ATOM },
+ { "SINGLE_LINK_DVI_I", CONNECTOR_DVI_I_ATOM },
+ { "DUAL_LINK_DVI_I", CONNECTOR_DVI_I_ATOM },
+ { "SINGLE_LINK_DVI_D", CONNECTOR_DVI_D_ATOM },
+ { "DUAL_LINK_DVI_D", CONNECTOR_DVI_D_ATOM },
+ { "VGA", CONNECTOR_VGA_ATOM },
+ { "COMPOSITE", CONNECTOR_CTV_ATOM },
+ { "SVIDEO", CONNECTOR_STV_ATOM },
+ { "D_CONNECTOR", CONNECTOR_NONE_ATOM },
+ { "9PIN_DIN", CONNECTOR_NONE_ATOM },
+ { "SCART", CONNECTOR_SCART_ATOM },
+ { "HDMI_TYPE_A", CONNECTOR_HDMI_TYPE_A_ATOM },
+ { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM },
+ { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM },
+ { "LVDS", CONNECTOR_LVDS_ATOM },
+ { "7PIN_DIN", CONNECTOR_STV_ATOM },
+ { "PCIE_CONNECTOR", CONNECTOR_NONE_ATOM },
+ { "CROSSFIRE", CONNECTOR_NONE_ATOM },
+ { "HARDCODE_DVI", CONNECTOR_NONE_ATOM },
+ { "DISPLAYPORT", CONNECTOR_DISPLAY_PORT_ATOM }
};
static const int n_rhd_connector_objs = sizeof (rhd_connector_objs) / sizeof(struct _rhd_connector_objs);
static const struct _rhd_encoders
{
char *name;
- rhdOutputType ot;
+ RADEONOutputTypeATOM ot;
} rhd_encoders[] = {
- { "NONE", RHD_OUTPUT_NONE },
- { "INTERNAL_LVDS", RHD_OUTPUT_LVDS },
- { "INTERNAL_TMDS1", RHD_OUTPUT_TMDSA },
- { "INTERNAL_TMDS2", RHD_OUTPUT_TMDSB },
- { "INTERNAL_DAC1", RHD_OUTPUT_DACA },
- { "INTERNAL_DAC2", RHD_OUTPUT_DACB },
- { "INTERNAL_SDVOA", RHD_OUTPUT_NONE },
- { "INTERNAL_SDVOB", RHD_OUTPUT_NONE },
- { "SI170B", RHD_OUTPUT_NONE },
- { "CH7303", RHD_OUTPUT_NONE },
- { "CH7301", RHD_OUTPUT_NONE },
- { "INTERNAL_DVO1", RHD_OUTPUT_NONE },
- { "EXTERNAL_SDVOA", RHD_OUTPUT_NONE },
- { "EXTERNAL_SDVOB", RHD_OUTPUT_NONE },
- { "TITFP513", RHD_OUTPUT_NONE },
- { "INTERNAL_LVTM1", RHD_OUTPUT_LVTMA },
- { "VT1623", RHD_OUTPUT_NONE },
- { "HDMI_SI1930", RHD_OUTPUT_NONE },
- { "HDMI_INTERNAL", RHD_OUTPUT_NONE },
- { "INTERNAL_KLDSCP_TMDS1", RHD_OUTPUT_TMDSA },
- { "INTERNAL_KLSCP_DVO1", RHD_OUTPUT_NONE },
- { "INTERNAL_KLDSCP_DAC1", RHD_OUTPUT_DACA },
- { "INTERNAL_KLDSCP_DAC2", RHD_OUTPUT_DACB },
- { "SI178", RHD_OUTPUT_NONE },
- { "MVPU_FPGA", RHD_OUTPUT_NONE },
- { "INTERNAL_DDI", RHD_OUTPUT_NONE },
- { "VT1625", RHD_OUTPUT_NONE },
- { "HDMI_SI1932", RHD_OUTPUT_NONE },
- { "AN9801", RHD_OUTPUT_NONE },
- { "DP501", RHD_OUTPUT_NONE },
+ { "NONE", OUTPUT_NONE_ATOM },
+ { "INTERNAL_LVDS", OUTPUT_LVDS_ATOM },
+ { "INTERNAL_TMDS1", OUTPUT_TMDSA_ATOM },
+ { "INTERNAL_TMDS2", OUTPUT_TMDSB_ATOM },
+ { "INTERNAL_DAC1", OUTPUT_DACA_ATOM },
+ { "INTERNAL_DAC2", OUTPUT_DACB_ATOM },
+ { "INTERNAL_SDVOA", OUTPUT_NONE_ATOM },
+ { "INTERNAL_SDVOB", OUTPUT_NONE_ATOM },
+ { "SI170B", OUTPUT_NONE_ATOM },
+ { "CH7303", OUTPUT_NONE_ATOM },
+ { "CH7301", OUTPUT_NONE_ATOM },
+ { "INTERNAL_DVO1", OUTPUT_NONE_ATOM },
+ { "EXTERNAL_SDVOA", OUTPUT_NONE_ATOM },
+ { "EXTERNAL_SDVOB", OUTPUT_NONE_ATOM },
+ { "TITFP513", OUTPUT_NONE_ATOM },
+ { "INTERNAL_LVTM1", OUTPUT_LVTMA_ATOM },
+ { "VT1623", OUTPUT_NONE_ATOM },
+ { "HDMI_SI1930", OUTPUT_NONE_ATOM },
+ { "HDMI_INTERNAL", OUTPUT_NONE_ATOM },
+ { "INTERNAL_KLDSCP_TMDS1", OUTPUT_TMDSA_ATOM },
+ { "INTERNAL_KLSCP_DVO1", OUTPUT_NONE_ATOM },
+ { "INTERNAL_KLDSCP_DAC1", OUTPUT_DACA_ATOM },
+ { "INTERNAL_KLDSCP_DAC2", OUTPUT_DACB_ATOM },
+ { "SI178", OUTPUT_NONE_ATOM },
+ { "MVPU_FPGA", OUTPUT_NONE_ATOM },
+ { "INTERNAL_DDI", OUTPUT_NONE_ATOM },
+ { "VT1625", OUTPUT_NONE_ATOM },
+ { "HDMI_SI1932", OUTPUT_NONE_ATOM },
+ { "AN9801", OUTPUT_NONE_ATOM },
+ { "DP501", OUTPUT_NONE_ATOM },
};
static const int n_rhd_encoders = sizeof (rhd_encoders) / sizeof(struct _rhd_encoders);
static const struct _rhd_connectors
{
char *name;
- rhdConnectorType con;
+ RADEONConnectorTypeATOM con;
Bool dual;
} rhd_connectors[] = {
- {"NONE", RHD_CONNECTOR_NONE, FALSE },
- {"VGA", RHD_CONNECTOR_VGA, FALSE },
- {"DVI-I", RHD_CONNECTOR_DVI, TRUE },
- {"DVI-D", RHD_CONNECTOR_DVI, FALSE },
- {"DVI-A", RHD_CONNECTOR_DVI, FALSE },
- {"SVIDEO", RHD_CONNECTOR_TV, FALSE },
- {"COMPOSITE", RHD_CONNECTOR_TV, FALSE },
- {"PANEL", RHD_CONNECTOR_PANEL, FALSE },
- {"DIGITAL_LINK", RHD_CONNECTOR_NONE, FALSE },
- {"SCART", RHD_CONNECTOR_TV, FALSE },
- {"HDMI Type A", RHD_CONNECTOR_NONE, FALSE },
- {"HDMI Type B", RHD_CONNECTOR_NONE, FALSE },
- {"UNKNOWN", RHD_CONNECTOR_NONE, FALSE },
- {"UNKNOWN", RHD_CONNECTOR_NONE, FALSE },
- {"DVI+DIN", RHD_CONNECTOR_NONE, FALSE }
+ {"NONE", CONNECTOR_NONE_ATOM, FALSE },
+ {"VGA", CONNECTOR_VGA_ATOM, FALSE },
+ {"DVI-I", CONNECTOR_DVI_I_ATOM, TRUE },
+ {"DVI-D", CONNECTOR_DVI_D_ATOM, FALSE },
+ {"DVI-A", CONNECTOR_DVI_A_ATOM, FALSE },
+ {"SVIDEO", CONNECTOR_STV_ATOM, FALSE },
+ {"COMPOSITE", CONNECTOR_CTV_ATOM, FALSE },
+ {"PANEL", CONNECTOR_LVDS_ATOM, FALSE },
+ {"DIGITAL_LINK", CONNECTOR_DIGITAL_ATOM, FALSE },
+ {"SCART", CONNECTOR_SCART_ATOM, FALSE },
+ {"HDMI Type A", CONNECTOR_HDMI_TYPE_A_ATOM, FALSE },
+ {"HDMI Type B", CONNECTOR_HDMI_TYPE_B_ATOM, FALSE },
+ {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE },
+ {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE },
+ {"DVI+DIN", CONNECTOR_NONE_ATOM, FALSE }
};
static const int n_rhd_connectors = sizeof(rhd_connectors) / sizeof(struct _rhd_connectors);
static const struct _rhd_devices
{
char *name;
- rhdOutputType ot;
+ RADEONOutputTypeATOM ot;
} rhd_devices[] = {
- {" CRT1", RHD_OUTPUT_NONE },
- {" LCD1", RHD_OUTPUT_LVTMA },
- {" TV1", RHD_OUTPUT_NONE },
- {" DFP1", RHD_OUTPUT_TMDSA },
- {" CRT2", RHD_OUTPUT_NONE },
- {" LCD2", RHD_OUTPUT_LVTMA },
- {" TV2", RHD_OUTPUT_NONE },
- {" DFP2", RHD_OUTPUT_LVTMA },
- {" CV", RHD_OUTPUT_NONE },
- {" DFP3", RHD_OUTPUT_LVTMA }
+ {" CRT1", OUTPUT_NONE_ATOM },
+ {" LCD1", OUTPUT_LVTMA_ATOM },
+ {" TV1", OUTPUT_NONE_ATOM },
+ {" DFP1", OUTPUT_TMDSA_ATOM },
+ {" CRT2", OUTPUT_NONE_ATOM },
+ {" LCD2", OUTPUT_LVTMA_ATOM },
+ {" TV2", OUTPUT_NONE_ATOM },
+ {" DFP2", OUTPUT_LVTMA_ATOM },
+ {" CV", OUTPUT_NONE_ATOM },
+ {" DFP3", OUTPUT_LVTMA_ATOM }
};
static const int n_rhd_devices = sizeof(rhd_devices) / sizeof(struct _rhd_devices);
static const rhdDDC hwddc[] = { RHD_DDC_0, RHD_DDC_1, RHD_DDC_2, RHD_DDC_3 };
static const int n_hwddc = sizeof(hwddc) / sizeof(rhdDDC);
-static const rhdOutputType acc_dac[] = { RHD_OUTPUT_NONE, RHD_OUTPUT_DACA,
- RHD_OUTPUT_DACB, RHD_OUTPUT_DAC_EXTERNAL };
+static const rhdOutputType acc_dac[] = { OUTPUT_NONE_ATOM,
+ OUTPUT_DACA_ATOM,
+ OUTPUT_DACB_ATOM,
+ OUTPUT_DAC_EXTERNAL_ATOM };
static const int n_acc_dac = sizeof(acc_dac) / sizeof (rhdOutputType);
/*
@@ -1743,7 +1785,7 @@ rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle,
ATOM_CONNECTOR_INFO_I2C ci
= atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[n];
- devices[n].ot = RHD_OUTPUT_NONE;
+ devices[n].ot = OUTPUT_NONE_ATOM;
if (!(atomDataPtr->SupportedDevicesInfo
.SupportedDevicesInfo->usDeviceSupport & (1 << n)))
@@ -1774,11 +1816,11 @@ rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle,
n_acc_dac, "bfAssociatedDAC")) {
if ((devices[n].ot
= acc_dac[ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC])
- == RHD_OUTPUT_NONE) {
+ == OUTPUT_NONE_ATOM) {
devices[n].ot = rhd_devices[n].ot;
}
} else
- devices[n].ot = RHD_OUTPUT_NONE;
+ devices[n].ot = OUTPUT_NONE_ATOM;
RHDDebugCont("Output: %x ",devices[n].ot);
@@ -1834,15 +1876,15 @@ rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle,
for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) {
int i;
- if (devices[n].ot == RHD_OUTPUT_NONE)
+ if (devices[n].ot == OUTPUT_NONE_ATOM)
continue;
- if (devices[n].con == RHD_CONNECTOR_NONE)
+ if (devices[n].con == CONNECTOR_NONE_ATOM)
continue;
cp[ncon].DDC = devices[n].ddc;
cp[ncon].HPD = devices[n].hpd;
cp[ncon].Output[0] = devices[n].ot;
- cp[ncon].Output[1] = RHD_OUTPUT_NONE;
+ cp[ncon].Output[1] = OUTPUT_NONE_ATOM;
cp[ncon].Type = devices[n].con;
cp[ncon].Name = xf86strdup(devices[n].name);
cp[ncon].Name = RhdAppendString(cp[ncon].Name, devices[n].outputName);
@@ -1861,14 +1903,14 @@ rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle,
if (devices[n].ddc != devices[i].ddc)
continue;
- if (((devices[n].ot == RHD_OUTPUT_DACA
- || devices[n].ot == RHD_OUTPUT_DACB)
- && (devices[i].ot == RHD_OUTPUT_LVTMA
- || devices[i].ot == RHD_OUTPUT_TMDSA))
- || ((devices[i].ot == RHD_OUTPUT_DACA
- || devices[i].ot == RHD_OUTPUT_DACB)
- && (devices[n].ot == RHD_OUTPUT_LVTMA
- || devices[n].ot == RHD_OUTPUT_TMDSA))) {
+ if (((devices[n].ot == OUTPUT_DACA_ATOM
+ || devices[n].ot == OUTPUT_DACB_ATOM)
+ && (devices[i].ot == OUTPUT_LVTMA_ATOM
+ || devices[i].ot == OUTPUT_TMDSA_ATOM))
+ || ((devices[i].ot == OUTPUT_DACA_ATOM
+ || devices[i].ot == OUTPUT_DACB_ATOM)
+ && (devices[n].ot == OUTPUT_LVTMA_ATOM
+ || devices[n].ot == OUTPUT_TMDSA_ATOM))) {
cp[ncon].Output[1] = devices[i].ot;
@@ -1877,7 +1919,7 @@ rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle,
cp[ncon].Name = RhdAppendString(cp[ncon].Name,
devices[i].outputName);
- devices[i].ot = RHD_OUTPUT_NONE; /* zero the device */
+ devices[i].ot = OUTPUT_NONE_ATOM; /* zero the device */
}
}
}
@@ -1909,6 +1951,7 @@ rhdAtomConnectorInfo(atomBiosHandlePtr handle,
return rhdAtomConnectorInfoFromSupportedDevices(handle,
&data->connectorInfo);
}
+#endif
# ifdef ATOM_BIOS_PARSER
static AtomBiosResult
@@ -2047,6 +2090,9 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay)
UINT32
CailReadATIRegister(VOID* CAIL, UINT32 idx)
{
+ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
UINT32 ret;
CAILFUNC(CAIL);
@@ -2094,8 +2140,6 @@ CailReadFBData(VOID* CAIL, UINT32 idx)
VOID
CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data)
{
- ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
CAILFUNC(CAIL);
DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data));
@@ -2221,14 +2265,31 @@ VOID
CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data)
{
ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
CAILFUNC(CAIL);
DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data));
RADEONOUTPLL(pScrn, Address, Data);
}
-# endif
+void
+atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor)
+{
+ ATOM_MASTER_COMMAND_TABLE *cmd_table = atomBIOS->BIOSBase + atomBIOS->cmd_offset;
+ ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start;
+ ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr;
+
+ unsigned short *ptr;
+ unsigned short offset;
+
+ table_start = &cmd_table->ListOfCommandTables;
+
+ offset = *(((unsigned short *)table_start) + index);
+
+ table_hdr = atomBIOS->BIOSBase + offset;
+
+ *major = table_hdr->CommonHeader.ucTableFormatRevision;
+ *minor = table_hdr->CommonHeader.ucTableContentRevision;
+}
+
#endif /* ATOM_BIOS */
diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h
index 5e8cc24..33925a5 100644
--- a/src/radeon_atombios.h
+++ b/src/radeon_atombios.h
@@ -134,6 +134,7 @@ typedef unsigned short USHORT;
# include "atombios.h"
# include "ObjectID.h"
+
/*
* This works around a bug in atombios.h where
* ATOM_MAX_SUPPORTED_DEVICE_INFO is specified incorrectly.
@@ -218,6 +219,7 @@ typedef struct _atomBiosHandle {
int scrnIndex;
unsigned char *BIOSBase;
atomDataTablesPtr atomDataPtr;
+ unsigned int cmd_offset;
pointer *scratchBase;
CARD32 fbBase;
#if XSERVER_LIBPCIACCESS
diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c
index cdcb532..259366c 100644
--- a/src/radeon_atomwrapper.c
+++ b/src/radeon_atomwrapper.c
@@ -23,7 +23,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "radeon_atomwrapper.h"
+#ifdef HAVE_CONFIG_H
+# include "config.h"
+#endif
+
+//#include "radeon_atomwrapper.h"
#define INT32 INT32
#include "CD_Common_Types.h"
@@ -36,7 +40,7 @@ ParseTableWrapper(void *pspace, int index, void *handle, void *BIOSBase,
{
DEVICE_DATA deviceData;
int ret = 0;
-
+
/* FILL OUT PARAMETER SPACE */
deviceData.pParameterSpace = (UINT32*) pspace;
deviceData.CAIL = handle;
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 6bf0dce..5f098a7 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -106,6 +106,18 @@ typedef enum
CONNECTOR_UNSUPPORTED_ATOM
} RADEONConnectorTypeATOM;
+typedef enum {
+ OUTPUT_NONE_ATOM,
+ OUTPUT_DAC_EXTERNAL_ATOM,
+ OUTPUT_DACA_ATOM,
+ OUTPUT_DACB_ATOM,
+ OUTPUT_TMDSA_ATOM,
+ OUTPUT_LVTMA_ATOM,
+ OUTPUT_TMDSB_ATOM,
+ OUTPUT_LVDS_ATOM,
+ OUTPUT_LVTMB_ATOM
+} RADEONOutputTypeATOM;
+
typedef enum
{
DAC_UNKNOWN = -1,
commit b155fa872ee4ca5d801e942aee6e619cef104f35
Author: Alex Deucher <alex at botch2.(none)>
Date: Sat Nov 17 00:34:56 2007 -0500
WIP: more new ATOM integration work
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index a16c1f2..d12f631 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -28,11 +28,8 @@
#endif
#include "xf86.h"
#include "xf86_OSproc.h"
-#include "xf86_ansic.h"
-#include "xf86Pci.h"
+//#include "xf86_ansic.h"
-#include "xf86.h"
-#include "xf86_OSproc.h"
#include "radeon.h"
#include "radeon_atombios.h"
#include "radeon_macros.h"
@@ -710,8 +707,8 @@ rhdAtomLvdsTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd)
mode->VRefresh = (1000.0 * ((float) mode->Clock))
/ ((float)(((float)mode->HTotal) * ((float)mode->VTotal)));
- xf86snprintf(name, NAME_LEN, "%dx%d",
- mode->HDisplay, mode->VDisplay);
+ snprintf(name, NAME_LEN, "%dx%d",
+ mode->HDisplay, mode->VDisplay);
mode->name = xstrdup(name);
RHDDebug(handle->scrnIndex,"%s: LVDS Modeline: %s "
@@ -2061,7 +2058,7 @@ CailReadATIRegister(VOID* CAIL, UINT32 idx)
VOID
CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data)
{
- ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
CAILFUNC(CAIL);
@@ -2073,7 +2070,7 @@ CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data)
UINT32
CailReadFBData(VOID* CAIL, UINT32 idx)
{
- ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
UINT32 ret;
@@ -2081,7 +2078,7 @@ CailReadFBData(VOID* CAIL, UINT32 idx)
if (((atomBiosHandlePtr)CAIL)->fbBase) {
CARD8 *FBBase = (CARD8*)info->FB;
- ret = *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + idx));
+ ret = *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx));
DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));
} else if (((atomBiosHandlePtr)CAIL)->scratchBase) {
ret = *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx);
@@ -2097,15 +2094,15 @@ CailReadFBData(VOID* CAIL, UINT32 idx)
VOID
CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data)
{
- ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
CAILFUNC(CAIL);
DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data));
if (((atomBiosHandlePtr)CAIL)->fbBase) {
CARD8 *FBBase = (CARD8*)
- RADEONPTR(xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex])->FB;
- *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + idx)) = data;
+ RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->FB;
+ *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data;
} else if (((atomBiosHandlePtr)CAIL)->scratchBase) {
*(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data;
} else
@@ -2116,7 +2113,7 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data)
ULONG
CailReadMC(VOID *CAIL, ULONG Address)
{
- ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
ULONG ret;
CAILFUNC(CAIL);
@@ -2129,7 +2126,7 @@ CailReadMC(VOID *CAIL, ULONG Address)
VOID
CailWriteMC(VOID *CAIL, ULONG Address, ULONG data)
{
- ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
CAILFUNC(CAIL);
DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data));
@@ -2141,14 +2138,14 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data)
VOID
CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size)
{
- pci_device_cfg_read(RADEONPTR(xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex])->PciInfo,
+ pci_device_cfg_read(RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->PciInfo,
ret,idx << 2 , size >> 3, NULL);
}
VOID
CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size)
{
- pci_device_cfg_write(RADEONPTR(xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex])->PciInfo,
+ pci_device_cfg_write(RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->PciInfo,
src, idx << 2, size >> 3, NULL);
}
@@ -2210,7 +2207,7 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size)
ULONG
CailReadPLL(VOID *CAIL, ULONG Address)
{
- ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
ULONG ret;
CAILFUNC(CAIL);
@@ -2223,7 +2220,7 @@ CailReadPLL(VOID *CAIL, ULONG Address)
VOID
CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data)
{
- ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
CAILFUNC(CAIL);
diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h
index 3cfa673..5e8cc24 100644
--- a/src/radeon_atombios.h
+++ b/src/radeon_atombios.h
@@ -27,7 +27,7 @@
#ifndef RHD_ATOMBIOS_H_
# define RHD_ATOMBIOS_H_
-#include "radeon.h"
+//#include "radeon.h"
# ifdef ATOM_BIOS
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 061dc15..0e14d94 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -139,9 +139,10 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
#if 1
AtomBiosArgRec atomBiosArg;
- if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) == ATOM_SUCCESS) {
- info->atomBIOS = atomBiosArg.ptr;
- }
+ if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg)
+ == ATOM_SUCCESS) {
+ info->atomBIOS = atomBiosArg.atomhandle;
+ }
atomBiosArg.fb.start = info->FbFreeStart;
atomBiosArg.fb.size = info->FbFreeSize;
@@ -151,6 +152,24 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->FbFreeStart = atomBiosArg.fb.start;
info->FbFreeSize = atomBiosArg.fb.size;
}
+
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK,
+ &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK,
+ &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_MAX_PIXEL_CLK, &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_REF_CLOCK, &atomBiosArg);
+
#endif
info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32);
}
commit 67db114d97abed7a607467e5d67c7b4ffa2c347e
Merge: 7d06a87... ea15346...
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 16 14:29:53 2007 -0500
Merge branch 'agd-atom' of /home/alex/git/airlied/xf86-video-ati2 into agd-atom
commit ea1534659de87d3d75eb20d808d039cff22cb537
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Nov 16 18:46:02 2007 +1000
avivo: fixup some i2c stuff
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 815bab5..e61b978 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2326,27 +2326,8 @@ Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio_reg)
temp &= ~((1 << 0) | (1 << 8));
}
OUTREG(gpio_reg + 4, temp);
+ temp = INREG(gpio_reg + 4);
- switch(lock_state) {
- case 0:
- temp = INREG(AVIVO_I2C_CNTL);
- OUTREG(AVIVO_I2C_CNTL, temp | 0x100);
- /* enable hdcp block */
- OUTREG(R520_PCLK_HDCP_CNTL, 0x0);
- break;
- case 1:
- /* disable hdcp block */
- OUTREG(R520_PCLK_HDCP_CNTL, 0x1);
- usleep(1);
- OUTREG(AVIVO_I2C_CNTL, 0x1);
- usleep(1);
- temp = INREG(AVIVO_I2C_CNTL);
- if (!(temp & 0x2)) {
- ErrorF("Lock failed %08X\n", temp);
- return FALSE;
- }
- break;
- }
return TRUE;
}
@@ -2360,14 +2341,11 @@ avivo_i2c_gpio_get_bits(I2CBusPtr b, int *Clock, int *data)
/* Get the result */
if (b->DriverPrivate.uval == AVIVO_GPIO_0) {
- val = INREG(b->DriverPrivate.uval + 0xC);
+ val = INREG(b->DriverPrivate.uval + 0xc);
*Clock = (val & (1<<19)) != 0;
*data = (val & (1<<18)) != 0;
} else {
- if (INREG(b->DriverPrivate.uval) == 0)
- OUTREG(b->DriverPrivate.uval, (1<<0) | (1<<8));
-
- val = INREG(b->DriverPrivate.uval + 0xC);
+ val = INREG(b->DriverPrivate.uval + 0xc);
*Clock = (val & (1<<0)) != 0;
*data = (val & (1<<8)) != 0;
}
@@ -2390,6 +2368,7 @@ avivo_i2c_gpio_put_bits(I2CBusPtr b, int Clock, int data)
val |= (data ? 0:(1<<8));
}
+
OUTREG(b->DriverPrivate.uval + 0x8, val);
/* read back to improve reliability on some cards. */
val = INREG(b->DriverPrivate.uval + 0x8);
commit 7d06a8791839ce6b22e2449646832b79cebf1b21
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 16 02:43:00 2007 -0500
WIP: sync up with the latest ATOM bios code in rhd
doesn't compile ATM
diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h
index 7a0f27f..44a0b35 100644
--- a/src/AtomBios/includes/CD_Common_Types.h
+++ b/src/AtomBios/includes/CD_Common_Types.h
@@ -47,7 +47,7 @@ Revision History:
// typedef __int64 int64_t;
typedef unsigned __int32 uint32_t;
typedef __int32 int32_t;
-#elif defined (linux) || defined (__NetBSD__)
+#elif defined (__linux__) || defined (__NetBSD__) || defined(__sun) || defined(__OpenBSD__) || defined (__FreeBSD__)
typedef unsigned int uint32_t;
typedef int int32_t;
#else
@@ -55,7 +55,11 @@ Revision History:
typedef signed long int32_t;
#endif
typedef unsigned char uint8_t;
+#if (defined(__sun) && defined(_CHAR_IS_SIGNED))
+ typedef char int8_t;
+#else
typedef signed char int8_t;
+#endif
typedef unsigned short uint16_t;
typedef signed short int16_t;
#endif
diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h
new file mode 100644
index 0000000..a630c69
--- /dev/null
+++ b/src/AtomBios/includes/ObjectID.h
@@ -0,0 +1,448 @@
+/*
+* Copyright 2006-2007 Advanced Micro Devices, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*/
+/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */
+
+#ifndef _OBJECTID_H
+#define _OBJECTID_H
+
+#if defined(_X86_)
+#pragma pack(1)
+#endif
+
+/****************************************************/
+/* Graphics Object Type Definition */
+/****************************************************/
+#define GRAPH_OBJECT_TYPE_NONE 0x0
+#define GRAPH_OBJECT_TYPE_GPU 0x1
+#define GRAPH_OBJECT_TYPE_ENCODER 0x2
+#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
+#define GRAPH_OBJECT_TYPE_ROUTER 0x4
+/* deleted */
+
+/****************************************************/
+/* Encoder Object ID Definition */
+/****************************************************/
+#define ENCODER_OBJECT_ID_NONE 0x00
+
+/* Radeon Class Display Hardware */
+#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
+#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02
+#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03
+#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04
+#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */
+#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06
+#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07
+
+/* External Third Party Encoders */
+#define ENCODER_OBJECT_ID_SI170B 0x08
+#define ENCODER_OBJECT_ID_CH7303 0x09
+#define ENCODER_OBJECT_ID_CH7301 0x0A
+#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */
+#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C
+#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D
+#define ENCODER_OBJECT_ID_TITFP513 0x0E
+#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */
+#define ENCODER_OBJECT_ID_VT1623 0x10
+#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11
+#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12
+/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */
+#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */
+#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */
+#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19
+#define ENCODER_OBJECT_ID_VT1625 0x1A
+#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B
+#define ENCODER_OBJECT_ID_DP_AN9801 0x1C
+#define ENCODER_OBJECT_ID_DP_DP501 0x1D
+
+/****************************************************/
+/* Connector Object ID Definition */
+/****************************************************/
+#define CONNECTOR_OBJECT_ID_NONE 0x00
+#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
+#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
+#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
+#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04
+#define CONNECTOR_OBJECT_ID_VGA 0x05
+#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06
+#define CONNECTOR_OBJECT_ID_SVIDEO 0x07
+#define CONNECTOR_OBJECT_ID_YPbPr 0x08
+#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09
+#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */
+#define CONNECTOR_OBJECT_ID_SCART 0x0B
+#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C
+#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D
+#define CONNECTOR_OBJECT_ID_LVDS 0x0E
+#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F
+#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10
+#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11
+#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12
+#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13
+
+/* deleted */
+
+/****************************************************/
+/* Router Object ID Definition */
+/****************************************************/
+#define ROUTER_OBJECT_ID_NONE 0x00
+#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01
+
+/****************************************************/
+// Graphics Object ENUM ID Definition */
+/****************************************************/
+#define GRAPH_OBJECT_ENUM_ID1 0x01
+#define GRAPH_OBJECT_ENUM_ID2 0x02
+#define GRAPH_OBJECT_ENUM_ID3 0x03
+#define GRAPH_OBJECT_ENUM_ID4 0x04
+
+/****************************************************/
+/* Graphics Object ID Bit definition */
+/****************************************************/
+#define OBJECT_ID_MASK 0x00FF
+#define ENUM_ID_MASK 0x0700
+#define RESERVED1_ID_MASK 0x0800
+#define OBJECT_TYPE_MASK 0x7000
+#define RESERVED2_ID_MASK 0x8000
+
+#define OBJECT_ID_SHIFT 0x00
+#define ENUM_ID_SHIFT 0x08
+#define OBJECT_TYPE_SHIFT 0x0C
+
+
+/****************************************************/
+/* Graphics Object family definition */
+/****************************************************/
+#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
+ GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT)
+/****************************************************/
+/* GPU Object ID definition - Shared with BIOS */
+/****************************************************/
+#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
+
+/****************************************************/
+/* Encoder Object ID definition - Shared with BIOS */
+/****************************************************/
+/*
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
+#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
+#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
+#define ENCODER_SIL170B_ENUM_ID1 0x2108
+#define ENCODER_CH7303_ENUM_ID1 0x2109
+#define ENCODER_CH7301_ENUM_ID1 0x210A
+#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C
+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D
+#define ENCODER_TITFP513_ENUM_ID1 0x210E
+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F
+#define ENCODER_VT1623_ENUM_ID1 0x2110
+#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111
+#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
+#define ENCODER_SI178_ENUM_ID1 0x2117
+#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
+#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
+#define ENCODER_VT1625_ENUM_ID1 0x211A
+*/
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT
+
+#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
+
+#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
+
+#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
+/****************************************************/
+/* Connector Object ID definition - Shared with BIOS */
+/****************************************************/
+/*
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104
+#define CONNECTOR_VGA_ENUM_ID1 0x3105
+#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106
+#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107
+#define CONNECTOR_YPbPr_ENUM_ID1 0x3108
+#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109
+#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A
+#define CONNECTOR_SCART_ENUM_ID1 0x310B
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D
+#define CONNECTOR_LVDS_ENUM_ID1 0x310E
+#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110
+*/
+#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+/****************************************************/
+/* Router Object ID definition - Shared with BIOS */
+/****************************************************/
+#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
+
+/* deleted */
+
+/****************************************************/
+/* Object Cap definition - Shared with BIOS */
+/****************************************************/
+#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L
+#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L
+
+
+#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01
+#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02
+#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03
+
+#if defined(_X86_)
+#pragma pack()
+#endif
+
+#endif /*GRAPHICTYPE */
+
+
+
+
diff --git a/src/radeon.h b/src/radeon.h
index 7c32693..fc3509a 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -543,7 +543,7 @@ typedef enum {
CARD_PCIE
} RADEONCardType;
-typedef struct _atomBIOSHandle *atomBIOSHandlePtr;
+typedef struct _atomBiosHandle *atomBiosHandlePtr;
typedef struct {
EntityInfoPtr pEnt;
@@ -919,8 +919,9 @@ typedef struct {
RADEONMacModel MacModel;
#endif
- atomBIOSHandlePtr atomBIOS;
+ atomBiosHandlePtr atomBIOS;
unsigned long FbFreeStart, FbFreeSize;
+ unsigned char* BIOSCopy;
int cursor_width;
int cursor_height;
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 009df2f..a16c1f2 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -28,6 +28,11 @@
#endif
#include "xf86.h"
#include "xf86_OSproc.h"
+#include "xf86_ansic.h"
+#include "xf86Pci.h"
+
+#include "xf86.h"
+#include "xf86_OSproc.h"
#include "radeon.h"
#include "radeon_atombios.h"
#include "radeon_macros.h"
@@ -37,38 +42,149 @@
#warning pciaccess defined
#endif
-char *AtomBIOSQueryStr[] = {
- "Default Engine Clock",
- "Default Memory Clock",
- "Maximum Pixel ClockPLL Frequency Output",
- "Minimum Pixel ClockPLL Frequency Output",
- "Maximum Pixel ClockPLL Frequency Input",
- "Minimum Pixel ClockPLL Frequency Input",
- "Minimum Pixel Clock",
- "Reference Clock",
- "Start of VRAM area used by Firmware",
- "Framebuffer space used by Firmware (kb)",
- "TDMS Frequency",
- "PLL ChargePump",
- "PLL DutyCycle",
- "PLL VCO Gain",
- "PLL VoltageSwing"
+/* only for testing now */
+#include "xf86DDC.h"
+
+typedef AtomBiosResult (*AtomBiosRequestFunc)(atomBiosHandlePtr handle,
+ AtomBiosRequestID unused, AtomBiosArgPtr data);
+typedef struct rhdConnectorInfo *rhdConnectorInfoPtr;
+
+static AtomBiosResult rhdAtomInit(atomBiosHandlePtr unused1,
+ AtomBiosRequestID unused2, AtomBiosArgPtr data);
+static AtomBiosResult rhdAtomTearDown(atomBiosHandlePtr handle,
+ AtomBiosRequestID unused1, AtomBiosArgPtr unused2);
+static AtomBiosResult rhdAtomVramInfoQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data);
+static AtomBiosResult rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data);
+static AtomBiosResult rhdAtomAllocateFbScratch(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data);
+static AtomBiosResult rhdAtomLvdsGetTimings(atomBiosHandlePtr handle,
+ AtomBiosRequestID unused, AtomBiosArgPtr data);
+static AtomBiosResult rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data);
+static AtomBiosResult rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data);
+static AtomBiosResult rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data);
+static AtomBiosResult rhdAtomConnectorInfo(atomBiosHandlePtr handle,
+ AtomBiosRequestID unused, AtomBiosArgPtr data);
+# ifdef ATOM_BIOS_PARSER
+static AtomBiosResult rhdAtomExec(atomBiosHandlePtr handle,
+ AtomBiosRequestID unused, AtomBiosArgPtr data);
+# endif
+static AtomBiosResult
+rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data);
+
+
+enum msgDataFormat {
+ MSG_FORMAT_NONE,
+ MSG_FORMAT_HEX,
+ MSG_FORMAT_DEC
};
-char *AtomBIOSFuncStr[] = {
- "AtomBIOS Init",
- "AtomBIOS Teardown",
- "AtomBIOS Exec",
- "AtomBIOS Set FB Space"
+struct atomBIOSRequests {
+ AtomBiosRequestID id;
+ AtomBiosRequestFunc request;
+ char *message;
+ enum msgDataFormat message_format;
+} AtomBiosRequestList [] = {
+ {ATOMBIOS_INIT, rhdAtomInit,
+ "AtomBIOS Init", MSG_FORMAT_NONE},
+ {ATOMBIOS_TEARDOWN, rhdAtomTearDown,
+ "AtomBIOS Teardown", MSG_FORMAT_NONE},
+# ifdef ATOM_BIOS_PARSER
+ {ATOMBIOS_EXEC, rhdAtomExec,
+ "AtomBIOS Exec", MSG_FORMAT_NONE},
+#endif
+ {ATOMBIOS_ALLOCATE_FB_SCRATCH, rhdAtomAllocateFbScratch,
+ "AtomBIOS Set FB Space", MSG_FORMAT_NONE},
+ {ATOMBIOS_GET_CONNECTORS, rhdAtomConnectorInfo,
+ "AtomBIOS Get Connectors", MSG_FORMAT_NONE},
+ {ATOMBIOS_GET_PANEL_MODE, rhdAtomLvdsGetTimings,
+ "AtomBIOS Get Panel Mode", MSG_FORMAT_NONE},
+ {ATOMBIOS_GET_PANEL_EDID, rhdAtomLvdsGetTimings,
+ "AtomBIOS Get Panel EDID", MSG_FORMAT_NONE},
+ {GET_DEFAULT_ENGINE_CLOCK, rhdAtomFirmwareInfoQuery,
+ "Default Engine Clock", MSG_FORMAT_DEC},
+ {GET_DEFAULT_MEMORY_CLOCK, rhdAtomFirmwareInfoQuery,
+ "Default Memory Clock", MSG_FORMAT_DEC},
+ {GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, rhdAtomFirmwareInfoQuery,
+ "Maximum Pixel ClockPLL Frequency Output", MSG_FORMAT_DEC},
+ {GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, rhdAtomFirmwareInfoQuery,
+ "Minimum Pixel ClockPLL Frequency Output", MSG_FORMAT_DEC},
+ {GET_MAX_PIXEL_CLOCK_PLL_INPUT, rhdAtomFirmwareInfoQuery,
+ "Maximum Pixel ClockPLL Frequency Input", MSG_FORMAT_DEC},
+ {GET_MIN_PIXEL_CLOCK_PLL_INPUT, rhdAtomFirmwareInfoQuery,
+ "Minimum Pixel ClockPLL Frequency Input", MSG_FORMAT_DEC},
+ {GET_MAX_PIXEL_CLK, rhdAtomFirmwareInfoQuery,
+ "Maximum Pixel Clock", MSG_FORMAT_DEC},
+ {GET_REF_CLOCK, rhdAtomFirmwareInfoQuery,
+ "Reference Clock", MSG_FORMAT_DEC},
+ {GET_FW_FB_START, rhdAtomVramInfoQuery,
+ "Start of VRAM area used by Firmware", MSG_FORMAT_HEX},
+ {GET_FW_FB_SIZE, rhdAtomVramInfoQuery,
+ "Framebuffer space used by Firmware (kb)", MSG_FORMAT_DEC},
+ {ATOM_TMDS_FREQUENCY, rhdAtomTmdsInfoQuery,
+ "TMDS Frequency", MSG_FORMAT_DEC},
+ {ATOM_TMDS_PLL_CHARGE_PUMP, rhdAtomTmdsInfoQuery,
+ "TMDS PLL ChargePump", MSG_FORMAT_DEC},
+ {ATOM_TMDS_PLL_DUTY_CYCLE, rhdAtomTmdsInfoQuery,
+ "TMDS PLL DutyCycle", MSG_FORMAT_DEC},
+ {ATOM_TMDS_PLL_VCO_GAIN, rhdAtomTmdsInfoQuery,
+ "TMDS PLL VCO Gain", MSG_FORMAT_DEC},
+ {ATOM_TMDS_PLL_VOLTAGE_SWING, rhdAtomTmdsInfoQuery,
+ "TMDS PLL VoltageSwing", MSG_FORMAT_DEC},
+ {ATOM_LVDS_SUPPORTED_REFRESH_RATE, rhdAtomLvdsInfoQuery,
+ "LVDS Supported Refresh Rate", MSG_FORMAT_DEC},
+ {ATOM_LVDS_OFF_DELAY, rhdAtomLvdsInfoQuery,
+ "LVDS Off Delay", MSG_FORMAT_DEC},
+ {ATOM_LVDS_SEQ_DIG_ONTO_DE, rhdAtomLvdsInfoQuery,
+ "LVDS SEQ Dig onto DE", MSG_FORMAT_DEC},
+ {ATOM_LVDS_SEQ_DE_TO_BL, rhdAtomLvdsInfoQuery,
+ "LVDS SEQ DE to BL", MSG_FORMAT_DEC},
+ {ATOM_LVDS_DITHER, rhdAtomLvdsInfoQuery,
+ "LVDS Ditherc", MSG_FORMAT_HEX},
+ {ATOM_LVDS_DUALLINK, rhdAtomLvdsInfoQuery,
+ "LVDS Duallink", MSG_FORMAT_HEX},
+ {ATOM_LVDS_GREYLVL, rhdAtomLvdsInfoQuery,
+ "LVDS Grey Level", MSG_FORMAT_HEX},
+ {ATOM_LVDS_FPDI, rhdAtomLvdsInfoQuery,
+ "LVDS FPDI", MSG_FORMAT_HEX},
+ {ATOM_LVDS_24BIT, rhdAtomLvdsInfoQuery,
+ "LVDS 24Bit", MSG_FORMAT_HEX},
+ {ATOM_GPIO_I2C_CLK_MASK, rhdAtomGPIOI2CInfoQuery,
+ "GPIO_I2C_Clk_Mask", MSG_FORMAT_HEX},
+ {ATOM_DAC1_BG_ADJ, rhdAtomCompassionateDataQuery,
+ "DAC1 BG Adjustment", MSG_FORMAT_HEX},
+ {ATOM_DAC1_DAC_ADJ, rhdAtomCompassionateDataQuery,
+ "DAC1 DAC Adjustment", MSG_FORMAT_HEX},
+ {ATOM_DAC1_FORCE, rhdAtomCompassionateDataQuery,
+ "DAC1 Force Data", MSG_FORMAT_HEX},
+ {ATOM_DAC2_CRTC2_BG_ADJ, rhdAtomCompassionateDataQuery,
+ "DAC2_CRTC2 BG Adjustment", MSG_FORMAT_HEX},
+ {ATOM_DAC2_CRTC2_DAC_ADJ, rhdAtomCompassionateDataQuery,
+ "DAC2_CRTC2 DAC Adjustment", MSG_FORMAT_HEX},
+ {ATOM_DAC2_CRTC2_FORCE, rhdAtomCompassionateDataQuery,
+ "DAC2_CRTC2 Force", MSG_FORMAT_HEX},
+ {ATOM_DAC2_CRTC2_MUX_REG_IND,rhdAtomCompassionateDataQuery,
+ "DAC2_CRTC2 Mux Register Index", MSG_FORMAT_HEX},
+ {ATOM_DAC2_CRTC2_MUX_REG_INFO,rhdAtomCompassionateDataQuery,
+ "DAC2_CRTC2 Mux Register Info", MSG_FORMAT_HEX},
+ {FUNC_END, NULL,
+ NULL, MSG_FORMAT_NONE}
};
-#define DEBUGP(x) {x;}
-#define LOG_DEBUG 7
+enum {
+ legacyBIOSLocation = 0xC0000,
+ legacyBIOSMax = 0x10000
+};
-#ifdef ATOM_BIOS
-# define LOG_CAIL LOG_DEBUG + 1
+# ifdef ATOM_BIOS_PARSER
+
+# define LOG_CAIL LOG_DEBUG + 1
-#ifdef ATOM_BIOS_PARSER
static void
CailDebug(int scrnIndex, const char *format, ...)
{
@@ -78,19 +194,13 @@ CailDebug(int scrnIndex, const char *format, ...)
xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_CAIL, format, ap);
va_end(ap);
}
-#endif
+# define CAILFUNC(ptr) \
+ CailDebug(((atomBiosHandlePtr)(ptr))->scrnIndex, "CAIL: %s\n", __func__)
-# define CAILFUNC(ptr) \
- CailDebug(((atomBIOSHandlePtr)(ptr))->scrnIndex, "CAIL: %s\n", __func__)
-
-
-enum {
- legacyBIOSLocation = 0xC0000,
- legacyBIOSMax = 0x10000
-};
+# endif
static int
-rhdAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr)
+rhdAtomAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr)
{
if (hdr->usStructureSize == 0xaa55)
return FALSE;
@@ -99,34 +209,33 @@ rhdAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr)
}
static int
-rhdAnalyzeRomHdr(unsigned char *rombase,
+rhdAtomAnalyzeRomHdr(unsigned char *rombase,
ATOM_ROM_HEADER *hdr,
- int *data_offset, int *command_offset)
+ unsigned int *data_offset)
{
- if (rhdAnalyzeCommonHdr(&hdr->sHeader) == -1) {
+ if (!rhdAtomAnalyzeCommonHdr(&hdr->sHeader)) {
return FALSE;
}
- xf86ErrorF("\tSubsysemVendorID: 0x%4.4x SubsystemID: 0x%4.4x\n",
+ xf86DrvMsg(-1,X_NONE,"\tSubsystemVendorID: 0x%4.4x SubsystemID: 0x%4.4x\n",
hdr->usSubsystemVendorID,hdr->usSubsystemID);
- xf86ErrorF("\tIOBaseAddress: 0x%4.4x\n",hdr->usIoBaseAddress);
- xf86ErrorFVerb(3,"\tFilename: %s\n",rombase + hdr->usConfigFilenameOffset);
- xf86ErrorFVerb(3,"\tBIOS Bootup Message: %s\n",
+ xf86DrvMsg(-1,X_NONE,"\tIOBaseAddress: 0x%4.4x\n",hdr->usIoBaseAddress);
+ xf86DrvMsgVerb(-1,X_NONE,3,"\tFilename: %s\n",rombase + hdr->usConfigFilenameOffset);
+ xf86DrvMsgVerb(-1,X_NONE,3,"\tBIOS Bootup Message: %s\n",
rombase + hdr->usBIOS_BootupMessageOffset);
*data_offset = hdr->usMasterDataTableOffset;
- *command_offset = hdr->usMasterCommandTableOffset;
return TRUE;
}
static int
-rhdAnalyzeRomDataTable(unsigned char *base, int offset,
- void *ptr,short *size)
+rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset,
+ void *ptr,unsigned short *size)
{
ATOM_COMMON_TABLE_HEADER *table = (ATOM_COMMON_TABLE_HEADER *)
(base + offset);
- if (!*size || rhdAnalyzeCommonHdr(table) == -1) {
+ if (!*size || !rhdAtomAnalyzeCommonHdr(table)) {
if (*size) *size -= 2;
*(void **)ptr = NULL;
return FALSE;
@@ -137,10 +246,10 @@ rhdAnalyzeRomDataTable(unsigned char *base, int offset,
}
static Bool
-rhdGetAtomBiosTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr,
- CARD8 *contentRev,
- CARD8 *formatRev,
- short *size)
+rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr,
+ CARD8 *contentRev,
+ CARD8 *formatRev,
+ unsigned short *size)
{
if (!hdr)
return FALSE;
@@ -153,24 +262,25 @@ rhdGetAtomBiosTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr,
}
static Bool
-rhdAnalyzeMasterDataTable(unsigned char *base,
- ATOM_MASTER_DATA_TABLE *table,
- atomDataTablesPtr data)
+rhdAtomAnalyzeMasterDataTable(unsigned char *base,
+ ATOM_MASTER_DATA_TABLE *table,
+ atomDataTablesPtr data)
{
ATOM_MASTER_LIST_OF_DATA_TABLES *data_table =
&table->ListOfDataTables;
- short size;
+ unsigned short size;
- if (!rhdAnalyzeCommonHdr(&table->sHeader))
+ if (!rhdAtomAnalyzeCommonHdr(&table->sHeader))
return FALSE;
- if (!rhdGetAtomBiosTableRevisionAndSize(&table->sHeader,NULL,NULL,&size))
+ if (!rhdAtomGetTableRevisionAndSize(&table->sHeader,NULL,NULL,
+ &size))
return FALSE;
# define SET_DATA_TABLE(x) {\
- rhdAnalyzeRomDataTable(base,data_table->x,(void *)(&(data->x)),&size); \
+ rhdAtomAnalyzeRomDataTable(base,data_table->x,(void *)(&(data->x)),&size); \
}
# define SET_DATA_TABLE_VERS(x) {\
- rhdAnalyzeRomDataTable(base,data_table->x,&(data->x.base),&size); \
+ rhdAtomAnalyzeRomDataTable(base,data_table->x,&(data->x.base),&size); \
}
SET_DATA_TABLE(UtilityPipeLine);
@@ -212,55 +322,72 @@ rhdAnalyzeMasterDataTable(unsigned char *base,
return TRUE;
}
-Bool
-rhdGetAtombiosDataTable(int scrnIndex, unsigned char *base, int *cmd_offset,
- atomDataTables *atomDataPtr)
+static Bool
+rhdAtomGetDataTable(int scrnIndex, unsigned char *base,
+ atomDataTables *atomDataPtr, unsigned int BIOSImageSize)
{
- int data_offset;
- unsigned short atom_romhdr_off = *(unsigned short*)
+ unsigned int data_offset;
+ unsigned int atom_romhdr_off = *(unsigned short*)
(base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER);
ATOM_ROM_HEADER *atom_rom_hdr =
(ATOM_ROM_HEADER *)(base + atom_romhdr_off);
- // RHDFUNCI(scrnIndex)
+ //RHDFUNCI(scrnIndex);
+
+ if (atom_romhdr_off + sizeof(ATOM_ROM_HEADER) > BIOSImageSize) {
+ xf86DrvMsg(scrnIndex,X_ERROR,
+ "%s: AtomROM header extends beyond BIOS image\n",__func__);
+ return FALSE;
+ }
if (memcmp("ATOM",&atom_rom_hdr->uaFirmWareSignature,4)) {
- xf86DrvMsg(scrnIndex,X_ERROR,"No AtomBios signature found\n");
+ xf86DrvMsg(scrnIndex,X_ERROR,"%s: No AtomBios signature found\n",
+ __func__);
return FALSE;
}
xf86DrvMsg(scrnIndex, X_INFO, "ATOM BIOS Rom: \n");
- if (!rhdAnalyzeRomHdr(base, atom_rom_hdr, &data_offset, cmd_offset)) {
+ if (!rhdAtomAnalyzeRomHdr(base, atom_rom_hdr, &data_offset)) {
xf86DrvMsg(scrnIndex, X_ERROR, "RomHeader invalid\n");
return FALSE;
}
- if (!rhdAnalyzeMasterDataTable(base, (ATOM_MASTER_DATA_TABLE *)
- (base + data_offset),
- atomDataPtr)) {
- xf86DrvMsg(scrnIndex, X_ERROR, "ROM Master Table invalid\n");
+
+ if (data_offset + sizeof (ATOM_MASTER_DATA_TABLE) > BIOSImageSize) {
+ xf86DrvMsg(scrnIndex,X_ERROR,"%s: Atom data table outside of BIOS\n",
+ __func__);
+ }
+
+ if (!rhdAtomAnalyzeMasterDataTable(base, (ATOM_MASTER_DATA_TABLE *)
+ (base + data_offset),
+ atomDataPtr)) {
+ xf86DrvMsg(scrnIndex, X_ERROR, "%s: ROM Master Table invalid\n",
+ __func__);
return FALSE;
}
return TRUE;
}
static Bool
-rhdBIOSGetFbBaseAndSize(int scrnIndex, atomBIOSHandlePtr handle, unsigned int *base, unsigned int *size)
+rhdAtomGetFbBaseAndSize(atomBiosHandlePtr handle, unsigned int *base,
+ unsigned int *size)
{
- AtomBIOSArg data;
- if (RHDAtomBIOSFunc(scrnIndex, handle, GET_FW_FB_SIZE, &data)
+ AtomBiosArgRec data;
+ if (RHDAtomBiosFunc(handle->scrnIndex, handle, GET_FW_FB_SIZE, &data)
== ATOM_SUCCESS) {
if (data.val == 0) {
- xf86DrvMsg(scrnIndex, X_WARNING, "%s: AtomBIOS specified VRAM "
+ xf86DrvMsg(handle->scrnIndex, X_WARNING, "%s: AtomBIOS specified VRAM "
"scratch space size invalid\n", __func__);
return FALSE;
}
- *size = (int)data.val;
+ if (size)
+ *size = (int)data.val;
} else
return FALSE;
- if (RHDAtomBIOSFunc(scrnIndex, handle, GET_FW_FB_START, &data)
+ if (RHDAtomBiosFunc(handle->scrnIndex, handle, GET_FW_FB_START, &data)
== ATOM_SUCCESS) {
if (data.val == 0)
return FALSE;
- *base = (int)data.val;
+ if (base)
+ *base = (int)data.val;
}
return TRUE;
}
@@ -268,82 +395,84 @@ rhdBIOSGetFbBaseAndSize(int scrnIndex, atomBIOSHandlePtr handle, unsigned int *b
/*
* Uses videoRam form ScrnInfoRec.
*/
-static Bool
-rhdAtomBIOSAllocateFbScratch(int scrnIndex, atomBIOSHandlePtr handle,
- unsigned *start, unsigned int *size)
+static AtomBiosResult
+rhdAtomAllocateFbScratch(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data)
{
unsigned int fb_base = 0;
unsigned int fb_size = 0;
+ unsigned int start = data->fb.start;
+ unsigned int size = data->fb.size;
handle->scratchBase = NULL;
handle->fbBase = 0;
- if (rhdBIOSGetFbBaseAndSize(scrnIndex, handle, &fb_base, &fb_size)) {
- xf86DrvMsg(scrnIndex, X_INFO, "AtomBIOS requests %ikB"
+ if (rhdAtomGetFbBaseAndSize(handle, &fb_base, &fb_size)) {
+ xf86DrvMsg(handle->scrnIndex, X_INFO, "AtomBIOS requests %ikB"
" of VRAM scratch space\n",fb_size);
fb_size *= 1024; /* convert to bytes */
- xf86DrvMsg(scrnIndex, X_INFO, "AtomBIOS VRAM scratch base: 0x%x\n",
+ xf86DrvMsg(handle->scrnIndex, X_INFO, "AtomBIOS VRAM scratch base: 0x%x\n",
fb_base);
} else {
fb_size = 20 * 1024;
- xf86DrvMsg(scrnIndex, X_INFO, " default to: %i\n",fb_size);
+ xf86DrvMsg(handle->scrnIndex, X_INFO, " default to: %i\n",fb_size);
}
- if (fb_base && fb_size && *size) {
+ if (fb_base && fb_size && size) {
/* 4k align */
fb_size = (fb_size & ~(CARD32)0xfff) + ((fb_size & 0xfff) ? 1 : 0);
- if ((fb_base + fb_size) > (*start + *size)) {
- xf86DrvMsg(scrnIndex, X_WARNING,
+ if ((fb_base + fb_size) > (start + size)) {
+ xf86DrvMsg(handle->scrnIndex, X_WARNING,
"%s: FW FB scratch area %i (size: %i)"
" extends beyond available framebuffer size %i\n",
- __func__, fb_base, fb_size, *size);
- } else if ((fb_base + fb_size) < (*start + *size)) {
- xf86DrvMsg(scrnIndex, X_WARNING,
+ __func__, fb_base, fb_size, size);
+ } else if ((fb_base + fb_size) < (start + size)) {
+ xf86DrvMsg(handle->scrnIndex, X_WARNING,
"%s: FW FB scratch area not located "
"at the end of VRAM. Scratch End: "
"0x%x VRAM End: 0x%x\n", __func__,
(unsigned int)(fb_base + fb_size),
- *size);
- } else if (fb_base < *start) {
- xf86DrvMsg(scrnIndex, X_WARNING,
+ size);
+ } else if (fb_base < start) {
+ xf86DrvMsg(handle->scrnIndex, X_WARNING,
"%s: FW FB scratch area extends below "
"the base of the free VRAM: 0x%x Base: 0x%x\n",
- __func__, (unsigned int)(fb_base), *start);
+ __func__, (unsigned int)(fb_base), start);
} else {
- *size -= fb_size;
+ size -= fb_size;
handle->fbBase = fb_base;
- return TRUE;
+ return ATOM_SUCCESS;
}
}
if (!handle->fbBase) {
- xf86DrvMsg(scrnIndex, X_INFO,
+ xf86DrvMsg(handle->scrnIndex, X_INFO,
"Cannot get VRAM scratch space. "
"Allocating in main memory instead\n");
handle->scratchBase = xcalloc(fb_size,1);
- return TRUE;
+ return ATOM_SUCCESS;
}
- return FALSE;
+ return ATOM_FAILED;
}
# ifdef ATOM_BIOS_PARSER
static Bool
-rhdASICInit(atomBIOSHandlePtr handle)
+rhdAtomASICInit(atomBiosHandlePtr handle)
{
ASIC_INIT_PS_ALLOCATION asicInit;
- AtomBIOSArg data;
+ AtomBiosArgRec data;
- RHDAtomBIOSFunc(handle->scrnIndex, handle,
+ RHDAtomBiosFunc(handle->scrnIndex, handle,
GET_DEFAULT_ENGINE_CLOCK,
&data);
- asicInit.sASICInitClocks.ulDefaultEngineClock = data.val; /* in 10 Khz */
- RHDAtomBIOSFunc(handle->scrnIndex, handle,
+ asicInit.sASICInitClocks.ulDefaultEngineClock = data.val / 10;/*in 10 Khz*/
+ RHDAtomBiosFunc(handle->scrnIndex, handle,
GET_DEFAULT_MEMORY_CLOCK,
&data);
- asicInit.sASICInitClocks.ulDefaultMemoryClock = data.val; /* in 10 Khz */
+ asicInit.sASICInitClocks.ulDefaultMemoryClock = data.val / 10;/*in 10 Khz*/
data.exec.dataSpace = NULL;
data.exec.index = 0x0;
data.exec.pspace = &asicInit;
xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling ASIC Init\n");
- if (RHDAtomBIOSFunc(handle->scrnIndex, handle,
+ if (RHDAtomBiosFunc(handle->scrnIndex, handle,
ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Successful\n");
return TRUE;
@@ -351,30 +480,97 @@ rhdASICInit(atomBIOSHandlePtr handle)
xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Failed\n");
return FALSE;
}
+
+Bool
+rhdAtomSetScaler(atomBiosHandlePtr handle, unsigned char scalerID, int setting)
+{
+ ENABLE_SCALER_PARAMETERS scaler;
+ AtomBiosArgRec data;
+
+ scaler.ucScaler = scalerID;
+ scaler.ucEnable = setting;
+ data.exec.dataSpace = NULL;
+ data.exec.index = 0x21;
+ data.exec.pspace = &scaler;
+ xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling EnableScaler\n");
+ if (RHDAtomBiosFunc(handle->scrnIndex, handle,
+ ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ xf86DrvMsg(handle->scrnIndex, X_INFO, "EnableScaler Successful\n");
+ return TRUE;
+ }
+ xf86DrvMsg(handle->scrnIndex, X_INFO, "EableScaler Failed\n");
+ return FALSE;
+}
+
# endif
-static atomBIOSHandlePtr
-rhdInitAtomBIOS(int scrnIndex)
+static AtomBiosResult
+rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2,
+ AtomBiosArgPtr data)
{
+ int scrnIndex = data->val;
RADEONInfoPtr info = RADEONPTR(xf86Screens[scrnIndex]);
- unsigned char *ptr = info->VBIOS;
+ unsigned char *ptr;
atomDataTablesPtr atomDataPtr;
- atomBIOSHandlePtr handle = NULL;
- unsigned int dummy;
- int cmd_offset;
+ atomBiosHandlePtr handle = NULL;
+ unsigned int BIOSImageSize = 0;
+ data->atomhandle = NULL;
- if (!(atomDataPtr = xcalloc(sizeof(atomDataTables),1))) {
+ //RHDFUNCI(scrnIndex);
+
+ /*if (info->BIOSCopy) {
+ xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from INT10\n");
+ ptr = info->BIOSCopy;
+ info->BIOSCopy = NULL;
+
+ BIOSImageSize = ptr[2] * 512;
+ if (BIOSImageSize > legacyBIOSMax) {
+ xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n");
+ return ATOM_FAILED;
+ }
+ } else*/ {
+ /*if (!xf86IsEntityPrimary(info->entityIndex)) {
+ if (!(BIOSImageSize = RHDReadPCIBios(info, &ptr)))
+ return ATOM_FAILED;
+ } else*/ {
+ int read_len;
+ unsigned char tmp[32];
+ xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from legacy VBIOS location\n");
+ if (xf86ReadBIOS(legacyBIOSLocation, 0, tmp, 32) < 0) {
+ xf86DrvMsg(scrnIndex,X_ERROR,
+ "Cannot obtain POSTed BIOS header\n");
+ return ATOM_FAILED;
+ }
+ BIOSImageSize = tmp[2] * 512;
+ if (BIOSImageSize > legacyBIOSMax) {
+ xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n");
+ return ATOM_FAILED;
+ }
+ if (!(ptr = xcalloc(1,BIOSImageSize))) {
+ xf86DrvMsg(scrnIndex,X_ERROR,
+ "Cannot allocate %i bytes of memory "
+ "for BIOS image\n",BIOSImageSize);
+ return ATOM_FAILED;
+ }
+ if ((read_len = xf86ReadBIOS(legacyBIOSLocation, 0, ptr, BIOSImageSize)
+ < 0)) {
+ xf86DrvMsg(scrnIndex,X_ERROR,"Cannot read POSTed BIOS\n");
+ goto error;
+ }
+ }
+ }
+
+ if (!(atomDataPtr = xcalloc(1, sizeof(atomDataTables)))) {
xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory for "
"ATOM BIOS data tabes\n");
goto error;
}
- if (!rhdGetAtombiosDataTable(scrnIndex, ptr, &cmd_offset, atomDataPtr))
+ if (!rhdAtomGetDataTable(scrnIndex, ptr, atomDataPtr,BIOSImageSize))
goto error1;
- if (!(handle = xcalloc(sizeof(atomBIOSHandle),1))) {
+ if (!(handle = xcalloc(1, sizeof(atomBiosHandleRec)))) {
xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory\n");
goto error1;
}
- handle->cmd_offset = cmd_offset;
handle->BIOSBase = ptr;
handle->atomDataPtr = atomDataPtr;
handle->scrnIndex = scrnIndex;
@@ -383,42 +579,49 @@ rhdInitAtomBIOS(int scrnIndex)
#else
handle->PciTag = info->PciTag;
#endif
+ handle->BIOSImageSize = BIOSImageSize;
-#if ATOM_BIOS_PARSER
+# if ATOM_BIOS_PARSER
/* Try to find out if BIOS has been posted (either by system or int10 */
- if (!rhdBIOSGetFbBaseAndSize(scrnIndex, handle, &dummy, &dummy)) {
+ if (!rhdAtomGetFbBaseAndSize(handle, NULL, NULL)) {
/* run AsicInit */
- if (!rhdASICInit(handle))
+ if (!rhdAtomASICInit(handle))
xf86DrvMsg(scrnIndex, X_WARNING,
"%s: AsicInit failed. Won't be able to obtain in VRAM "
"FB scratch space\n",__func__);
}
-#endif
- return handle;
+# endif
+
+ data->atomhandle = handle;
+ return ATOM_SUCCESS;
error1:
xfree(atomDataPtr);
error:
xfree(ptr);
- return NULL;
+ return ATOM_FAILED;
}
-void
-rhdTearDownAtomBIOS(int scrnIndex, atomBIOSHandlePtr handle)
+static AtomBiosResult
+rhdAtomTearDown(atomBiosHandlePtr handle,
+ AtomBiosRequestID unused1, AtomBiosArgPtr unused2)
{
- // RHDFUNCI(scrnIndex);
+ //RHDFUNC(handle);
xfree(handle->BIOSBase);
xfree(handle->atomDataPtr);
+ if (handle->scratchBase) xfree(handle->scratchBase);
xfree(handle);
+ return ATOM_SUCCESS;
}
-AtomBiosResult
-rhdAtomBIOSVramInfoQuery(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func,
- CARD32 *val)
+
+static AtomBiosResult
+rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func,
+ AtomBiosArgPtr data)
{
atomDataTablesPtr atomDataPtr;
-
- // RHDFUNCI(scrnIndex);
+ CARD32 *val = &data->val;
+ //RHDFUNC(handle);
atomDataPtr = handle->atomDataPtr;
@@ -437,36 +640,38 @@ rhdAtomBIOSVramInfoQuery(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc f
return ATOM_SUCCESS;
}
-AtomBiosResult
-rhdAtomBIOSTmdsInfoQuery(int scrnIndex, atomBIOSHandlePtr handle,
- AtomBiosFunc func, int index, CARD32 *val)
+static AtomBiosResult
+rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data)
{
atomDataTablesPtr atomDataPtr;
+ CARD32 *val = &data->val;
+ int idx = *val;
atomDataPtr = handle->atomDataPtr;
- if (!rhdGetAtomBiosTableRevisionAndSize(
- (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base),
+ if (!rhdAtomGetTableRevisionAndSize(
+ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->TMDS_Info),
NULL,NULL,NULL)) {
return ATOM_FAILED;
}
- // RHDFUNCI(scrnIndex);
+ //RHDFUNC(handle);
switch (func) {
case ATOM_TMDS_FREQUENCY:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[index].usFrequency;
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].usFrequency;
break;
case ATOM_TMDS_PLL_CHARGE_PUMP:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_ChargePump;
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_ChargePump;
break;
case ATOM_TMDS_PLL_DUTY_CYCLE:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_DutyCycle;
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_DutyCycle;
break;
case ATOM_TMDS_PLL_VCO_GAIN:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_VCO_Gain;
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_VCO_Gain;
break;
case ATOM_TMDS_PLL_VOLTAGE_SWING:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_VoltageSwing;
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_VoltageSwing;
break;
default:
return ATOM_NOT_IMPLEMENTED;
@@ -474,54 +679,440 @@ rhdAtomBIOSTmdsInfoQuery(int scrnIndex, atomBIOSHandlePtr handle,
return ATOM_SUCCESS;
}
-AtomBiosResult
-rhdAtomBIOSFirmwareInfoQuery(int scrnIndex, atomBIOSHandlePtr handle,
- AtomBiosFunc func, CARD32 *val)
+static DisplayModePtr
+rhdAtomLvdsTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd)
+{
+ DisplayModePtr mode;
+#define NAME_LEN 16
+ char name[NAME_LEN];
+
+ //RHDFUNC(handle);
+
+ if (!(mode = (DisplayModePtr)xcalloc(1,sizeof(DisplayModeRec))))
+ return NULL;
+
+ mode->CrtcHDisplay = mode->HDisplay = dtd->usHActive;
+ mode->CrtcVDisplay = mode->VDisplay = dtd->usVActive;
+ mode->CrtcHBlankStart = dtd->usHActive + dtd->ucHBorder;
+ mode->CrtcHBlankEnd = mode->CrtcHBlankStart + dtd->usHBlanking_Time;
+ mode->CrtcHTotal = mode->HTotal = mode->CrtcHBlankEnd + dtd->ucHBorder;
+ mode->CrtcVBlankStart = dtd->usVActive + dtd->ucVBorder;
+ mode->CrtcVBlankEnd = mode->CrtcVBlankStart + dtd->usVBlanking_Time;
+ mode->CrtcVTotal = mode->VTotal = mode->CrtcVBlankEnd + dtd->ucVBorder;
+ mode->CrtcHSyncStart = mode->HSyncStart = dtd->usHActive + dtd->usHSyncOffset;
+ mode->CrtcHSyncEnd = mode->HSyncEnd = mode->HSyncStart + dtd->usHSyncWidth;
+ mode->CrtcVSyncStart = mode->VSyncStart = dtd->usVActive + dtd->usVSyncOffset;
+ mode->CrtcVSyncEnd = mode->VSyncEnd = mode->VSyncStart + dtd->usVSyncWidth;
+
+ mode->SynthClock = mode->Clock = dtd->usPixClk * 10;
+
+ mode->HSync = ((float) mode->Clock) / ((float)mode->HTotal);
+ mode->VRefresh = (1000.0 * ((float) mode->Clock))
+ / ((float)(((float)mode->HTotal) * ((float)mode->VTotal)));
+
+ xf86snprintf(name, NAME_LEN, "%dx%d",
+ mode->HDisplay, mode->VDisplay);
+ mode->name = xstrdup(name);
+
+ RHDDebug(handle->scrnIndex,"%s: LVDS Modeline: %s "
+ "%2.d %i (%i) %i %i (%i) %i %i (%i) %i %i (%i) %i\n",
+ __func__, mode->name, mode->Clock,
+ mode->HDisplay, mode->CrtcHBlankStart, mode->HSyncStart, mode->CrtcHSyncEnd,
+ mode->CrtcHBlankEnd, mode->HTotal,
+ mode->VDisplay, mode->CrtcVBlankStart, mode->VSyncStart, mode->VSyncEnd,
+ mode->CrtcVBlankEnd, mode->VTotal);
+
+ return mode;
+}
+
+static unsigned char*
+rhdAtomLvdsDDC(atomBiosHandlePtr handle, CARD32 offset, unsigned char *record)
+{
+ unsigned char *EDIDBlock;
+
+ //RHDFUNC(handle);
+
+ while (*record != ATOM_RECORD_END_TYPE) {
+
+ switch (*record) {
+ case LCD_MODE_PATCH_RECORD_MODE_TYPE:
+ offset += sizeof(ATOM_PATCH_RECORD_MODE);
+ if (offset > handle->BIOSImageSize) break;
+ record += sizeof(ATOM_PATCH_RECORD_MODE);
+ break;
+
+ case LCD_RTS_RECORD_TYPE:
+ offset += sizeof(ATOM_LCD_RTS_RECORD);
+ if (offset > handle->BIOSImageSize) break;
+ record += sizeof(ATOM_LCD_RTS_RECORD);
+ break;
+
+ case LCD_CAP_RECORD_TYPE:
+ offset += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
+ if (offset > handle->BIOSImageSize) break;
+ record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
+ break;
+
+ case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
+ offset += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
+ /* check if the structure still fully lives in the BIOS image */
+ if (offset > handle->BIOSImageSize) break;
+ offset += ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength
+ - sizeof(UCHAR);
+ if (offset > handle->BIOSImageSize) break;
+ /* dup string as we free it later */
+ if (!(EDIDBlock = (unsigned char *)xalloc(
+ ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength)))
+ return NULL;
+ memcpy(EDIDBlock,&((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDString,
+ ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength);
+
+ /* for testing */
+ {
+ xf86MonPtr mon = xf86InterpretEDID(handle->scrnIndex,EDIDBlock);
+ xf86PrintEDID(mon);
+ xfree(mon);
+ }
+ return EDIDBlock;
+
+ case LCD_PANEL_RESOLUTION_RECORD_TYPE:
+ offset += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
+ if (offset > handle->BIOSImageSize) break;
+ record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
+ break;
+
+ default:
+ xf86DrvMsg(handle->scrnIndex, X_ERROR,
+ "%s: unknown record type: %x\n",__func__,*record);
+ return NULL;
+ }
+ }
+
+ return NULL;
+}
+
+static AtomBiosResult
+rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func,
+ AtomBiosArgPtr data)
+{
+ atomDataTablesPtr atomDataPtr;
+ CARD8 crev, frev;
+ unsigned long offset;
+
+ //RHDFUNC(handle);
+
+ atomDataPtr = handle->atomDataPtr;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->LVDS_Info.base),
+ &frev,&crev,NULL)) {
+ return ATOM_FAILED;
+ }
+
+ switch (crev) {
+
+ case 1:
+ switch (func) {
+ case ATOMBIOS_GET_PANEL_MODE:
+ data->mode = rhdAtomLvdsTimings(handle,
+ &atomDataPtr->LVDS_Info
+ .LVDS_Info->sLCDTiming);
+ if (data->mode)
+ return ATOM_SUCCESS;
+ default:
+ return ATOM_FAILED;
+ }
+ case 2:
+ switch (func) {
+ case ATOMBIOS_GET_PANEL_MODE:
+ data->mode = rhdAtomLvdsTimings(handle,
+ &atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->sLCDTiming);
+ if (data->mode)
+ return ATOM_SUCCESS;
+ return ATOM_FAILED;
+
+ case ATOMBIOS_GET_PANEL_EDID:
+ offset = (unsigned long)&atomDataPtr->LVDS_Info.base
+ - (unsigned long)handle->BIOSBase
+ + atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->usExtInfoTableOffset;
+
+ data->EDIDBlock
+ = rhdAtomLvdsDDC(handle, offset,
+ (unsigned char *)
+ &atomDataPtr->LVDS_Info.base
+ + atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->usExtInfoTableOffset);
+ if (data->EDIDBlock)
+ return ATOM_SUCCESS;
+ default:
+ return ATOM_FAILED;
+ }
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+/*NOTREACHED*/
+}
+
+static AtomBiosResult
+rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data)
+{
+ atomDataTablesPtr atomDataPtr;
+ CARD8 crev, frev;
+ CARD32 *val = &data->val;
+
+ //RHDFUNC(handle);
+
+ atomDataPtr = handle->atomDataPtr;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->LVDS_Info.base),
+ &frev,&crev,NULL)) {
+ return ATOM_FAILED;
+ }
+
+ switch (crev) {
+ case 1:
+ switch (func) {
+ case ATOM_LVDS_SUPPORTED_REFRESH_RATE:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info->usSupportedRefreshRate;
+ break;
+ case ATOM_LVDS_OFF_DELAY:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info->usOffDelayInMs;
+ break;
+ case ATOM_LVDS_SEQ_DIG_ONTO_DE:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info->ucPowerSequenceDigOntoDEin10Ms * 10;
+ break;
+ case ATOM_LVDS_SEQ_DE_TO_BL:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info->ucPowerSequenceDEtoBLOnin10Ms * 10;
+ break;
+ case ATOM_LVDS_DITHER:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info->ucLVDS_Misc & 0x40;
+ break;
+ case ATOM_LVDS_DUALLINK:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info->ucLVDS_Misc & 0x01;
+ break;
+ case ATOM_LVDS_24BIT:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info->ucLVDS_Misc & 0x02;
+ break;
+ case ATOM_LVDS_GREYLVL:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info->ucLVDS_Misc & 0x0C;
+ break;
+ case ATOM_LVDS_FPDI:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info->ucLVDS_Misc * 0x10;
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ break;
+ case 2:
+ switch (func) {
+ case ATOM_LVDS_SUPPORTED_REFRESH_RATE:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->usSupportedRefreshRate;
+ break;
+ case ATOM_LVDS_OFF_DELAY:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->usOffDelayInMs;
+ break;
+ case ATOM_LVDS_SEQ_DIG_ONTO_DE:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->ucPowerSequenceDigOntoDEin10Ms * 10;
+ break;
+ case ATOM_LVDS_SEQ_DE_TO_BL:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->ucPowerSequenceDEtoBLOnin10Ms * 10;
+ break;
+ case ATOM_LVDS_DITHER:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->ucLVDS_Misc & 0x40;
+ break;
+ case ATOM_LVDS_DUALLINK:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->ucLVDS_Misc & 0x01;
+ break;
+ case ATOM_LVDS_24BIT:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->ucLVDS_Misc & 0x02;
+ break;
+ case ATOM_LVDS_GREYLVL:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->ucLVDS_Misc & 0x0C;
+ break;
+ case ATOM_LVDS_FPDI:
+ *val = atomDataPtr->LVDS_Info
+ .LVDS_Info_v12->ucLVDS_Misc * 0x10;
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+
+ return ATOM_SUCCESS;
+}
+
+static AtomBiosResult
+rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data)
+{
+ atomDataTablesPtr atomDataPtr;
+ CARD8 crev, frev;
+ CARD32 *val = &data->val;
+
+ //RHDFUNC(handle);
+
+ atomDataPtr = handle->atomDataPtr;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->CompassionateData),
+ &frev,&crev,NULL)) {
+ return ATOM_FAILED;
+ }
+
+ switch (func) {
+ case ATOM_DAC1_BG_ADJ:
+ *val = atomDataPtr->CompassionateData->
+ ucDAC1_BG_Adjustment;
+ break;
+ case ATOM_DAC1_DAC_ADJ:
+ *val = atomDataPtr->CompassionateData->
+ ucDAC1_DAC_Adjustment;
+ break;
+ case ATOM_DAC1_FORCE:
+ *val = atomDataPtr->CompassionateData->
+ usDAC1_FORCE_Data;
+ break;
+ case ATOM_DAC2_CRTC2_BG_ADJ:
+ *val = atomDataPtr->CompassionateData->
+ ucDAC2_CRT2_BG_Adjustment;
+ break;
+ case ATOM_DAC2_CRTC2_DAC_ADJ:
+ *val = atomDataPtr->CompassionateData->
+ ucDAC2_CRT2_DAC_Adjustment;
+ break;
+ case ATOM_DAC2_CRTC2_FORCE:
+ *val = atomDataPtr->CompassionateData->
+ usDAC2_CRT2_FORCE_Data;
+ break;
+ case ATOM_DAC2_CRTC2_MUX_REG_IND:
+ *val = atomDataPtr->CompassionateData->
+ usDAC2_CRT2_MUX_RegisterIndex;
+ break;
+ case ATOM_DAC2_CRTC2_MUX_REG_INFO:
+ *val = atomDataPtr->CompassionateData->
+ ucDAC2_CRT2_MUX_RegisterInfo;
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ return ATOM_SUCCESS;
+}
+
+static AtomBiosResult
+rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data)
+{
+ atomDataTablesPtr atomDataPtr;
+ CARD8 crev, frev;
+ CARD32 *val = &data->val;
+ unsigned short size;
+
+ //RHDFUNC(handle);
+
+ atomDataPtr = handle->atomDataPtr;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->GPIO_I2C_Info),
+ &frev,&crev,&size)) {
+ return ATOM_FAILED;
+ }
+
+ switch (func) {
+ case ATOM_GPIO_I2C_CLK_MASK:
+ if ((sizeof(ATOM_COMMON_TABLE_HEADER)
+ + (*val * sizeof(ATOM_GPIO_I2C_ASSIGMENT))) > size) {
+ xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: GPIO_I2C Device "
+ "num %lu exeeds table size %u\n",__func__,
+ (unsigned long)val,
+ size);
+ return ATOM_FAILED;
+ }
+
+ *val = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[*val]
+ .usClkMaskRegisterIndex;
+ break;
+
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ return ATOM_SUCCESS;
+}
+
+static AtomBiosResult
+rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle,
+ AtomBiosRequestID func, AtomBiosArgPtr data)
{
atomDataTablesPtr atomDataPtr;
CARD8 crev, frev;
+ CARD32 *val = &data->val;
- // RHDFUNCI(scrnIndex);
+ //RHDFUNC(handle);
atomDataPtr = handle->atomDataPtr;
- if (!rhdGetAtomBiosTableRevisionAndSize(
+
+ if (!rhdAtomGetTableRevisionAndSize(
(ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base),
&crev,&frev,NULL)) {
return ATOM_FAILED;
}
+
switch (crev) {
case 1:
switch (func) {
case GET_DEFAULT_ENGINE_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->ulDefaultEngineClock;
+ .FirmwareInfo->ulDefaultEngineClock * 10;
break;
case GET_DEFAULT_MEMORY_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->ulDefaultMemoryClock;
+ .FirmwareInfo->ulDefaultMemoryClock * 10;
break;
case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->ulMaxPixelClockPLL_Output;
+ .FirmwareInfo->ulMaxPixelClockPLL_Output * 10;
break;
case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usMinPixelClockPLL_Output;
+ .FirmwareInfo->usMinPixelClockPLL_Output * 10;
case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usMaxPixelClockPLL_Input;
+ .FirmwareInfo->usMaxPixelClockPLL_Input * 10;
break;
case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usMinPixelClockPLL_Input;
+ .FirmwareInfo->usMinPixelClockPLL_Input * 10;
break;
case GET_MAX_PIXEL_CLK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usMaxPixelClock;
+ .FirmwareInfo->usMaxPixelClock * 10;
break;
case GET_REF_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usReferenceClock;
+ .FirmwareInfo->usReferenceClock * 10;
break;
default:
return ATOM_NOT_IMPLEMENTED;
@@ -530,35 +1121,35 @@ rhdAtomBIOSFirmwareInfoQuery(int scrnIndex, atomBIOSHandlePtr handle,
switch (func) {
case GET_DEFAULT_ENGINE_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->ulDefaultEngineClock;
+ .FirmwareInfo_V_1_2->ulDefaultEngineClock * 10;
break;
case GET_DEFAULT_MEMORY_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->ulDefaultMemoryClock;
+ .FirmwareInfo_V_1_2->ulDefaultMemoryClock * 10;
break;
case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output;
+ .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output * 10;
break;
case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output;
+ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output * 10;
break;
case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input;
+ .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input * 10;
break;
case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input;
+ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input * 10;
break;
case GET_MAX_PIXEL_CLK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usMaxPixelClock;
+ .FirmwareInfo_V_1_2->usMaxPixelClock * 10;
break;
case GET_REF_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usReferenceClock;
+ .FirmwareInfo_V_1_2->usReferenceClock * 10;
break;
default:
return ATOM_NOT_IMPLEMENTED;
@@ -568,35 +1159,35 @@ rhdAtomBIOSFirmwareInfoQuery(int scrnIndex, atomBIOSHandlePtr handle,
switch (func) {
case GET_DEFAULT_ENGINE_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->ulDefaultEngineClock;
+ .FirmwareInfo_V_1_3->ulDefaultEngineClock * 10;
break;
case GET_DEFAULT_MEMORY_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->ulDefaultMemoryClock;
+ .FirmwareInfo_V_1_3->ulDefaultMemoryClock * 10;
break;
case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output;
+ .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output * 10;
break;
case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output;
+ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output * 10;
break;
case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input;
+ .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input * 10;
break;
case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input;
+ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input * 10;
break;
case GET_MAX_PIXEL_CLK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usMaxPixelClock;
+ .FirmwareInfo_V_1_3->usMaxPixelClock * 10;
break;
case GET_REF_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usReferenceClock;
+ .FirmwareInfo_V_1_3->usReferenceClock * 10;
break;
default:
return ATOM_NOT_IMPLEMENTED;
@@ -606,35 +1197,35 @@ rhdAtomBIOSFirmwareInfoQuery(int scrnIndex, atomBIOSHandlePtr handle,
switch (func) {
case GET_DEFAULT_ENGINE_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->ulDefaultEngineClock;
+ .FirmwareInfo_V_1_4->ulDefaultEngineClock * 10;
break;
case GET_DEFAULT_MEMORY_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->ulDefaultMemoryClock;
+ .FirmwareInfo_V_1_4->ulDefaultMemoryClock * 10;
break;
case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input;
+ .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input * 10;
break;
case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input;
+ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input * 10;
break;
case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output;
+ .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output * 10;
break;
case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output;
+ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output * 10;
break;
case GET_MAX_PIXEL_CLK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usMaxPixelClock;
+ .FirmwareInfo_V_1_4->usMaxPixelClock * 10;
break;
case GET_REF_CLOCK:
*val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usReferenceClock;
+ .FirmwareInfo_V_1_4->usReferenceClock * 10;
break;
default:
return ATOM_NOT_IMPLEMENTED;
@@ -646,30 +1237,711 @@ rhdAtomBIOSFirmwareInfoQuery(int scrnIndex, atomBIOSHandlePtr handle,
return ATOM_SUCCESS;
}
-# ifdef ATOM_BIOS_PARSER
+#define Limit(n,max,name) ((n >= max) ? ( \
+ xf86DrvMsg(handle->scrnIndex,X_ERROR,"%s: %s %i exceeds maximum %i\n", \
+ __func__,name,n,max), TRUE) : FALSE)
+
+static const struct _rhd_connector_objs
+{
+ char *name;
+ rhdConnectorType con;
+} rhd_connector_objs[] = {
+ { "NONE", RHD_CONNECTOR_NONE },
+ { "SINGLE_LINK_DVI_I", RHD_CONNECTOR_DVI },
+ { "DUAL_LINK_DVI_I", RHD_CONNECTOR_DVI_DUAL },
+ { "SINGLE_LINK_DVI_D", RHD_CONNECTOR_DVI },
+ { "DUAL_LINK_DVI_D", RHD_CONNECTOR_DVI_DUAL },
+ { "VGA", RHD_CONNECTOR_VGA },
+ { "COMPOSITE", RHD_CONNECTOR_TV },
+ { "SVIDEO", RHD_CONNECTOR_TV, },
+ { "D_CONNECTOR", RHD_CONNECTOR_NONE, },
+ { "9PIN_DIN", RHD_CONNECTOR_NONE },
+ { "SCART", RHD_CONNECTOR_TV },
+ { "HDMI_TYPE_A", RHD_CONNECTOR_NONE },
+ { "HDMI_TYPE_B", RHD_CONNECTOR_NONE },
+ { "HDMI_TYPE_B", RHD_CONNECTOR_NONE },
+ { "LVDS", RHD_CONNECTOR_PANEL },
+ { "7PIN_DIN", RHD_CONNECTOR_TV },
+ { "PCIE_CONNECTOR", RHD_CONNECTOR_NONE },
+ { "CROSSFIRE", RHD_CONNECTOR_NONE },
+ { "HARDCODE_DVI", RHD_CONNECTOR_NONE },
+ { "DISPLAYPORT", RHD_CONNECTOR_NONE}
+};
+static const int n_rhd_connector_objs = sizeof (rhd_connector_objs) / sizeof(struct _rhd_connector_objs);
+
+static const struct _rhd_encoders
+{
+ char *name;
+ rhdOutputType ot;
+} rhd_encoders[] = {
+ { "NONE", RHD_OUTPUT_NONE },
+ { "INTERNAL_LVDS", RHD_OUTPUT_LVDS },
+ { "INTERNAL_TMDS1", RHD_OUTPUT_TMDSA },
+ { "INTERNAL_TMDS2", RHD_OUTPUT_TMDSB },
+ { "INTERNAL_DAC1", RHD_OUTPUT_DACA },
+ { "INTERNAL_DAC2", RHD_OUTPUT_DACB },
+ { "INTERNAL_SDVOA", RHD_OUTPUT_NONE },
+ { "INTERNAL_SDVOB", RHD_OUTPUT_NONE },
+ { "SI170B", RHD_OUTPUT_NONE },
+ { "CH7303", RHD_OUTPUT_NONE },
+ { "CH7301", RHD_OUTPUT_NONE },
+ { "INTERNAL_DVO1", RHD_OUTPUT_NONE },
+ { "EXTERNAL_SDVOA", RHD_OUTPUT_NONE },
+ { "EXTERNAL_SDVOB", RHD_OUTPUT_NONE },
+ { "TITFP513", RHD_OUTPUT_NONE },
+ { "INTERNAL_LVTM1", RHD_OUTPUT_LVTMA },
+ { "VT1623", RHD_OUTPUT_NONE },
+ { "HDMI_SI1930", RHD_OUTPUT_NONE },
+ { "HDMI_INTERNAL", RHD_OUTPUT_NONE },
+ { "INTERNAL_KLDSCP_TMDS1", RHD_OUTPUT_TMDSA },
+ { "INTERNAL_KLSCP_DVO1", RHD_OUTPUT_NONE },
+ { "INTERNAL_KLDSCP_DAC1", RHD_OUTPUT_DACA },
+ { "INTERNAL_KLDSCP_DAC2", RHD_OUTPUT_DACB },
+ { "SI178", RHD_OUTPUT_NONE },
+ { "MVPU_FPGA", RHD_OUTPUT_NONE },
+ { "INTERNAL_DDI", RHD_OUTPUT_NONE },
+ { "VT1625", RHD_OUTPUT_NONE },
+ { "HDMI_SI1932", RHD_OUTPUT_NONE },
+ { "AN9801", RHD_OUTPUT_NONE },
+ { "DP501", RHD_OUTPUT_NONE },
+};
+static const int n_rhd_encoders = sizeof (rhd_encoders) / sizeof(struct _rhd_encoders);
+
+static const struct _rhd_connectors
+{
+ char *name;
+ rhdConnectorType con;
+ Bool dual;
+} rhd_connectors[] = {
+ {"NONE", RHD_CONNECTOR_NONE, FALSE },
+ {"VGA", RHD_CONNECTOR_VGA, FALSE },
+ {"DVI-I", RHD_CONNECTOR_DVI, TRUE },
+ {"DVI-D", RHD_CONNECTOR_DVI, FALSE },
+ {"DVI-A", RHD_CONNECTOR_DVI, FALSE },
+ {"SVIDEO", RHD_CONNECTOR_TV, FALSE },
+ {"COMPOSITE", RHD_CONNECTOR_TV, FALSE },
+ {"PANEL", RHD_CONNECTOR_PANEL, FALSE },
+ {"DIGITAL_LINK", RHD_CONNECTOR_NONE, FALSE },
+ {"SCART", RHD_CONNECTOR_TV, FALSE },
+ {"HDMI Type A", RHD_CONNECTOR_NONE, FALSE },
+ {"HDMI Type B", RHD_CONNECTOR_NONE, FALSE },
+ {"UNKNOWN", RHD_CONNECTOR_NONE, FALSE },
+ {"UNKNOWN", RHD_CONNECTOR_NONE, FALSE },
+ {"DVI+DIN", RHD_CONNECTOR_NONE, FALSE }
+};
+static const int n_rhd_connectors = sizeof(rhd_connectors) / sizeof(struct _rhd_connectors);
+
+static const struct _rhd_devices
+{
+ char *name;
+ rhdOutputType ot;
+} rhd_devices[] = {
+ {" CRT1", RHD_OUTPUT_NONE },
+ {" LCD1", RHD_OUTPUT_LVTMA },
+ {" TV1", RHD_OUTPUT_NONE },
+ {" DFP1", RHD_OUTPUT_TMDSA },
+ {" CRT2", RHD_OUTPUT_NONE },
+ {" LCD2", RHD_OUTPUT_LVTMA },
+ {" TV2", RHD_OUTPUT_NONE },
+ {" DFP2", RHD_OUTPUT_LVTMA },
+ {" CV", RHD_OUTPUT_NONE },
+ {" DFP3", RHD_OUTPUT_LVTMA }
+};
+static const int n_rhd_devices = sizeof(rhd_devices) / sizeof(struct _rhd_devices);
+
+static const rhdDDC hwddc[] = { RHD_DDC_0, RHD_DDC_1, RHD_DDC_2, RHD_DDC_3 };
+static const int n_hwddc = sizeof(hwddc) / sizeof(rhdDDC);
+
+static const rhdOutputType acc_dac[] = { RHD_OUTPUT_NONE, RHD_OUTPUT_DACA,
+ RHD_OUTPUT_DACB, RHD_OUTPUT_DAC_EXTERNAL };
+static const int n_acc_dac = sizeof(acc_dac) / sizeof (rhdOutputType);
+
+/*
+ *
+ */
static Bool
-rhdAtomExec (atomBIOSHandlePtr handle, int index, void *pspace, pointer *dataSpace)
+rhdAtomInterpretObjectID(atomBiosHandlePtr handle,
+ CARD16 id, CARD8 *obj_type, CARD8 *obj_id,
+ CARD8 *num, char **name)
+{
+ *obj_id = (id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+ *num = (id & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
+ *obj_type = (id & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+
+ *name = NULL;
+
+ switch (*obj_type) {
+ case GRAPH_OBJECT_TYPE_CONNECTOR:
+ if (!Limit(*obj_id, n_rhd_connector_objs, "obj_id"))
+ *name = rhd_connector_objs[*obj_id].name;
+ break;
+ case GRAPH_OBJECT_TYPE_ENCODER:
+ if (!Limit(*obj_id, n_rhd_encoders, "obj_id"))
+ *name = rhd_encoders[*obj_id].name;
+ break;
+ default:
+ break;
+ }
+ return TRUE;
+}
+
+/*
+ *
+ */
+static void
+rhdAtomDDCFromI2CRecord(atomBiosHandlePtr handle,
+ ATOM_I2C_RECORD *Record, rhdDDC *DDC)
+{
+ RHDDebug(handle->scrnIndex,
+ " %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n",
+ __func__,
+ Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID",
+ Record->sucI2cId.bfI2C_LineMux,
+ Record->sucI2cId.bfHW_EngineID,
+ Record->ucI2CAddr);
+
+ if (!*(unsigned char *)&(Record->sucI2cId))
+ *DDC = RHD_DDC_NONE;
+ else {
+
+ if (Record->ucI2CAddr != 0)
+ return;
+
+ if (Record->sucI2cId.bfHW_Capable) {
+
+ *DDC = (rhdDDC)Record->sucI2cId.bfI2C_LineMux;
+ if (*DDC >= RHD_DDC_MAX)
+ *DDC = RHD_DDC_NONE;
+
+ } else {
+ *DDC = RHD_DDC_GPIO;
+ /* add GPIO pin parsing */
+ }
+ }
+}
+
+/*
+ *
+ */
+static void
+rhdAtomParseGPIOLutForHPD(atomBiosHandlePtr handle,
+ CARD8 pinID, rhdHPD *HPD)
+{
+ atomDataTablesPtr atomDataPtr;
+ ATOM_GPIO_PIN_LUT *gpio_pin_lut;
+ unsigned short size;
+ int i = 0;
+
+ //RHDFUNC(handle);
+
+ atomDataPtr = handle->atomDataPtr;
+
+ *HPD = RHD_HPD_NONE;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ &atomDataPtr->GPIO_Pin_LUT->sHeader, NULL, NULL, &size)) {
+ xf86DrvMsg(handle->scrnIndex, X_ERROR,
+ "%s: No valid GPIO pin LUT in AtomBIOS\n",__func__);
+ return;
+ }
+ gpio_pin_lut = atomDataPtr->GPIO_Pin_LUT;
+
+ while (1) {
+ if (gpio_pin_lut->asGPIO_Pin[i].ucGPIO_ID == pinID) {
+
+ if ((sizeof(ATOM_COMMON_TABLE_HEADER)
+ + (i * sizeof(ATOM_GPIO_PIN_ASSIGNMENT))) > size)
+ return;
+
+ RHDDebug(handle->scrnIndex,
+ " %s: GPIO PinID: %i Index: %x Shift: %i\n",
+ __func__,
+ pinID,
+ gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex,
+ gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift);
+
+ /* grr... map backwards: register indices -> line numbers */
+ if (gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex
+ == (DC_GPIO_HPD_A >> 2)) {
+ switch (gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift) {
+ case 0:
+ *HPD = RHD_HPD_0;
+ return;
+ case 8:
+ *HPD = RHD_HPD_1;
+ return;
+ case 16:
+ *HPD = RHD_HPD_2;
+ return;
+ }
+ }
+ }
+ i++;
+ }
+}
+
+/*
+ *
+ */
+static void
+rhdAtomHPDFromRecord(atomBiosHandlePtr handle,
+ ATOM_HPD_INT_RECORD *Record, rhdHPD *HPD)
+{
+ RHDDebug(handle->scrnIndex,
+ " %s: HPD Record: GPIO ID: %x Plugged_PinState: %x\n",
+ __func__,
+ Record->ucHPDIntGPIOID,
+ Record->ucPluggged_PinState);
+ rhdAtomParseGPIOLutForHPD(handle, Record->ucHPDIntGPIOID, HPD);
+}
+
+/*
+ *
+ */
+static char *
+rhdAtomDeviceTagsFromRecord(atomBiosHandlePtr handle,
+ ATOM_CONNECTOR_DEVICE_TAG_RECORD *Record)
+{
+ int i, j, k;
+ char *devices;
+
+ //RHDFUNC(handle);
+
+ RHDDebug(handle->scrnIndex," NumberOfDevice: %i\n",
+ Record->ucNumberOfDevice);
+
+ if (!Record->ucNumberOfDevice) return NULL;
+
+ devices = (char *)xcalloc(Record->ucNumberOfDevice * 4 + 1,1);
+
+ for (i = 0; i < Record->ucNumberOfDevice; i++) {
+ k = 0;
+ j = Record->asDeviceTag[i].usDeviceID;
+
+ while (!(j & 0x1)) { j >>= 1; k++; };
+
+ if (!Limit(k,n_rhd_devices,"usDeviceID"))
+ strcat(devices, rhd_devices[k].name);
+ }
+
+ RHDDebug(handle->scrnIndex," Devices:%s\n",devices);
+
+ return devices;
+}
+
+/*
+ *
+ */
+static AtomBiosResult
+rhdAtomConnectorInfoFromObjectHeader(atomBiosHandlePtr handle,
+ rhdConnectorInfoPtr *ptr)
+{
+ atomDataTablesPtr atomDataPtr;
+ CARD8 crev, frev;
+ ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
+ rhdConnectorInfoPtr cp;
+ unsigned long object_header_end;
+ int ncon = 0;
+ int i,j;
+ unsigned short object_header_size;
+
+ //RHDFUNC(handle);
+
+ atomDataPtr = handle->atomDataPtr;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ &atomDataPtr->Object_Header->sHeader,
+ &crev,&frev,&object_header_size)) {
+ return ATOM_NOT_IMPLEMENTED;
+ }
+
+ if (crev < 2) /* don't bother with anything below rev 2 */
+ return ATOM_NOT_IMPLEMENTED;
+
+ if (!(cp = (rhdConnectorInfoPtr)xcalloc(sizeof(struct rhdConnectorInfo),
+ RHD_CONNECTORS_MAX)))
+ return ATOM_FAILED;
+
+ object_header_end =
+ atomDataPtr->Object_Header->usConnectorObjectTableOffset
+ + object_header_size;
+
+ RHDDebug(handle->scrnIndex,"ObjectTable - size: %u, BIOS - size: %u "
+ "TableOffset: %u object_header_end: %u\n",
+ object_header_size, handle->BIOSImageSize,
+ atomDataPtr->Object_Header->usConnectorObjectTableOffset,
+ object_header_end);
+
+ if ((object_header_size > handle->BIOSImageSize)
+ || (atomDataPtr->Object_Header->usConnectorObjectTableOffset
+ > handle->BIOSImageSize)
+ || object_header_end > handle->BIOSImageSize) {
+ xf86DrvMsg(handle->scrnIndex, X_ERROR,
+ "%s: Object table information is bogus\n",__func__);
+ return ATOM_FAILED;
+ }
+
+ if (((unsigned long)&atomDataPtr->Object_Header->sHeader
+ + object_header_end) > ((unsigned long)handle->BIOSBase
+ + handle->BIOSImageSize)) {
+ xf86DrvMsg(handle->scrnIndex, X_ERROR,
+ "%s: Object table extends beyond BIOS Image\n",__func__);
+ return ATOM_FAILED;
+ }
+
+ con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
+ ((char *)&atomDataPtr->Object_Header->sHeader +
+ atomDataPtr->Object_Header->usConnectorObjectTableOffset);
+
+ for (i = 0; i < con_obj->ucNumberOfObjects; i++) {
+ ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable;
+ ATOM_COMMON_RECORD_HEADER *Record;
+ int record_base;
+ CARD8 obj_type, obj_id, num;
+ char *name;
+ int nout = 0;
+
+ rhdAtomInterpretObjectID(handle, con_obj->asObjects[i].usObjectID,
+ &obj_type, &obj_id, &num, &name);
+
+ RHDDebug(handle->scrnIndex, "Object: ID: %x name: %s type: %x id: %x\n",
+ con_obj->asObjects[i].usObjectID, name ? name : "",
+ obj_type, obj_id);
+
+
+ if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR)
+ continue;
+
+ SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
+ ((char *)&atomDataPtr->Object_Header->sHeader
+ + con_obj->asObjects[i].usSrcDstTableOffset);
+
+ if (con_obj->asObjects[i].usSrcDstTableOffset
+ + (SrcDstTable->ucNumberOfSrc
+ * sizeof(ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT))
+ > handle->BIOSImageSize) {
+ xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: SrcDstTable[%i] extends "
+ "beyond Object_Header table\n",__func__,i);
+ continue;
+ }
+
+ cp[ncon].Type = rhd_connector_objs[obj_id].con;
+ cp[ncon].Name = RhdAppendString(cp[ncon].Name,name);
+
+ for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) {
+ CARD8 stype, sobj_id, snum;
+ char *sname;
+
+ rhdAtomInterpretObjectID(handle, SrcDstTable->usSrcObjectID[j],
+ &stype, &sobj_id, &snum, &sname);
+
+ RHDDebug(handle->scrnIndex, " * SrcObject: ID: %x name: %s\n",
+ SrcDstTable->usSrcObjectID[j], sname);
+
+ cp[ncon].Output[nout] = rhd_encoders[sobj_id].ot;
+ if (++nout >= MAX_OUTPUTS_PER_CONNECTOR)
+ break;
+ }
+
+ Record = (ATOM_COMMON_RECORD_HEADER *)
+ ((char *)&atomDataPtr->Object_Header->sHeader
+ + con_obj->asObjects[i].usRecordOffset);
+
+ record_base = con_obj->asObjects[i].usRecordOffset;
+
+ while (Record->ucRecordType > 0
+ && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) {
+ char *taglist;
+
+ if ((record_base += Record->ucRecordSize)
+ > object_header_size) {
+ xf86DrvMsg(handle->scrnIndex, X_ERROR,
+ "%s: Object Records extend beyond Object Table\n",
+ __func__);
+ break;
+ }
+
+ RHDDebug(handle->scrnIndex, " - Record Type: %x\n",
+ Record->ucRecordType);
+
+ switch (Record->ucRecordType) {
+
+ case ATOM_I2C_RECORD_TYPE:
+ rhdAtomDDCFromI2CRecord(handle,
+ (ATOM_I2C_RECORD *)Record,
+ &cp[ncon].DDC);
+ break;
+
+ case ATOM_HPD_INT_RECORD_TYPE:
+ rhdAtomHPDFromRecord(handle,
+ (ATOM_HPD_INT_RECORD *)Record,
+ &cp[ncon].HPD);
+ break;
+
+ case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE:
+ taglist = rhdAtomDeviceTagsFromRecord(handle,
+ (ATOM_CONNECTOR_DEVICE_TAG_RECORD *)Record);
+ if (taglist) {
+ cp[ncon].Name = RhdAppendString(cp[ncon].Name,taglist);
+ xfree(taglist);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ Record = (ATOM_COMMON_RECORD_HEADER*)
+ ((char *)Record + Record->ucRecordSize);
+
+ }
+
+ if ((++ncon) == RHD_CONNECTORS_MAX)
+ break;
+ }
+ *ptr = cp;
+
+ RhdPrintConnectorInfo(handle->scrnIndex, cp);
+
+ return ATOM_SUCCESS;
+}
+
+/*
+ *
+ */
+static AtomBiosResult
+rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle,
+ rhdConnectorInfoPtr *ptr)
+{
+ atomDataTablesPtr atomDataPtr;
+ CARD8 crev, frev;
+ rhdConnectorInfoPtr cp;
+ struct {
+ rhdOutputType ot;
+ rhdConnectorType con;
+ rhdDDC ddc;
+ rhdHPD hpd;
+ Bool dual;
+ char *name;
+ char *outputName;
+ } devices[ATOM_MAX_SUPPORTED_DEVICE];
+ int ncon = 0;
+ int n;
+
+ //RHDFUNC(handle);
+
+ atomDataPtr = handle->atomDataPtr;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader),
+ &crev,&frev,NULL)) {
+ return ATOM_NOT_IMPLEMENTED;
+ }
+
+ if (!(cp = (rhdConnectorInfoPtr)xcalloc(RHD_CONNECTORS_MAX,
+ sizeof(struct rhdConnectorInfo))))
+ return ATOM_FAILED;
+
+ for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) {
+ ATOM_CONNECTOR_INFO_I2C ci
+ = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[n];
+
+ devices[n].ot = RHD_OUTPUT_NONE;
+
+ if (!(atomDataPtr->SupportedDevicesInfo
+ .SupportedDevicesInfo->usDeviceSupport & (1 << n)))
+ continue;
+
+ if (Limit(ci.sucConnectorInfo.sbfAccess.bfConnectorType,
+ n_rhd_connectors, "bfConnectorType"))
+ continue;
+
+ devices[n].con
+ = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].con;
+ if (devices[n].con == RHD_CONNECTOR_NONE)
+ continue;
+
+ devices[n].dual
+ = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].dual;
+ devices[n].name
+ = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].name;
+
+ RHDDebug(handle->scrnIndex,"AtomBIOS Connector[%i]: %s Device:%s ",n,
+ rhd_connectors[ci.sucConnectorInfo
+ .sbfAccess.bfConnectorType].name,
+ rhd_devices[n].name);
+
+ devices[n].outputName = rhd_devices[n].name;
+
+ if (!Limit(ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC,
+ n_acc_dac, "bfAssociatedDAC")) {
+ if ((devices[n].ot
+ = acc_dac[ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC])
+ == RHD_OUTPUT_NONE) {
+ devices[n].ot = rhd_devices[n].ot;
+ }
+ } else
+ devices[n].ot = RHD_OUTPUT_NONE;
+
+ RHDDebugCont("Output: %x ",devices[n].ot);
+
+ if (ci.sucI2cId.sbfAccess.bfHW_Capable) {
+
+ RHDDebugCont("HW DDC %i ",
+ ci.sucI2cId.sbfAccess.bfI2C_LineMux);
+
+ if (Limit(ci.sucI2cId.sbfAccess.bfI2C_LineMux,
+ n_hwddc, "bfI2C_LineMux"))
+ devices[n].ddc = RHD_DDC_NONE;
+ else
+ devices[n].ddc = hwddc[ci.sucI2cId.sbfAccess.bfI2C_LineMux];
+
+ } else if (ci.sucI2cId.sbfAccess.bfI2C_LineMux) {
+
+ RHDDebugCont("GPIO DDC ");
+ devices[n].ddc = RHD_DDC_GPIO;
+
+ /* add support for GPIO line */
+ } else {
+
+ RHDDebugCont("NO DDC ");
+ devices[n].ddc = RHD_DDC_NONE;
+
+ }
+
+ if (crev > 1) {
+ ATOM_CONNECTOR_INC_SRC_BITMAP isb
+ = atomDataPtr->SupportedDevicesInfo
+ .SupportedDevicesInfo_HD->asIntSrcInfo[n];
+
+ switch (isb.ucIntSrcBitmap) {
+ case 0x4:
+ RHDDebugCont("HPD 0\n");
+ devices[n].hpd = RHD_HPD_0;
+ break;
+ case 0xa:
+ RHDDebugCont("HPD 1\n");
+ devices[n].hpd = RHD_HPD_1;
+ break;
+ default:
+ RHDDebugCont("NO HPD\n");
+ devices[n].hpd = RHD_HPD_NONE;
+ break;
+ }
+ } else {
+ RHDDebugCont("NO HPD\n");
+ devices[n].hpd = RHD_HPD_NONE;
+ }
+ }
+ /* sort devices for connectors */
+ for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) {
+ int i;
+
+ if (devices[n].ot == RHD_OUTPUT_NONE)
+ continue;
+ if (devices[n].con == RHD_CONNECTOR_NONE)
+ continue;
+
+ cp[ncon].DDC = devices[n].ddc;
+ cp[ncon].HPD = devices[n].hpd;
+ cp[ncon].Output[0] = devices[n].ot;
+ cp[ncon].Output[1] = RHD_OUTPUT_NONE;
+ cp[ncon].Type = devices[n].con;
+ cp[ncon].Name = xf86strdup(devices[n].name);
+ cp[ncon].Name = RhdAppendString(cp[ncon].Name, devices[n].outputName);
+
+ if (devices[n].dual) {
+ if (devices[n].ddc == RHD_DDC_NONE)
+ xf86DrvMsg(handle->scrnIndex, X_ERROR,
+ "No DDC channel for device %s found."
+ " Cannot find matching device.\n",devices[n].name);
+ else {
+ for (i = n + 1; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+
+ if (!devices[i].dual)
+ continue;
+
+ if (devices[n].ddc != devices[i].ddc)
+ continue;
+
+ if (((devices[n].ot == RHD_OUTPUT_DACA
+ || devices[n].ot == RHD_OUTPUT_DACB)
+ && (devices[i].ot == RHD_OUTPUT_LVTMA
+ || devices[i].ot == RHD_OUTPUT_TMDSA))
+ || ((devices[i].ot == RHD_OUTPUT_DACA
+ || devices[i].ot == RHD_OUTPUT_DACB)
+ && (devices[n].ot == RHD_OUTPUT_LVTMA
+ || devices[n].ot == RHD_OUTPUT_TMDSA))) {
+
+ cp[ncon].Output[1] = devices[i].ot;
+
+ if (cp[ncon].HPD == RHD_HPD_NONE)
+ cp[ncon].HPD = devices[i].hpd;
+
+ cp[ncon].Name = RhdAppendString(cp[ncon].Name,
+ devices[i].outputName);
+ devices[i].ot = RHD_OUTPUT_NONE; /* zero the device */
+ }
+ }
+ }
+ }
+
+ if ((++ncon) == RHD_CONNECTORS_MAX)
+ break;
+ }
+ *ptr = cp;
+
+ RhdPrintConnectorInfo(handle->scrnIndex, cp);
+
+ return ATOM_SUCCESS;
+}
+
+/*
+ *
+ */
+static AtomBiosResult
+rhdAtomConnectorInfo(atomBiosHandlePtr handle,
+ AtomBiosRequestID unused, AtomBiosArgPtr data)
+{
+ data->connectorInfo = NULL;
+
+ if (rhdAtomConnectorInfoFromObjectHeader(handle,&data->connectorInfo)
+ == ATOM_SUCCESS)
+ return ATOM_SUCCESS;
+ else
+ return rhdAtomConnectorInfoFromSupportedDevices(handle,
+ &data->connectorInfo);
+}
+
+# ifdef ATOM_BIOS_PARSER
+static AtomBiosResult
+rhdAtomExec (atomBiosHandlePtr handle,
+ AtomBiosRequestID unused, AtomBiosArgPtr data)
{
RADEONInfoPtr info = RADEONPTR (xf86Screens[handle->scrnIndex]);
Bool ret = FALSE;
char *msg;
+ int idx = data->exec.index;
+ void *pspace = data->exec.pspace;
+ pointer *dataSpace = data->exec.dataSpace;
+
+ //RHDFUNCI(handle->scrnIndex);
- // RHDFUNCI(handle->scrnIndex);
if (dataSpace) {
if (!handle->fbBase && !handle->scratchBase)
- return FALSE;
+ return ATOM_FAILED;
if (handle->fbBase) {
if (!info->FB) {
xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: "
"Cannot exec AtomBIOS: framebuffer not mapped\n",
__func__);
- return FALSE;
+ return ATOM_FAILED;
}
*dataSpace = (CARD8*)info->FB + handle->fbBase;
} else
*dataSpace = (CARD8*)handle->scratchBase;
}
- ret = ParseTableWrapper(pspace, index, handle,
+ ret = ParseTableWrapper(pspace, idx, handle,
handle->BIOSBase,
&msg);
if (!ret)
@@ -677,74 +1949,75 @@ rhdAtomExec (atomBIOSHandlePtr handle, int index, void *pspace, pointer *dataSp
else
xf86DrvMsgVerb(handle->scrnIndex, X_INFO, 5, "%s\n",msg);
- return (ret) ? TRUE : FALSE;
+ return (ret) ? ATOM_SUCCESS : ATOM_FAILED;
}
# endif
AtomBiosResult
-RHDAtomBIOSFunc(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func,
- AtomBIOSArgPtr data)
+RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle,
+ AtomBiosRequestID id, AtomBiosArgPtr data)
{
- AtomBiosResult ret = ATOM_NOT_IMPLEMENTED;
- CARD32 val;
-
-# define do_return(x) { \
- if (func < sizeof(AtomBIOSFuncStr)) \
- xf86DrvMsgVerb(scrnIndex, (x == ATOM_SUCCESS) ? 7 : 1, \
- (x == ATOM_SUCCESS) ? X_INFO : X_WARNING, \
- "Call to %s %s\n", AtomBIOSFuncStr[func], \
- (x == ATOM_SUCCESS) ? "succeeded" : "FAILED"); \
- return (x); \
- }
- assert (sizeof(AtomBIOSQueryStr) == (FUNC_END - ATOM_QUERY_FUNCS + 1));
+ AtomBiosResult ret = ATOM_FAILED;
+ int i;
+ char *msg = NULL;
+ enum msgDataFormat msg_f = MSG_FORMAT_NONE;
+ AtomBiosRequestFunc req_func = NULL;
- if (func == ATOMBIOS_INIT) {
- if (!(data->atomp = rhdInitAtomBIOS(scrnIndex)))
- do_return(ATOM_FAILED);
- do_return(ATOM_SUCCESS);
- }
- if (!handle)
- do_return(ATOM_FAILED);
- if (func == ATOMBIOS_ALLOCATE_FB_SCRATCH) {
- if (rhdAtomBIOSAllocateFbScratch( scrnIndex, handle, &data->fb.start, &data->fb.size)) {
- do_return(ATOM_SUCCESS);
- } else {
- do_return(ATOM_FAILED);
+ //RHDFUNCI(scrnIndex);
+
+ for (i = 0; AtomBiosRequestList[i].id != FUNC_END; i++) {
+ if (id == AtomBiosRequestList[i].id) {
+ req_func = AtomBiosRequestList[i].request;
+ msg = AtomBiosRequestList[i].message;
+ msg_f = AtomBiosRequestList[i].message_format;
+ break;
}
}
- if (func <= ATOMBIOS_TEARDOWN) {
- rhdTearDownAtomBIOS(scrnIndex, handle);
- do_return(ATOM_SUCCESS);
+
+ if (req_func == NULL) {
+ xf86DrvMsg(scrnIndex, X_ERROR, "Unknown AtomBIOS request: %i\n",id);
+ return ATOM_NOT_IMPLEMENTED;
}
-# ifdef ATOM_BIOS_PARSER
- if (func == ATOMBIOS_EXEC) {
- if (!rhdAtomExec(handle, data->exec.index,
- data->exec.pspace, data->exec.dataSpace)) {
- do_return(ATOM_FAILED);
- } else {
- do_return(ATOM_SUCCESS);
+ /* Hack for now */
+ if (id == ATOMBIOS_INIT)
+ data->val = scrnIndex;
+
+ if (id == ATOMBIOS_INIT || handle)
+ ret = req_func(handle, id, data);
+
+ if (ret == ATOM_SUCCESS) {
+
+ switch (msg_f) {
+ case MSG_FORMAT_DEC:
+ xf86DrvMsg(scrnIndex,X_INFO,"%s: %li\n", msg,
+ (unsigned long) data->val);
+ break;
+ case MSG_FORMAT_HEX:
+ xf86DrvMsg(scrnIndex,X_INFO,"%s: 0x%lx\n",msg ,
+ (unsigned long) data->val);
+ break;
+ case MSG_FORMAT_NONE:
+ xf86DrvMsgVerb(scrnIndex, 7, X_INFO,
+ "Call to %s succeeded\n", msg);
+ break;
}
- } else
-# endif
- if (func >= ATOM_QUERY_FUNCS && func < ATOM_VRAM_QUERIES) {
- ret = rhdAtomBIOSFirmwareInfoQuery(scrnIndex, handle, func, &val);
- data->val = val;
- } else if (func >= ATOM_VRAM_QUERIES && func < FUNC_END) {
- ret = rhdAtomBIOSVramInfoQuery(scrnIndex, handle, func, &val);
- data->val = val;
+
} else {
- xf86DrvMsg(scrnIndex,X_INFO,"%s: Received unknown query\n",__func__);
- return ATOM_NOT_IMPLEMENTED;
+
+ char *result = (ret == ATOM_FAILED) ? "failed"
+ : "not implemented";
+ switch (msg_f) {
+ case MSG_FORMAT_DEC:
+ case MSG_FORMAT_HEX:
+ xf86DrvMsgVerb(scrnIndex, 1, X_WARNING,
+ "Call to %s %s\n", msg, result);
+ break;
+ case MSG_FORMAT_NONE:
+ xf86DrvMsg(scrnIndex,X_INFO,"Query for %s: %s\n", msg, result);
+ break;
+ }
}
- if (ret == ATOM_SUCCESS)
- xf86DrvMsg(scrnIndex,X_INFO,"%s: %i 0x%08x\n",
- AtomBIOSQueryStr[func - ATOM_QUERY_FUNCS], (unsigned int)val, (unsigned int)val);
- else
- xf86DrvMsg(scrnIndex,X_INFO,"Query for %s: %s\n",
- AtomBIOSQueryStr[func - ATOM_QUERY_FUNCS],
- ret == ATOM_FAILED ? "failed" : "not implemented");
return ret;
-
}
# ifdef ATOM_BIOS_PARSER
@@ -771,54 +2044,50 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay)
usleep(delay);
- // DEBUGP(xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay));
+ DEBUGP(xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay));
}
UINT32
-CailReadATIRegister(VOID* CAIL, UINT32 index)
+CailReadATIRegister(VOID* CAIL, UINT32 idx)
{
UINT32 ret;
- ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
CAILFUNC(CAIL);
- ret = INREG(index << 2);
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index << 2,ret));
+ ret = INREG(idx << 2);
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx << 2,ret));
return ret;
}
VOID
-CailWriteATIRegister(VOID *CAIL, UINT32 index, UINT32 data)
+CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data)
{
- CAILFUNC(CAIL);
ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
+ CAILFUNC(CAIL);
- OUTREG(index << 2,data);
- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index << 2,data));
+ OUTREG(idx << 2,data);
+ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data));
}
UINT32
-CailReadFBData(VOID* CAIL, UINT32 index)
+CailReadFBData(VOID* CAIL, UINT32 idx)
{
- UINT32 ret;
ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
+ UINT32 ret;
CAILFUNC(CAIL);
- if (((atomBIOSHandlePtr)CAIL)->fbBase) {
+ if (((atomBiosHandlePtr)CAIL)->fbBase) {
CARD8 *FBBase = (CARD8*)info->FB;
- ret = *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + index));
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index,ret));
- } else if (((atomBIOSHandlePtr)CAIL)->scratchBase) {
- ret = *(CARD32*)((CARD8*)(((atomBIOSHandlePtr)CAIL)->scratchBase) + index);
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index,ret));
+ ret = *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + idx));
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));
+ } else if (((atomBiosHandlePtr)CAIL)->scratchBase) {
+ ret = *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx);
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));
} else {
- xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR,
+ xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR,
"%s: no fbbase set\n",__func__);
return 0;
}
@@ -826,27 +2095,30 @@ CailReadFBData(VOID* CAIL, UINT32 index)
}
VOID
-CailWriteFBData(VOID *CAIL, UINT32 index, UINT32 data)
+CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data)
{
+ ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
CAILFUNC(CAIL);
- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index,data));
- if (((atomBIOSHandlePtr)CAIL)->fbBase) {
+ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data));
+ if (((atomBiosHandlePtr)CAIL)->fbBase) {
CARD8 *FBBase = (CARD8*)
RADEONPTR(xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex])->FB;
- *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + index)) = data;
- } else if (((atomBIOSHandlePtr)CAIL)->scratchBase) {
- *(CARD32*)((CARD8*)(((atomBIOSHandlePtr)CAIL)->scratchBase) + index) = data;
+ *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + idx)) = data;
+ } else if (((atomBiosHandlePtr)CAIL)->scratchBase) {
+ *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data;
} else
- xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR,
+ xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR,
"%s: no fbbase set\n",__func__);
}
ULONG
CailReadMC(VOID *CAIL, ULONG Address)
{
- ULONG ret;
ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ ULONG ret;
+
CAILFUNC(CAIL);
ret = INMC(pScrn, Address);
@@ -857,116 +2129,88 @@ CailReadMC(VOID *CAIL, ULONG Address)
VOID
CailWriteMC(VOID *CAIL, ULONG Address, ULONG data)
{
- CAILFUNC(CAIL);
ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+
+ CAILFUNC(CAIL);
DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data));
OUTMC(pScrn, Address, data);
}
+#ifdef XSERVER_LIBPCIACCESS
+
VOID
-CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 index,UINT16 size)
+CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size)
{
-#if !XSERVER_LIBPCIACCESS
- PCITAG tag = ((atomBIOSHandlePtr)CAIL)->PciTag;
+ pci_device_cfg_read(RADEONPTR(xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex])->PciInfo,
+ ret,idx << 2 , size >> 3, NULL);
+}
- CAILFUNC(CAIL);
+VOID
+CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size)
+{
+ pci_device_cfg_write(RADEONPTR(xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex])->PciInfo,
+ src, idx << 2, size >> 3, NULL);
+}
- switch (size) {
- case 8:
- *(CARD8*)ret = pciReadByte(tag,index << 2);
- break;
- case 16:
- *(CARD16*)ret = pciReadWord(tag,index << 2);
- break;
- case 32:
- *(CARD32*)ret = pciReadLong(tag,index << 2);
- break;
- default:
- xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,
- X_ERROR,"%s: Unsupported size: %i\n",
- __func__,(int)size);
- return;
- break;
- }
#else
- struct pci_device *device = ((atomBIOSHandlePtr)CAIL)->device;
+
+VOID
+CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size)
+{
+ PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag;
CAILFUNC(CAIL);
switch (size) {
case 8:
- pci_device_cfg_read_u8(device, (CARD8*)ret, index << 2);
+ *(CARD8*)ret = pciReadByte(tag,idx << 2);
break;
case 16:
- pci_device_cfg_read_u16(device, (CARD16*)ret, index << 2);
+ *(CARD16*)ret = pciReadWord(tag,idx << 2);
break;
case 32:
- pci_device_cfg_read_u32(device, (uint32_t*)ret, index << 2);
+ *(CARD32*)ret = pciReadLong(tag,idx << 2);
break;
default:
- xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,
+ xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,
X_ERROR,"%s: Unsupported size: %i\n",
__func__,(int)size);
return;
break;
}
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index,*(unsigned int*)ret));
-#endif
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,*(unsigned int*)ret));
+
}
VOID
-CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 index,UINT16 size)
+CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size)
{
-#if !XSERVER_LIBPCIACCESS
- PCITAG tag = ((atomBIOSHandlePtr)CAIL)->PciTag;
-
- CAILFUNC(CAIL);
- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index,(*(unsigned int*)src)));
- switch (size) {
- case 8:
- pciWriteByte(tag,index << 2,*(CARD8*)src);
- break;
- case 16:
- pciWriteWord(tag,index << 2,*(CARD16*)src);
- break;
- case 32:
- pciWriteLong(tag,index << 2,*(CARD32*)src);
- break;
- default:
- xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR,
- "%s: Unsupported size: %i\n",__func__,(int)size);
- break;
- }
-#else
- struct pci_device *device = ((atomBIOSHandlePtr)CAIL)->device;
+ PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag;
CAILFUNC(CAIL);
- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index,(*(unsigned int*)src)));
+ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src)));
switch (size) {
case 8:
- pci_device_cfg_write_u8(device,index << 2,*(CARD8*)src);
+ pciWriteByte(tag,idx << 2,*(CARD8*)src);
break;
case 16:
- pci_device_cfg_write_u16(device,index << 2,*(uint16_t *)src);
+ pciWriteWord(tag,idx << 2,*(CARD16*)src);
break;
case 32:
- pci_device_cfg_write_u32(device,index << 2,*(uint32_t *)src);
+ pciWriteLong(tag,idx << 2,*(CARD32*)src);
break;
default:
- xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR,
+ xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR,
"%s: Unsupported size: %i\n",__func__,(int)size);
break;
}
-#endif
}
+#endif
ULONG
CailReadPLL(VOID *CAIL, ULONG Address)
{
ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
ULONG ret;
CAILFUNC(CAIL);
@@ -988,117 +2232,6 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data)
RADEONOUTPLL(pScrn, Address, Data);
}
-void
-rhdTestAtomBIOS(atomBIOSHandlePtr atomBIOS)
-{
- READ_EDID_FROM_HW_I2C_DATA_PARAMETERS i2cData;
- AtomBIOSArg data;
- int i;
- unsigned char *space;
-
- i2cData.usPrescale = 0x7fff;
- i2cData.usVRAMAddress = 0;
- i2cData.usStatus = 128;
- i2cData.ucSlaveAddr = 0xA0;
-
- data.exec.dataSpace = (void*)&space;
- data.exec.index = GetIndexIntoMasterTable(COMMAND, ReadEDIDFromHWAssistedI2C);
- data.exec.pspace = &i2cData;
-
- for (i = 0; i < 4; i++) {
- i2cData.ucLineNumber = i;
- if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- int j;
- CARD8 chksum = 0;
- xf86DrvMsg(atomBIOS->scrnIndex, X_INFO,"%s: I2C channel %i STATUS: %x\n",
- __func__,i,i2cData.usStatus);
- /* read good ? */
- if ((i2cData.usStatus >> 8) == HW_ASSISTED_I2C_STATUS_SUCCESS) {
- /* checksum good? */
- ErrorF("i2c data ustatus good %04X\n", i2cData.usStatus);
- if (!(i2cData.usStatus & 0xff)) {
-#if 0
- RhdDebugDump(atomBIOS->scrnIndex, space, 128);
-#endif
- for (j = 0; j < 128; j++)
- chksum += space[i];
- xf86DrvMsg(atomBIOS->scrnIndex, X_INFO, "DDC Checksum: %i\n",chksum);
- }
- }
- }
- }
-}
# endif
-#else /* ATOM_BIOS */
-
-AtomBiosResult
-RHDAtomBIOSFunc(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func,
- AtomBIOSArgPtr data)
-{
- assert (sizeof(AtomBIOSQueryStr) == (FUNC_END - ATOM_QUERY_FUNCS + 1));
-
- if (func < ATOM_QUERY_FUNCS) {
- if (func >= 0 && func < sizeof(AtomBIOSFuncStr))
- xf86DrvMsgVerb(scrnIndex, 5, X_WARNING,
- "AtomBIOS support not available, cannot execute %s\n",
- AtomBIOSFuncStr[func]);
- else
- xf86DrvMsg(scrnIndex, X_ERROR,"Invalid AtomBIOS func %x\n",func);
- } else {
-
- if (func < FUNC_END)
- xf86DrvMsgVerb(scrnIndex, 5, X_WARNING,
- "AtomBIOS not available, cannot get %s\n",
- AtomBIOSQueryStr[func - ATOM_QUERY_FUNCS]);
- else
- xf86DrvMsg(scrnIndex, X_ERROR, "Invalid AtomBIOS query %x\n",func);
- }
- return ATOM_NOT_IMPLEMENTED;
-}
-
#endif /* ATOM_BIOS */
-
-
-AtomBiosResult
-RADEONAtomBIOSSetCrtcSource(atomBIOSHandlePtr atomBIOS, int crtc, int output_mask)
-{
- SELECT_CRTC_SOURCE_PARAMETERS crtc_data;
- AtomBIOSArg data;
- unsigned char *space;
-
- crtc_data.ucCRTC = crtc;
- crtc_data.ucDevice = ATOM_DEVICE_CRT1_SUPPORT;
-
- data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &crtc_data;
-
- if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Set CRTC source success\n");
- return ATOM_SUCCESS ;
- }
-
- ErrorF("Set CRTC source failed\n");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-void
-atombios_get_command_table_version(atomBIOSHandlePtr atomBIOS, int index, int *major, int *minor)
-{
- ATOM_MASTER_COMMAND_TABLE *cmd_table = atomBIOS->BIOSBase + atomBIOS->cmd_offset;
- ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start;
- ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr;
-
- unsigned short *ptr;
- unsigned short offset;
-
- table_start = &cmd_table->ListOfCommandTables;
-
- offset = *(((unsigned short *)table_start) + index);
-
- table_hdr = atomBIOS->BIOSBase + offset;
-
- *major = table_hdr->CommonHeader.ucTableFormatRevision;
- *minor = table_hdr->CommonHeader.ucTableContentRevision;
-}
diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h
index b9ce53a..3cfa673 100644
--- a/src/radeon_atombios.h
+++ b/src/radeon_atombios.h
@@ -29,13 +29,19 @@
#include "radeon.h"
-typedef enum {
+# ifdef ATOM_BIOS
+
+typedef enum _AtomBiosRequestID {
ATOMBIOS_INIT,
ATOMBIOS_TEARDOWN,
+# ifdef ATOM_BIOS_PARSER
ATOMBIOS_EXEC,
+#endif
ATOMBIOS_ALLOCATE_FB_SCRATCH,
- ATOM_QUERY_FUNCS = 0x1000,
- GET_DEFAULT_ENGINE_CLOCK = ATOM_QUERY_FUNCS,
+ ATOMBIOS_GET_CONNECTORS,
+ ATOMBIOS_GET_PANEL_MODE,
+ ATOMBIOS_GET_PANEL_EDID,
+ GET_DEFAULT_ENGINE_CLOCK,
GET_DEFAULT_MEMORY_CLOCK,
GET_MAX_PIXEL_CLOCK_PLL_OUTPUT,
GET_MIN_PIXEL_CLOCK_PLL_OUTPUT,
@@ -43,58 +49,67 @@ typedef enum {
GET_MIN_PIXEL_CLOCK_PLL_INPUT,
GET_MAX_PIXEL_CLK,
GET_REF_CLOCK,
- ATOM_VRAM_QUERIES,
- GET_FW_FB_START = ATOM_VRAM_QUERIES,
+ GET_FW_FB_START,
GET_FW_FB_SIZE,
- ATOM_TMDS_QUERIES,
- ATOM_TMDS_FREQUENCY = ATOM_TMDS_QUERIES,
+ ATOM_TMDS_FREQUENCY,
ATOM_TMDS_PLL_CHARGE_PUMP,
ATOM_TMDS_PLL_DUTY_CYCLE,
ATOM_TMDS_PLL_VCO_GAIN,
ATOM_TMDS_PLL_VOLTAGE_SWING,
+ ATOM_LVDS_SUPPORTED_REFRESH_RATE,
+ ATOM_LVDS_OFF_DELAY,
+ ATOM_LVDS_SEQ_DIG_ONTO_DE,
+ ATOM_LVDS_SEQ_DE_TO_BL,
+ ATOM_LVDS_DITHER,
+ ATOM_LVDS_DUALLINK,
+ ATOM_LVDS_24BIT,
+ ATOM_LVDS_GREYLVL,
+ ATOM_LVDS_FPDI,
+ ATOM_GPIO_QUERIES,
+ ATOM_GPIO_I2C_CLK_MASK,
+ ATOM_DAC1_BG_ADJ,
+ ATOM_DAC1_DAC_ADJ,
+ ATOM_DAC1_FORCE,
+ ATOM_DAC2_CRTC2_BG_ADJ,
+ ATOM_DAC2_CRTC2_DAC_ADJ,
+ ATOM_DAC2_CRTC2_FORCE,
+ ATOM_DAC2_CRTC2_MUX_REG_IND,
+ ATOM_DAC2_CRTC2_MUX_REG_INFO,
FUNC_END
-} AtomBiosFunc;
+} AtomBiosRequestID;
-typedef enum {
+typedef enum _AtomBiosResult {
ATOM_SUCCESS,
ATOM_FAILED,
ATOM_NOT_IMPLEMENTED
} AtomBiosResult;
-typedef struct {
+typedef struct AtomExec {
int index;
pointer pspace;
pointer *dataSpace;
-} AtomExec, *AtomExecPtr;
+} AtomExecRec, *AtomExecPtr;
-typedef struct {
+typedef struct AtomFb {
unsigned int start;
unsigned int size;
-} AtomFb, *AtomFbPtr;
+} AtomFbRec, *AtomFbPtr;
-typedef union
+typedef union AtomBiosArg
{
CARD32 val;
-
- pointer ptr;
- atomBIOSHandlePtr atomp;
- AtomExec exec;
- AtomFb fb;
-} AtomBIOSArg, *AtomBIOSArgPtr;
-
-
-extern void
-atombios_get_command_table_version(atomBIOSHandlePtr atomBIOS, int index, int *major, int *minor);
+ struct rhdConnectorInfo *connectorInfo;
+ unsigned char* EDIDBlock;
+ atomBiosHandlePtr atomhandle;
+ DisplayModePtr mode;
+ AtomExecRec exec;
+ AtomFbRec fb;
+} AtomBiosArgRec, *AtomBiosArgPtr;
extern AtomBiosResult
-RHDAtomBIOSFunc(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func,
- AtomBIOSArgPtr data);
-
-/* only for testing */
-void rhdTestAtomBIOS(atomBIOSHandlePtr atomBIOS);
+RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle,
+ AtomBiosRequestID id, AtomBiosArgPtr data);
-#ifdef ATOM_BIOS
-//# include "rhd_atomwrapper.h"
# include "xf86int10.h"
# ifdef ATOM_BIOS_PARSER
# define INT8 INT8
@@ -102,7 +117,7 @@ void rhdTestAtomBIOS(atomBIOSHandlePtr atomBIOS);
# define INT32 INT32
# include "CD_Common_Types.h"
# else
-# ifndef ULONG
+# ifndef ULONG
typedef unsigned int ULONG;
# define ULONG ULONG
# endif
@@ -110,14 +125,28 @@ typedef unsigned int ULONG;
typedef unsigned char UCHAR;
# define UCHAR UCHAR
# endif
-# ifndef USHORT
+# ifndef USHORT
typedef unsigned short USHORT;
# define USHORT USHORT
# endif
# endif
-#include "atombios.h"
+# include "atombios.h"
+# include "ObjectID.h"
+/*
+ * This works around a bug in atombios.h where
+ * ATOM_MAX_SUPPORTED_DEVICE_INFO is specified incorrectly.
+ */
+
+#define ATOM_MAX_SUPPORTED_DEVICE_INFO_HD (ATOM_DEVICE_RESERVEDF_INDEX+1)
+typedef struct _ATOM_SUPPORTED_DEVICES_INFO_HD
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usDeviceSupport;
+ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD];
+ ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD];
+} ATOM_SUPPORTED_DEVICES_INFO_HD;
typedef struct _atomDataTables
{
@@ -145,6 +174,7 @@ typedef struct _atomDataTables
ATOM_SUPPORTED_DEVICES_INFO *SupportedDevicesInfo;
ATOM_SUPPORTED_DEVICES_INFO_2 *SupportedDevicesInfo_2;
ATOM_SUPPORTED_DEVICES_INFO_2d1 *SupportedDevicesInfo_2d1;
+ ATOM_SUPPORTED_DEVICES_INFO_HD *SupportedDevicesInfo_HD;
} SupportedDevicesInfo;
ATOM_GPIO_I2C_INFO *GPIO_I2C_Info;
ATOM_VRAM_USAGE_BY_FIRMWARE *VRAM_UsageByFirmware;
@@ -184,19 +214,20 @@ typedef struct _atomDataTables
ATOM_POWER_SOURCE_INFO *PowerSourceInfo;
} atomDataTables, *atomDataTablesPtr;
-typedef struct _atomBIOSHandle {
+typedef struct _atomBiosHandle {
int scrnIndex;
unsigned char *BIOSBase;
atomDataTablesPtr atomDataPtr;
pointer *scratchBase;
CARD32 fbBase;
- int cmd_offset;
#if XSERVER_LIBPCIACCESS
struct pci_device *device;
#else
PCITAG PciTag;
#endif
-} atomBIOSHandle;
+ unsigned int BIOSImageSize;
+} atomBiosHandleRec;
+
+# endif
-#endif
#endif /* RHD_ATOMBIOS_H_ */
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 52be98c..061dc15 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -137,21 +137,20 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
if (info->IsAtomBios) {
#if 1
- AtomBIOSArg atomBiosArg;
+ AtomBiosArgRec atomBiosArg;
- if (RHDAtomBIOSFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) == ATOM_SUCCESS) {
+ if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) == ATOM_SUCCESS) {
info->atomBIOS = atomBiosArg.ptr;
}
atomBiosArg.fb.start = info->FbFreeStart;
atomBiosArg.fb.size = info->FbFreeSize;
- if (RHDAtomBIOSFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH,
+ if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH,
&atomBiosArg) == ATOM_SUCCESS) {
info->FbFreeStart = atomBiosArg.fb.start;
info->FbFreeSize = atomBiosArg.fb.size;
}
- //rhdTestAtomBIOS(info->atomBIOS);
#endif
info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32);
}
commit 3614d80ceb9a7b3615b0baab3cf2dd34ed4ab464
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Nov 16 17:22:39 2007 +1000
add missing hpd register
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index e299481..290869f 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3646,6 +3646,7 @@
#define AVIVO_GPIO_2 0x7e50
#define AVIVO_GPIO_3 0x7e60
+#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
#define R520_PCLK_HDCP_CNTL 0x494
#define AVIVO_I2C_STATUS 0x7d30
commit 9a2715fda97ac0ebcb45650a416e0652aab575b8
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Nov 16 17:22:25 2007 +1000
make i2c unlock/lock registers for gpios
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 4cc964e..815bab5 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -154,7 +154,7 @@ static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color
static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color);
static RADEONMonitorType radeon_detect_ext_dac(ScrnInfoPtr pScrn);
static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output);
-static Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state);
+static Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio);
extern void atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr mode,
@@ -283,9 +283,9 @@ avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
RADEONDDCType DDCType = radeon_output->DDCType;
if (radeon_output->pI2CBus) {
- AVIVOI2CDoLock(output->scrn, 1);
+ AVIVOI2CDoLock(output->scrn, 1, radeon_output->gpio);
MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
- AVIVOI2CDoLock(output->scrn, 0);
+ AVIVOI2CDoLock(output->scrn, 0, radeon_output->gpio);
}
if (MonInfo) {
if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
@@ -2307,12 +2307,26 @@ Bool AVIVOI2CReset(ScrnInfoPtr pScrn)
}
static
-Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state)
+Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio_reg)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
CARD32 temp;
+ temp = INREG(gpio_reg + 4);
+ if (gpio_reg == AVIVO_GPIO_0) {
+ if (lock_state == 0)
+ temp |= (1 << 19) | (1 << 18);
+ else
+ temp &= ~((1 << 19) | (1 << 18));
+ } else {
+ if (lock_state == 0)
+ temp |= (1 << 0) | (1 << 8);
+ else
+ temp &= ~((1 << 0) | (1 << 8));
+ }
+ OUTREG(gpio_reg + 4, temp);
+
switch(lock_state) {
case 0:
temp = INREG(AVIVO_I2C_CNTL);
commit 20dc549fff9a4137c93ebed449d05e0c437b6bc1
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Nov 16 17:01:33 2007 +1000
avivo i2c: consolidate the avivo i2c code
diff --git a/src/radeon_output.c b/src/radeon_output.c
index ccbc306..4cc964e 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2337,55 +2337,30 @@ Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state)
}
void
-avivo_i2c_gpio0_get_bits(I2CBusPtr b, int *Clock, int *data)
+avivo_i2c_gpio_get_bits(I2CBusPtr b, int *Clock, int *data)
{
ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
RADEONInfoPtr info = RADEONPTR(screen_info);
unsigned char *RADEONMMIO = info->MMIO;
unsigned long val;
- ErrorF("INREG %08x\n", INREG(b->DriverPrivate.uval));
/* Get the result */
- val = INREG(b->DriverPrivate.uval + 0xC);
- *Clock = (val & (1<<19)) != 0;
- *data = (val & (1<<18)) != 0;
-}
-
-void
-avivo_i2c_gpio0_put_bits(I2CBusPtr b, int Clock, int data)
-{
- ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(screen_info);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned long val;
-
- val = 0;
- val |= (Clock ? 0:(1<<19));
- val |= (data ? 0:(1<<18));
- OUTREG(b->DriverPrivate.uval + 0x8, val);
- /* read back to improve reliability on some cards. */
- val = INREG(b->DriverPrivate.uval + 0x8);
-}
-
-void
-avivo_i2c_gpio123_get_bits(I2CBusPtr b, int *Clock, int *data)
-{
- ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(screen_info);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned long val;
-
- if (INREG(b->DriverPrivate.uval) == 0)
- OUTREG(b->DriverPrivate.uval, (1<<0) | (1<<8));
-
- /* Get the result */
- val = INREG(b->DriverPrivate.uval + 0xC);
- *Clock = (val & (1<<0)) != 0;
- *data = (val & (1<<8)) != 0;
+ if (b->DriverPrivate.uval == AVIVO_GPIO_0) {
+ val = INREG(b->DriverPrivate.uval + 0xC);
+ *Clock = (val & (1<<19)) != 0;
+ *data = (val & (1<<18)) != 0;
+ } else {
+ if (INREG(b->DriverPrivate.uval) == 0)
+ OUTREG(b->DriverPrivate.uval, (1<<0) | (1<<8));
+
+ val = INREG(b->DriverPrivate.uval + 0xC);
+ *Clock = (val & (1<<0)) != 0;
+ *data = (val & (1<<8)) != 0;
+ }
}
static void
-avivo_i2c_gpio123_put_bits(I2CBusPtr b, int Clock, int data)
+avivo_i2c_gpio_put_bits(I2CBusPtr b, int Clock, int data)
{
ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
RADEONInfoPtr info = RADEONPTR(screen_info);
@@ -2393,8 +2368,14 @@ avivo_i2c_gpio123_put_bits(I2CBusPtr b, int Clock, int data)
unsigned long val;
val = 0;
- val |= (Clock ? 0:(1<<0));
- val |= (data ? 0:(1<<8));
+ if (b->DriverPrivate.uval == AVIVO_GPIO_0) {
+ val |= (Clock ? 0:(1<<19));
+ val |= (data ? 0:(1<<18));
+ } else {
+ val |= (Clock ? 0:(1<<0));
+ val |= (data ? 0:(1<<8));
+
+ }
OUTREG(b->DriverPrivate.uval + 0x8, val);
/* read back to improve reliability on some cards. */
val = INREG(b->DriverPrivate.uval + 0x8);
@@ -2410,13 +2391,8 @@ avivo_i2c_init(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
pI2CBus->BusName = name;
pI2CBus->scrnIndex = pScrn->scrnIndex;
- if (i2c_reg == AVIVO_GPIO_0) {
- pI2CBus->I2CPutBits = avivo_i2c_gpio0_put_bits;
- pI2CBus->I2CGetBits = avivo_i2c_gpio0_get_bits;
- } else {
- pI2CBus->I2CPutBits = avivo_i2c_gpio123_put_bits;
- pI2CBus->I2CGetBits = avivo_i2c_gpio123_get_bits;
- }
+ pI2CBus->I2CPutBits = avivo_i2c_gpio_put_bits;
+ pI2CBus->I2CGetBits = avivo_i2c_gpio_get_bits;
pI2CBus->AcknTimeout = 5;
pI2CBus->DriverPrivate.uval = i2c_reg;
commit 3e62730f79a13883a65a568bc821bc56055a4ab7
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Nov 16 15:19:00 2007 +1000
atombios: fixup warnings in atombios files
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 34dd65c..9305592 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -260,21 +260,18 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
- double c;
- int div1, div2, clock;
- int sclock;
- uint16_t ref_div, fb_div;
- uint8_t post_div;
- int mul;
+ int sclock = mode->Clock;
+ uint16_t ref_div = 0, fb_div = 0;
+ uint8_t post_div = 0;
int major, minor;
SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
void *ptr;
AtomBIOSArg data;
unsigned char *space;
RADEONSavePtr save = &info->ModeReg;
-
+
+ sclock = mode->Clock;
if (IS_AVIVO_VARIANT) {
PLLCalculate(mode->Clock, &ref_div, &fb_div, &post_div);
} else {
@@ -339,7 +336,6 @@ atombios_set_crtc_source(xf86CrtcPtr crtc)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
AtomBIOSArg data;
unsigned char *space;
SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
@@ -412,9 +408,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
- int regval;
- AtomBiosResult atom_res;
- RADEONSavePtr restore = &info->ModeReg;
Bool tilingOld = info->tilingEnabled;
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 6c26982..2893455 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -48,7 +48,6 @@ atom_bios_display_device_control(atomBIOSHandlePtr atomBIOS, int device, Bool st
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data;
AtomBIOSArg data;
unsigned char *space;
- AtomBiosResult ret;
disp_data.ucAction = state;
data.exec.index = device;
@@ -84,7 +83,6 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
AtomBIOSArg data;
unsigned char *space;
- AtomBiosResult ret;
disp_data.ucAction = 1;
disp_data.ucDacStandard = 1;
@@ -115,12 +113,10 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
int
atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data;
AtomBIOSArg data;
unsigned char *space;
- AtomBiosResult ret;
disp_data.sXTmdsEncoder.ucEnable = 1;
@@ -141,21 +137,17 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
return ATOM_SUCCESS;
}
- ErrorF("External TMDS enable failed\n", radeon_output->DACType);
+ ErrorF("External TMDS enable failed\n");
return ATOM_NOT_IMPLEMENTED;
}
static int
atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned int tmp;
TMDS1_ENCODER_CONTROL_PS_ALLOCATION disp_data;
AtomBIOSArg data;
unsigned char *space;
- AtomBiosResult ret;
disp_data.ucAction = 1;
if (mode->Clock > 165000)
@@ -183,16 +175,13 @@ atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
#endif
}
-static void
+static int
atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode)
{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
- unsigned int tmp;
TMDS2_ENCODER_CONTROL_PS_ALLOCATION disp_data;
AtomBIOSArg data;
unsigned char *space;
- AtomBiosResult ret;
disp_data.ucAction = 1;
if (mode->Clock > 165000)
@@ -234,7 +223,6 @@ atombios_output_dac_dpms(xf86OutputPtr output, int mode)
static void
atombios_output_tmds1_dpms(xf86OutputPtr output, int mode)
{
- RADEONOutputPrivatePtr avivo_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
switch(mode) {
@@ -255,9 +243,7 @@ atombios_output_tmds1_dpms(xf86OutputPtr output, int mode)
static void
atombios_output_tmds2_dpms(xf86OutputPtr output, int mode)
{
- RADEONOutputPrivatePtr avivo_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
switch(mode) {
case DPMSModeOn:
@@ -331,8 +317,6 @@ atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr mode,
DisplayModePtr adjusted_mode)
{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
if (radeon_output->MonType == MT_CRT) {
@@ -384,7 +368,7 @@ atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
ret = atom_bios_dac_load_detect(info->atomBIOS, radeon_output->DACType);
if (ret == ATOM_SUCCESS) {
- ErrorF("DAC connect %08X\n", INREG(0x10));
+ ErrorF("DAC connect %08X\n", (unsigned int)INREG(0x10));
bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH);
if (radeon_output->DACType == DAC_PRIMARY) {
commit cca7af3c4910983f7f090792986fcbfa0dc97cfb
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Nov 16 15:04:01 2007 +1000
remove avivo_reg.h
diff --git a/src/avivo_reg.h b/src/avivo_reg.h
deleted file mode 100644
index 0a53303..0000000
--- a/src/avivo_reg.h
+++ /dev/null
@@ -1,502 +0,0 @@
-/* AVIVO registers are specific to the AVIVO display engine, first
- * introduced on R5xx.
- *
- * CRTCs are the master unit. A CRTC controls scanout, and both the
- * DACs (be it TV or VGA) and TMDS transmitters take their input from
- * the CRTC.
- */
-
-/* Core engine. */
-#define AVIVO_ENGINE_STATUS 0x0014
-
-/* Memory mapping. */
-#define AVIVO_MC_INDEX 0x0070
-/* AVIVO_MC_MEMORY_MAP control memory mapping of the video card ram:
- * base is higher 16bits of the starting address at which card
- * sees it own memory. end is higher 16bits address at which card
- * memory should end (might be usefull if you want to use half memory
- * but don't know what does the card if you address out of bound
- * memory, likely trigger pci stuff which often end in bad things).
- */
-# define MC00 0x00
-#define R520_MC_STATUS 0x00
-#define R520_MC_STATUS_IDLE (1<<1)
-# define MC01 0x01
-# define MC02 0x02
-# define MC03 0x03
-# define AVIVO_MC_MEMORY_MAP 0x04
-# define AVIVO_MC_MEMORY_MAP_BASE_MASK (0xFFFF << 0)
-# define AVIVO_MC_MEMORY_MAP_BASE_SHIFT 0
-# define AVIVO_MC_MEMORY_MAP_END_MASK (0xFFFF << 16)
-# define AVIVO_MC_MEMORY_MAP_END_SHIFT 16
-# define MC05 0x05
-# define MC06 0x06
-# define MC07 0x07
-# define MC08 0x08
-#define RV515_MC_STATUS 0x08
-#define RV515_MC_STATUS_IDLE (1<<4)
-# define MC09 0x09
-# define MC0a 0x0a
-# define MC0b 0x0b
-# define MC0c 0x0c
-# define MC0d 0x0d
-# define MC0e 0x0e
-# define MC0f 0x0f
-# define MC10 0x10
-# define MC11 0x11
-# define MC12 0x12
-# define MC13 0x13
-# define MC14 0x14
-# define MC15 0x15
-# define MC16 0x16
-# define MC17 0x17
-# define MC18 0x18
-# define MC19 0x19
-# define MC1a 0x1a
-# define MC1b 0x1b
-# define MC1c 0x1c
-# define MC1d 0x1d
-# define MC1e 0x1e
-# define MC1f 0x1f
-#define AVIVO_MC_DATA 0x0074
-
-/*
- * You set memory base at which card see its memory (should be the
- * same as AVIVO_MC_MEMORY_MAP lower 16bits
- */
-#define AVIVO_VGA_MEMORY_BASE 0x0134
-#define AVIVO_VGA_FB_START 0x0310
-#define AVIVO_VGA1_CONTROL 0x0330
- #define AVIVO_VGA1_CONTROL_MODE_ENABLE (1<<0)
- #define AVIVO_VGA1_CONTROL_TIMING_SELECT (1<<8)
- #define AVIVO_VGA1_CONTROL_SYNC_POLARITY_SELECT (1<<9)
- #define AVIVO_VGA1_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
- #define AVIVO_VGA1_CONTROL_OVERSCAN_COLOR_EN (1<<16)
- #define AVIVO_VGA1_CONTROL_ROTATE (1<<24)
-#define AVIVO_VGA2_CONTROL 0x0338
- #define AVIVO_VGA2_CONTROL_MODE_ENABLE (1<<0)
- #define AVIVO_VGA2_CONTROL_TIMING_SELECT (1<<8)
- #define AVIVO_VGA2_CONTROL_SYNC_POLARITY_SELECT (1<<9)
- #define AVIVO_VGA2_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
- #define AVIVO_VGA2_CONTROL_OVERSCAN_COLOR_EN (1<<16)
- #define AVIVO_VGA2_CONTROL_ROTATE (1<<24)
-
-/*
- * We believe reference clock is 108Mhz, we likely can change that using
- * mystery PLL reg spoted below more dump are needed in order to find out.
- *
- * The formula we derived so far seems to work for card we have:
- * (vclk is video mode clock)
- * vclk = (1080 * AVIVO_PLL_POST_MUL) /
- * (AVIVO_PLL_DIVIDER * AVIVO_PLL_POST_DIV * 40)
- * It seems that AVIVO_PLL_DIVIDER * AVIVO_PLL_POST_DIV needs to be
- * above 40 and that AVIVO_DIVIDER should be greater than AVIVO_PLL_POST_DIV
- * Try to keep this constraint while computing PLL values.
- */
-#define AVIVO_PLL1_POST_DIV_CNTL 0x0400 // REF_DIV_SRC
-# define AVIVO_PLL_POST_DIV_EN (1 << 0)
-#define AVIVO_PLL1_POST_DIV 0x0404 // REF_DIV
-#define AVIVO_PLL1_POST_DIV_MYSTERY 0x040C
-# define AVIVO_PLL_POST_DIV_MYSTERY_VALUE 0x10000
-#define AVIVO_PLL2_POST_DIV_CNTL 0x0410
-#define AVIVO_PLL2_POST_DIV 0x0414
-#define AVIVO_PLL2_POST_DIV_MYSTERY 0x041C
-#define AVIVO_PLL1_POST_MUL 0x0430 // FB_DIV
-# define AVIVO_PLL_POST_MUL_SHIFT 16
-#define AVIVO_PLL2_POST_MUL 0x0434 // FB_DIV
-#define AVIVO_PLL1_DIVIDER_CNTL 0x0438 // POST DIV_SRC
-# define AVIVO_PLL_DIVIDER_EN (1 << 0)
-#define AVIVO_PLL1_DIVIDER 0x043C // POST DIV
-#define AVIVO_PLL2_DIVIDER_CNTL 0x0440
-#define AVIVO_PLL2_DIVIDER 0x0444 // POST_DIV
-#define AVIVO_PLL1_MYSTERY0 0x0448 // POST_DIV_SRC
-# define AVIVO_PLL_MYSTERY0_VALUE 0x20704
-#define AVIVO_PLL2_MYSTERY0 0x044C
-#define AVIVO_PLL1_MYSTERY1 0x0450
-# define AVIVO_PLL_MYSTERY1_VALUE 0x4310000
-#define AVIVO_PLL2_MYSTERY1 0x0454
-#define AVIVO_CRTC_PLL_SOURCE 0x0484
-# define AVIVO_CRTC1_PLL_SOURCE_SHIFT 0
-# define AVIVO_CRTC2_PLL_SOURCE_SHIFT 16
-
-/* CRTC controls; these appear to influence the DAC's scanout. */
-#define AVIVO_CRTC1_H_TOTAL 0x6000
-#define AVIVO_CRTC1_H_BLANK 0x6004
-#define AVIVO_CRTC1_H_SYNC_WID 0x6008
-#define AVIVO_CRTC1_H_SYNC_POL 0x600c
-#define AVIVO_CRTC1_V_TOTAL 0x6020
-#define AVIVO_CRTC1_V_BLANK 0x6024
-#define AVIVO_CRTC1_V_SYNC_WID 0x6028
-#define AVIVO_CRTC1_V_SYNC_POL 0x602c
-#define AVIVO_CRTC1_CNTL 0x6080
-# define AVIVO_CRTC_EN (1 << 0)
-#define AVIVO_CRTC1_BLANK_STATUS 0x6084
-#define AVIVO_CRTC1_STEREO_STATUS 0x60c0
-
-/* These all appear to control the scanout from the framebuffer.
- * Flicking SCAN_ENABLE low results in a black screen -- aside from
- * the cursor. Messing with PITCH gives you the obvious symptoms,
- * and messing with X_LENGTH and Y_LENGTH will give you a black
- * screen beyond those bounds if you make it shorter.
- *
- * Messing with the format gives you ... odd results. Setting it
- * to 3 exactly quadruples my display size, with the next three
- * panes displaying the next parts of FB memory. BPP?
- *
- * FB_LOCATION gives me the obvious result; FB_END is exactly
- * FB_LOCATION + (xres * yres * 2). FB_END doesn't appear to actually
- * function as an upper bound.
- */
-#define AVIVO_CRTC1_SCAN_ENABLE 0x6100
-# define AVIVO_CRTC_SCAN_EN (1 << 0)
-#define AVIVO_CRTC1_FB_FORMAT 0x6104
-# define AVIVO_CRTC_FORMAT_ARGB15 (1 << 0)
-# define AVIVO_CRTC_FORMAT_ARGB16 ((1 << 0) | (1 << 8))
-# define AVIVO_CRTC_FORMAT_ARGB32 (1 << 1)
-# define AVIVO_CRTC_TILED (1 << 20)
-# define AVIVO_CRTC_MACRO_ADDRESS_MODE (1 << 21)
-#define AVIVO_CRTC1_FB_LOCATION 0x6110
-#define AVIVO_CRTC1_FB_END 0x6118
-/* This is in pixels, not bytes. Obviously. */
-#define AVIVO_CRTC1_PITCH 0x6120
-#define AVIVO_CRTC1_X_LENGTH 0x6134
-#define AVIVO_CRTC1_Y_LENGTH 0x6138
-
-#define AVIVO_CRTC1_OFFSET_END 0x6454
-
-#define AVIVO_CRTC1_FB_HEIGHT 0x652c
-#define AVIVO_CRTC1_OFFSET_START 0x6580
-#define AVIVO_CRTC1_EXPANSION_SOURCE 0x6584
-#define AVIVO_CRTC1_EXPANSION_CNTL 0x6590
-# define AVIVO_CRTC_EXPANSION_EN (1 << 0)
-#define AVIVO_CRTC1_6594 0x6594
-# define AVIVO_CRTC1_6594_VALUE ((1 << 8) | (1 << 0))
-#define AVIVO_CRTC1_659C 0x659C
-# define AVIVO_CRTC1_659C_VALUE ((1 << 1))
-#define AVIVO_CRTC1_65A4 0x65a4
-# define AVIVO_CRTC1_65A4_VALUE ((1 << 16) | (1 << 0))
-#define AVIVO_CRTC1_65A8 0x65a8
-# define AVIVO_CRTC1_65A8_VALUE ((1 << 16) | (1 << 14))
-#define AVIVO_CRTC1_65AC 0x65ac
-# define AVIVO_CRTC1_65AC_VALUE ((1 << 15) | (1 << 14) | (1 << 13))
-#define AVIVO_CRTC1_65B0 0x65b0
-# define AVIVO_CRTC1_65B0_VALUE ((1 << 17) | (1 << 16) | (1 << 8))
-#define AVIVO_CRTC1_65B8 0x65b8
-# define AVIVO_CRTC1_65B8_VALUE ((1 << 16))
-#define AVIVO_CRTC1_65BC 0x65bc
-# define AVIVO_CRTC1_65BC_VALUE ((1 << 16))
-#define AVIVO_CRTC1_65C0 0x65c0
-# define AVIVO_CRTC1_65C0_VALUE ((1 << 17) | (1 << 16) | (1 << 8))
-#define AVIVO_CRTC1_65C8 0x65c8
-# define AVIVO_CRTC1_65C8_VALUE ((1 << 16))
-
-#define AVIVO_CRTC2_H_TOTAL 0x6800
-#define AVIVO_CRTC2_H_BLANK 0x6804
-#define AVIVO_CRTC2_H_SYNC_WID 0x6808
-#define AVIVO_CRTC2_H_SYNC_POL 0x680c
-#define AVIVO_CRTC2_V_TOTAL 0x6820
-#define AVIVO_CRTC2_V_BLANK 0x6824
-#define AVIVO_CRTC2_V_SYNC_WID 0x6828
-#define AVIVO_CRTC2_V_SYNC_POL 0x682c
-#define AVIVO_CRTC2_CNTL 0x6880
-#define AVIVO_CRTC2_BLANK_STATUS 0x6884
-
-#define AVIVO_CRTC2_SCAN_ENABLE 0x6900
-#define AVIVO_CRTC2_FB_FORMAT 0x6904
-#define AVIVO_CRTC2_FB_LOCATION 0x6910
-#define AVIVO_CRTC2_FB_END 0x6918
-#define AVIVO_CRTC2_PITCH 0x6920
-#define AVIVO_CRTC2_X_LENGTH 0x6934
-#define AVIVO_CRTC2_Y_LENGTH 0x6938
-
-#define AVIVO_CRTC2_OFFSET_END 0x6c54
-
-#define AVIVO_CRTC2_FB_HEIGHT 0x6d2c
-#define AVIVO_CRTC2_OFFSET_START 0x6d80
-#define AVIVO_CRTC2_EXPANSION_SOURCE 0x6d84
-#define AVIVO_CRTC2_EXPANSION_CNTL 0x6d90
-#define AVIVO_CRTC2_6594 0x6d94
-#define AVIVO_CRTC2_659C 0x6d9C
-#define AVIVO_CRTC2_65A4 0x6da4
-#define AVIVO_CRTC2_65A8 0x6da8
-#define AVIVO_CRTC2_65AC 0x6dac
-#define AVIVO_CRTC2_65B0 0x6db0
-#define AVIVO_CRTC2_65B8 0x6db8
-#define AVIVO_CRTC2_65BC 0x6dbc
-#define AVIVO_CRTC2_65C0 0x6dc0
-#define AVIVO_CRTC2_65C8 0x6dc8
-
-#define AVIVO_DACA_CNTL 0x7800
-#define AVIVO_DACA_CRTC_SOURCE 0x7804
-# define AVIVO_DAC_EN (1 << 0)
-#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
-#define AVIVO_DACA_POWERDOWN 0x7850
-# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
-# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
-# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
-# define AVIVO_DACA_POWERDOWN_RED (1 << 24)
-
-#define AVIVO_DACB_CNTL 0x7a00
-#define AVIVO_DACB_CRTC_SOURCE 0x7a04
-#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
-#define AVIVO_DACB_POWERDOWN 0x7a50
-# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
-# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
-# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
-# define AVIVO_DACB_POWERDOWN_RED (1 << 24)
-
-/* Frustratingly, at least on my R580, the DAC and TMDS orders
- * appear inversed: 7800 and 7a80 enable/disable the same physical
- * connector; ditto 7a00 and 7880. O brave new world!
- */
-/* TMDS_CNTL only lower bit of each half bytes matters.
- * UNK0 seems to have no effect on LVDS but kill the feed of DVI connector
- * UNK1 really unknow: so far no visible change from setting it or not
- * UNK2 really unknow: so far no visible change from setting it or not
- * UNK3 really unknow: so far no visible change from setting it or not
- * UNK4 seems to switch red & blue encoding
- * UNK5 is the fun bits on some card people will see their desktop
- * tiled 4 times but for most cards this will give wrong pictures
- * UNK6 seems to kill the feed LVDS & DVI
- */
-#define AVIVO_TMDSA_CNTL 0x7880
-# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
-# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
-# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
-# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
-# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
-# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
-# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
-#define AVIVO_TMDSA_CRTC_SOURCE 0x7884
-/* 78a8 appears to be some kind of (reasonably tolerant) clock?
- * 78d0 definitely hits the transmitter, definitely clock. */
-/* MYSTERY1 This appears to control dithering? */
-#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
-#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
-#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
-# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
-# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
-#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
-#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
-
-/* I don't know any of the bits here, only that enabling (1 << 5)
- * without (1 << 4) makes things go utterly mental ... seems to be
- * the transmitter clock again. */
-/* 790c is a clock?
- * 7910 appears to be some kind of control field, again. (1 << 25)
- * must be enabled to get a signal on my monitor. */
-#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
-
-#define AVIVO_LVTMA_CNTL 0x7a80
-# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
-# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
-# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
-# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
-# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
-# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
-# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
-#define AVIVO_LVTMA_CRTC_SOURCE 0x7a84
-#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
-
-#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
-
-#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
-# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
-# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
-#define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00
-
-#define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
-
-#define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
-
-#define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0
-# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
-# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
-# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
-# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
-# define AVIVO_LVTMA_SYNCEN (1 << 8)
-# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
-# define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
-# define AVIVO_LVTMA_DIGON (1 << 16)
-# define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
-# define AVIVO_LVTMA_DIGON_POL (1 << 18)
-# define AVIVO_LVTMA_BLON (1 << 24)
-# define AVIVO_LVTMA_BLON_OVRD (1 << 25)
-# define AVIVO_LVTMA_BLON_POL (1 << 26)
-
-#define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4
-# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
-# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
-# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
-# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
-# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
-# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
-
-#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
-# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
-# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
-# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
-
-/* The BIOS says so, anyway ... */
-#define AVIVO_GPIO_0 0x7e30
-#define AVIVO_GPIO_1 0x7e40
-#define AVIVO_GPIO_2 0x7e50
-#define AVIVO_GPIO_3 0x7e60
-
-#define AVIVO_TMDS_STATUS 0x7e9c
-# define AVIVO_TMDSA_CONNECTED (1 << 0)
-# define AVIVO_LVTMA_CONNECTED (1 << 8)
-
-/* Cursor registers. */
-#define AVIVO_CURSOR1_CNTL 0x6400
-# define AVIVO_CURSOR_EN (1 << 0)
-# define AVIVO_CURSOR_FORMAT_MASK (3 << 8)
-# define AVIVO_CURSOR_FORMAT_ABGR 0x1
-# define AVIVO_CURSOR_FORMAT_ARGB 0x2
-# define AVIVO_CURSOR_FORMAT_SHIFT 8
-#define AVIVO_CURSOR1_LOCATION 0x6408
-/* x is in the top 16 bits; y in the lower 16. Note that _SIZE does not
- * impact the in-memory format: it is always 64x64. */
-#define AVIVO_CURSOR1_SIZE 0x6410
-#define AVIVO_CURSOR1_POSITION 0x6414
-
-#define AVIVO_I2C_STATUS 0x7d30
-# define AVIVO_I2C_STATUS_DONE (1 << 0)
-# define AVIVO_I2C_STATUS_NACK (1 << 1)
-# define AVIVO_I2C_STATUS_HALT (1 << 2)
-# define AVIVO_I2C_STATUS_GO (1 << 3)
-# define AVIVO_I2C_STATUS_MASK 0x7
-/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
- * DONE? */
-# define AVIVO_I2C_STATUS_CMD_RESET 0x7
-# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3)
-#define AVIVO_I2C_STOP 0x7d34
-#define AVIVO_I2C_START_CNTL 0x7d38
-# define AVIVO_I2C_START (1 << 8)
-# define AVIVO_I2C_CONNECTOR0 (0 << 16)
-# define AVIVO_I2C_CONNECTOR1 (1 << 16)
-#define R520_I2C_START (1<<0)
-#define R520_I2C_STOP (1<<1)
-#define R520_I2C_RX (1<<2)
-#define R520_I2C_EN (1<<8)
-#define R520_I2C_DDC1 (0<<16)
-#define R520_I2C_DDC2 (1<<16)
-#define R520_I2C_DDC3 (2<<16)
-#define R520_I2C_DDC_MASK (3<<16)
-#define AVIVO_I2C_CONTROL2 0x7d3c
-# define AVIVO_I2C_7D3C_SIZE_SHIFT 8
-# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8)
-#define AVIVO_I2C_CONTROL3 0x7d40
-/* Reading is done 4 bytes at a time: read the bottom 8 bits from
- * 7d44, four times in a row.
- * Writing is a little more complex. First write DATA with
- * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
- * magic number, zz is, I think, the slave address, and yy is the byte
- * you want to write. */
-#define AVIVO_I2C_DATA 0x7d44
-#define R520_I2C_ADDR_COUNT_MASK (0x7)
-#define R520_I2C_DATA_COUNT_SHIFT (8)
-#define R520_I2C_DATA_COUNT_MASK (0xF00)
-#define AVIVO_I2C_CNTL 0x7d50
-# define AVIVO_I2C_EN (1 << 0)
-# define AVIVO_I2C_RESET (1 << 8)
-
-
-#define R520_PCLK_HDCP_CNTL 0x494
-
-#define AVIVO_HDP_FB_LOCATION 0x134
-#define AVIVO_VGA_MEM_BASE 0x310
-#define AVIVO_VGA_SURF_ADDR 0x318
-#define AVIVO_D1VGA_CTRL 0x330
-#define AVIVO_D2VGA_CTRL 0x338
-
-#define AVIVO_DVGA_MODE_ENABLE (1<<0)
-
-
commit d39eb2077c6b2fc094ccd952772528eb9428c587
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Nov 16 15:00:50 2007 +1000
radeon: rename a large section of avivo regs to documented names
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 38450bb..34dd65c 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -104,9 +104,7 @@ atombios_crtc_enable(xf86CrtcPtr crtc, int enable)
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int scan_enable, cntl;
- AtomBiosResult res;
+
atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable);
//TODOavivo_wait_idle(avivo);
@@ -465,55 +463,46 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4;
switch (crtc->scrn->bitsPerPixel) {
case 15:
- radeon_crtc->fb_format = AVIVO_CRTC_FORMAT_ARGB15;
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
break;
case 16:
- radeon_crtc->fb_format = AVIVO_CRTC_FORMAT_ARGB16;
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
break;
case 24:
case 32:
- radeon_crtc->fb_format = AVIVO_CRTC_FORMAT_ARGB32;
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
break;
default:
FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
}
if (info->tilingEnabled) {
- radeon_crtc->fb_format |= AVIVO_CRTC_MACRO_ADDRESS_MODE;
+ radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
}
if (radeon_crtc->crtc_id == 0)
- OUTREG(AVIVO_VGA1_CONTROL, 0);
+ OUTREG(AVIVO_D1VGA_CONTROL, 0);
else
- OUTREG(AVIVO_VGA2_CONTROL, 0);
+ OUTREG(AVIVO_D1VGA_CONTROL, 0);
/* setup fb format and location
*/
- OUTREG(AVIVO_CRTC1_EXPANSION_SOURCE + radeon_crtc->crtc_offset,
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
(mode->HDisplay << 16) | mode->VDisplay);
- OUTREG(AVIVO_CRTC1_FB_LOCATION + radeon_crtc->crtc_offset, fb_location);
- OUTREG(AVIVO_CRTC1_FB_END + radeon_crtc->crtc_offset, fb_location);
- OUTREG(AVIVO_CRTC1_FB_FORMAT + radeon_crtc->crtc_offset,
+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset,
radeon_crtc->fb_format);
- OUTREG(AVIVO_CRTC1_X_LENGTH + radeon_crtc->crtc_offset,
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset,
crtc->scrn->virtualX);
- OUTREG(AVIVO_CRTC1_Y_LENGTH + radeon_crtc->crtc_offset,
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset,
crtc->scrn->virtualY);
- OUTREG(AVIVO_CRTC1_PITCH + radeon_crtc->crtc_offset,
+ OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
crtc->scrn->displayWidth);
- /* avivo can only shift offset by 4 pixel in x if you program somethings
- * not multiple of 4 you gonna drive the GPU crazy and likely won't
- * be able to restore it without cold reboot (vbe post not enough)
- */
- x = x & ~3;
- OUTREG(AVIVO_CRTC1_OFFSET_END + radeon_crtc->crtc_offset,
- ((mode->HDisplay + x -128) << 16) | (mode->VDisplay + y - 128));
- OUTREG(AVIVO_CRTC1_OFFSET_START + radeon_crtc->crtc_offset, (x << 16) | y);
-
- OUTREG(AVIVO_CRTC1_SCAN_ENABLE + radeon_crtc->crtc_offset, 1);
-
+ OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
}
atombios_set_crtc_source(crtc);
diff --git a/src/radeon.h b/src/radeon.h
index 766c174..7c32693 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -198,6 +198,70 @@ typedef struct {
CARD16 rr4_offset;
} RADEONBIOSInitTable;
+struct avivo_pll_state {
+ CARD32 ref_div_src;
+ CARD32 ref_div;
+ CARD32 fb_div;
+ CARD32 post_div_src;
+ CARD32 post_div;
+ CARD32 ext_ppll_cntl;
+ CARD32 pll_cntl;
+ CARD32 int_ss_cntl;
+};
+
+struct avivo_crtc_state {
+ CARD32 pll_source;
+ CARD32 h_total;
+ CARD32 h_blank_start_end;
+ CARD32 h_sync_a;
+ CARD32 h_sync_a_cntl;
+ CARD32 h_sync_b;
+ CARD32 h_sync_b_cntl;
+ CARD32 v_total;
+ CARD32 v_blank_start_end;
+ CARD32 v_sync_a;
+ CARD32 v_sync_a_cntl;
+ CARD32 v_sync_b;
+ CARD32 v_sync_b_cntl;
+ CARD32 control;
+ CARD32 blank_control;
+ CARD32 interlace_control;
+ CARD32 stereo_control;
+};
+
+struct avivo_grph_state {
+ CARD32 enable;
+ CARD32 control;
+ CARD32 prim_surf_addr;
+ CARD32 sec_surf_addr;
+ CARD32 pitch;
+ CARD32 x_offset;
+ CARD32 y_offset;
+ CARD32 x_start;
+ CARD32 y_start;
+ CARD32 x_end;
+ CARD32 y_end;
+
+ CARD32 viewport_start;
+ CARD32 viewport_size;
+ CARD32 scl_enable;
+};
+
+struct avivo_dac_state {
+ CARD32 enable;
+ CARD32 source_select;
+ CARD32 force_output_cntl;
+ CARD32 powerdown;
+};
+
+struct avivo_dig_state {
+ CARD32 cntl;
+ CARD32 bit_depth_cntl;
+ CARD32 data_sync;
+ CARD32 transmitter_enable;
+ CARD32 transmitter_cntl;
+};
+
struct avivo_state
{
CARD32 hdp_fb_location;
@@ -208,96 +272,24 @@ struct avivo_state
CARD32 vga1_cntl;
CARD32 vga2_cntl;
- CARD32 pll1_post_div_cntl;
- CARD32 pll1_post_div;
- CARD32 pll1_post_div_mystery;
- CARD32 pll1_post_mul;
- CARD32 pll1_divider_cntl;
- CARD32 pll1_divider;
- CARD32 pll1_mystery0;
- CARD32 pll1_mystery1;
-
- CARD32 pll2_post_div_cntl;
- CARD32 pll2_post_div;
- CARD32 pll2_post_div_mystery;
- CARD32 pll2_post_mul;
- CARD32 pll2_divider_cntl;
- CARD32 pll2_divider;
- CARD32 pll2_mystery0;
- CARD32 pll2_mystery1;
-
- CARD32 crtc_pll_source;
- CARD32 crtc1_h_total;
- CARD32 crtc1_h_blank;
- CARD32 crtc1_h_sync_wid;
- CARD32 crtc1_h_sync_pol;
- CARD32 crtc1_v_total;
- CARD32 crtc1_v_blank;
- CARD32 crtc1_v_sync_wid;
- CARD32 crtc1_v_sync_pol;
- CARD32 crtc1_cntl;
- CARD32 crtc1_blank_status;
- CARD32 crtc1_stereo_status;
- CARD32 crtc1_scan_enable;
- CARD32 crtc1_fb_format;
- CARD32 crtc1_fb_location;
- CARD32 crtc1_fb_end;
- CARD32 crtc1_pitch;
- CARD32 crtc1_x_length;
- CARD32 crtc1_y_length;
- CARD32 crtc1_fb_height;
- CARD32 crtc1_offset_start;
- CARD32 crtc1_offset_end;
- CARD32 crtc1_expn_size;
- CARD32 crtc1_expn_cntl;
- CARD32 crtc1_6594;
- CARD32 crtc1_659c;
- CARD32 crtc1_65a4;
- CARD32 crtc1_65a8;
- CARD32 crtc1_65ac;
- CARD32 crtc1_65b0;
- CARD32 crtc1_65b8;
- CARD32 crtc1_65bc;
- CARD32 crtc1_65c0;
- CARD32 crtc1_65c8;
-
- CARD32 crtc2_h_total;
- CARD32 crtc2_h_blank;
- CARD32 crtc2_h_sync_wid;
- CARD32 crtc2_h_sync_pol;
- CARD32 crtc2_v_total;
- CARD32 crtc2_v_blank;
- CARD32 crtc2_v_sync_wid;
- CARD32 crtc2_v_sync_pol;
- CARD32 crtc2_cntl;
- CARD32 crtc2_blank_status;
- CARD32 crtc2_scan_enable;
- CARD32 crtc2_fb_format;
- CARD32 crtc2_fb_location;
- CARD32 crtc2_fb_end;
- CARD32 crtc2_pitch;
- CARD32 crtc2_x_length;
- CARD32 crtc2_y_length;
-
- CARD32 dac1_cntl;
- CARD32 dac1_force_output_cntl;
- CARD32 dac1_powerdown;
-
- CARD32 tmds1_cntl;
- CARD32 tmds1_bit_depth_cntl;
- CARD32 tmds1_data_sync;
- CARD32 tmds1_transmitter_enable;
- CARD32 tmds1_transmitter_cntl;
-
- CARD32 dac2_cntl;
- CARD32 dac2_force_output_cntl;
- CARD32 dac2_powerdown;
-
- CARD32 tmds2_cntl;
- CARD32 tmds2_bit_depth_cntl;
- CARD32 tmds2_data_sync;
- CARD32 tmds2_transmitter_enable;
- CARD32 tmds2_transmitter_cntl;
+ CARD32 crtc_master_en;
+ CARD32 crtc_tv_control;
+
+ struct avivo_pll_state pll1;
+ struct avivo_pll_state pll2;
+
+ struct avivo_crtc_state crtc1;
+ struct avivo_crtc_state crtc2;
+
+ struct avivo_grph_state grph1;
+ struct avivo_grph_state grph2;
+
+ struct avivo_dac_state daca;
+ struct avivo_dac_state dacb;
+
+ struct avivo_dig_state tmds1;
+ struct avivo_dig_state tmds2;
+
};
typedef struct {
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 64f8037..9192a9e 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -1280,7 +1280,8 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn)
pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
pRADEONEnt->Controller[1]->crtc_id = 1;
- pRADEONEnt->Controller[1]->crtc_offset = AVIVO_CRTC2_H_TOTAL - AVIVO_CRTC1_H_TOTAL;
+ pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
+
return TRUE;
}
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index d46c098..948ecd4 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -96,15 +96,15 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable)
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 0);
if (enable) {
- OUTREG(AVIVO_CURSOR1_LOCATION + radeon_crtc->crtc_offset,
+ OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
info->fbLocation + info->cursor_offset);
- OUTREG(AVIVO_CURSOR1_SIZE + radeon_crtc->crtc_offset,
+ OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
((info->cursor_width -1) << 16) | (info->cursor_height-1));
- OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset,
- AVIVO_CURSOR_EN | (AVIVO_CURSOR_FORMAT_ARGB << AVIVO_CURSOR_FORMAT_SHIFT));
+ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
+ AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
}
}
@@ -124,9 +124,9 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc)
RADEON_SYNC(info, pScrn);
if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset,
- INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset)
- | AVIVO_CURSOR_EN);
+ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
+ INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset)
+ | AVIVO_D1CURSOR_EN);
avivo_setup_cursor(crtc, TRUE);
} else {
if (crtc_id == 0)
@@ -158,9 +158,9 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
RADEON_SYNC(info, pScrn);
if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_CURSOR1_CNTL+ radeon_crtc->crtc_offset,
- INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset)
- & ~(AVIVO_CURSOR_EN));
+ OUTREG(AVIVO_D1CUR_CONTROL+ radeon_crtc->crtc_offset,
+ INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset)
+ & ~(AVIVO_D1CURSOR_EN));
avivo_setup_cursor(crtc, FALSE);
} else {
if (crtc_id == 0)
@@ -202,7 +202,7 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
if (y < 0)
y = 0;
- OUTREG(AVIVO_CURSOR1_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
+ OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
radeon_crtc->cursor_x = x;
radeon_crtc->cursor_y = y;
} else {
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 02e38bd..cabc539 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1273,13 +1273,11 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
if (IS_AVIVO_VARIANT) {
if (info->ChipFamily == CHIP_FAMILY_RV515) {
- info->mc_fb_location = INMC(pScrn, MC01);
- ErrorF("mc fb is %08X\n", info->mc_fb_location);
- info->mc_agp_location = INMC(pScrn, MC02);
+ info->mc_fb_location = INMC(pScrn, RV515_MC_FB_LOCATION);
+ info->mc_agp_location = INMC(pScrn, RV515_MC_AGP_LOCATION);
} else {
- info->mc_fb_location = INMC(pScrn, AVIVO_MC_MEMORY_MAP);
- ErrorF("mc fb is %08X\n", info->mc_fb_location);
- info->mc_agp_location = INMC(pScrn, MC05);
+ info->mc_fb_location = INMC(pScrn, R520_MC_FB_LOCATION);
+ info->mc_agp_location = INMC(pScrn, R520_MC_AGP_LOCATION);
}
} else {
/* Default to existing values */
@@ -3922,17 +3920,16 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
if (IS_AVIVO_VARIANT) {
CARD32 mc_fb_loc, mc_agp_loc;
if (info->ChipFamily == CHIP_FAMILY_RV515) {
- mc_fb_loc = INMC(pScrn, MC01);
- ErrorF("%s: save mc is %08x\n", __func__, mc_fb_loc);
- mc_agp_loc = INMC(pScrn, MC02);
+ mc_fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION);
+ mc_agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION);
} else {
- mc_fb_loc = INMC(pScrn, AVIVO_MC_MEMORY_MAP);
- mc_agp_loc = INMC(pScrn, MC05);
+ mc_fb_loc = INMC(pScrn, R520_MC_FB_LOCATION);
+ mc_agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION);
}
#if 1
/* disable VGA CTRL */
- OUTREG(AVIVO_D1VGA_CTRL, INREG(AVIVO_D1VGA_CTRL) & ~AVIVO_DVGA_MODE_ENABLE);
- OUTREG(AVIVO_D2VGA_CTRL, INREG(AVIVO_D2VGA_CTRL) & ~AVIVO_DVGA_MODE_ENABLE);
+ OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+ OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
#endif
if (mc_fb_loc != info->mc_fb_location ||
mc_agp_loc != info->mc_agp_location) {
@@ -3941,14 +3938,13 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
RADEONWaitForIdleMMIO(pScrn);
/* Stop display & memory access */
- tmp = INREG(AVIVO_CRTC1_CNTL);
- OUTREG(AVIVO_CRTC1_CNTL, tmp & ~AVIVO_CRTC_EN);
+ tmp = INREG(AVIVO_D1CRTC_CONTROL);
+ OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
- tmp = INREG(AVIVO_CRTC2_CNTL);
- tmp &= ~AVIVO_CRTC_EN;
- OUTREG(AVIVO_CRTC2_CNTL, tmp);
+ tmp = INREG(AVIVO_D2CRTC_CONTROL);
+ OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
- tmp = INREG(AVIVO_CRTC2_CNTL);
+ tmp = INREG(AVIVO_D2CRTC_CONTROL);
usleep(10000);
timeout = 0;
@@ -3969,13 +3965,13 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
}
if (info->ChipFamily == CHIP_FAMILY_RV515) {
- OUTMC(pScrn, MC01, info->mc_fb_location);
- OUTMC(pScrn, MC02, 0x003f0000);
- (void)INMC(pScrn, MC02);
+ OUTMC(pScrn, RV515_MC_FB_LOCATION, info->mc_fb_location);
+ OUTMC(pScrn, RV515_MC_AGP_LOCATION, 0x003f0000);
+ (void)INMC(pScrn, RV515_MC_AGP_LOCATION);
} else {
- OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, info->mc_fb_location);
- OUTMC(pScrn, MC05, 0x003f0000);
- (void)INMC(pScrn, AVIVO_MC_MEMORY_MAP);
+ OUTMC(pScrn, R520_MC_FB_LOCATION, info->mc_fb_location);
+ OUTMC(pScrn, R520_MC_AGP_LOCATION, 0x003f0000);
+ (void)INMC(pScrn, R520_MC_FB_LOCATION);
}
OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
@@ -4132,11 +4128,11 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
if (IS_AVIVO_VARIANT) {
if (info->ChipFamily == CHIP_FAMILY_RV515) {
- fb = INMC(pScrn, MC01);
- agp = INMC(pScrn, MC02);
+ fb = INMC(pScrn, RV515_MC_FB_LOCATION);
+ agp = INMC(pScrn, RV515_MC_AGP_LOCATION);
} else {
- fb = INMC(pScrn, AVIVO_MC_MEMORY_MAP);
- agp = INMC(pScrn, MC05);
+ fb = INMC(pScrn, R520_MC_FB_LOCATION);
+ agp = INMC(pScrn, RV515_MC_AGP_LOCATION);
}
fb_loc_changed = (fb != info->mc_fb_location);
@@ -5524,101 +5520,129 @@ void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
unsigned char *RADEONMMIO = info->MMIO;
struct avivo_state *state = &save->avivo;
- state->mc_memory_map = INMC(pScrn, AVIVO_MC_MEMORY_MAP);
- state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE);
- state->vga_fb_start = INREG(AVIVO_VGA_FB_START);
- state->vga1_cntl = INREG(AVIVO_VGA1_CONTROL);
- state->vga2_cntl = INREG(AVIVO_VGA2_CONTROL);
-
- state->pll1_post_div_cntl = INREG(AVIVO_PLL1_POST_DIV_CNTL);
- state->pll1_post_div = INREG(AVIVO_PLL1_POST_DIV);
- state->pll1_post_div_mystery = INREG(AVIVO_PLL1_POST_DIV_MYSTERY);
- state->pll1_post_mul = INREG(AVIVO_PLL1_POST_MUL);
- state->pll1_divider_cntl = INREG(AVIVO_PLL1_DIVIDER_CNTL);
- state->pll1_divider = INREG(AVIVO_PLL1_DIVIDER);
- state->pll1_mystery0 = INREG(AVIVO_PLL1_MYSTERY0);
- state->pll1_mystery1 = INREG(AVIVO_PLL1_MYSTERY1);
- state->pll2_post_div_cntl = INREG(AVIVO_PLL2_POST_DIV_CNTL);
- state->pll2_post_div = INREG(AVIVO_PLL2_POST_DIV);
- state->pll2_post_div_mystery = INREG(AVIVO_PLL2_POST_DIV_MYSTERY);
- state->pll2_post_mul = INREG(AVIVO_PLL2_POST_MUL);
- state->pll2_divider_cntl = INREG(AVIVO_PLL2_DIVIDER_CNTL);
- state->pll2_divider = INREG(AVIVO_PLL2_DIVIDER);
- state->pll2_mystery0 = INREG(AVIVO_PLL2_MYSTERY0);
- state->pll2_mystery1 = INREG(AVIVO_PLL2_MYSTERY1);
- state->crtc_pll_source = INREG(AVIVO_CRTC_PLL_SOURCE);
-
- state->crtc1_h_total = INREG(AVIVO_CRTC1_H_TOTAL);
- state->crtc1_h_blank = INREG(AVIVO_CRTC1_H_BLANK);
- state->crtc1_h_sync_wid = INREG(AVIVO_CRTC1_H_SYNC_WID);
- state->crtc1_h_sync_pol = INREG(AVIVO_CRTC1_H_SYNC_POL);
- state->crtc1_v_total = INREG(AVIVO_CRTC1_V_TOTAL);
- state->crtc1_v_blank = INREG(AVIVO_CRTC1_V_BLANK);
- state->crtc1_v_sync_wid = INREG(AVIVO_CRTC1_V_SYNC_WID);
- state->crtc1_v_sync_pol = INREG(AVIVO_CRTC1_V_SYNC_POL);
- state->crtc1_cntl = INREG(AVIVO_CRTC1_CNTL);
- state->crtc1_blank_status = INREG(AVIVO_CRTC1_BLANK_STATUS);
- state->crtc1_stereo_status = INREG(AVIVO_CRTC1_STEREO_STATUS);
- state->crtc1_scan_enable = INREG(AVIVO_CRTC1_SCAN_ENABLE);
- state->crtc1_fb_format = INREG(AVIVO_CRTC1_FB_FORMAT);
- state->crtc1_fb_location = INREG(AVIVO_CRTC1_FB_LOCATION);
- state->crtc1_fb_end = INREG(AVIVO_CRTC1_FB_END);
- state->crtc1_pitch = INREG(AVIVO_CRTC1_PITCH);
- state->crtc1_x_length = INREG(AVIVO_CRTC1_X_LENGTH);
- state->crtc1_y_length = INREG(AVIVO_CRTC1_Y_LENGTH);
- state->crtc1_fb_height = INREG(AVIVO_CRTC1_FB_HEIGHT);
- state->crtc1_offset_start = INREG(AVIVO_CRTC1_OFFSET_START);
- state->crtc1_offset_end = INREG(AVIVO_CRTC1_OFFSET_END);
- state->crtc1_expn_size = INREG(AVIVO_CRTC1_EXPANSION_SOURCE);
- state->crtc1_expn_cntl = INREG(AVIVO_CRTC1_EXPANSION_CNTL);
- state->crtc1_6594 = INREG(AVIVO_CRTC1_6594);
- state->crtc1_659c = INREG(AVIVO_CRTC1_659C);
- state->crtc1_65a4 = INREG(AVIVO_CRTC1_65A4);
- state->crtc1_65a8 = INREG(AVIVO_CRTC1_65A8);
- state->crtc1_65ac = INREG(AVIVO_CRTC1_65AC);
- state->crtc1_65b0 = INREG(AVIVO_CRTC1_65B0);
- state->crtc1_65b8 = INREG(AVIVO_CRTC1_65B8);
- state->crtc1_65bc = INREG(AVIVO_CRTC1_65BC);
- state->crtc1_65c0 = INREG(AVIVO_CRTC1_65C0);
- state->crtc1_65c8 = INREG(AVIVO_CRTC1_65C8);
-
- state->crtc2_h_total = INREG(AVIVO_CRTC2_H_TOTAL);
- state->crtc2_h_blank = INREG(AVIVO_CRTC2_H_BLANK);
- state->crtc2_h_sync_wid = INREG(AVIVO_CRTC2_H_SYNC_WID);
- state->crtc2_h_sync_pol = INREG(AVIVO_CRTC2_H_SYNC_POL);
- state->crtc2_v_total = INREG(AVIVO_CRTC2_V_TOTAL);
- state->crtc2_v_blank = INREG(AVIVO_CRTC2_V_BLANK);
- state->crtc2_v_sync_wid = INREG(AVIVO_CRTC2_V_SYNC_WID);
- state->crtc2_v_sync_pol = INREG(AVIVO_CRTC2_V_SYNC_POL);
- state->crtc2_cntl = INREG(AVIVO_CRTC2_CNTL);
- state->crtc2_blank_status = INREG(AVIVO_CRTC2_BLANK_STATUS);
- state->crtc2_scan_enable = INREG(AVIVO_CRTC2_SCAN_ENABLE);
- state->crtc2_fb_format = INREG(AVIVO_CRTC2_FB_FORMAT);
- state->crtc2_fb_location = INREG(AVIVO_CRTC2_FB_LOCATION);
- state->crtc2_fb_end = INREG(AVIVO_CRTC2_FB_END);
- state->crtc2_pitch = INREG(AVIVO_CRTC2_PITCH);
- state->crtc2_x_length = INREG(AVIVO_CRTC2_X_LENGTH);
- state->crtc2_y_length = INREG(AVIVO_CRTC2_Y_LENGTH);
-
- state->dac1_cntl = INREG(AVIVO_DACA_CNTL);
- state->dac1_force_output_cntl = INREG(AVIVO_DACA_FORCE_OUTPUT_CNTL);
- state->dac1_powerdown = INREG(AVIVO_DACA_POWERDOWN);
-
- state->tmds1_cntl = INREG(AVIVO_TMDSA_CNTL);
- state->tmds1_bit_depth_cntl = INREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL);
- state->tmds1_data_sync = INREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION);
- state->tmds1_transmitter_enable = INREG(AVIVO_TMDSA_TRANSMITTER_ENABLE);
- state->tmds1_transmitter_cntl = INREG(AVIVO_TMDSA_TRANSMITTER_CONTROL);
-
- state->dac2_cntl = INREG(AVIVO_DACB_CNTL);
- state->dac2_force_output_cntl = INREG(AVIVO_DACB_FORCE_OUTPUT_CNTL);
- state->dac2_powerdown = INREG(AVIVO_DACB_POWERDOWN);
-
- state->tmds2_cntl = INREG(AVIVO_LVTMA_CNTL);
- state->tmds2_bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
- state->tmds2_data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION);
- state->tmds2_transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE);
- state->tmds2_transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL);
+ // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE);
+ // state->vga_fb_start = INREG(AVIVO_VGA_FB_START);
+ state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL);
+ state->vga2_cntl = INREG(AVIVO_D1VGA_CONTROL);
+
+ state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN);
+ state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL);
+
+ state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
+ state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV);
+ state->pll1.fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV);
+ state->pll1.post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC);
+ state->pll1.post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV);
+ state->pll1.ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL);
+ state->pll1.pll_cntl = INREG(AVIVO_P1PLL_CNTL);
+ state->pll1.int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+
+ state->pll2.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
+ state->pll2.ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV);
+ state->pll2.fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV);
+ state->pll2.post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC);
+ state->pll2.post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV);
+ state->pll2.ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL);
+ state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL);
+ state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+
+ state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL);
+
+ state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL);
+ state->crtc1.h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END);
+ state->crtc1.h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A);
+ state->crtc1.h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL);
+ state->crtc1.h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B);
+ state->crtc1.h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL);
+
+ state->crtc1.v_total = INREG(AVIVO_D1CRTC_V_TOTAL);
+ state->crtc1.v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END);
+ state->crtc1.v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A);
+ state->crtc1.v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL);
+ state->crtc1.v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B);
+ state->crtc1.v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL);
+
+ state->crtc1.control = INREG(AVIVO_D1CRTC_CONTROL);
+ state->crtc1.blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL);
+ state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL);
+ state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL);
+
+ state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE);
+ state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL);
+ state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL);
+ state->grph1.prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS);
+ state->grph1.sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS);
+ state->grph1.pitch = INREG(AVIVO_D1GRPH_PITCH);
+ state->grph1.x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X);
+ state->grph1.y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y);
+ state->grph1.x_start = INREG(AVIVO_D1GRPH_X_START);
+ state->grph1.y_start = INREG(AVIVO_D1GRPH_Y_START);
+ state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END);
+ state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END);
+
+ state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
+ state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
+ state->grph1.scl_enable = INREG(AVIVO_D1SCL_SCALER_ENABLE);
+
+ state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL);
+
+ state->crtc2.h_total = INREG(AVIVO_D2CRTC_H_TOTAL);
+ state->crtc2.h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END);
+ state->crtc2.h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A);
+ state->crtc2.h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL);
+ state->crtc2.h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B);
+ state->crtc2.h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL);
+
+ state->crtc2.v_total = INREG(AVIVO_D2CRTC_V_TOTAL);
+ state->crtc2.v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END);
+ state->crtc2.v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A);
+ state->crtc2.v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL);
+ state->crtc2.v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B);
+ state->crtc2.v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL);
+
+ state->crtc2.control = INREG(AVIVO_D2CRTC_CONTROL);
+ state->crtc2.blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL);
+ state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL);
+ state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL);
+
+ state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE);
+ state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL);
+ state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL);
+ state->grph2.prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS);
+ state->grph2.sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS);
+ state->grph2.pitch = INREG(AVIVO_D2GRPH_PITCH);
+ state->grph2.x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X);
+ state->grph2.y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y);
+ state->grph2.x_start = INREG(AVIVO_D2GRPH_X_START);
+ state->grph2.y_start = INREG(AVIVO_D2GRPH_Y_START);
+ state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END);
+ state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END);
+
+ state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
+ state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
+ state->grph2.scl_enable = INREG(AVIVO_D2SCL_SCALER_ENABLE);
+
+ state->daca.enable = INREG(AVIVO_DACA_ENABLE);
+ state->daca.source_select = INREG(AVIVO_DACA_SOURCE_SELECT);
+ state->daca.force_output_cntl = INREG(AVIVO_DACA_FORCE_OUTPUT_CNTL);
+ state->daca.powerdown = INREG(AVIVO_DACA_POWERDOWN);
+
+ state->dacb.enable = INREG(AVIVO_DACB_ENABLE);
+ state->dacb.source_select = INREG(AVIVO_DACB_SOURCE_SELECT);
+ state->dacb.force_output_cntl = INREG(AVIVO_DACB_FORCE_OUTPUT_CNTL);
+ state->dacb.powerdown = INREG(AVIVO_DACB_POWERDOWN);
+
+ state->tmds1.cntl = INREG(AVIVO_TMDSA_CNTL);
+ state->tmds1.bit_depth_cntl = INREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL);
+ state->tmds1.data_sync = INREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION);
+ state->tmds1.transmitter_enable = INREG(AVIVO_TMDSA_TRANSMITTER_ENABLE);
+ state->tmds1.transmitter_cntl = INREG(AVIVO_TMDSA_TRANSMITTER_CONTROL);
+
+ state->tmds2.cntl = INREG(AVIVO_LVTMA_CNTL);
+ state->tmds2.bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
+ state->tmds2.data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION);
+ state->tmds2.transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE);
+ state->tmds2.transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL);
}
@@ -5628,36 +5652,45 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
unsigned char *RADEONMMIO = info->MMIO;
struct avivo_state *state = &restore->avivo;
- OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map);
- OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base);
- OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start);
- OUTREG(AVIVO_VGA1_CONTROL, state->vga1_cntl);
- OUTREG(AVIVO_VGA2_CONTROL, state->vga2_cntl);
-
- OUTREG(AVIVO_PLL1_POST_DIV_CNTL, state->pll1_post_div_cntl);
- OUTREG(AVIVO_PLL1_POST_DIV, state->pll1_post_div);
- OUTREG(AVIVO_PLL1_POST_DIV_MYSTERY, state->pll1_post_div_mystery);
- OUTREG(AVIVO_PLL1_POST_MUL, state->pll1_post_mul);
- OUTREG(AVIVO_PLL1_DIVIDER_CNTL, state->pll1_divider_cntl);
- OUTREG(AVIVO_PLL1_DIVIDER, state->pll1_divider);
- OUTREG(AVIVO_PLL1_MYSTERY0, state->pll1_mystery0);
- OUTREG(AVIVO_PLL1_MYSTERY1, state->pll1_mystery1);
- OUTREG(AVIVO_PLL2_POST_DIV_CNTL, state->pll2_post_div_cntl);
- OUTREG(AVIVO_PLL2_POST_DIV, state->pll2_post_div);
- OUTREG(AVIVO_PLL2_POST_DIV_MYSTERY, state->pll2_post_div_mystery);
- OUTREG(AVIVO_PLL2_POST_MUL, state->pll2_post_mul);
- OUTREG(AVIVO_PLL2_DIVIDER_CNTL, state->pll2_divider_cntl);
- OUTREG(AVIVO_PLL2_DIVIDER, state->pll2_divider);
- OUTREG(AVIVO_PLL2_MYSTERY0, state->pll2_mystery0);
- OUTREG(AVIVO_PLL2_MYSTERY1, state->pll2_mystery1);
- OUTREG(AVIVO_CRTC_PLL_SOURCE, state->crtc_pll_source);
-
- OUTREG(AVIVO_CRTC1_H_TOTAL, state->crtc1_h_total);
- OUTREG(AVIVO_CRTC1_H_BLANK, state->crtc1_h_blank);
- OUTREG(AVIVO_CRTC1_H_SYNC_WID, state->crtc1_h_sync_wid);
- OUTREG(AVIVO_CRTC1_H_SYNC_POL, state->crtc1_h_sync_pol);
- OUTREG(AVIVO_CRTC1_V_TOTAL, state->crtc1_v_total);
- OUTREG(AVIVO_CRTC1_V_BLANK, state->crtc1_v_blank);
+ // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map);
+ // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base);
+ // OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start);
+
+ OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
+ OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
+
+ OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en);
+ OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control);
+
+ OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src);
+ OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div);
+ OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div);
+ OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll1.post_div_src);
+ OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll1.post_div);
+ OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll1.ext_ppll_cntl);
+ OUTREG(AVIVO_P1PLL_CNTL, state->pll1.pll_cntl);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll1.int_ss_cntl);
+
+ OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll2.ref_div_src);
+ OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll2.ref_div);
+ OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll2.fb_div);
+ OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll2.post_div_src);
+ OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll2.post_div);
+ OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll2.ext_ppll_cntl);
+ OUTREG(AVIVO_P2PLL_CNTL, state->pll2.pll_cntl);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl);
+
+ OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source);
+
+ OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total);
+ OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end);
+ OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a);
+ OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc1.h_sync_a_cntl);
+ OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc1.h_sync_b);
+ OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc1.h_sync_b_cntl);
+
+ OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total);
+ OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end);
/*
* Weird we shouldn't restore sync width when going back to text
* mode, it must not be a 0 value, i guess a deeper look in cold
@@ -5665,71 +5698,100 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
* truely needed to do.
*/
#if 0
- OUTREG(AVIVO_CRTC1_V_SYNC_WID, state->crtc1_v_sync_wid);
+ OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1_v_sync_a);
#endif
- OUTREG(AVIVO_CRTC1_V_SYNC_POL, state->crtc1_v_sync_pol);
- OUTREG(AVIVO_CRTC1_CNTL, state->crtc1_cntl);
- OUTREG(AVIVO_CRTC1_SCAN_ENABLE, state->crtc1_scan_enable);
- OUTREG(AVIVO_CRTC1_FB_FORMAT, state->crtc1_fb_format);
- OUTREG(AVIVO_CRTC1_FB_LOCATION, state->crtc1_fb_location);
- OUTREG(AVIVO_CRTC1_FB_END, state->crtc1_fb_end);
- OUTREG(AVIVO_CRTC1_PITCH, state->crtc1_pitch);
- OUTREG(AVIVO_CRTC1_X_LENGTH, state->crtc1_x_length);
- OUTREG(AVIVO_CRTC1_Y_LENGTH, state->crtc1_y_length);
- OUTREG(AVIVO_CRTC1_FB_HEIGHT, state->crtc1_fb_height);
- OUTREG(AVIVO_CRTC1_OFFSET_START, state->crtc1_offset_start);
- OUTREG(AVIVO_CRTC1_OFFSET_END, state->crtc1_offset_end);
- OUTREG(AVIVO_CRTC1_EXPANSION_SOURCE, state->crtc1_expn_size);
- OUTREG(AVIVO_CRTC1_EXPANSION_CNTL, state->crtc1_expn_cntl);
- OUTREG(AVIVO_CRTC1_6594, state->crtc1_6594);
- OUTREG(AVIVO_CRTC1_659C, state->crtc1_659c);
- OUTREG(AVIVO_CRTC1_65A4, state->crtc1_65a4);
- OUTREG(AVIVO_CRTC1_65A8, state->crtc1_65a8);
- OUTREG(AVIVO_CRTC1_65AC, state->crtc1_65ac);
- OUTREG(AVIVO_CRTC1_65B0, state->crtc1_65b0);
- OUTREG(AVIVO_CRTC1_65B8, state->crtc1_65b8);
- OUTREG(AVIVO_CRTC1_65BC, state->crtc1_65bc);
- OUTREG(AVIVO_CRTC1_65C0, state->crtc1_65c0);
- OUTREG(AVIVO_CRTC1_65C8, state->crtc1_65c8);
- OUTREG(AVIVO_CRTC2_H_TOTAL, state->crtc2_h_total);
- OUTREG(AVIVO_CRTC2_H_BLANK, state->crtc2_h_blank);
+ OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl);
+ OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b);
+ OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl);
+
+ OUTREG(AVIVO_D1CRTC_CONTROL, state->crtc1.control);
+ OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control);
+ OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control);
+ OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control);
+
+ OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable);
+ OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control);
+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr);
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr);
+ OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset);
+ OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start);
+ OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start);
+ OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end);
+ OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end);
+
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size);
+ OUTREG(AVIVO_D1SCL_SCALER_ENABLE, state->grph1.scl_enable);
+
+ OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source);
+
+ OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total);
+ OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end);
+ OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc2.h_sync_a);
+ OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc2.h_sync_a_cntl);
+ OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc2.h_sync_b);
+ OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc2.h_sync_b_cntl);
+
+ OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total);
+ OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end);
+ /*
+ * Weird we shouldn't restore sync width when going back to text
+ * mode, it must not be a 0 value, i guess a deeper look in cold
+ * text mode register value would help to understand what is
+ * truely needed to do.
+ */
#if 0
- OUTREG(AVIVO_CRTC2_H_SYNC_WID, state->crtc2_h_sync_wid);
+ OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2_v_sync_a);
#endif
- OUTREG(AVIVO_CRTC2_H_SYNC_POL, state->crtc2_h_sync_pol);
- OUTREG(AVIVO_CRTC2_V_TOTAL, state->crtc2_v_total);
- OUTREG(AVIVO_CRTC2_V_BLANK, state->crtc2_v_blank);
- OUTREG(AVIVO_CRTC2_V_SYNC_WID, state->crtc2_v_sync_wid);
- OUTREG(AVIVO_CRTC2_V_SYNC_POL, state->crtc2_v_sync_pol);
- OUTREG(AVIVO_CRTC2_CNTL, state->crtc2_cntl);
- OUTREG(AVIVO_CRTC2_BLANK_STATUS, state->crtc2_blank_status);
- OUTREG(AVIVO_CRTC2_SCAN_ENABLE, state->crtc2_scan_enable);
- OUTREG(AVIVO_CRTC2_FB_FORMAT, state->crtc2_fb_format);
- OUTREG(AVIVO_CRTC2_FB_LOCATION, state->crtc2_fb_location);
- OUTREG(AVIVO_CRTC2_FB_END, state->crtc2_fb_end);
- OUTREG(AVIVO_CRTC2_PITCH, state->crtc2_pitch);
- OUTREG(AVIVO_CRTC2_X_LENGTH, state->crtc2_x_length);
- OUTREG(AVIVO_CRTC2_Y_LENGTH, state->crtc2_y_length);
-
- OUTREG(AVIVO_DACA_CNTL, state->dac1_cntl);
- OUTREG(AVIVO_DACA_FORCE_OUTPUT_CNTL, state->dac1_force_output_cntl);
- OUTREG(AVIVO_DACA_POWERDOWN, state->dac1_powerdown);
-
- OUTREG(AVIVO_TMDSA_CNTL, state->tmds1_cntl);
- OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, state->tmds1_bit_depth_cntl);
- OUTREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION, state->tmds1_data_sync);
- OUTREG(AVIVO_TMDSA_TRANSMITTER_ENABLE, state->tmds1_transmitter_enable);
- OUTREG(AVIVO_TMDSA_TRANSMITTER_CONTROL, state->tmds1_transmitter_cntl);
-
- OUTREG(AVIVO_DACB_CNTL, state->dac2_cntl);
- OUTREG(AVIVO_DACB_FORCE_OUTPUT_CNTL, state->dac2_force_output_cntl);
- OUTREG(AVIVO_DACB_POWERDOWN, state->dac2_powerdown);
-
- OUTREG(AVIVO_LVTMA_CNTL, state->tmds2_cntl);
- OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2_bit_depth_cntl);
- OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2_data_sync);
- OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2_transmitter_enable);
- OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2_transmitter_cntl);
+ OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl);
+ OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b);
+ OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl);
+
+ OUTREG(AVIVO_D2CRTC_CONTROL, state->crtc2.control);
+ OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control);
+ OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control);
+ OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control);
+
+ OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable);
+ OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control);
+ OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr);
+ OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr);
+ OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch);
+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset);
+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset);
+ OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start);
+ OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start);
+ OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end);
+ OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end);
+
+ OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start);
+ OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size);
+ OUTREG(AVIVO_D2SCL_SCALER_ENABLE, state->grph2.scl_enable);
+
+
+ OUTREG(AVIVO_DACA_ENABLE, state->daca.enable);
+ OUTREG(AVIVO_DACA_SOURCE_SELECT, state->daca.source_select);
+ OUTREG(AVIVO_DACA_FORCE_OUTPUT_CNTL, state->daca.force_output_cntl);
+ OUTREG(AVIVO_DACA_POWERDOWN, state->daca.powerdown);
+
+ OUTREG(AVIVO_TMDSA_CNTL, state->tmds1.cntl);
+ OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, state->tmds1.bit_depth_cntl);
+ OUTREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION, state->tmds1.data_sync);
+ OUTREG(AVIVO_TMDSA_TRANSMITTER_ENABLE, state->tmds1.transmitter_enable);
+ OUTREG(AVIVO_TMDSA_TRANSMITTER_CONTROL, state->tmds1.transmitter_cntl);
+
+ OUTREG(AVIVO_DACB_ENABLE, state->dacb.enable);
+ OUTREG(AVIVO_DACB_SOURCE_SELECT, state->dacb.source_select);
+ OUTREG(AVIVO_DACB_FORCE_OUTPUT_CNTL, state->dacb.force_output_cntl);
+ OUTREG(AVIVO_DACB_POWERDOWN, state->dacb.powerdown);
+
+ OUTREG(AVIVO_LVTMA_CNTL, state->tmds2.cntl);
+ OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2.bit_depth_cntl);
+ OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2.data_sync);
+ OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
+ OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
}
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 1122f13..e299481 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3271,6 +3271,422 @@
#define RADEON_RS480_UNK_e38 0xe38
#define RADEON_RS480_UNK_e3c 0xe3c
-#include "avivo_reg.h"
+
+#define AVIVO_MC_INDEX 0x0070
+#define R520_MC_STATUS 0x00
+#define R520_MC_STATUS_IDLE (1<<1)
+#define RV515_MC_STATUS 0x08
+#define RV515_MC_STATUS_IDLE (1<<4)
+#define AVIVO_MC_DATA 0x0074
+
+#define RV515_MC_FB_LOCATION 0x1
+#define RV515_MC_AGP_LOCATION 0x2
+#define R520_MC_FB_LOCATION 0x4
+#define R520_MC_AGP_LOCATION 0x5
+
+#define AVIVO_HDP_FB_LOCATION 0x134
+
+#define AVIVO_D1VGA_CONTROL 0x0330
+# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
+# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
+# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
+# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
+# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
+# define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
+#define AVIVO_D2VGA_CONTROL 0x0338
+
+#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
+#define AVIVO_EXT1_PPLL_REF_DIV 0x404
+#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
+#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
+
+#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
+#define AVIVO_EXT2_PPLL_REF_DIV 0x414
+#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
+#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
+
+#define AVIVO_EXT1_PPLL_FB_DIV 0x430
+#define AVIVO_EXT2_PPLL_FB_DIV 0x434
+
+#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
+#define AVIVO_EXT1_PPLL_POST_DIV 0x43c
+
+#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
+#define AVIVO_EXT2_PPLL_POST_DIV 0x444
+
+#define AVIVO_EXT1_PPLL_CNTL 0x448
+#define AVIVO_EXT2_PPLL_CNTL 0x44c
+
+#define AVIVO_P1PLL_CNTL 0x450
+#define AVIVO_P2PLL_CNTL 0x454
+#define AVIVO_P1PLL_INT_SS_CNTL 0x458
+#define AVIVO_P2PLL_INT_SS_CNTL 0x45c
+#define AVIVO_P1PLL_TMDSA_CNTL 0x460
+#define AVIVO_P2PLL_LVTMA_CNTL 0x464
+
+#define AVIVO_PCLK_CRTC1_CNTL 0x480
+#define AVIVO_PCLK_CRTC2_CNTL 0x484
+
+#define AVIVO_D1CRTC_H_TOTAL 0x6000
+#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
+#define AVIVO_D1CRTC_H_SYNC_A 0x6008
+#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
+#define AVIVO_D1CRTC_H_SYNC_B 0x6010
+#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
+
+#define AVIVO_D1CRTC_V_TOTAL 0x6020
+#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
+#define AVIVO_D1CRTC_V_SYNC_A 0x6028
+#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
+#define AVIVO_D1CRTC_V_SYNC_B 0x6030
+#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
+
+#define AVIVO_D1CRTC_CONTROL 0x6080
+# define AVIVO_CRTC_EN (1<<0)
+#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
+#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
+#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
+#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
+
+/* master controls */
+#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
+#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
+
+#define AVIVO_D1GRPH_ENABLE 0x6100
+#define AVIVO_D1GRPH_CONTROL 0x6104
+# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0)
+# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0)
+# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0)
+# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0)
+
+# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8)
+
+# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8)
+# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8)
+# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8)
+# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8)
+# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8)
+
+# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8)
+# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8)
+# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8)
+# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8)
+
+
+# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8)
+
+# define AVIVO_D1GRPH_SWAP_RB (1<<16)
+# define AVIVO_D1GRPH_TILED (1<<20)
+# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21)
+
+#define AVIVO_D1GRPH_LUT_SEL 0x6108
+#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
+#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
+#define AVIVO_D1GRPH_PITCH 0x6120
+#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
+#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
+#define AVIVO_D1GRPH_X_START 0x612c
+#define AVIVO_D1GRPH_Y_START 0x6130
+#define AVIVO_D1GRPH_X_END 0x6134
+#define AVIVO_D1GRPH_Y_END 0x6138
+#define AVIVO_D1GRPH_UPDATE 0x6144
+#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
+
+#define AVIVO_D1CUR_CONTROL 0x6400
+# define AVIVO_D1CURSOR_EN (1<<0)
+# define AVIVO_D1CURSOR_MODE_SHIFT 8
+# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8)
+# define AVIVO_D1CURSOR_MODE_24BPP (0x2)
+#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
+#define AVIVO_D1CUR_SIZE 0x6410
+#define AVIVO_D1CUR_POSITION 0x6414
+
+#define AVIVO_D1MODE_VIEWPORT_START 0x6580
+#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
+#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
+#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
+
+#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
+
+/* second crtc */
+#define AVIVO_D2CRTC_H_TOTAL 0x6800
+#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
+#define AVIVO_D2CRTC_H_SYNC_A 0x6808
+#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
+#define AVIVO_D2CRTC_H_SYNC_B 0x6810
+#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
+
+#define AVIVO_D2CRTC_V_TOTAL 0x6820
+#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
+#define AVIVO_D2CRTC_V_SYNC_A 0x6828
+#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
+#define AVIVO_D2CRTC_V_SYNC_B 0x6830
+#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
+
+#define AVIVO_D2CRTC_CONTROL 0x6880
+#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
+#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
+#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
+#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
+
+#define AVIVO_D2GRPH_ENABLE 0x6900
+#define AVIVO_D2GRPH_CONTROL 0x6904
+#define AVIVO_D2GRPH_LUT_SEL 0x6908
+#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
+#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
+#define AVIVO_D2GRPH_PITCH 0x6920
+#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
+#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
+#define AVIVO_D2GRPH_X_START 0x692c
+#define AVIVO_D2GRPH_Y_START 0x6930
+#define AVIVO_D2GRPH_X_END 0x6934
+#define AVIVO_D2GRPH_Y_END 0x6938
+#define AVIVO_D2GRPH_UPDATE 0x6944
+#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
+
+#define AVIVO_D2CUR_CONTROL 0x6c00
+#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
+#define AVIVO_D2CUR_SIZE 0x6c10
+#define AVIVO_D2CUR_POSITION 0x6c14
+
+#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
+#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
+#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
+#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
+
+#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
+
+#define AVIVO_DACA_ENABLE 0x7800
+# define AVIVO_DAC_ENABLE (1 << 0)
+#define AVIVO_DACA_SOURCE_SELECT 0x7804
+# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
+# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
+# define AVIVO_DAC_SOURCE_TV (2 << 0)
+
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
+#define AVIVO_DACA_POWERDOWN 0x7850
+# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
+# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
+# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
+# define AVIVO_DACA_POWERDOWN_RED (1 << 24)
+
+#define AVIVO_DACB_ENABLE 0x7a00
+#define AVIVO_DACB_SOURCE_SELECT 0x7a04
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
+#define AVIVO_DACB_POWERDOWN 0x7a50
+# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
+# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
+# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
+# define AVIVO_DACB_POWERDOWN_RED
+
+#define AVIVO_TMDSA_CNTL 0x7880
+# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
+# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
+# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
+# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
+# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
+# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
+# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
+#define AVIVO_TMDSA_CRTC_SOURCE 0x7884
+/* 78a8 appears to be some kind of (reasonably tolerant) clock?
+ * 78d0 definitely hits the transmitter, definitely clock. */
+/* MYSTERY1 This appears to control dithering? */
+#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
+#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
+#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
+# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
+# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
+#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
+
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
+
+#define AVIVO_LVTMA_CNTL 0x7a80
+# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
+# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
+# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
+# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
+# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
+# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
+# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
+#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
+#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
+
+
+
+#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
+
+#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
+# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
+# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
+#define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00
+
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
+
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
+
+#define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0
+# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
+# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
+# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
+# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
+# define AVIVO_LVTMA_SYNCEN (1 << 8)
+# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
+# define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
+# define AVIVO_LVTMA_DIGON (1 << 16)
+# define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
+# define AVIVO_LVTMA_DIGON_POL (1 << 18)
+# define AVIVO_LVTMA_BLON (1 << 24)
+# define AVIVO_LVTMA_BLON_OVRD (1 << 25)
+# define AVIVO_LVTMA_BLON_POL (1 << 26)
+
+#define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4
+# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
+# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
+# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
+# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
+# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
+# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
+
+#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
+# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
+# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
+# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
+
+#define AVIVO_GPIO_0 0x7e30
+#define AVIVO_GPIO_1 0x7e40
+#define AVIVO_GPIO_2 0x7e50
+#define AVIVO_GPIO_3 0x7e60
+
+#define R520_PCLK_HDCP_CNTL 0x494
+
+#define AVIVO_I2C_STATUS 0x7d30
+# define AVIVO_I2C_STATUS_DONE (1 << 0)
+# define AVIVO_I2C_STATUS_NACK (1 << 1)
+# define AVIVO_I2C_STATUS_HALT (1 << 2)
+# define AVIVO_I2C_STATUS_GO (1 << 3)
+# define AVIVO_I2C_STATUS_MASK 0x7
+/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
+ * DONE? */
+# define AVIVO_I2C_STATUS_CMD_RESET 0x7
+# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3)
+#define AVIVO_I2C_STOP 0x7d34
+#define AVIVO_I2C_START_CNTL 0x7d38
+# define AVIVO_I2C_START (1 << 8)
+# define AVIVO_I2C_CONNECTOR0 (0 << 16)
+# define AVIVO_I2C_CONNECTOR1 (1 << 16)
+#define R520_I2C_START (1<<0)
+#define R520_I2C_STOP (1<<1)
+#define R520_I2C_RX (1<<2)
+#define R520_I2C_EN (1<<8)
+#define R520_I2C_DDC1 (0<<16)
+#define R520_I2C_DDC2 (1<<16)
+#define R520_I2C_DDC3 (2<<16)
+#define R520_I2C_DDC_MASK (3<<16)
+#define AVIVO_I2C_CONTROL2 0x7d3c
+# define AVIVO_I2C_7D3C_SIZE_SHIFT 8
+# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8)
+#define AVIVO_I2C_CONTROL3 0x7d40
+/* Reading is done 4 bytes at a time: read the bottom 8 bits from
+ * 7d44, four times in a row.
+ * Writing is a little more complex. First write DATA with
+ * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
+ * magic number, zz is, I think, the slave address, and yy is the byte
+ * you want to write. */
+#define AVIVO_I2C_DATA 0x7d44
+#define R520_I2C_ADDR_COUNT_MASK (0x7)
+#define R520_I2C_DATA_COUNT_SHIFT (8)
+#define R520_I2C_DATA_COUNT_MASK (0xF00)
+#define AVIVO_I2C_CNTL 0x7d50
+# define AVIVO_I2C_EN (1 << 0)
+# define AVIVO_I2C_RESET (1 << 8)
#endif
commit b7774c28dde72a205a40be78003df72eabfb9b1f
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Nov 16 14:48:36 2007 +1000
Add copyright headers
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 7a6fadf..38450bb 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -1,5 +1,33 @@
-/*
- * Copyright © 2007 Dave Airlie
+ /*
+ * Copyright © 2007 Red Hat, Inc.
+ *
+ * PLL code is:
+ * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+ * Copyright 2007 Matthias Hopf <mhopf at novell.com>
+ * Copyright 2007 Egbert Eich <eich at novell.com>
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Dave Airlie <airlied at redhat.com>
*
*/
/*
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 6a01863..6c26982 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -1,6 +1,31 @@
/*
- * Copyright © 2007 Dave Airlie
+ * Copyright © 2007 Red Hat, Inc.
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Dave Airlie <airlied at redhat.com>
+ *
*/
+
/*
* avivo output handling functions.
*/
commit 3cfcd2164b400bd0d1cb4ede8eeb01abba9d75c8
Merge: efac14e... 718bfd3...
Author: Alex Deucher <alex at botch2.(none)>
Date: Thu Nov 15 23:25:39 2007 -0500
Merge branch 'agd-atom' of /home/alex/git/airlied/xf86-video-ati2 into agd-atom
commit efac14e669a0c6184f8848191eb49ffb21934ee1
Author: Dave Airlie <airlied at linux.ie>
Date: Thu Nov 15 23:17:25 2007 -0500
r5xx: fix typo for crtc offset
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index a437f97..64f8037 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -1280,7 +1280,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn)
pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
pRADEONEnt->Controller[1]->crtc_id = 1;
- pRADEONEnt->Controller[0]->crtc_offset = AVIVO_CRTC2_H_TOTAL - AVIVO_CRTC1_H_TOTAL;
+ pRADEONEnt->Controller[1]->crtc_offset = AVIVO_CRTC2_H_TOTAL - AVIVO_CRTC1_H_TOTAL;
return TRUE;
}
commit e6db621c37ff615be286462f000d67a662c5c331
Author: Alex Deucher <alex at botch2.(none)>
Date: Thu Nov 15 23:15:56 2007 -0500
fix INMC() and OUTMC() on !AVIVO chips
WR_EN is bit 8 so don't use OUTREG8.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index e49ad42..02e38bd 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -736,7 +736,7 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr)
OUTREG(AVIVO_MC_INDEX, 0);
(void)INREG(AVIVO_MC_INDEX);
} else {
- OUTREG8(R300_MC_IND_INDEX, addr & 0x3f);
+ OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
(void)INREG(R300_MC_IND_INDEX);
data = INREG(R300_MC_IND_DATA);
@@ -760,8 +760,8 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data)
OUTREG(AVIVO_MC_INDEX, 0);
(void)INREG(AVIVO_MC_INDEX);
} else {
- OUTREG8(R300_MC_IND_INDEX, (((addr) & 0x3f) |
- R300_MC_IND_WR_EN));
+ OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) |
+ R300_MC_IND_WR_EN));
(void)INREG(R300_MC_IND_INDEX);
OUTREG(R300_MC_IND_DATA, data);
OUTREG(R300_MC_IND_INDEX, 0);
commit 52ba3fdd1ce05983fabedff234cfaf4c60fba38d
Author: Alex Deucher <alex at botch2.(none)>
Date: Thu Nov 15 23:12:30 2007 -0500
atombios_dac_detect() takes care of primary vs tv dac itself
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 235f838..ccbc306 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -687,11 +687,7 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (radeon_output->type == OUTPUT_LVDS)
radeon_output->MonType = MT_LCD;
if (!radeon_output->MonType) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
- } else if (radeon_output->DACType == DAC_TVDAC) {
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
- }
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
}
}
} else {
commit 718bfd3b61879172eee819fdab7080d5d4c0a756
Author: Dave Airlie <airlied at linux.ie>
Date: Fri Nov 16 10:37:04 2007 +1000
r5xx: fix typo for crtc offset
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index a437f97..64f8037 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -1280,7 +1280,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn)
pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
pRADEONEnt->Controller[1]->crtc_id = 1;
- pRADEONEnt->Controller[0]->crtc_offset = AVIVO_CRTC2_H_TOTAL - AVIVO_CRTC1_H_TOTAL;
+ pRADEONEnt->Controller[1]->crtc_offset = AVIVO_CRTC2_H_TOTAL - AVIVO_CRTC1_H_TOTAL;
return TRUE;
}
commit 7aeb35e5ad1aed6e78a3d8565fbfbfe66232ab45
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 11 19:29:30 2007 -0500
fix from last commit
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 7025afa..52be98c 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -231,7 +231,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
return FALSE;
}
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
for (j = 0; j < 8; j++) {
if (info->BiosConnector[j].valid && (i != j) ) {
commit 2ea95900547165e86ad3f8a41ce3331a05bad60e
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 11 18:43:03 2007 -0500
Add full parsing support for atom bios connector table
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 342e458..7025afa 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -170,8 +170,15 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
if (offset) {
tmp = RADEON_BIOS16(offset + 4);
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (tmp & (1 << i)) {
+
+ if (i == 8) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping Component Video\n");
+ info->BiosConnector[i].valid = FALSE;
+ continue;
+ }
+
info->BiosConnector[i].valid = TRUE;
portinfo = RADEON_BIOS16(offset + 6 + i * 2);
info->BiosConnector[i].DACType = (portinfo & 0xf) - 1;
@@ -210,6 +217,8 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
info->BiosConnector[i].TMDSType = TMDS_INT;
else if (i == 7)
info->BiosConnector[i].TMDSType = TMDS_EXT;
+ else if (i == 9)
+ info->BiosConnector[i].TMDSType = TMDS_EXT;
else
info->BiosConnector[i].TMDSType = TMDS_UNKNOWN;
@@ -227,10 +236,10 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
for (j = 0; j < 8; j++) {
if (info->BiosConnector[j].valid && (i != j) ) {
if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) {
- if ((i == 3) || (i == 7)) {
+ if ((i == 3) || (i == 7) || (i == 9)) {
info->BiosConnector[i].DACType = info->BiosConnector[j].DACType;
info->BiosConnector[j].valid = FALSE;
- } else if ((j == 3) || (j == 7)) {
+ } else if ((j == 3) || (j == 7) || (j == 9)) {
info->BiosConnector[j].DACType = info->BiosConnector[i].DACType;
info->BiosConnector[i].valid = FALSE;
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index c24993c..6bf0dce 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -245,7 +245,7 @@ typedef struct _RADEONOutputPrivateRec {
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
#define RADEON_MAX_CRTC 2
-#define RADEON_MAX_BIOS_CONNECTOR 8
+#define RADEON_MAX_BIOS_CONNECTOR 16
typedef struct
{
commit 7ce730828c293f0810dfdc554df48dfd76e35c49
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 11 12:37:01 2007 -0500
rework crtc output source setup
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 5e53731..7a6fadf 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -306,6 +306,74 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
return;
}
+static void
+atombios_set_crtc_source(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ AtomBIOSArg data;
+ unsigned char *space;
+ SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
+ int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
+ int major, minor, i;
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ ErrorF("select crtc source table is %d %d\n", major, minor);
+
+ crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
+ crtc_src_param.ucDevice = 0;
+
+ for (i = 0; i < xf86_config->num_output; i++) {
+ xf86OutputPtr output = xf86_config->output[i];
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+
+ switch(major) {
+ case 1: {
+ switch(minor) {
+ case 0:
+ case 1:
+ default:
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY)
+ crtc_src_param.ucDevice |= ATOM_DEVICE_CRT1_SUPPORT;
+ else
+ crtc_src_param.ucDevice |= ATOM_DEVICE_CRT2_SUPPORT;
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->TMDSType == TMDS_INT)
+ crtc_src_param.ucDevice |= ATOM_DEVICE_DFP1_SUPPORT;
+ else
+ crtc_src_param.ucDevice |= ATOM_DEVICE_DFP2_SUPPORT;
+ } else if (radeon_output->MonType == MT_LCD)
+ crtc_src_param.ucDevice |= ATOM_DEVICE_LCD1_SUPPORT;
+ else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV)
+ crtc_src_param.ucDevice |= ATOM_DEVICE_TV1_SUPPORT;
+ else if (radeon_output->MonType == MT_CV)
+ crtc_src_param.ucDevice |= ATOM_DEVICE_CV_SUPPORT;
+ break;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_src_param;
+
+ if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC Source success\n");
+ return;
+ }
+
+ ErrorF("Set CRTC Source failed\n");
+ return;
+}
void
atombios_crtc_mode_set(xf86CrtcPtr crtc,
@@ -420,8 +488,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
}
- // moved to output
- //atombios_set_crtc_source(crtc);
+ atombios_set_crtc_source(crtc);
atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 3c5e8a8..6a01863 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -301,67 +301,6 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
#endif
}
-static void
-atombios_set_crtc_source(xf86OutputPtr output)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
- AtomBIOSArg data;
- unsigned char *space;
- SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
- int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
- int major, minor;
-
- atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
-
- ErrorF("select crtc source table is %d %d\n", major, minor);
-
- switch(major) {
- case 1: {
- switch(minor) {
- case 0:
- case 1:
- default:
- crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY)
- crtc_src_param.ucDevice = 0;
- else
- crtc_src_param.ucDevice = 4;
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT)
- crtc_src_param.ucDevice = 3;
- else
- crtc_src_param.ucDevice = 7;
- } else if (radeon_output->MonType == MT_LCD)
- crtc_src_param.ucDevice = 1;
- else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV)
- crtc_src_param.ucDevice = 2;
- else if (radeon_output->MonType == MT_CV)
- crtc_src_param.ucDevice = 8;
- break;
- }
- break;
- }
- default:
- break;
- }
-
- data.exec.index = index;
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &crtc_src_param;
-
- if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Set CRTC Source success\n");
- return;
- }
-
- ErrorF("Set CRTC Source failed\n");
- return;
-}
-
void
atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr mode,
@@ -371,8 +310,6 @@ atombios_output_mode_set(xf86OutputPtr output,
unsigned char *RADEONMMIO = info->MMIO;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- atombios_set_crtc_source(output);
-
if (radeon_output->MonType == MT_CRT) {
atombios_output_dac_setup(output, adjusted_mode);
} else if (radeon_output->MonType == MT_DFP) {
commit d61b6c78aa7810a2f9b9e2d9d95aab4295de80ce
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 11 11:58:17 2007 -0500
make sure i2c bus exists before using it
diff --git a/src/radeon_output.c b/src/radeon_output.c
index e6b5e3f..235f838 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -282,9 +282,11 @@ avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONDDCType DDCType = radeon_output->DDCType;
- AVIVOI2CDoLock(output->scrn, 1);
- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
- AVIVOI2CDoLock(output->scrn, 0);
+ if (radeon_output->pI2CBus) {
+ AVIVOI2CDoLock(output->scrn, 1);
+ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
+ AVIVOI2CDoLock(output->scrn, 0);
+ }
if (MonInfo) {
if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
xf86OutputSetEDID(output, MonInfo);
commit 342e3e207efda42ba679731c30dfb9d5e9d5643f
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 9 17:11:43 2007 -0500
combine outputs based on id
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 9218079..342e458 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -162,7 +162,7 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
- int offset, i, tmp, tmp0, crtc, portinfo, gpio;
+ int offset, i, j, tmp, tmp0, id, portinfo, gpio;
if (!info->VBIOS) return FALSE;
@@ -176,10 +176,11 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
portinfo = RADEON_BIOS16(offset + 6 + i * 2);
info->BiosConnector[i].DACType = (portinfo & 0xf) - 1;
info->BiosConnector[i].ConnectorType = (portinfo >> 4) & 0xf;
- crtc = (portinfo >> 8) & 0xf;
+ id = (portinfo >> 8) & 0xf;
tmp0 = RADEON_BIOS16(info->MasterDataStart + 24);
- gpio = RADEON_BIOS16(tmp0 + 4 + 27 * crtc) * 4;
+ gpio = RADEON_BIOS16(tmp0 + 4 + 27 * id) * 4;
info->BiosConnector[i].gpio = gpio;
+ info->BiosConnector[i].output_id = id;
switch(gpio) {
case RADEON_GPIO_MONID:
@@ -221,18 +222,25 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
return FALSE;
}
- /* DVI-I ports have 2 entries: one for analog, one for digital. combine them */
- if (info->BiosConnector[0].valid && info->BiosConnector[7].valid) {
- info->BiosConnector[7].DACType = info->BiosConnector[0].DACType;
- info->BiosConnector[0].valid = FALSE;
- }
-
- if (info->BiosConnector[4].valid && info->BiosConnector[3].valid) {
- info->BiosConnector[3].DACType = info->BiosConnector[4].DACType;
- info->BiosConnector[4].valid = FALSE;
+ for (i = 0; i < 8; i++) {
+ if (info->BiosConnector[i].valid) {
+ for (j = 0; j < 8; j++) {
+ if (info->BiosConnector[j].valid && (i != j) ) {
+ if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) {
+ if ((i == 3) || (i == 7)) {
+ info->BiosConnector[i].DACType = info->BiosConnector[j].DACType;
+ info->BiosConnector[j].valid = FALSE;
+ } else if ((j == 3) || (j == 7)) {
+ info->BiosConnector[j].DACType = info->BiosConnector[i].DACType;
+ info->BiosConnector[i].valid = FALSE;
+ }
+ /* other possible combos? */
+ }
+ }
+ }
+ }
}
-
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n");
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
diff --git a/src/radeon_output.c b/src/radeon_output.c
index ca9b110..e6b5e3f 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -3240,6 +3240,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
radeon_output->MonType = MT_UNKNOWN;
radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType;
radeon_output->gpio = info->BiosConnector[i].gpio;
+ radeon_output->output_id = info->BiosConnector[i].output_id;
radeon_output->DDCType = info->BiosConnector[i].DDCType;
if (info->IsAtomBios) {
if (radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM)
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index db808d2..c24993c 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -192,6 +192,7 @@ typedef struct {
RADEONConnectorType ConnectorType;
Bool valid;
int gpio;
+ int output_id;
} RADEONBIOSConnector;
typedef struct _RADEONOutputPrivateRec {
@@ -240,6 +241,7 @@ typedef struct _RADEONOutputPrivateRec {
unsigned long gpio;
char *name;
+ int output_id;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
#define RADEON_MAX_CRTC 2
commit 8078c299d5941460243944d55051547c1a4d3791
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 9 16:35:08 2007 -0500
use atom to program plls on r4xx
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 397942a..a437f97 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -907,18 +907,18 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
ErrorF("restore crtc1\n");
RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
ErrorF("restore pll1\n");
- /*if (info->IsAtomBios)
+ if (info->IsAtomBios)
atombios_crtc_set_pll(crtc, adjusted_mode);
- else*/
+ else
RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
break;
case 1:
ErrorF("restore crtc2\n");
RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg);
ErrorF("restore pll2\n");
- /*if (info->IsAtomBios)
+ if (info->IsAtomBios)
atombios_crtc_set_pll(crtc, adjusted_mode);
- else*/
+ else
RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
break;
}
commit 5febe2c96642f61d006abe6e8081e69d5b95adc0
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Nov 9 16:24:56 2007 -0500
turn off vga control when using ext modes
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 3a748fc..5e53731 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -384,6 +384,12 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
if (info->tilingEnabled) {
radeon_crtc->fb_format |= AVIVO_CRTC_MACRO_ADDRESS_MODE;
}
+
+ if (radeon_crtc->crtc_id == 0)
+ OUTREG(AVIVO_VGA1_CONTROL, 0);
+ else
+ OUTREG(AVIVO_VGA2_CONTROL, 0);
+
/* setup fb format and location
*/
OUTREG(AVIVO_CRTC1_EXPANSION_SOURCE + radeon_crtc->crtc_offset,
commit 83f170c32c08c74a9e3466ffa0e0a0606c74427b
Author: Alex Deucher <alex at botch2.(none)>
Date: Thu Nov 8 19:33:13 2007 -0500
add pci ids for X1550PRO
diff --git a/src/atipciids.h b/src/atipciids.h
index ab74492..685b811 100644
--- a/src/atipciids.h
+++ b/src/atipciids.h
@@ -287,6 +287,7 @@
#define PCI_CHIP_RS350_7835 0x7835
#define PCI_CHIP_RV515_7142 0x7142
+#define PCI_CHIP_RV515_7183 0x7183
/* Misc */
diff --git a/src/radeon_chipset.h b/src/radeon_chipset.h
index 890babd..d6d8bae 100644
--- a/src/radeon_chipset.h
+++ b/src/radeon_chipset.h
@@ -137,6 +137,8 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" },
{ PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" },
{ PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" },
+ { PCI_CHIP_RV515_7142, "ATI AVIVO X1300 (PCIE)"},
+ { PCI_CHIP_RV515_7183, "ATI AVIVO X1550PRO (PCI/PCIE)"},
{ -1, NULL }
};
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 9914446..e49ad42 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1838,6 +1838,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
break;
case PCI_CHIP_RV515_7142:
+ case PCI_CHIP_RV515_7183:
info->ChipFamily = CHIP_FAMILY_RV515;
break;
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index 5253cd7..7a3c908 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -193,6 +193,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA },
{ PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA },
{ PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
commit 5cdcaba0f6e9de2d15cfcc109ab97d9fd423e3bf
Author: Alex Deucher <alex at botch2.(none)>
Date: Thu Nov 8 19:28:03 2007 -0500
make sure to assign gpio
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 60e17db..ca9b110 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -258,7 +258,7 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn)
radeon_output = output->driver_private;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Port%d:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n",
+ "Port%d:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s [0x%x]\n",
o,
MonTypeName[radeon_output->MonType+1],
info->IsAtomBios ?
@@ -266,7 +266,8 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn)
ConnectorTypeName[radeon_output->ConnectorType],
DACTypeName[radeon_output->DACType+1],
TMDSTypeName[radeon_output->TMDSType+1],
- DDCTypeName[radeon_output->DDCType]);
+ DDCTypeName[radeon_output->DDCType],
+ radeon_output->gpio);
}
}
@@ -3238,6 +3239,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
}
radeon_output->MonType = MT_UNKNOWN;
radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType;
+ radeon_output->gpio = info->BiosConnector[i].gpio;
radeon_output->DDCType = info->BiosConnector[i].DDCType;
if (info->IsAtomBios) {
if (radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM)
commit 2dcb852778301b9284a2b4906dcf64f95ed638b7
Author: Alex Deucher <alex at botch2.(none)>
Date: Thu Nov 8 18:39:23 2007 -0500
pull in another of Dave's fixes
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index f15c707..3a748fc 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -401,6 +401,15 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
OUTREG(AVIVO_CRTC1_PITCH + radeon_crtc->crtc_offset,
crtc->scrn->displayWidth);
+ /* avivo can only shift offset by 4 pixel in x if you program somethings
+ * not multiple of 4 you gonna drive the GPU crazy and likely won't
+ * be able to restore it without cold reboot (vbe post not enough)
+ */
+ x = x & ~3;
+ OUTREG(AVIVO_CRTC1_OFFSET_END + radeon_crtc->crtc_offset,
+ ((mode->HDisplay + x -128) << 16) | (mode->VDisplay + y - 128));
+ OUTREG(AVIVO_CRTC1_OFFSET_START + radeon_crtc->crtc_offset, (x << 16) | y);
+
OUTREG(AVIVO_CRTC1_SCAN_ENABLE + radeon_crtc->crtc_offset, 1);
}
commit 96273016a0bbdfa4d3a4e6275a3b09eeeadaa534
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 7 01:22:30 2007 -0500
fix and move crtc source set up atombios_output.c
it's really more output related.
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index baa8c1b..f15c707 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -103,51 +103,6 @@ atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
}
}
-static void
-atombios_set_crtc_source(xf86CrtcPtr crtc)
-{
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
- AtomBIOSArg data;
- unsigned char *space;
- SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
- int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
- int major, minor;
-
- atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
-
- ErrorF("select crtc source table is %d %d\n", major, minor);
-
- switch(major) {
- case 1: {
- switch(minor) {
- case 0:
- case 1:
- default:
- crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
- crtc_src_param.ucDevice = radeon_crtc->crtc_id? 0: 3;
- break;
- }
- break;
- }
- default:
- break;
- }
-
- data.exec.index = index;
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &crtc_src_param;
-
- if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Set CRTC Source success\n");
- return;
- }
-
- ErrorF("Set CRTC Source failed\n");
- return;
-}
-
static AtomBiosResult
atombios_set_crtc_timing(atomBIOSHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
{
@@ -450,7 +405,8 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
}
- atombios_set_crtc_source(crtc);
+ // moved to output
+ //atombios_set_crtc_source(crtc);
atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 210ce7a..3c5e8a8 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -257,7 +257,7 @@ atombios_output_lvds_dpms(xf86OutputPtr output, int mode)
void
atombios_output_dpms(xf86OutputPtr output, int mode)
{
- RADEONOutputPrivatePtr avivo_output = output->driver_private;
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
unsigned char *RADEONMMIO = info->MMIO;
int tmp, count;
@@ -284,12 +284,12 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
ErrorF("AGD: output dpms\n");
- if (avivo_output->MonType == MT_LCD) {
+ if (radeon_output->MonType == MT_LCD) {
atombios_output_tmds2_dpms(output, mode);
- } else if (avivo_output->MonType == MT_DFP) {
+ } else if (radeon_output->MonType == MT_DFP) {
ErrorF("AGD: tmds dpms\n");
atombios_output_tmds1_dpms(output, mode);
- } else if (avivo_output->MonType == MT_CRT) {
+ } else if (radeon_output->MonType == MT_CRT) {
ErrorF("AGD: dac dpms\n");
atombios_output_dac_dpms(output, mode);
}
@@ -301,22 +301,81 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
#endif
}
+static void
+atombios_set_crtc_source(xf86OutputPtr output)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ AtomBIOSArg data;
+ unsigned char *space;
+ SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
+ int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
+ int major, minor;
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ ErrorF("select crtc source table is %d %d\n", major, minor);
+
+ switch(major) {
+ case 1: {
+ switch(minor) {
+ case 0:
+ case 1:
+ default:
+ crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY)
+ crtc_src_param.ucDevice = 0;
+ else
+ crtc_src_param.ucDevice = 4;
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->TMDSType == TMDS_INT)
+ crtc_src_param.ucDevice = 3;
+ else
+ crtc_src_param.ucDevice = 7;
+ } else if (radeon_output->MonType == MT_LCD)
+ crtc_src_param.ucDevice = 1;
+ else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV)
+ crtc_src_param.ucDevice = 2;
+ else if (radeon_output->MonType == MT_CV)
+ crtc_src_param.ucDevice = 8;
+ break;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_src_param;
+
+ if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC Source success\n");
+ return;
+ }
+
+ ErrorF("Set CRTC Source failed\n");
+ return;
+}
+
void
atombios_output_mode_set(xf86OutputPtr output,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode)
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode)
{
RADEONInfoPtr info = RADEONPTR(output->scrn);
unsigned char *RADEONMMIO = info->MMIO;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ atombios_set_crtc_source(output);
+
if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- ErrorF("AGD: atom dac setup\n");
- atombios_output_dac_setup(output, adjusted_mode);
- }
+ atombios_output_dac_setup(output, adjusted_mode);
} else if (radeon_output->MonType == MT_DFP) {
- ErrorF("AGD: atom tmds setup\n");
if (radeon_output->TMDSType == TMDS_INT)
atombios_output_tmds1_setup(output, adjusted_mode);
else
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 3b493b8..db808d2 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -71,7 +71,8 @@ typedef enum
MT_LCD = 2,
MT_DFP = 3,
MT_CTV = 4,
- MT_STV = 5
+ MT_STV = 5,
+ MT_CV = 6
} RADEONMonitorType;
typedef enum
commit 5c495c81cc3bcd4a38d06954243ed3bdc85bdc07
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 7 01:04:11 2007 -0500
add support for initing external tmds via ATOM
diff --git a/src/atombios_output.c b/src/atombios_output.c
index a43397e..210ce7a 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -87,6 +87,38 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
#endif
}
+int
+atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data;
+ AtomBIOSArg data;
+ unsigned char *space;
+ AtomBiosResult ret;
+
+ disp_data.sXTmdsEncoder.ucEnable = 1;
+
+ if (mode->Clock > 165000)
+ disp_data.sXTmdsEncoder.ucMisc = 1;
+ else
+ disp_data.sXTmdsEncoder.ucMisc = 0;
+
+ if (!info->dac6bits)
+ disp_data.sXTmdsEncoder.ucMisc |= (1 << 1);
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableExternalTMDS_Encoder);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+
+ if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("External TMDS enable success\n");
+ return ATOM_SUCCESS;
+ }
+
+ ErrorF("External TMDS enable failed\n", radeon_output->DACType);
+ return ATOM_NOT_IMPLEMENTED;
+}
static int
atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 706f9ab..60e17db 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -161,6 +161,7 @@ extern void atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr adjusted_mode);
extern void atombios_output_dpms(xf86OutputPtr output, int mode);
extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output);
+extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode);
Bool
RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch)
@@ -1237,7 +1238,10 @@ legacy_mode_set(xf86OutputPtr output, DisplayModePtr mode,
RADEONRestoreFPRegisters(pScrn, &info->ModeReg);
} else {
ErrorF("restore FP2\n");
- RADEONRestoreDVOChip(pScrn, output);
+ if (info->IsAtomBios)
+ atombios_external_tmds_setup(output, mode);
+ else
+ RADEONRestoreDVOChip(pScrn, output);
RADEONRestoreFP2Registers(pScrn, &info->ModeReg);
}
break;
commit 5c13d9355280e6de44ebbf8de7ea89a6b91c7388
Author: Alex Deucher <alex at botch2.(none)>
Date: Wed Nov 7 00:17:28 2007 -0500
add avivo output stuff
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 18e6d3c..a43397e 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -17,10 +17,8 @@
#include "radeon_macros.h"
#include "radeon_atombios.h"
-static
-Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state);
-
-static AtomBiosResult atom_bios_display_device_control(atomBIOSHandlePtr atomBIOS, int device, Bool state)
+static AtomBiosResult
+atom_bios_display_device_control(atomBIOSHandlePtr atomBIOS, int device, Bool state)
{
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data;
AtomBIOSArg data;
@@ -81,11 +79,12 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
ErrorF("Output DAC %d enable failed\n", radeon_output->DACType);
return ATOM_NOT_IMPLEMENTED;
+#if 0
atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, CRT1OutputControl), ATOM_TRANSMITTER_ACTION_INIT);
atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, CRT1OutputControl), ATOM_TRANSMITTER_ACTION_SETUP);
atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, CRT1OutputControl), ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT);
return ATOM_SUCCESS;
-
+#endif
}
@@ -119,10 +118,12 @@ atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
ErrorF("Output TMDS1 enable failed\n");
return ATOM_NOT_IMPLEMENTED;
+#if 0
atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, DFP1OutputControl), ATOM_TRANSMITTER_ACTION_INIT);
atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, DFP1OutputControl), ATOM_TRANSMITTER_ACTION_SETUP);
atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, DFP1OutputControl), ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT);
return ATOM_SUCCESS;
+#endif
}
static void
@@ -268,34 +269,6 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
#endif
}
-static int
-atombios_output_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
-{
- if (pMode->Flags & V_DBLSCAN)
- return MODE_NO_DBLESCAN;
-
- if (pMode->Clock > 400000 || pMode->Clock < 25000)
- return MODE_CLOCK_RANGE;
-
- return MODE_OK;
-}
-
-static Bool
-atombios_output_mode_fixup(xf86OutputPtr output,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode)
-{
- return TRUE;
-}
-
-static void
-atombios_output_prepare(xf86OutputPtr output)
-{
- output->funcs->dpms(output, DPMSModeOff);
-}
-
-
-
void
atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr mode,
@@ -321,708 +294,6 @@ atombios_output_mode_set(xf86OutputPtr output,
}
}
-static void
-atombios_output_commit(xf86OutputPtr output)
-{
- output->funcs->dpms(output, DPMSModeOn);
-}
-
-DisplayModePtr
-atombios_output_get_modes(xf86OutputPtr output)
-{
- RADEONOutputPrivatePtr atombios_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
- xf86MonPtr edid_mon;
- DisplayModePtr modes;
-
- modes = RADEONProbeOutputModes(output);
- return modes;
-}
-
-static void
-atombios_output_destroy(xf86OutputPtr output)
-{
- RADEONOutputPrivatePtr avivo_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (avivo_output == NULL)
- return;
- xf86DestroyI2CBusRec(avivo_output->pI2CBus, TRUE, TRUE);
- xfree(avivo_output->name);
- xfree(avivo_output);
-}
-
-
-Bool
-atombios_output_lfp_mode_fixup(xf86OutputPtr output,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
-
-#if 0
- if (avivo->lfp_fixed_mode) {
- adjusted_mode->HDisplay = info->lfp_fixed_mode->HDisplay;
- adjusted_mode->HSyncStart = info->lfp_fixed_mode->HSyncStart;
- adjusted_mode->HSyncEnd = info->lfp_fixed_mode->HSyncEnd;
- adjusted_mode->HTotal = info->lfp_fixed_mode->HTotal;
- adjusted_mode->VDisplay = info->lfp_fixed_mode->VDisplay;
- adjusted_mode->VSyncStart = info->lfp_fixed_mode->VSyncStart;
- adjusted_mode->VSyncEnd = info->lfp_fixed_mode->VSyncEnd;
- adjusted_mode->VTotal = info->lfp_fixed_mode->VTotal;
- adjusted_mode->Clock = info->lfp_fixed_mode->Clock;
- xf86SetModeCrtc(adjusted_mode, 0);
- }
-#endif
- return TRUE;
-}
-
-DisplayModePtr
-atombios_output_lfp_get_modes(xf86OutputPtr output)
-{
- ScrnInfoPtr screen_info = output->scrn;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- DisplayModePtr modes = NULL;
-
- modes = atombios_output_get_modes(output);
- if (modes == NULL) {
- /* DDC EDID failed try to get timing from BIOS */
- xf86DrvMsg(screen_info->scrnIndex, X_WARNING,
- "Failed to get EDID over i2c for LFP try BIOS timings.\n");
- modes = atombios_bios_get_lfp_timing(screen_info);
- }
-#if 0
- if (modes) {
- xf86DeleteMode(&info->lfp_fixed_mode, info->lfp_fixed_mode);
- info->lfp_fixed_mode = xf86DuplicateMode(modes);
- }
-#endif
- return modes;
-}
-
-
-
-void
-atombios_i2c_gpio0_get_bits(I2CBusPtr b, int *Clock, int *data)
-{
- ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(screen_info);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned long val;
-
- ErrorF("INREG %08x\n", INREG(b->DriverPrivate.uval));
- /* Get the result */
- val = INREG(b->DriverPrivate.uval + 0xC);
- *Clock = (val & (1<<19)) != 0;
- *data = (val & (1<<18)) != 0;
-}
-
-void
-atombios_i2c_gpio0_put_bits(I2CBusPtr b, int Clock, int data)
-{
- ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(screen_info);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned long val;
-
- val = 0;
- val |= (Clock ? 0:(1<<19));
- val |= (data ? 0:(1<<18));
- OUTREG(b->DriverPrivate.uval + 0x8, val);
- /* read back to improve reliability on some cards. */
- val = INREG(b->DriverPrivate.uval + 0x8);
-}
-
-void
-atombios_i2c_gpio123_get_bits(I2CBusPtr b, int *Clock, int *data)
-{
- ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(screen_info);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned long val;
-
- if (INREG(b->DriverPrivate.uval) == 0)
- OUTREG(b->DriverPrivate.uval, (1<<0) | (1<<8));
-
- /* Get the result */
- val = INREG(b->DriverPrivate.uval + 0xC);
- *Clock = (val & (1<<0)) != 0;
- *data = (val & (1<<8)) != 0;
-}
-
-void
-atombios_i2c_gpio123_put_bits(I2CBusPtr b, int Clock, int data)
-{
- ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(screen_info);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned long val;
-
- val = 0;
- val |= (Clock ? 0:(1<<0));
- val |= (data ? 0:(1<<8));
- OUTREG(b->DriverPrivate.uval + 0x8, val);
- /* read back to improve reliability on some cards. */
- val = INREG(b->DriverPrivate.uval + 0x8);
-}
-
-static xf86OutputStatus
-atombios_output_detect(xf86OutputPtr output)
-{
- RADEONOutputPrivatePtr avivo_output = output->driver_private;
- ScrnInfoPtr screen_info = output->scrn;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
- AtomBiosResult ret;
- uint32_t bios_0_scratch;
-
- return radeon_detect(output);
-}
-
-static const xf86OutputFuncsRec atombios_output_dac_funcs = {
- .dpms = atombios_output_dpms,
- .save = NULL,
- .restore = NULL,
- .mode_valid = atombios_output_mode_valid,
- .mode_fixup = atombios_output_mode_fixup,
- .prepare = atombios_output_prepare,
- .mode_set = atombios_output_mode_set,
- .commit = atombios_output_commit,
- .detect = atombios_output_detect,
- .get_modes = atombios_output_get_modes,
- .destroy = atombios_output_destroy
-};
-
-static const xf86OutputFuncsRec atombios_output_tmds_funcs = {
- .dpms = atombios_output_dpms,
- .save = NULL,
- .restore = NULL,
- .mode_valid = atombios_output_mode_valid,
- .mode_fixup = atombios_output_mode_fixup,
- .prepare = atombios_output_prepare,
- .mode_set = atombios_output_mode_set,
- .commit = atombios_output_commit,
- .detect = atombios_output_detect,
- .get_modes = atombios_output_get_modes,
- .destroy = atombios_output_destroy
-};
-
-static const xf86OutputFuncsRec atombios_output_lfp_funcs = {
- .dpms = atombios_output_dpms,
- .save = NULL,
- .restore = NULL,
- .mode_valid = atombios_output_mode_valid,
- .mode_fixup = atombios_output_lfp_mode_fixup,
- .prepare = atombios_output_prepare,
- .mode_set = atombios_output_mode_set,
- .commit = atombios_output_commit,
- .detect = atombios_output_detect,
- .get_modes = atombios_output_get_modes,
- .destroy = atombios_output_destroy
-};
-
-Bool
-atombios_output_exist(ScrnInfoPtr screen_info, xf86ConnectorType type,
- int number, unsigned long ddc_reg)
-{
- xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(screen_info);
- int i;
-
- for (i = 0; i < config->num_output; i++) {
- xf86OutputPtr output = config->output[i];
- RADEONOutputPrivatePtr avivo_output = output->driver_private;
- if (avivo_output->num == number && avivo_output->type == type)
- return TRUE;
- /* LVTMA is shared by LFP & DVI-I */
- if (avivo_output->type == XF86ConnectorLFP && number >= 1)
- return TRUE;
- if (type == XF86ConnectorLFP && avivo_output->num >= 1) {
- avivo_output->type = type;
- avivo_output->pI2CBus->DriverPrivate.uval = ddc_reg;
- return TRUE;
- }
- }
- return FALSE;
-}
-
-#if 0
-Bool
-avivo_output_init(ScrnInfoPtr screen_info, xf86ConnectorType type,
- int number, unsigned long ddc_reg)
-{
- xf86OutputPtr output = {0,};
- RADEONOutputPrivateRec *avivo_output;
- int name_size;
-
- /* allocate & initialize private output structure */
- avivo_output = xcalloc(sizeof(RADEONOutputPrivateRec), 1);
- if (avivo_output == NULL)
- return FALSE;
- name_size = snprintf(NULL, 0, "%s connector %d",
- xf86ConnectorGetName(type), number);
- avivo_output->name = xcalloc(name_size + 1, 1);
- if (avivo_output->name == NULL) {
- xfree(avivo_output);
- xf86DrvMsg(screen_info->scrnIndex, X_ERROR,
- "Failed to allocate memory for I2C bus name\n");
- return FALSE;
- }
- snprintf(avivo_output->name, name_size + 1, "%s connector %d",
- xf86ConnectorGetName(type), number);
- avivo_output->pI2CBus = xf86CreateI2CBusRec();
- if (!avivo_output->pI2CBus) {
- xfree(avivo_output);
- xf86DrvMsg(screen_info->scrnIndex, X_ERROR,
- "Couldn't create I2C bus for %s connector %d\n",
- xf86ConnectorGetName(type), number);
- return FALSE;
- }
- avivo_output->pI2CBus->BusName = avivo_output->name;
- avivo_output->pI2CBus->scrnIndex = screen_info->scrnIndex;
- if (ddc_reg == AVIVO_GPIO_0) {
- avivo_output->pI2CBus->I2CPutBits = atombios_i2c_gpio0_put_bits;
- avivo_output->pI2CBus->I2CGetBits = atombios_i2c_gpio0_get_bits;
- } else {
- avivo_output->pI2CBus->I2CPutBits = avivo_i2c_gpio123_put_bits;
- avivo_output->pI2CBus->I2CGetBits = avivo_i2c_gpio123_get_bits;
- }
- avivo_output->pI2CBus->AcknTimeout = 5;
- avivo_output->pI2CBus->DriverPrivate.uval = ddc_reg;
- if (!xf86I2CBusInit(avivo_output->pI2CBus)) {
- xf86DrvMsg(screen_info->scrnIndex, X_ERROR,
- "Couldn't initialise I2C bus for %s connector %d\n",
- xf86ConnectorGetName(type), number);
- return FALSE;
- }
- avivo_output->gpio = ddc_reg;
- avivo_output->type = type;
- avivo_output->num = number;
- switch (avivo_output->type) {
- case XF86ConnectorVGA:
- avivo_output->setup = avivo_output_dac_setup;
- avivo_output->dpms = avivo_output_dac_dpms;
- output = xf86OutputCreate (screen_info,
- &avivo_output_dac_funcs,
- xf86ConnectorGetName(type));
- break;
- case XF86ConnectorLFP:
- avivo_output->setup = avivo_output_tmds2_setup;
- avivo_output->dpms = avivo_output_lvds_dpms;
- output = xf86OutputCreate (screen_info,
- &avivo_output_lfp_funcs,
- xf86ConnectorGetName(type));
- break;
- case XF86ConnectorDVI_I:
- case XF86ConnectorDVI_D:
- case XF86ConnectorDVI_A:
- if (!number) {
- avivo_output->setup = avivo_output_tmds1_setup;
- avivo_output->dpms = avivo_output_tmds1_dpms;
- } else {
- avivo_output->setup = avivo_output_tmds2_setup;
- avivo_output->dpms = avivo_output_tmds2_dpms;
- }
- output = xf86OutputCreate (screen_info,
- &avivo_output_tmds_funcs,
- xf86ConnectorGetName(type));
- break;
- default:
- avivo_output->setup = NULL;
- break;
- }
-
- if (output == NULL) {
- xf86DestroyI2CBusRec(avivo_output->pI2CBus, TRUE, TRUE);
- xfree(avivo_output);
- return FALSE;
- }
- output->driver_private = avivo_output;
- output->interlaceAllowed = FALSE;
- output->doubleScanAllowed = FALSE;
- xf86DrvMsg(screen_info->scrnIndex, X_INFO,
- "added %s connector %d (0x%04lX)\n",
- xf86ConnectorGetName(type), number, ddc_reg);
-
- return TRUE;
-}
-#endif
-extern void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output);
-extern void RADEONInitConnector(xf86OutputPtr output);
-extern const char *OutputType[], *DDCTypeName[];
-
-
-static
-Bool AVIVOI2CReset(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(AVIVO_I2C_STOP, 1);
- INREG(AVIVO_I2C_STOP);
- OUTREG(AVIVO_I2C_STOP, 0x0);
- return TRUE;
-}
-
-static
-Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 temp;
- int count=0;
-
- switch(lock_state) {
- case 0:
- temp = INREG(AVIVO_I2C_CNTL);
- OUTREG(AVIVO_I2C_CNTL, temp | 0x100);
- /* enable hdcp block */
- OUTREG(R520_PCLK_HDCP_CNTL, 0x0);
- break;
- case 1:
- /* disable hdcp block */
- OUTREG(R520_PCLK_HDCP_CNTL, 0x1);
- usleep(1);
- OUTREG(AVIVO_I2C_CNTL, 0x1);
- usleep(1);
- temp = INREG(AVIVO_I2C_CNTL);
- if (!(temp & 0x2)) {
- ErrorF("Lock failed %08X\n", temp);
- return FALSE;
- }
- break;
- }
- return TRUE;
-}
-
-#if 0
-static Bool
-AVIVOI2CSendData(I2CDevPtr d, int address, int nWrite, I2CByte *data)
-{
- I2CBusPtr b = d->pI2CBus;
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 temp;
- int count, i;
-
- OUTREG(AVIVO_I2C_STATUS, (AVIVO_I2C_STATUS_DONE | AVIVO_I2C_STATUS_NACK | AVIVO_I2C_STATUS_HALT));
- temp = INREG(AVIVO_I2C_START_CNTL);
- temp |= R520_I2C_START | R520_I2C_STOP | R520_I2C_RX | R520_I2C_EN;
-
- temp &= ~R520_I2C_DDC_MASK;
-
- switch(b->DriverPrivate.uval)
- {
- case 0x7e40:
- temp |= R520_I2C_DDC1;
- break;
- case 0x7e50:
- default:
- temp |= R520_I2C_DDC2;
- break;
- }
-
- OUTREG(AVIVO_I2C_START_CNTL, temp);
-
- temp = INREG(AVIVO_I2C_CONTROL2);
- temp &= ~R520_I2C_DATA_COUNT_MASK;
- temp |= 1 << R520_I2C_DATA_COUNT_SHIFT;
- temp &= ~R520_I2C_ADDR_COUNT_MASK;
- temp |= 1;
- OUTREG(AVIVO_I2C_CONTROL2, temp);
-
- temp = INREG(AVIVO_I2C_CONTROL3);
- OUTREG(AVIVO_I2C_CONTROL3, temp);
-
- OUTREG(AVIVO_I2C_DATA, address);
- for (i=0; i<nWrite; i++)
- OUTREG(AVIVO_I2C_DATA, data[i]);
-
- /* set to i2c tx mode */
- temp = INREG(AVIVO_I2C_START_CNTL);
- temp &= ~R520_I2C_RX;
- OUTREG(AVIVO_I2C_START_CNTL, temp);
-
- /* set go flag */
- OUTREG(AVIVO_I2C_STATUS, AVIVO_I2C_STATUS_GO);
-
- count = 0;
- do {
- temp = INREG(AVIVO_I2C_STATUS);
- if (temp & AVIVO_I2C_STATUS_DONE)
- break;
- usleep(1);
- count++;
- } while(count<10);
-
- if (count == 10)
- return FALSE;
- OUTREG(AVIVO_I2C_STATUS, temp);
-
- return TRUE;
-}
-static Bool
-AVIVOI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite,
- I2CByte *ReadBuffer, int nRead)
-{
- I2CBusPtr b = d->pI2CBus;
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 temp;
- int i, count;
- int sofar, thisread;
- I2CByte offbuf[1];
- Bool ret;
-
- AVIVOI2CReset(pScrn);
-
- /* set the control1 flags */
- if (nWrite > 1)
- {
- ret = AVIVOI2CSendData(d, d->SlaveAddr, nWrite, WriteBuffer);
- if (ret==FALSE)
- return FALSE;
- }
-
- if (nRead > 0 && nWrite == 1)
- {
- /* okay this is a standard read - the i2c hw can only do 15 bytes */
- sofar = 0;
- do {
- thisread = nRead - sofar;
- if (thisread > 15)
- thisread = 15;
-
- offbuf[0] = sofar;
- ret = AVIVOI2CSendData(d, d->SlaveAddr, 1, offbuf);
- if (ret==FALSE)
- return FALSE;
-
- OUTREG(AVIVO_I2C_DATA, d->SlaveAddr | 0x1);
-
- temp = INREG(AVIVO_I2C_START_CNTL);
- temp |= R520_I2C_RX;
- OUTREG(AVIVO_I2C_START_CNTL, temp);
-
- temp = INREG(AVIVO_I2C_CONTROL2);
- temp &= ~R520_I2C_DATA_COUNT_MASK;
- temp |= thisread << R520_I2C_DATA_COUNT_SHIFT;
- temp &= ~R520_I2C_ADDR_COUNT_MASK;
- temp |= 1;
- OUTREG(AVIVO_I2C_CONTROL2, temp);
-
- OUTREG(AVIVO_I2C_STATUS, AVIVO_I2C_STATUS_GO);
- count = 0;
- do {
- temp = INREG(AVIVO_I2C_STATUS);
- if (temp & AVIVO_I2C_STATUS_DONE)
- break;
- usleep(1);
- count++;
- } while(count<100);
- if (count == 100)
- return FALSE;
-
- OUTREG(AVIVO_I2C_STATUS, temp);
-
- for (i=0; i<thisread; i++)
- {
- temp = INREG(AVIVO_I2C_DATA);
- ReadBuffer[sofar+i] = (I2CByte)(temp & 0xff);
- }
- sofar += thisread;
- } while(sofar < nRead);
- }
- return TRUE;
-}
-
-
-Bool atombios_i2c_init(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- I2CBusPtr pI2CBus;
-
- pI2CBus = xf86CreateI2CBusRec();
- if (!pI2CBus)
- return FALSE;
-
- pI2CBus->BusName = name;
- pI2CBus->scrnIndex = pScrn->scrnIndex;
- pI2CBus->I2CWriteRead = AVIVOI2CWriteRead;
- pI2CBus->DriverPrivate.uval = i2c_reg;
-
- ErrorF("uval is %04X\n", i2c_reg);
- if (!xf86I2CBusInit(pI2CBus))
- return FALSE;
-
- *bus_ptr = pI2CBus;
- return TRUE;
-}
-
-#else
-Bool
-atom_bios_i2c_init(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
-{
- I2CBusPtr pI2CBus;
-
- pI2CBus = xf86CreateI2CBusRec();
- if (!pI2CBus) return FALSE;
-
- pI2CBus->BusName = name;
- pI2CBus->scrnIndex = pScrn->scrnIndex;
- if (i2c_reg == AVIVO_GPIO_0) {
- pI2CBus->I2CPutBits = atombios_i2c_gpio0_put_bits;
- pI2CBus->I2CGetBits = atombios_i2c_gpio0_get_bits;
- } else {
- pI2CBus->I2CPutBits = atombios_i2c_gpio123_put_bits;
- pI2CBus->I2CGetBits = atombios_i2c_gpio123_get_bits;
- }
- pI2CBus->AcknTimeout = 5;
- pI2CBus->DriverPrivate.uval = i2c_reg;
-
- if (!xf86I2CBusInit(pI2CBus)) return FALSE;
-
- *bus_ptr = pI2CBus;
- return TRUE;
-}
-#endif
-
-void atombios_init_connector(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int DDCReg = 0;
- char* name = (char*) DDCTypeName[radeon_output->DDCType];
-
- if (radeon_output->gpio) {
- radeon_output->DDCReg = radeon_output->gpio;
- if (IS_AVIVO_VARIANT)
- atom_bios_i2c_init(pScrn, &radeon_output->pI2CBus, radeon_output->gpio, output->name);
- else
- RADEONI2CInit(pScrn, &radeon_output->pI2CBus, radeon_output->DDCReg, name);
- }
-
- if (radeon_output->type == OUTPUT_LVDS) {
- RADEONGetLVDSInfo(output);
- }
-
- if (radeon_output->type == OUTPUT_DVI) {
- // RADEONGetTMDSInfo(output);
- }
-
- if (radeon_output->type == OUTPUT_STV ||
- radeon_output->type == OUTPUT_CTV) {
- // RADEONGetTVInfo(output);
- }
-
- if (radeon_output->DACType == DAC_TVDAC) {
- radeon_output->tv_on = FALSE;
- // RADEONGetTVDacAdjInfo(output);
- }
-
-}
-
-Bool atombios_setup_outputs(ScrnInfoPtr pScrn, int num_vga, int num_dvi)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86OutputPtr output;
- int i;
-
- for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- if (info->BiosConnector[i].valid) {
- RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
- if (!radeon_output) {
- return FALSE;
- }
- radeon_output->MonType = MT_UNKNOWN;
- radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType;
- radeon_output->DDCType = info->BiosConnector[i].DDCType;
- radeon_output->gpio = info->BiosConnector[i].gpio;
- if (info->IsAtomBios) {
- if (radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM)
- radeon_output->DACType = DAC_NONE;
- else
- radeon_output->DACType = info->BiosConnector[i].DACType;
-
- if (radeon_output->ConnectorType == CONNECTOR_VGA_ATOM)
- radeon_output->TMDSType = TMDS_NONE;
- else
- radeon_output->TMDSType = info->BiosConnector[i].TMDSType;
- } else {
- if (radeon_output->ConnectorType == CONNECTOR_DVI_D)
- radeon_output->DACType = DAC_NONE;
- else
- radeon_output->DACType = info->BiosConnector[i].DACType;
-
- if (radeon_output->ConnectorType == CONNECTOR_CRT)
- radeon_output->TMDSType = TMDS_NONE;
- else
- radeon_output->TMDSType = info->BiosConnector[i].TMDSType;
- }
- RADEONSetOutputType(pScrn, radeon_output);
- fprintf(stderr,"output type is %d\n", radeon_output->type);
- if (info->IsAtomBios) {
- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D_ATOM) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I_ATOM) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A_ATOM)) {
- if (num_dvi > 1) {
- output = xf86OutputCreate(pScrn, &atombios_output_tmds_funcs, "DVI-1");
- num_dvi--;
- } else {
- output = xf86OutputCreate(pScrn, &atombios_output_tmds_funcs, "DVI-0");
- }
- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA_ATOM) {
- if (num_vga > 1) {
- output = xf86OutputCreate(pScrn, &atombios_output_dac_funcs, "VGA-1");
- num_vga--;
- } else {
- output = xf86OutputCreate(pScrn, &atombios_output_dac_funcs, "VGA-0");
- }
- } else if (info->BiosConnector[i].ConnectorType != CONNECTOR_STV)
- output = xf86OutputCreate(pScrn, &atombios_output_lfp_funcs, OutputType[radeon_output->type]);
- } else {
- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I)) {
- if (num_dvi > 1) {
- output = xf86OutputCreate(pScrn, &atombios_output_tmds_funcs, "DVI-1");
- num_dvi--;
- } else {
- output = xf86OutputCreate(pScrn, &atombios_output_tmds_funcs, "DVI-0");
- }
- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT) {
- if (num_vga > 1) {
- output = xf86OutputCreate(pScrn, &atombios_output_dac_funcs, "VGA-1");
- num_vga--;
- } else {
- output = xf86OutputCreate(pScrn, &atombios_output_dac_funcs, "VGA-0");
- }
- } else
- output = xf86OutputCreate(pScrn, &atombios_output_lfp_funcs, OutputType[radeon_output->type]);
- }
-
- if (!output) {
- return FALSE;
- }
- output->driver_private = radeon_output;
- output->possible_crtcs = 1;
- /* crtc2 can drive LVDS, it just doesn't have RMX */
- if (radeon_output->type != OUTPUT_LVDS)
- output->possible_crtcs |= 2;
-
- /* we can clone the DACs, and probably TV-out,
- but I'm not sure it's worth the trouble */
- output->possible_clones = 0;
-
- atombios_init_connector(output);
- }
- }
- return TRUE;
-}
-
static AtomBiosResult
atom_bios_dac_load_detect(atomBIOSHandlePtr atomBIOS, int dac)
{
@@ -1048,7 +319,8 @@ atom_bios_dac_load_detect(atomBIOSHandlePtr atomBIOS, int dac)
return ATOM_NOT_IMPLEMENTED;
}
-static RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
+RADEONMonitorType
+atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
@@ -1073,116 +345,3 @@ static RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr ou
return MonType;
}
-static RADEONMonitorType atombios_port_check_nonddc(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONMonitorType MonType = MT_NONE;
- uint32_t bios_0_scratch;
- int ret;
- if (radeon_output->type == OUTPUT_LVDS) {
- MonType = MT_LCD;
- }
-#if 0
- else if (radeon_output->type == OUTPUT_DVI) {
- if (radeon_output->TMDSType == TMDS_INT) {
- if (INREG(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
- MonType = MT_DFP;
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- if (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
- MonType = MT_DFP;
- }
- }
-#endif
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Detected Monitor Type: %d\n", MonType);
-
- return MonType;
-
-}
-
-
-static RADEONMonitorType
-atombios_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned long DDCReg;
- RADEONMonitorType MonType = MT_NONE;
- xf86MonPtr* MonInfo = &output->MonInfo;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONDDCType DDCType = radeon_output->DDCType;
- int i, j;
-
- if (!IS_AVIVO_VARIANT) {
- ErrorF("AGD: DDCConnected\n");
- return RADEONDisplayDDCConnected(pScrn, output);
- }
-
- AVIVOI2CDoLock(output->scrn, 1);
- *MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
- AVIVOI2CDoLock(output->scrn, 0);
- if (*MonInfo) {
- if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_LVDS_ATOM) ||
- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_PROPRIETARY)) {
- MonType = MT_LCD;
- } else if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM) ||
- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D)) {
- MonType = MT_DFP;
- } else if (radeon_output->type == OUTPUT_DVI &&
- ((*MonInfo)->rawData[0x14] & 0x80)) { /* if it's digital and DVI */
- MonType = MT_DFP;
- } else {
- MonType = MT_CRT;
- }
- } else MonType = MT_NONE;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "DDC Type: %d[%04x], Detected Monitor Type: %d\n", DDCType, radeon_output->gpio, MonType);
-
- return MonType;
-}
-
-extern const char *ConnectorTypeNameATOM[];
-extern const char *ConnectorTypeName[];
-
-void atombios_connector_find_monitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- ErrorF("AGD: atom connector find monitor\n");
-
- if (radeon_output->MonType == MT_UNKNOWN) {
- radeon_output->MonType = atombios_display_ddc_connected(pScrn, output);
- if (!radeon_output->MonType) {
- ErrorF("AGD: No DDC\n");
- if (radeon_output->type == OUTPUT_LVDS || radeon_output->type == OUTPUT_DVI)
- radeon_output->MonType = atombios_port_check_nonddc(pScrn, output);
-#if 0
- if (!radeon_output->MonType) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
- } else if (radeon_output->DACType == DAC_TVDAC) {
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
- }
- }
-#endif
- if (!radeon_output->MonType) {
- radeon_output->MonType = MT_NONE;
- }
- }
- }
- /* update panel info for RMX */
- // if (radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP)
- // RADEONUpdatePanelSize(output);
-
- if (output->MonInfo) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on connector: %s ----------------------\n",
- info->IsAtomBios ?
- ConnectorTypeNameATOM[radeon_output->ConnectorType]:
- ConnectorTypeName[radeon_output->ConnectorType]
- );
- xf86PrintEDID( output->MonInfo );
- }
-}
diff --git a/src/radeon_output.c b/src/radeon_output.c
index eb1abe4..706f9ab 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -154,11 +154,13 @@ static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color
static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color);
static RADEONMonitorType radeon_detect_ext_dac(ScrnInfoPtr pScrn);
static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output);
+static Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state);
extern void atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr mode,
DisplayModePtr adjusted_mode);
extern void atombios_output_dpms(xf86OutputPtr output, int mode);
+extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output);
Bool
RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch)
@@ -269,6 +271,42 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn)
}
static RADEONMonitorType
+avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned long DDCReg;
+ RADEONMonitorType MonType = MT_NONE;
+ xf86MonPtr MonInfo = NULL;
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONDDCType DDCType = radeon_output->DDCType;
+
+ AVIVOI2CDoLock(output->scrn, 1);
+ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
+ AVIVOI2CDoLock(output->scrn, 0);
+ if (MonInfo) {
+ if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
+ xf86OutputSetEDID(output, MonInfo);
+ if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_LVDS_ATOM) ||
+ (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_PROPRIETARY)) {
+ MonType = MT_LCD;
+ } else if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM) ||
+ (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D)) {
+ MonType = MT_DFP;
+ } else if (radeon_output->type == OUTPUT_DVI &&
+ (MonInfo->rawData[0x14] & 0x80)) { /* if it's digital and DVI */
+ MonType = MT_DFP;
+ } else {
+ MonType = MT_CRT;
+ }
+ } else MonType = MT_NONE;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DDC Type: %d[%04x], Detected Monitor Type: %d\n", DDCType, radeon_output->gpio, MonType);
+
+ return MonType;
+}
+
+static RADEONMonitorType
RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -635,22 +673,39 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
radeon_output->MonType = MT_NONE;
}
} else {
- radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output);
+ if (IS_AVIVO_VARIANT)
+ radeon_output->MonType = avivo_display_ddc_connected(pScrn, output);
+ else
+ radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output);
if (!radeon_output->MonType) {
- if (radeon_output->type == OUTPUT_LVDS || radeon_output->type == OUTPUT_DVI)
- radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output);
- if (!radeon_output->MonType) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- if (radeon_output->load_detection)
- radeon_output->MonType = radeon_detect_primary_dac(pScrn, TRUE);
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (radeon_output->load_detection) {
- if (info->ChipFamily == CHIP_FAMILY_R200)
- radeon_output->MonType = radeon_detect_ext_dac(pScrn);
- else
- radeon_output->MonType = radeon_detect_tv_dac(pScrn, TRUE);
- } else
- radeon_output->MonType = MT_NONE;
+ if (IS_AVIVO_VARIANT) {
+ if (!radeon_output->MonType) {
+ if (radeon_output->type == OUTPUT_LVDS)
+ radeon_output->MonType = MT_LCD;
+ if (!radeon_output->MonType) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
+ }
+ }
+ }
+ } else {
+ if (radeon_output->type == OUTPUT_LVDS || radeon_output->type == OUTPUT_DVI)
+ radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output);
+ if (!radeon_output->MonType) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ if (radeon_output->load_detection)
+ radeon_output->MonType = radeon_detect_primary_dac(pScrn, TRUE);
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ if (radeon_output->load_detection) {
+ if (info->ChipFamily == CHIP_FAMILY_R200)
+ radeon_output->MonType = radeon_detect_ext_dac(pScrn);
+ else
+ radeon_output->MonType = radeon_detect_tv_dac(pScrn, TRUE);
+ } else
+ radeon_output->MonType = MT_NONE;
+ }
}
}
}
@@ -1216,9 +1271,6 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
static void
radeon_mode_commit(xf86OutputPtr output)
{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
radeon_dpms(output, DPMSModeOn);
}
@@ -2239,6 +2291,138 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output
radeon_output->type = output;
}
+static
+Bool AVIVOI2CReset(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ OUTREG(AVIVO_I2C_STOP, 1);
+ INREG(AVIVO_I2C_STOP);
+ OUTREG(AVIVO_I2C_STOP, 0x0);
+ return TRUE;
+}
+
+static
+Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CARD32 temp;
+
+ switch(lock_state) {
+ case 0:
+ temp = INREG(AVIVO_I2C_CNTL);
+ OUTREG(AVIVO_I2C_CNTL, temp | 0x100);
+ /* enable hdcp block */
+ OUTREG(R520_PCLK_HDCP_CNTL, 0x0);
+ break;
+ case 1:
+ /* disable hdcp block */
+ OUTREG(R520_PCLK_HDCP_CNTL, 0x1);
+ usleep(1);
+ OUTREG(AVIVO_I2C_CNTL, 0x1);
+ usleep(1);
+ temp = INREG(AVIVO_I2C_CNTL);
+ if (!(temp & 0x2)) {
+ ErrorF("Lock failed %08X\n", temp);
+ return FALSE;
+ }
+ break;
+ }
+ return TRUE;
+}
+
+void
+avivo_i2c_gpio0_get_bits(I2CBusPtr b, int *Clock, int *data)
+{
+ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(screen_info);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long val;
+
+ ErrorF("INREG %08x\n", INREG(b->DriverPrivate.uval));
+ /* Get the result */
+ val = INREG(b->DriverPrivate.uval + 0xC);
+ *Clock = (val & (1<<19)) != 0;
+ *data = (val & (1<<18)) != 0;
+}
+
+void
+avivo_i2c_gpio0_put_bits(I2CBusPtr b, int Clock, int data)
+{
+ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(screen_info);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long val;
+
+ val = 0;
+ val |= (Clock ? 0:(1<<19));
+ val |= (data ? 0:(1<<18));
+ OUTREG(b->DriverPrivate.uval + 0x8, val);
+ /* read back to improve reliability on some cards. */
+ val = INREG(b->DriverPrivate.uval + 0x8);
+}
+
+void
+avivo_i2c_gpio123_get_bits(I2CBusPtr b, int *Clock, int *data)
+{
+ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(screen_info);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long val;
+
+ if (INREG(b->DriverPrivate.uval) == 0)
+ OUTREG(b->DriverPrivate.uval, (1<<0) | (1<<8));
+
+ /* Get the result */
+ val = INREG(b->DriverPrivate.uval + 0xC);
+ *Clock = (val & (1<<0)) != 0;
+ *data = (val & (1<<8)) != 0;
+}
+
+static void
+avivo_i2c_gpio123_put_bits(I2CBusPtr b, int Clock, int data)
+{
+ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(screen_info);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long val;
+
+ val = 0;
+ val |= (Clock ? 0:(1<<0));
+ val |= (data ? 0:(1<<8));
+ OUTREG(b->DriverPrivate.uval + 0x8, val);
+ /* read back to improve reliability on some cards. */
+ val = INREG(b->DriverPrivate.uval + 0x8);
+}
+
+static Bool
+avivo_i2c_init(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
+{
+ I2CBusPtr pI2CBus;
+
+ pI2CBus = xf86CreateI2CBusRec();
+ if (!pI2CBus) return FALSE;
+
+ pI2CBus->BusName = name;
+ pI2CBus->scrnIndex = pScrn->scrnIndex;
+ if (i2c_reg == AVIVO_GPIO_0) {
+ pI2CBus->I2CPutBits = avivo_i2c_gpio0_put_bits;
+ pI2CBus->I2CGetBits = avivo_i2c_gpio0_get_bits;
+ } else {
+ pI2CBus->I2CPutBits = avivo_i2c_gpio123_put_bits;
+ pI2CBus->I2CGetBits = avivo_i2c_gpio123_get_bits;
+ }
+ pI2CBus->AcknTimeout = 5;
+ pI2CBus->DriverPrivate.uval = i2c_reg;
+
+ if (!xf86I2CBusInit(pI2CBus)) return FALSE;
+
+ *bus_ptr = pI2CBus;
+ return TRUE;
+}
+
static void RADEONI2CGetBits(I2CBusPtr b, int *Clock, int *data)
{
ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
@@ -2592,18 +2776,28 @@ RADEONGetTVInfo(xf86OutputPtr output)
void RADEONInitConnector(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
int DDCReg = 0;
char* name = (char*) DDCTypeName[radeon_output->DDCType];
- switch(radeon_output->DDCType) {
- case DDC_MONID: DDCReg = RADEON_GPIO_MONID; break;
- case DDC_DVI : DDCReg = RADEON_GPIO_DVI_DDC; break;
- case DDC_VGA : DDCReg = RADEON_GPIO_VGA_DDC; break;
- case DDC_CRT2 : DDCReg = RADEON_GPIO_CRT2_DDC; break;
- case DDC_LCD : DDCReg = RADEON_LCD_GPIO_MASK; break;
- case DDC_GPIO : DDCReg = RADEON_MDGPIO_EN_REG; break;
- default: break;
+ if (IS_AVIVO_VARIANT) {
+ if (radeon_output->gpio)
+ avivo_i2c_init(pScrn, &radeon_output->pI2CBus, radeon_output->gpio, name);
+ } else {
+ switch(radeon_output->DDCType) {
+ case DDC_MONID: DDCReg = RADEON_GPIO_MONID; break;
+ case DDC_DVI : DDCReg = RADEON_GPIO_DVI_DDC; break;
+ case DDC_VGA : DDCReg = RADEON_GPIO_VGA_DDC; break;
+ case DDC_CRT2 : DDCReg = RADEON_GPIO_CRT2_DDC; break;
+ case DDC_LCD : DDCReg = RADEON_LCD_GPIO_MASK; break;
+ case DDC_GPIO : DDCReg = RADEON_MDGPIO_EN_REG; break;
+ default: break;
+ }
+ if (DDCReg) {
+ radeon_output->DDCReg = DDCReg;
+ RADEONI2CInit(pScrn, &radeon_output->pI2CBus, DDCReg, name);
+ }
}
if (radeon_output->DACType == DAC_PRIMARY)
@@ -2614,11 +2808,6 @@ void RADEONInitConnector(xf86OutputPtr output)
else
radeon_output->load_detection = 0; /* shared tvdac between vga/dvi/tv */
- if (DDCReg) {
- radeon_output->DDCReg = DDCReg;
- RADEONI2CInit(pScrn, &radeon_output->pI2CBus, DDCReg, name);
- }
-
if (radeon_output->type == OUTPUT_LVDS) {
radeon_output->rmx_type = RMX_FULL;
RADEONGetLVDSInfo(output);
commit 68e7f5c67e2e9d2162b469ce31f452f3f89756b5
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 6 23:43:29 2007 -0500
more avivo updates
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 125b6dd..baa8c1b 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -17,6 +17,12 @@
#include "radeon_macros.h"
#include "radeon_atombios.h"
+#ifdef XF86DRI
+#define _XF86DRI_SERVER_
+#include "radeon_dri.h"
+#include "radeon_sarea.h"
+#include "sarea.h"
+#endif
AtomBiosResult
atombios_enable_crtc(atomBIOSHandlePtr atomBIOS, int crtc, int state)
@@ -348,23 +354,39 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
void
atombios_crtc_mode_set(xf86CrtcPtr crtc,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode,
- int x, int y)
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode,
+ int x, int y)
{
- ScrnInfoPtr screen_info = crtc->scrn;
+ ScrnInfoPtr pScrn = crtc->scrn;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
int regval;
AtomBiosResult atom_res;
RADEONSavePtr restore = &info->ModeReg;
+ Bool tilingOld = info->tilingEnabled;
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
memset(&crtc_timing, 0, sizeof(crtc_timing));
+ if (info->allowColorTiling) {
+ info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
+#ifdef XF86DRI
+ if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
+ RADEONSAREAPrivPtr pSAREAPriv;
+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "[drm] failed changing tiling status\n");
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
+ info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
+ }
+#endif
+ }
+
crtc_timing.ucCRTC = radeon_crtc->crtc_id;
crtc_timing.usH_Total = adjusted_mode->CrtcHTotal;
crtc_timing.usH_Disp = adjusted_mode->CrtcHDisplay;
@@ -387,7 +409,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
if (IS_AVIVO_VARIANT) {
radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay;
- radeon_crtc->fb_height = screen_info->virtualY;
+ radeon_crtc->fb_height = pScrn->virtualY;
radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay;
radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4;
switch (crtc->scrn->bitsPerPixel) {
@@ -434,5 +456,16 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
atombios_crtc_set_pll(crtc, adjusted_mode);
+ if (info->tilingEnabled != tilingOld) {
+ /* need to redraw front buffer, I guess this can be considered a hack ? */
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE);
+ RADEONChangeSurfaces(pScrn);
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE);
+ /* xf86SetRootClip would do, but can't access that here */
+ }
+
}
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 64e03e1..397942a 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -54,13 +54,13 @@
#endif
void radeon_crtc_load_lut(xf86CrtcPtr crtc);
-#if 0
+
extern void atombios_crtc_mode_set(xf86CrtcPtr crtc,
DisplayModePtr mode,
DisplayModePtr adjusted_mode,
int x, int y);
extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode);
-#endif
+
static void
radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
{
@@ -70,12 +70,10 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
-#if 0
- if (info->IsAtomBios) {
+ if (IS_AVIVO_VARIANT) {
atombios_crtc_dpms(crtc, mode);
return;
}
-#endif
mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS);
@@ -799,7 +797,7 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore)
}
static void
-radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
+legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
DisplayModePtr adjusted_mode, int x, int y)
{
ScrnInfoPtr pScrn = crtc->scrn;
@@ -828,13 +826,6 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
#endif
}
-#if 0
- if (info->IsAtomBios) {
- atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
- return;
- }
-#endif
-
for (i = 0; i < xf86_config->num_output; i++) {
xf86OutputPtr output = xf86_config->output[i];
RADEONOutputPrivatePtr radeon_output = output->driver_private;
@@ -916,18 +907,18 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
ErrorF("restore crtc1\n");
RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
ErrorF("restore pll1\n");
- if (info->IsAtomBios)
+ /*if (info->IsAtomBios)
atombios_crtc_set_pll(crtc, adjusted_mode);
- else
+ else*/
RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
break;
case 1:
ErrorF("restore crtc2\n");
RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg);
ErrorF("restore pll2\n");
- if (info->IsAtomBios)
+ /*if (info->IsAtomBios)
atombios_crtc_set_pll(crtc, adjusted_mode);
- else
+ else*/
RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
break;
}
@@ -956,6 +947,20 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
}
static void
+radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode, int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ if (IS_AVIVO_VARIANT) {
+ atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
+ } else {
+ legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
+ }
+}
+
+static void
radeon_crtc_mode_commit(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
@@ -990,8 +995,13 @@ radeon_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green,
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
int i, j;
+ // fix me
+ if (IS_AVIVO_VARIANT)
+ return;
+
if (pScrn->depth == 16) {
for (i = 0; i < 64; i++) {
if (i <= 31) {
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 8fccd88..9914446 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -3470,9 +3470,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONSave(pScrn);
- RADEONDisableDisplays(pScrn);
+ if (!IS_AVIVO_VARIANT)
+ RADEONDisableDisplays(pScrn);
- if (info->IsMobility) {
+ if (info->IsMobility && !IS_AVIVO_VARIANT) {
if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
RADEONSetDynamicClock(pScrn, 1);
} else {
diff --git a/src/radeon_output.c b/src/radeon_output.c
index be542a4..eb1abe4 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -154,12 +154,11 @@ static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color
static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color);
static RADEONMonitorType radeon_detect_ext_dac(ScrnInfoPtr pScrn);
static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output);
-#if 0
+
extern void atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr mode,
DisplayModePtr adjusted_mode);
extern void atombios_output_dpms(xf86OutputPtr output, int mode);
-#endif
Bool
RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch)
@@ -715,12 +714,10 @@ radeon_dpms(xf86OutputPtr output, int mode)
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
-#if 0
- if (info->IsAtomBios) {
+ if (IS_AVIVO_VARIANT) {
atombios_output_dpms(output, mode);
return;
}
-#endif
switch(mode) {
case DPMSModeOn:
@@ -1160,7 +1157,7 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
}
static void
-radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
+legacy_mode_set(xf86OutputPtr output, DisplayModePtr mode,
DisplayModePtr adjusted_mode)
{
ScrnInfoPtr pScrn = output->scrn;
@@ -1169,15 +1166,6 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
xf86CrtcPtr crtc = output->crtc;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-#if 0
- if (info->IsAtomBios) {
- ErrorF("AGD: output mode set start\n");
- atombios_output_mode_set(output, mode, adjusted_mode);
- ErrorF("AGD: output mode set end\n");
- return;
- }
-#endif
-
RADEONInitOutputRegisters(pScrn, &info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id);
if (radeon_crtc->crtc_id == 0)
@@ -1209,14 +1197,19 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
RADEONRestoreDACRegisters(pScrn, &info->ModeReg);
}
-#if 0
- if (info->IsAtomBios) {
- ErrorF("AGD: output mode set start\n");
+}
+
+static void
+radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ if (IS_AVIVO_VARIANT)
atombios_output_mode_set(output, mode, adjusted_mode);
- ErrorF("AGD: output mode set end\n");
- //return;
- }
-#endif
+ else
+ legacy_mode_set(output, mode, adjusted_mode);
}
@@ -1225,12 +1218,8 @@ radeon_mode_commit(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
-#if 0
- if (info->IsAtomBios)
- atombios_output_dpms(output, DPMSModeOn);
- else
-#endif
- RADEONEnableDisplay(output, TRUE);
+
+ radeon_dpms(output, DPMSModeOn);
}
/* the following functions are based on the load detection code
commit 303562dfb57e13c027b2aa9289d54e547c829ff1
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 6 23:06:46 2007 -0500
add additional connector types
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 78fc9ff..3b493b8 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -97,6 +97,11 @@ typedef enum
CONNECTOR_CTV_ATOM,
CONNECTOR_LVDS_ATOM,
CONNECTOR_DIGITAL_ATOM,
+ CONNECTOR_SCART_ATOM,
+ CONNECTOR_HDMI_TYPE_A_ATOM,
+ CONNECTOR_HDMI_TYPE_B_ATOM,
+ CONNECTOR_CASE_1_ATOM,
+ CONNECTOR_DISPLAY_PORT_ATOM,
CONNECTOR_UNSUPPORTED_ATOM
} RADEONConnectorTypeATOM;
commit 0d3e0735f710cb7b9505e4330997aa332f73c102
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 6 22:59:25 2007 -0500
First round of avivo support
diff --git a/src/atipciids.h b/src/atipciids.h
index 2aa8a3e..ab74492 100644
--- a/src/atipciids.h
+++ b/src/atipciids.h
@@ -286,6 +286,9 @@
#define PCI_CHIP_RS350_7834 0x7834
#define PCI_CHIP_RS350_7835 0x7835
+#define PCI_CHIP_RV515_7142 0x7142
+
+
/* Misc */
#define PCI_CHIP_AMD761 0x700E
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 8c0f5c1..125b6dd 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -14,7 +14,6 @@
#include "radeon.h"
#include "radeon_reg.h"
-#include "avivo_reg.h"
#include "radeon_macros.h"
#include "radeon_atombios.h"
@@ -289,25 +288,21 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
unsigned char *space;
RADEONSavePtr save = &info->ModeReg;
- PLLCalculate(mode->Clock, &ref_div, &fb_div, &post_div);
-
- xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
- "crtc(%d) Clock: mode %d, PLL %d\n",
- radeon_crtc->crtc_id, mode->Clock, sclock);
- xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
- "crtc(%d) PLL : refdiv %d, fbdiv 0x%X(%d), pdiv %d\n",
- radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
-
- xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
- "AGD: crtc(%d) PLL : refdiv %d, fbdiv 0x%X(%d), pdiv %d\n",
- radeon_crtc->crtc_id, save->ppll_ref_div, save->feedback_div, save->feedback_div, save->post_div);
-
- if (1) {
+ if (IS_AVIVO_VARIANT) {
+ PLLCalculate(mode->Clock, &ref_div, &fb_div, &post_div);
+ } else {
fb_div = save->feedback_div;
post_div = save->post_div;
ref_div = save->ppll_ref_div;
}
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) Clock: mode %d, PLL %d\n",
+ radeon_crtc->crtc_id, mode->Clock, sclock);
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) PLL : refdiv %d, fbdiv 0x%X(%d), pdiv %d\n",
+ radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
+
atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
ErrorF("table is %d %d\n", major, minor);
@@ -390,7 +385,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
- if (0) {
+ if (IS_AVIVO_VARIANT) {
radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay;
radeon_crtc->fb_height = screen_info->virtualY;
radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay;
@@ -441,96 +436,3 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
}
-
-
-static void
-atombios_setup_cursor(ScrnInfoPtr pScrn, int id, int enable)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- if (id == 0) {
- OUTREG(AVIVO_CURSOR1_CNTL, 0);
-
- if (enable) {
- OUTREG(AVIVO_CURSOR1_LOCATION, info->fbLocation +
- info->cursor_offset);
- OUTREG(AVIVO_CURSOR1_SIZE, ((info->cursor_width -1) << 16) |
- (info->cursor_height-1));
- OUTREG(AVIVO_CURSOR1_CNTL, AVIVO_CURSOR_EN |
- (AVIVO_CURSOR_FORMAT_ARGB <<
- AVIVO_CURSOR_FORMAT_SHIFT));
- }
- }
-}
-
-void
-atombios_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y)
-{
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int crtc_id = radeon_crtc->crtc_id;
-
- if (x < 0)
- x = 0;
- if (y < 0)
- y = 0;
-
- OUTREG(AVIVO_CURSOR1_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
- radeon_crtc->cursor_x = x;
- radeon_crtc->cursor_y = y;
-}
-
-
-void
-atombios_crtc_show_cursor(xf86CrtcPtr crtc)
-{
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
-#ifdef XF86DRI
- if (info->CPStarted && crtc->scrn->pScreen) DRILock(crtc->scrn->pScreen, 0);
-#endif
-
- RADEON_SYNC(info, crtc->scrn);
-
- OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset,
- INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset)
- | AVIVO_CURSOR_EN);
- atombios_setup_cursor(crtc->scrn, radeon_crtc->crtc_id, 1);
-
-#ifdef XF86DRI
- if (info->CPStarted && crtc->scrn->pScreen) DRIUnlock(crtc->scrn->pScreen);
-#endif
-}
-
-void
-atombios_crtc_hide_cursor(xf86CrtcPtr crtc)
-{
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
-#ifdef XF86DRI
- if (info->CPStarted && crtc->scrn->pScreen) DRILock(crtc->scrn->pScreen, 0);
-#endif
-
- RADEON_SYNC(info, crtc->scrn);
-
- OUTREG(AVIVO_CURSOR1_CNTL+ radeon_crtc->crtc_offset,
- INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset)
- & ~(AVIVO_CURSOR_EN));
- atombios_setup_cursor(crtc->scrn, radeon_crtc->crtc_id, 0);
-
-#ifdef XF86DRI
- if (info->CPStarted && crtc->scrn->pScreen) DRIUnlock(crtc->scrn->pScreen);
-#endif
-}
-
-static void
-atombios_crtc_destroy(xf86CrtcPtr crtc)
-{
- if (crtc->driver_private)
- xfree(crtc->driver_private);
-}
diff --git a/src/avivo_reg.h b/src/avivo_reg.h
index f2bdc96..0a53303 100644
--- a/src/avivo_reg.h
+++ b/src/avivo_reg.h
@@ -5,7 +5,6 @@
* DACs (be it TV or VGA) and TMDS transmitters take their input from
* the CRTC.
*/
-#define IS_AVIVO_VARIANT 1
/* Core engine. */
#define AVIVO_ENGINE_STATUS 0x0014
diff --git a/src/radeon.h b/src/radeon.h
index 1d2235c..766c174 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -198,7 +198,110 @@ typedef struct {
CARD16 rr4_offset;
} RADEONBIOSInitTable;
+struct avivo_state
+{
+ CARD32 hdp_fb_location;
+ CARD32 mc_memory_map;
+ CARD32 vga_memory_base;
+ CARD32 vga_fb_start;
+
+ CARD32 vga1_cntl;
+ CARD32 vga2_cntl;
+
+ CARD32 pll1_post_div_cntl;
+ CARD32 pll1_post_div;
+ CARD32 pll1_post_div_mystery;
+ CARD32 pll1_post_mul;
+ CARD32 pll1_divider_cntl;
+ CARD32 pll1_divider;
+ CARD32 pll1_mystery0;
+ CARD32 pll1_mystery1;
+
+ CARD32 pll2_post_div_cntl;
+ CARD32 pll2_post_div;
+ CARD32 pll2_post_div_mystery;
+ CARD32 pll2_post_mul;
+ CARD32 pll2_divider_cntl;
+ CARD32 pll2_divider;
+ CARD32 pll2_mystery0;
+ CARD32 pll2_mystery1;
+
+ CARD32 crtc_pll_source;
+ CARD32 crtc1_h_total;
+ CARD32 crtc1_h_blank;
+ CARD32 crtc1_h_sync_wid;
+ CARD32 crtc1_h_sync_pol;
+ CARD32 crtc1_v_total;
+ CARD32 crtc1_v_blank;
+ CARD32 crtc1_v_sync_wid;
+ CARD32 crtc1_v_sync_pol;
+ CARD32 crtc1_cntl;
+ CARD32 crtc1_blank_status;
+ CARD32 crtc1_stereo_status;
+ CARD32 crtc1_scan_enable;
+ CARD32 crtc1_fb_format;
+ CARD32 crtc1_fb_location;
+ CARD32 crtc1_fb_end;
+ CARD32 crtc1_pitch;
+ CARD32 crtc1_x_length;
+ CARD32 crtc1_y_length;
+ CARD32 crtc1_fb_height;
+ CARD32 crtc1_offset_start;
+ CARD32 crtc1_offset_end;
+ CARD32 crtc1_expn_size;
+ CARD32 crtc1_expn_cntl;
+ CARD32 crtc1_6594;
+ CARD32 crtc1_659c;
+ CARD32 crtc1_65a4;
+ CARD32 crtc1_65a8;
+ CARD32 crtc1_65ac;
+ CARD32 crtc1_65b0;
+ CARD32 crtc1_65b8;
+ CARD32 crtc1_65bc;
+ CARD32 crtc1_65c0;
+ CARD32 crtc1_65c8;
+
+ CARD32 crtc2_h_total;
+ CARD32 crtc2_h_blank;
+ CARD32 crtc2_h_sync_wid;
+ CARD32 crtc2_h_sync_pol;
+ CARD32 crtc2_v_total;
+ CARD32 crtc2_v_blank;
+ CARD32 crtc2_v_sync_wid;
+ CARD32 crtc2_v_sync_pol;
+ CARD32 crtc2_cntl;
+ CARD32 crtc2_blank_status;
+ CARD32 crtc2_scan_enable;
+ CARD32 crtc2_fb_format;
+ CARD32 crtc2_fb_location;
+ CARD32 crtc2_fb_end;
+ CARD32 crtc2_pitch;
+ CARD32 crtc2_x_length;
+ CARD32 crtc2_y_length;
+
+ CARD32 dac1_cntl;
+ CARD32 dac1_force_output_cntl;
+ CARD32 dac1_powerdown;
+
+ CARD32 tmds1_cntl;
+ CARD32 tmds1_bit_depth_cntl;
+ CARD32 tmds1_data_sync;
+ CARD32 tmds1_transmitter_enable;
+ CARD32 tmds1_transmitter_cntl;
+
+ CARD32 dac2_cntl;
+ CARD32 dac2_force_output_cntl;
+ CARD32 dac2_powerdown;
+
+ CARD32 tmds2_cntl;
+ CARD32 tmds2_bit_depth_cntl;
+ CARD32 tmds2_data_sync;
+ CARD32 tmds2_transmitter_enable;
+ CARD32 tmds2_transmitter_cntl;
+};
+
typedef struct {
+ struct avivo_state avivo;
/* Common registers */
CARD32 ovr_clr;
CARD32 ovr_wid_left_right;
@@ -399,6 +502,9 @@ typedef enum {
CHIP_FAMILY_R420, /* R420/R423/M18 */
CHIP_FAMILY_RV410, /* RV410, M26 */
CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */
+ CHIP_FAMILY_RV515, /* rv515 */
+ CHIP_FAMILY_R520, /* r520 */
+ CHIP_FAMILY_R600, /* r60 */
CHIP_FAMILY_LAST
} RADEONChipFamily;
@@ -419,6 +525,8 @@ typedef enum {
(info->ChipFamily == CHIP_FAMILY_RV410) || \
(info->ChipFamily == CHIP_FAMILY_RS400))
+#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515))
+
/*
* Errata workarounds
*/
@@ -858,6 +966,9 @@ extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data);
+extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
+extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data);
+
extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 6028aff..eb833fb 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -250,7 +250,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn)
host_path_cntl = INREG(RADEON_HOST_PATH_CNTL);
rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
- if (IS_R300_VARIANT) {
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
CARD32 tmp;
OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
@@ -284,7 +284,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn)
INREG(RADEON_HOST_PATH_CNTL);
OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl);
- if (!IS_R300_VARIANT)
+ if (!IS_R300_VARIANT && !IS_AVIVO_VARIANT)
OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c
index 212131f..6fbbc13 100644
--- a/src/radeon_accelfuncs.c
+++ b/src/radeon_accelfuncs.c
@@ -1309,7 +1309,7 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
a->CPUToScreenTextureFormats = RADEONTextureFormats;
a->CPUToScreenTextureDstFormats = RADEONDstFormats;
- if (IS_R300_VARIANT) {
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
"unsupported on Radeon 9500/9700 and newer.\n");
} else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 972001b..9218079 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -179,6 +179,8 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
crtc = (portinfo >> 8) & 0xf;
tmp0 = RADEON_BIOS16(info->MasterDataStart + 24);
gpio = RADEON_BIOS16(tmp0 + 4 + 27 * crtc) * 4;
+ info->BiosConnector[i].gpio = gpio;
+
switch(gpio) {
case RADEON_GPIO_MONID:
info->BiosConnector[i].DDCType = DDC_MONID;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 4a017c0..64e03e1 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -1252,6 +1252,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn)
pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
pRADEONEnt->Controller[0]->crtc_id = 0;
+ pRADEONEnt->Controller[0]->crtc_offset = 0;
if (!pRADEONEnt->HasCRTC2)
return TRUE;
@@ -1269,6 +1270,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn)
pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
pRADEONEnt->Controller[1]->crtc_id = 1;
+ pRADEONEnt->Controller[0]->crtc_offset = AVIVO_CRTC2_H_TOTAL - AVIVO_CRTC1_H_TOTAL;
return TRUE;
}
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 3e60d23..d46c098 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -89,6 +89,25 @@
#endif
+static void
+avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset, 0);
+
+ if (enable) {
+ OUTREG(AVIVO_CURSOR1_LOCATION + radeon_crtc->crtc_offset,
+ info->fbLocation + info->cursor_offset);
+ OUTREG(AVIVO_CURSOR1_SIZE + radeon_crtc->crtc_offset,
+ ((info->cursor_width -1) << 16) | (info->cursor_height-1));
+ OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset,
+ AVIVO_CURSOR_EN | (AVIVO_CURSOR_FORMAT_ARGB << AVIVO_CURSOR_FORMAT_SHIFT));
+ }
+}
+
void
radeon_crtc_show_cursor (xf86CrtcPtr crtc)
{
@@ -104,12 +123,19 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc)
RADEON_SYNC(info, pScrn);
- if (crtc_id == 0)
- OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN | 2 << 20,
- ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
- else if (crtc_id == 1)
- OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN | 2 << 20,
- ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_CUR_MODE_MASK));
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset,
+ INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset)
+ | AVIVO_CURSOR_EN);
+ avivo_setup_cursor(crtc, TRUE);
+ } else {
+ if (crtc_id == 0)
+ OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN | 2 << 20,
+ ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
+ else if (crtc_id == 1)
+ OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN | 2 << 20,
+ ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_CUR_MODE_MASK));
+ }
#ifdef XF86DRI
if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
@@ -131,10 +157,17 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
RADEON_SYNC(info, pScrn);
- if (crtc_id == 0)
- OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_CUR_EN);
- else if (crtc_id == 1)
- OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN);
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_CURSOR1_CNTL+ radeon_crtc->crtc_offset,
+ INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset)
+ & ~(AVIVO_CURSOR_EN));
+ avivo_setup_cursor(crtc, FALSE);
+ } else {
+ if (crtc_id == 0)
+ OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_CUR_EN);
+ else if (crtc_id == 1)
+ OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN);
+ }
#ifdef XF86DRI
if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
@@ -163,30 +196,40 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
else if (mode->Flags & V_DBLSCAN)
y *= 2;
- if (crtc_id == 0) {
- OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK
- | (xorigin << 16)
- | yorigin));
- OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK
- | ((xorigin ? 0 : x) << 16)
- | (yorigin ? 0 : y)));
- RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
- OUTREG(RADEON_CUR_OFFSET,
- info->cursor_offset + pScrn->fbOffset + yorigin * stride);
- } else if (crtc_id == 1) {
- OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK
- | (xorigin << 16)
- | yorigin));
- OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK
- | ((xorigin ? 0 : x) << 16)
- | (yorigin ? 0 : y)));
- RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
- OUTREG(RADEON_CUR2_OFFSET,
- info->cursor_offset + pScrn->fbOffset + yorigin * stride);
+ if (IS_AVIVO_VARIANT) {
+ if (x < 0)
+ x = 0;
+ if (y < 0)
+ y = 0;
+
+ OUTREG(AVIVO_CURSOR1_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
+ radeon_crtc->cursor_x = x;
+ radeon_crtc->cursor_y = y;
+ } else {
+ if (crtc_id == 0) {
+ OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK
+ | (xorigin << 16)
+ | yorigin));
+ OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK
+ | ((xorigin ? 0 : x) << 16)
+ | (yorigin ? 0 : y)));
+ RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
+ info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
+ OUTREG(RADEON_CUR_OFFSET,
+ info->cursor_offset + pScrn->fbOffset + yorigin * stride);
+ } else if (crtc_id == 1) {
+ OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK
+ | (xorigin << 16)
+ | yorigin));
+ OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK
+ | ((xorigin ? 0 : x) << 16)
+ | (yorigin ? 0 : y)));
+ RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
+ info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
+ OUTREG(RADEON_CUR2_OFFSET,
+ info->cursor_offset + pScrn->fbOffset + yorigin * stride);
+ }
}
-
}
void
@@ -270,10 +313,11 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
#ifdef USE_XAA
if (!info->useEXA) {
+ int align = IS_AVIVO_VARIANT ? 4096 : 256;
FBAreaPtr fbarea;
fbarea = xf86AllocateOffscreenArea(pScreen, width, height,
- 256, NULL, NULL, NULL);
+ align, NULL, NULL, NULL);
if (!fbarea) {
info->cursor_offset = 0;
@@ -284,7 +328,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
info->cursor_offset = RADEON_ALIGN((fbarea->box.x1 +
fbarea->box.y1 * width) *
info->CurrentLayout.pixel_bytes,
- 256);
+ align);
info->cursor_end = info->cursor_offset + size_bytes;
}
RADEONCTRACE(("RADEONCursorInit (0x%08x-0x%08x)\n",
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 04a117b..8fccd88 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -438,18 +438,20 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr)
CARD32 CardTmp;
static struct RADEONInt10Save SaveStruct = { 0, 0, 0 };
- /* Save the values and zap MEM_CNTL */
- SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
- SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
- SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
+ if (!IS_AVIVO_VARIANT) {
+ /* Save the values and zap MEM_CNTL */
+ SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
+ SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
+ SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
- /*
- * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
- */
- OUTREG(RADEON_MEM_CNTL, 0);
- CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu;
- CardTmp |= 0x04 << 24;
- OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
+ /*
+ * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
+ */
+ OUTREG(RADEON_MEM_CNTL, 0);
+ CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu;
+ CardTmp |= 0x04 << 24;
+ OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
+ }
*pPtr = (void *)&SaveStruct;
}
@@ -466,6 +468,9 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr)
if (!pSave || !pSave->MEM_CNTL)
return;
+ if (IS_AVIVO_VARIANT)
+ return;
+
/*
* If either MEM_CNTL is currently zero or inconistent (configured for
* two channels with the two channels configured differently), restore
@@ -723,21 +728,62 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr)
unsigned char *RADEONMMIO = info->MMIO;
CARD32 data;
- OUTREG8(R300_MC_IND_INDEX, addr & 0x3f);
- data = INREG(R300_MC_IND_DATA);
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
+ (void)INREG(AVIVO_MC_INDEX);
+ data = INREG(AVIVO_MC_DATA);
+
+ OUTREG(AVIVO_MC_INDEX, 0);
+ (void)INREG(AVIVO_MC_INDEX);
+ } else {
+ OUTREG8(R300_MC_IND_INDEX, addr & 0x3f);
+ (void)INREG(R300_MC_IND_INDEX);
+ data = INREG(R300_MC_IND_DATA);
+
+ OUTREG(R300_MC_IND_INDEX, 0);
+ (void)INREG(R300_MC_IND_INDEX);
+ }
return data;
}
-/* Write PLL information */
+/* Write MC information */
void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG8(R300_MC_IND_INDEX, (((addr) & 0x3f) |
- R300_MC_IND_WR_EN));
- OUTREG(R300_MC_IND_DATA, data);
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000);
+ (void)INREG(AVIVO_MC_INDEX);
+ OUTREG(AVIVO_MC_DATA, data);
+ OUTREG(AVIVO_MC_INDEX, 0);
+ (void)INREG(AVIVO_MC_INDEX);
+ } else {
+ OUTREG8(R300_MC_IND_INDEX, (((addr) & 0x3f) |
+ R300_MC_IND_WR_EN));
+ (void)INREG(R300_MC_IND_INDEX);
+ OUTREG(R300_MC_IND_DATA, data);
+ OUTREG(R300_MC_IND_INDEX, 0);
+ (void)INREG(R300_MC_IND_INDEX);
+ }
+}
+
+Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
+ return TRUE;
+ else
+ return FALSE;
+ } else {
+ if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE)
+ return TRUE;
+ else
+ return FALSE;
+ }
}
#if 0
@@ -1206,11 +1252,16 @@ static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
RADEONInfoPtr info)
{
- save->mc_fb_location = info->mc_fb_location;
- save->mc_agp_location = info->mc_agp_location;
- save->display_base_addr = info->fbLocation;
- save->display2_base_addr = info->fbLocation;
- save->ov0_base_addr = info->fbLocation;
+ if (IS_AVIVO_VARIANT) {
+ save->mc_fb_location = info->mc_fb_location;
+ save->mc_agp_location = info->mc_agp_location;
+ } else {
+ save->mc_fb_location = info->mc_fb_location;
+ save->mc_agp_location = info->mc_agp_location;
+ save->display_base_addr = info->fbLocation;
+ save->display2_base_addr = info->fbLocation;
+ save->ov0_base_addr = info->fbLocation;
+ }
}
static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
@@ -1220,9 +1271,21 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
CARD32 mem_size;
CARD32 aper_size;
- /* Default to existing values */
- info->mc_fb_location = INREG(RADEON_MC_FB_LOCATION);
- info->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION);
+ if (IS_AVIVO_VARIANT) {
+ if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ info->mc_fb_location = INMC(pScrn, MC01);
+ ErrorF("mc fb is %08X\n", info->mc_fb_location);
+ info->mc_agp_location = INMC(pScrn, MC02);
+ } else {
+ info->mc_fb_location = INMC(pScrn, AVIVO_MC_MEMORY_MAP);
+ ErrorF("mc fb is %08X\n", info->mc_fb_location);
+ info->mc_agp_location = INMC(pScrn, MC05);
+ }
+ } else {
+ /* Default to existing values */
+ info->mc_fb_location = INREG(RADEON_MC_FB_LOCATION);
+ info->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION);
+ }
/* We shouldn't use info->videoRam here which might have been clipped
* but the real video RAM instead
@@ -1376,7 +1439,8 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
info->ChipFamily == CHIP_FAMILY_RV350 ||
info->ChipFamily == CHIP_FAMILY_RV380 ||
info->ChipFamily == CHIP_FAMILY_R420 ||
- info->ChipFamily == CHIP_FAMILY_RV410) {
+ info->ChipFamily == CHIP_FAMILY_RV410 ||
+ IS_AVIVO_VARIANT) {
OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
~RADEON_HDP_APER_CNTL);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -1449,7 +1513,8 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
if (pScrn->videoRam > accessible)
pScrn->videoRam = accessible;
- info->MemCntl = INREG(RADEON_SDRAM_MODE_REG);
+ if (!IS_AVIVO_VARIANT)
+ info->MemCntl = INREG(RADEON_SDRAM_MODE_REG);
info->BusCntl = INREG(RADEON_BUS_CNTL);
RADEONGetVRamType(pScrn);
@@ -1772,6 +1837,10 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->ChipFamily = CHIP_FAMILY_R420; /*CHIP_FAMILY_R480*/
break;
+ case PCI_CHIP_RV515_7142:
+ info->ChipFamily = CHIP_FAMILY_RV515;
+ break;
+
default:
/* Original Radeon/7200 */
info->ChipFamily = CHIP_FAMILY_RADEON;
@@ -2304,7 +2373,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn)
info->allowColorTiling = xf86ReturnOptValBool(info->Options,
OPTION_COLOR_TILING, TRUE);
- if (IS_R300_VARIANT) {
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
/* this may be 4096 on r4xx -- need to double check */
info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/
info->MaxLines = 4096;
@@ -2774,7 +2843,7 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
crtc_max_X = 1600;
crtc_max_Y = 1200;
} else {
- if (IS_R300_VARIANT) {
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
crtc_max_X = 2560;
crtc_max_Y = 1200;
} else {
@@ -3787,9 +3856,11 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONDGAInit(pScreen);
/* Init Xv */
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing Xv\n");
- RADEONInitVideo(pScreen);
+ if (!IS_AVIVO_VARIANT) {
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Initializing Xv\n");
+ RADEONInitVideo(pScreen);
+ }
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
/* Wrap CloseScreen */
@@ -3846,142 +3917,208 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
" MC_AGP_LOCATION : 0x%08x\n",
(unsigned)restore->mc_agp_location);
- /* Write memory mapping registers only if their value change
- * since we must ensure no access is done while they are
- * reprogrammed
- */
- if (INREG(RADEON_MC_FB_LOCATION) != restore->mc_fb_location ||
- INREG(RADEON_MC_AGP_LOCATION) != restore->mc_agp_location) {
- CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl;
- CARD32 old_mc_status, status_idle;
+ if (IS_AVIVO_VARIANT) {
+ CARD32 mc_fb_loc, mc_agp_loc;
+ if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ mc_fb_loc = INMC(pScrn, MC01);
+ ErrorF("%s: save mc is %08x\n", __func__, mc_fb_loc);
+ mc_agp_loc = INMC(pScrn, MC02);
+ } else {
+ mc_fb_loc = INMC(pScrn, AVIVO_MC_MEMORY_MAP);
+ mc_agp_loc = INMC(pScrn, MC05);
+ }
+#if 1
+ /* disable VGA CTRL */
+ OUTREG(AVIVO_D1VGA_CTRL, INREG(AVIVO_D1VGA_CTRL) & ~AVIVO_DVGA_MODE_ENABLE);
+ OUTREG(AVIVO_D2VGA_CTRL, INREG(AVIVO_D2VGA_CTRL) & ~AVIVO_DVGA_MODE_ENABLE);
+#endif
+ if (mc_fb_loc != info->mc_fb_location ||
+ mc_agp_loc != info->mc_agp_location) {
+ CARD32 tmp;
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- " Map Changed ! Applying ...\n");
+ RADEONWaitForIdleMMIO(pScrn);
- /* Make sure engine is idle. We assume the CCE is stopped
- * at this point
- */
- RADEONWaitForIdleMMIO(pScrn);
+ /* Stop display & memory access */
+ tmp = INREG(AVIVO_CRTC1_CNTL);
+ OUTREG(AVIVO_CRTC1_CNTL, tmp & ~AVIVO_CRTC_EN);
- if (info->IsIGP)
- goto igp_no_mcfb;
+ tmp = INREG(AVIVO_CRTC2_CNTL);
+ tmp &= ~AVIVO_CRTC_EN;
+ OUTREG(AVIVO_CRTC2_CNTL, tmp);
- /* Capture MC_STATUS in case things go wrong ... */
- old_mc_status = INREG(RADEON_MC_STATUS);
-
- /* Stop display & memory access */
- ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
- OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
- crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
- OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
- crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
- RADEONWaitForVerticalSync(pScrn);
- OUTREG(RADEON_CRTC_GEN_CNTL,
- (crtc_gen_cntl
- & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN))
- | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
-
- if (pRADEONEnt->HasCRTC2) {
- crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
- RADEONWaitForVerticalSync2(pScrn);
- OUTREG(RADEON_CRTC2_GEN_CNTL,
- (crtc2_gen_cntl
- & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN))
- | RADEON_CRTC2_DISP_REQ_EN_B);
- }
-
- /* Make sure the chip settles down (paranoid !) */
- usleep(100000);
+ tmp = INREG(AVIVO_CRTC2_CNTL);
- /* Wait for MC idle */
- if (IS_R300_VARIANT)
- status_idle = R300_MC_IDLE;
- else
- status_idle = RADEON_MC_IDLE;
+ usleep(10000);
+ timeout = 0;
+ while (!(avivo_get_mc_idle(pScrn))) {
+ if (++timeout > 1000000) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Timeout trying to update memory controller settings !\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "You will probably crash now ... \n");
+ /* Nothing we can do except maybe try to kill the server,
+ * let's wait 2 seconds to leave the above message a chance
+ * to maybe hit the disk and continue trying to setup despite
+ * the MC being non-idle
+ */
+ usleep(2000000);
+ }
+ usleep(10);
+ }
- timeout = 0;
- while (!(INREG(RADEON_MC_STATUS) & status_idle)) {
- if (++timeout > 1000000) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Timeout trying to update memory controller settings !\n");
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "MC_STATUS = 0x%08x (on entry = 0x%08x)\n",
- INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status);
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "You will probably crash now ... \n");
- /* Nothing we can do except maybe try to kill the server,
- * let's wait 2 seconds to leave the above message a chance
- * to maybe hit the disk and continue trying to setup despite
- * the MC being non-idle
- */
- usleep(2000000);
+ if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ OUTMC(pScrn, MC01, info->mc_fb_location);
+ OUTMC(pScrn, MC02, 0x003f0000);
+ (void)INMC(pScrn, MC02);
+ } else {
+ OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, info->mc_fb_location);
+ OUTMC(pScrn, MC05, 0x003f0000);
+ (void)INMC(pScrn, AVIVO_MC_MEMORY_MAP);
}
- usleep(10);
+ OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
+
+ /* Reset the engine and HDP */
+ RADEONEngineReset(pScrn);
}
+ } else {
- /* Update maps, first clearing out AGP to make sure we don't get
- * a temporary overlap
+ /* Write memory mapping registers only if their value change
+ * since we must ensure no access is done while they are
+ * reprogrammed
*/
- OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc);
- OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location);
- igp_no_mcfb:
- OUTREG(RADEON_MC_AGP_LOCATION, restore->mc_agp_location);
- /* Make sure map fully reached the chip */
- (void)INREG(RADEON_MC_FB_LOCATION);
+ if (INREG(RADEON_MC_FB_LOCATION) != restore->mc_fb_location ||
+ INREG(RADEON_MC_AGP_LOCATION) != restore->mc_agp_location) {
+ CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl;
+ CARD32 old_mc_status, status_idle;
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- " Map applied, resetting engine ...\n");
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ " Map Changed ! Applying ...\n");
- /* Reset the engine and HDP */
- RADEONEngineReset(pScrn);
+ /* Make sure engine is idle. We assume the CCE is stopped
+ * at this point
+ */
+ RADEONWaitForIdleMMIO(pScrn);
- /* Make sure we have sane offsets before re-enabling the CRTCs, disable
- * stereo, clear offsets, and wait for offsets to catch up with hw
- */
+ if (info->IsIGP)
+ goto igp_no_mcfb;
- OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL);
- OUTREG(RADEON_CRTC_OFFSET, 0);
- OUTREG(RADEON_CUR_OFFSET, 0);
- timeout = 0;
- while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) {
- if (timeout++ > 1000000) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Timeout waiting for CRTC offset to update !\n");
- break;
+ /* Capture MC_STATUS in case things go wrong ... */
+ old_mc_status = INREG(RADEON_MC_STATUS);
+
+ /* Stop display & memory access */
+ ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
+ OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
+ crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
+ OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
+ crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
+ RADEONWaitForVerticalSync(pScrn);
+ OUTREG(RADEON_CRTC_GEN_CNTL,
+ (crtc_gen_cntl
+ & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN))
+ | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
+
+ if (pRADEONEnt->HasCRTC2) {
+ crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
+ RADEONWaitForVerticalSync2(pScrn);
+ OUTREG(RADEON_CRTC2_GEN_CNTL,
+ (crtc2_gen_cntl
+ & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN))
+ | RADEON_CRTC2_DISP_REQ_EN_B);
}
- usleep(1000);
- }
- if (pRADEONEnt->HasCRTC2) {
- OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL);
- OUTREG(RADEON_CRTC2_OFFSET, 0);
- OUTREG(RADEON_CUR2_OFFSET, 0);
+
+ /* Make sure the chip settles down (paranoid !) */
+ usleep(100000);
+
+ /* Wait for MC idle */
+ if (IS_R300_VARIANT)
+ status_idle = R300_MC_IDLE;
+ else
+ status_idle = RADEON_MC_IDLE;
+
timeout = 0;
- while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) {
+ while (!(INREG(RADEON_MC_STATUS) & status_idle)) {
+ if (++timeout > 1000000) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Timeout trying to update memory controller settings !\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "MC_STATUS = 0x%08x (on entry = 0x%08x)\n",
+ INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status);
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "You will probably crash now ... \n");
+ /* Nothing we can do except maybe try to kill the server,
+ * let's wait 2 seconds to leave the above message a chance
+ * to maybe hit the disk and continue trying to setup despite
+ * the MC being non-idle
+ */
+ usleep(2000000);
+ }
+ usleep(10);
+ }
+
+ /* Update maps, first clearing out AGP to make sure we don't get
+ * a temporary overlap
+ */
+ OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc);
+ OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location);
+ igp_no_mcfb:
+ OUTREG(RADEON_MC_AGP_LOCATION, restore->mc_agp_location);
+ /* Make sure map fully reached the chip */
+ (void)INREG(RADEON_MC_FB_LOCATION);
+
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ " Map applied, resetting engine ...\n");
+
+ /* Reset the engine and HDP */
+ RADEONEngineReset(pScrn);
+
+ /* Make sure we have sane offsets before re-enabling the CRTCs, disable
+ * stereo, clear offsets, and wait for offsets to catch up with hw
+ */
+
+ OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL);
+ OUTREG(RADEON_CRTC_OFFSET, 0);
+ OUTREG(RADEON_CUR_OFFSET, 0);
+ timeout = 0;
+ while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) {
if (timeout++ > 1000000) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Timeout waiting for CRTC2 offset to update !\n");
+ "Timeout waiting for CRTC offset to update !\n");
break;
}
usleep(1000);
}
+ if (pRADEONEnt->HasCRTC2) {
+ OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL);
+ OUTREG(RADEON_CRTC2_OFFSET, 0);
+ OUTREG(RADEON_CUR2_OFFSET, 0);
+ timeout = 0;
+ while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) {
+ if (timeout++ > 1000000) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Timeout waiting for CRTC2 offset to update !\n");
+ break;
+ }
+ usleep(1000);
+ }
+ }
}
- }
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Updating display base addresses...\n");
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Updating display base addresses...\n");
- OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr);
- if (pRADEONEnt->HasCRTC2)
- OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr);
- OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr);
- (void)INREG(RADEON_OV0_BASE_ADDR);
+ OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr);
+ if (pRADEONEnt->HasCRTC2)
+ OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr);
+ OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr);
+ (void)INREG(RADEON_OV0_BASE_ADDR);
- /* More paranoia delays, wait 100ms */
- usleep(100000);
+ /* More paranoia delays, wait 100ms */
+ usleep(100000);
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Memory map updated.\n");
- }
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Memory map updated.\n");
+ }
+}
#ifdef XF86DRI
static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
@@ -3989,11 +4126,45 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
CARD32 fb, agp;
+ int fb_loc_changed;
- fb = INREG(RADEON_MC_FB_LOCATION);
- agp = INREG(RADEON_MC_AGP_LOCATION);
+ if (IS_AVIVO_VARIANT) {
+ if (info->ChipFamily == CHIP_FAMILY_RV515) {
+ fb = INMC(pScrn, MC01);
+ agp = INMC(pScrn, MC02);
+ } else {
+ fb = INMC(pScrn, AVIVO_MC_MEMORY_MAP);
+ agp = INMC(pScrn, MC05);
+ }
+ fb_loc_changed = (fb != info->mc_fb_location);
- if (fb != info->mc_fb_location || agp != info->mc_agp_location) {
+ if (fb_loc_changed || agp != info->mc_agp_location) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "DRI init changed memory map, adjusting ...\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
+ info->mc_fb_location, fb);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
+ info->mc_agp_location, agp);
+ info->mc_fb_location = fb;
+ info->mc_agp_location = agp;
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
+ info->dst_pitch_offset =
+ (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
+ << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
+ RADEONInitMemMapRegisters(pScrn, save, info);
+
+ /* If MC_FB_LOCATION was changed, adjust the various offsets */
+ if (fb_loc_changed)
+ RADEONRestoreMemMapRegisters(pScrn, save);
+ }
+ } else {
+
+ fb = INREG(RADEON_MC_FB_LOCATION);
+ agp = INREG(RADEON_MC_AGP_LOCATION);
+
+ if (fb != info->mc_fb_location || agp != info->mc_agp_location) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"DRI init changed memory map, adjusting ...\n");
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
@@ -4014,6 +4185,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
/* Adjust the various offsets */
RADEONRestoreMemMapRegisters(pScrn, save);
+ }
}
#ifdef USE_EXA
@@ -4907,7 +5079,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
#endif
if (info->ChipFamily < CHIP_FAMILY_R200) {
color_pattern = RADEON_SURF_TILE_COLOR_MACRO;
- } else if (IS_R300_VARIANT) {
+ } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
color_pattern = R300_SURF_TILE_COLOR_MACRO;
} else {
color_pattern = R200_SURF_TILE_COLOR_MACRO;
@@ -4946,7 +5118,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
drmsurfalloc.flags = swap_pattern;
if (info->tilingEnabled) {
- if (IS_R300_VARIANT)
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
drmsurfalloc.flags |= (width_bytes / 8) | color_pattern;
else
drmsurfalloc.flags |= (width_bytes / 16) | color_pattern;
@@ -4971,7 +5143,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP;
else
depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP;
- } else if (IS_R300_VARIANT) {
+ } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
if (depthCpp == 2)
depth_pattern = R300_SURF_TILE_COLOR_MACRO;
else
@@ -4990,7 +5162,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
drmRadeonSurfaceAlloc drmsurfalloc;
drmsurfalloc.size = depthBufferSize;
drmsurfalloc.address = info->depthOffset;
- if (IS_R300_VARIANT)
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern;
else
drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern;
@@ -5008,7 +5180,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
unsigned char *RADEONMMIO = info->MMIO;
/* we don't need anything like WaitForFifo, no? */
if (info->tilingEnabled) {
- if (IS_R300_VARIANT)
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
surf_info |= (width_bytes / 8) | color_pattern;
else
surf_info |= (width_bytes / 16) | color_pattern;
@@ -5344,6 +5516,221 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
#endif
+void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ struct avivo_state *state = &save->avivo;
+
+ state->mc_memory_map = INMC(pScrn, AVIVO_MC_MEMORY_MAP);
+ state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE);
+ state->vga_fb_start = INREG(AVIVO_VGA_FB_START);
+ state->vga1_cntl = INREG(AVIVO_VGA1_CONTROL);
+ state->vga2_cntl = INREG(AVIVO_VGA2_CONTROL);
+
+ state->pll1_post_div_cntl = INREG(AVIVO_PLL1_POST_DIV_CNTL);
+ state->pll1_post_div = INREG(AVIVO_PLL1_POST_DIV);
+ state->pll1_post_div_mystery = INREG(AVIVO_PLL1_POST_DIV_MYSTERY);
+ state->pll1_post_mul = INREG(AVIVO_PLL1_POST_MUL);
+ state->pll1_divider_cntl = INREG(AVIVO_PLL1_DIVIDER_CNTL);
+ state->pll1_divider = INREG(AVIVO_PLL1_DIVIDER);
+ state->pll1_mystery0 = INREG(AVIVO_PLL1_MYSTERY0);
+ state->pll1_mystery1 = INREG(AVIVO_PLL1_MYSTERY1);
+ state->pll2_post_div_cntl = INREG(AVIVO_PLL2_POST_DIV_CNTL);
+ state->pll2_post_div = INREG(AVIVO_PLL2_POST_DIV);
+ state->pll2_post_div_mystery = INREG(AVIVO_PLL2_POST_DIV_MYSTERY);
+ state->pll2_post_mul = INREG(AVIVO_PLL2_POST_MUL);
+ state->pll2_divider_cntl = INREG(AVIVO_PLL2_DIVIDER_CNTL);
+ state->pll2_divider = INREG(AVIVO_PLL2_DIVIDER);
+ state->pll2_mystery0 = INREG(AVIVO_PLL2_MYSTERY0);
+ state->pll2_mystery1 = INREG(AVIVO_PLL2_MYSTERY1);
+ state->crtc_pll_source = INREG(AVIVO_CRTC_PLL_SOURCE);
+
+ state->crtc1_h_total = INREG(AVIVO_CRTC1_H_TOTAL);
+ state->crtc1_h_blank = INREG(AVIVO_CRTC1_H_BLANK);
+ state->crtc1_h_sync_wid = INREG(AVIVO_CRTC1_H_SYNC_WID);
+ state->crtc1_h_sync_pol = INREG(AVIVO_CRTC1_H_SYNC_POL);
+ state->crtc1_v_total = INREG(AVIVO_CRTC1_V_TOTAL);
+ state->crtc1_v_blank = INREG(AVIVO_CRTC1_V_BLANK);
+ state->crtc1_v_sync_wid = INREG(AVIVO_CRTC1_V_SYNC_WID);
+ state->crtc1_v_sync_pol = INREG(AVIVO_CRTC1_V_SYNC_POL);
+ state->crtc1_cntl = INREG(AVIVO_CRTC1_CNTL);
+ state->crtc1_blank_status = INREG(AVIVO_CRTC1_BLANK_STATUS);
+ state->crtc1_stereo_status = INREG(AVIVO_CRTC1_STEREO_STATUS);
+ state->crtc1_scan_enable = INREG(AVIVO_CRTC1_SCAN_ENABLE);
+ state->crtc1_fb_format = INREG(AVIVO_CRTC1_FB_FORMAT);
+ state->crtc1_fb_location = INREG(AVIVO_CRTC1_FB_LOCATION);
+ state->crtc1_fb_end = INREG(AVIVO_CRTC1_FB_END);
+ state->crtc1_pitch = INREG(AVIVO_CRTC1_PITCH);
+ state->crtc1_x_length = INREG(AVIVO_CRTC1_X_LENGTH);
+ state->crtc1_y_length = INREG(AVIVO_CRTC1_Y_LENGTH);
+ state->crtc1_fb_height = INREG(AVIVO_CRTC1_FB_HEIGHT);
+ state->crtc1_offset_start = INREG(AVIVO_CRTC1_OFFSET_START);
+ state->crtc1_offset_end = INREG(AVIVO_CRTC1_OFFSET_END);
+ state->crtc1_expn_size = INREG(AVIVO_CRTC1_EXPANSION_SOURCE);
+ state->crtc1_expn_cntl = INREG(AVIVO_CRTC1_EXPANSION_CNTL);
+ state->crtc1_6594 = INREG(AVIVO_CRTC1_6594);
+ state->crtc1_659c = INREG(AVIVO_CRTC1_659C);
+ state->crtc1_65a4 = INREG(AVIVO_CRTC1_65A4);
+ state->crtc1_65a8 = INREG(AVIVO_CRTC1_65A8);
+ state->crtc1_65ac = INREG(AVIVO_CRTC1_65AC);
+ state->crtc1_65b0 = INREG(AVIVO_CRTC1_65B0);
+ state->crtc1_65b8 = INREG(AVIVO_CRTC1_65B8);
+ state->crtc1_65bc = INREG(AVIVO_CRTC1_65BC);
+ state->crtc1_65c0 = INREG(AVIVO_CRTC1_65C0);
+ state->crtc1_65c8 = INREG(AVIVO_CRTC1_65C8);
+
+ state->crtc2_h_total = INREG(AVIVO_CRTC2_H_TOTAL);
+ state->crtc2_h_blank = INREG(AVIVO_CRTC2_H_BLANK);
+ state->crtc2_h_sync_wid = INREG(AVIVO_CRTC2_H_SYNC_WID);
+ state->crtc2_h_sync_pol = INREG(AVIVO_CRTC2_H_SYNC_POL);
+ state->crtc2_v_total = INREG(AVIVO_CRTC2_V_TOTAL);
+ state->crtc2_v_blank = INREG(AVIVO_CRTC2_V_BLANK);
+ state->crtc2_v_sync_wid = INREG(AVIVO_CRTC2_V_SYNC_WID);
+ state->crtc2_v_sync_pol = INREG(AVIVO_CRTC2_V_SYNC_POL);
+ state->crtc2_cntl = INREG(AVIVO_CRTC2_CNTL);
+ state->crtc2_blank_status = INREG(AVIVO_CRTC2_BLANK_STATUS);
+ state->crtc2_scan_enable = INREG(AVIVO_CRTC2_SCAN_ENABLE);
+ state->crtc2_fb_format = INREG(AVIVO_CRTC2_FB_FORMAT);
+ state->crtc2_fb_location = INREG(AVIVO_CRTC2_FB_LOCATION);
+ state->crtc2_fb_end = INREG(AVIVO_CRTC2_FB_END);
+ state->crtc2_pitch = INREG(AVIVO_CRTC2_PITCH);
+ state->crtc2_x_length = INREG(AVIVO_CRTC2_X_LENGTH);
+ state->crtc2_y_length = INREG(AVIVO_CRTC2_Y_LENGTH);
+
+ state->dac1_cntl = INREG(AVIVO_DACA_CNTL);
+ state->dac1_force_output_cntl = INREG(AVIVO_DACA_FORCE_OUTPUT_CNTL);
+ state->dac1_powerdown = INREG(AVIVO_DACA_POWERDOWN);
+
+ state->tmds1_cntl = INREG(AVIVO_TMDSA_CNTL);
+ state->tmds1_bit_depth_cntl = INREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL);
+ state->tmds1_data_sync = INREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION);
+ state->tmds1_transmitter_enable = INREG(AVIVO_TMDSA_TRANSMITTER_ENABLE);
+ state->tmds1_transmitter_cntl = INREG(AVIVO_TMDSA_TRANSMITTER_CONTROL);
+
+ state->dac2_cntl = INREG(AVIVO_DACB_CNTL);
+ state->dac2_force_output_cntl = INREG(AVIVO_DACB_FORCE_OUTPUT_CNTL);
+ state->dac2_powerdown = INREG(AVIVO_DACB_POWERDOWN);
+
+ state->tmds2_cntl = INREG(AVIVO_LVTMA_CNTL);
+ state->tmds2_bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
+ state->tmds2_data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION);
+ state->tmds2_transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE);
+ state->tmds2_transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL);
+
+}
+
+void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ struct avivo_state *state = &restore->avivo;
+
+ OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map);
+ OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base);
+ OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start);
+ OUTREG(AVIVO_VGA1_CONTROL, state->vga1_cntl);
+ OUTREG(AVIVO_VGA2_CONTROL, state->vga2_cntl);
+
+ OUTREG(AVIVO_PLL1_POST_DIV_CNTL, state->pll1_post_div_cntl);
+ OUTREG(AVIVO_PLL1_POST_DIV, state->pll1_post_div);
+ OUTREG(AVIVO_PLL1_POST_DIV_MYSTERY, state->pll1_post_div_mystery);
+ OUTREG(AVIVO_PLL1_POST_MUL, state->pll1_post_mul);
+ OUTREG(AVIVO_PLL1_DIVIDER_CNTL, state->pll1_divider_cntl);
+ OUTREG(AVIVO_PLL1_DIVIDER, state->pll1_divider);
+ OUTREG(AVIVO_PLL1_MYSTERY0, state->pll1_mystery0);
+ OUTREG(AVIVO_PLL1_MYSTERY1, state->pll1_mystery1);
+ OUTREG(AVIVO_PLL2_POST_DIV_CNTL, state->pll2_post_div_cntl);
+ OUTREG(AVIVO_PLL2_POST_DIV, state->pll2_post_div);
+ OUTREG(AVIVO_PLL2_POST_DIV_MYSTERY, state->pll2_post_div_mystery);
+ OUTREG(AVIVO_PLL2_POST_MUL, state->pll2_post_mul);
+ OUTREG(AVIVO_PLL2_DIVIDER_CNTL, state->pll2_divider_cntl);
+ OUTREG(AVIVO_PLL2_DIVIDER, state->pll2_divider);
+ OUTREG(AVIVO_PLL2_MYSTERY0, state->pll2_mystery0);
+ OUTREG(AVIVO_PLL2_MYSTERY1, state->pll2_mystery1);
+ OUTREG(AVIVO_CRTC_PLL_SOURCE, state->crtc_pll_source);
+
+ OUTREG(AVIVO_CRTC1_H_TOTAL, state->crtc1_h_total);
+ OUTREG(AVIVO_CRTC1_H_BLANK, state->crtc1_h_blank);
+ OUTREG(AVIVO_CRTC1_H_SYNC_WID, state->crtc1_h_sync_wid);
+ OUTREG(AVIVO_CRTC1_H_SYNC_POL, state->crtc1_h_sync_pol);
+ OUTREG(AVIVO_CRTC1_V_TOTAL, state->crtc1_v_total);
+ OUTREG(AVIVO_CRTC1_V_BLANK, state->crtc1_v_blank);
+ /*
+ * Weird we shouldn't restore sync width when going back to text
+ * mode, it must not be a 0 value, i guess a deeper look in cold
+ * text mode register value would help to understand what is
+ * truely needed to do.
+ */
+#if 0
+ OUTREG(AVIVO_CRTC1_V_SYNC_WID, state->crtc1_v_sync_wid);
+#endif
+ OUTREG(AVIVO_CRTC1_V_SYNC_POL, state->crtc1_v_sync_pol);
+ OUTREG(AVIVO_CRTC1_CNTL, state->crtc1_cntl);
+ OUTREG(AVIVO_CRTC1_SCAN_ENABLE, state->crtc1_scan_enable);
+ OUTREG(AVIVO_CRTC1_FB_FORMAT, state->crtc1_fb_format);
+ OUTREG(AVIVO_CRTC1_FB_LOCATION, state->crtc1_fb_location);
+ OUTREG(AVIVO_CRTC1_FB_END, state->crtc1_fb_end);
+ OUTREG(AVIVO_CRTC1_PITCH, state->crtc1_pitch);
+ OUTREG(AVIVO_CRTC1_X_LENGTH, state->crtc1_x_length);
+ OUTREG(AVIVO_CRTC1_Y_LENGTH, state->crtc1_y_length);
+ OUTREG(AVIVO_CRTC1_FB_HEIGHT, state->crtc1_fb_height);
+ OUTREG(AVIVO_CRTC1_OFFSET_START, state->crtc1_offset_start);
+ OUTREG(AVIVO_CRTC1_OFFSET_END, state->crtc1_offset_end);
+ OUTREG(AVIVO_CRTC1_EXPANSION_SOURCE, state->crtc1_expn_size);
+ OUTREG(AVIVO_CRTC1_EXPANSION_CNTL, state->crtc1_expn_cntl);
+ OUTREG(AVIVO_CRTC1_6594, state->crtc1_6594);
+ OUTREG(AVIVO_CRTC1_659C, state->crtc1_659c);
+ OUTREG(AVIVO_CRTC1_65A4, state->crtc1_65a4);
+ OUTREG(AVIVO_CRTC1_65A8, state->crtc1_65a8);
+ OUTREG(AVIVO_CRTC1_65AC, state->crtc1_65ac);
+ OUTREG(AVIVO_CRTC1_65B0, state->crtc1_65b0);
+ OUTREG(AVIVO_CRTC1_65B8, state->crtc1_65b8);
+ OUTREG(AVIVO_CRTC1_65BC, state->crtc1_65bc);
+ OUTREG(AVIVO_CRTC1_65C0, state->crtc1_65c0);
+ OUTREG(AVIVO_CRTC1_65C8, state->crtc1_65c8);
+ OUTREG(AVIVO_CRTC2_H_TOTAL, state->crtc2_h_total);
+ OUTREG(AVIVO_CRTC2_H_BLANK, state->crtc2_h_blank);
+#if 0
+ OUTREG(AVIVO_CRTC2_H_SYNC_WID, state->crtc2_h_sync_wid);
+#endif
+ OUTREG(AVIVO_CRTC2_H_SYNC_POL, state->crtc2_h_sync_pol);
+ OUTREG(AVIVO_CRTC2_V_TOTAL, state->crtc2_v_total);
+ OUTREG(AVIVO_CRTC2_V_BLANK, state->crtc2_v_blank);
+ OUTREG(AVIVO_CRTC2_V_SYNC_WID, state->crtc2_v_sync_wid);
+ OUTREG(AVIVO_CRTC2_V_SYNC_POL, state->crtc2_v_sync_pol);
+ OUTREG(AVIVO_CRTC2_CNTL, state->crtc2_cntl);
+ OUTREG(AVIVO_CRTC2_BLANK_STATUS, state->crtc2_blank_status);
+ OUTREG(AVIVO_CRTC2_SCAN_ENABLE, state->crtc2_scan_enable);
+ OUTREG(AVIVO_CRTC2_FB_FORMAT, state->crtc2_fb_format);
+ OUTREG(AVIVO_CRTC2_FB_LOCATION, state->crtc2_fb_location);
+ OUTREG(AVIVO_CRTC2_FB_END, state->crtc2_fb_end);
+ OUTREG(AVIVO_CRTC2_PITCH, state->crtc2_pitch);
+ OUTREG(AVIVO_CRTC2_X_LENGTH, state->crtc2_x_length);
+ OUTREG(AVIVO_CRTC2_Y_LENGTH, state->crtc2_y_length);
+
+ OUTREG(AVIVO_DACA_CNTL, state->dac1_cntl);
+ OUTREG(AVIVO_DACA_FORCE_OUTPUT_CNTL, state->dac1_force_output_cntl);
+ OUTREG(AVIVO_DACA_POWERDOWN, state->dac1_powerdown);
+
+ OUTREG(AVIVO_TMDSA_CNTL, state->tmds1_cntl);
+ OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, state->tmds1_bit_depth_cntl);
+ OUTREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION, state->tmds1_data_sync);
+ OUTREG(AVIVO_TMDSA_TRANSMITTER_ENABLE, state->tmds1_transmitter_enable);
+ OUTREG(AVIVO_TMDSA_TRANSMITTER_CONTROL, state->tmds1_transmitter_cntl);
+
+ OUTREG(AVIVO_DACB_CNTL, state->dac2_cntl);
+ OUTREG(AVIVO_DACB_FORCE_OUTPUT_CNTL, state->dac2_force_output_cntl);
+ OUTREG(AVIVO_DACB_POWERDOWN, state->dac2_powerdown);
+
+ OUTREG(AVIVO_LVTMA_CNTL, state->tmds2_cntl);
+ OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2_bit_depth_cntl);
+ OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2_data_sync);
+ OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2_transmitter_enable);
+ OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2_transmitter_cntl);
+
+}
+
/* Save everything needed to restore the original VC state */
static void RADEONSave(ScrnInfoPtr pScrn)
{
@@ -5374,26 +5761,32 @@ static void RADEONSave(ScrnInfoPtr pScrn)
vgaHWLock(hwp);
}
#endif
- save->dp_datatype = INREG(RADEON_DP_DATATYPE);
- save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
- save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
- RADEONPllErrataAfterIndex(info);
- RADEONSaveMemMapRegisters(pScrn, save);
- RADEONSaveCommonRegisters(pScrn, save);
- RADEONSavePLLRegisters(pScrn, save);
- RADEONSaveCrtcRegisters(pScrn, save);
- RADEONSaveFPRegisters(pScrn, save);
- RADEONSaveBIOSRegisters(pScrn, save);
- RADEONSaveDACRegisters(pScrn, save);
- if (pRADEONEnt->HasCRTC2) {
- RADEONSaveCrtc2Registers(pScrn, save);
- RADEONSavePLL2Registers(pScrn, save);
+ if (IS_AVIVO_VARIANT) {
+ avivo_save(pScrn, save);
+ } else {
+ save->dp_datatype = INREG(RADEON_DP_DATATYPE);
+ save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
+ save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
+ RADEONPllErrataAfterIndex(info);
+
+ RADEONSaveMemMapRegisters(pScrn, save);
+ RADEONSaveCommonRegisters(pScrn, save);
+ RADEONSavePLLRegisters(pScrn, save);
+ RADEONSaveCrtcRegisters(pScrn, save);
+ RADEONSaveFPRegisters(pScrn, save);
+ RADEONSaveBIOSRegisters(pScrn, save);
+ RADEONSaveDACRegisters(pScrn, save);
+ if (pRADEONEnt->HasCRTC2) {
+ RADEONSaveCrtc2Registers(pScrn, save);
+ RADEONSavePLL2Registers(pScrn, save);
+ }
+ if (info->InternalTVOut)
+ RADEONSaveTVRegisters(pScrn, save);
}
- if (info->InternalTVOut)
- RADEONSaveTVRegisters(pScrn, save);
- RADEONSaveSurfaces(pScrn, save);
+ RADEONSaveSurfaces(pScrn, save);
+
}
/* Restore the original (text) mode */
@@ -5416,31 +5809,36 @@ void RADEONRestore(ScrnInfoPtr pScrn)
RADEONBlank(pScrn);
- OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
- RADEONPllErrataAfterIndex(info);
- OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
- OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
- OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
- OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
+ if (IS_AVIVO_VARIANT) {
+ avivo_restore(pScrn, restore);
+ } else {
+ OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
+ RADEONPllErrataAfterIndex(info);
+ OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
+ OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
+ OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
+ OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
- RADEONRestoreMemMapRegisters(pScrn, restore);
- RADEONRestoreCommonRegisters(pScrn, restore);
+ RADEONRestoreMemMapRegisters(pScrn, restore);
+ RADEONRestoreCommonRegisters(pScrn, restore);
- if (pRADEONEnt->HasCRTC2) {
- RADEONRestoreCrtc2Registers(pScrn, restore);
- RADEONRestorePLL2Registers(pScrn, restore);
- }
+ if (pRADEONEnt->HasCRTC2) {
+ RADEONRestoreCrtc2Registers(pScrn, restore);
+ RADEONRestorePLL2Registers(pScrn, restore);
+ }
+
+ RADEONRestoreBIOSRegisters(pScrn, restore);
+ RADEONRestoreCrtcRegisters(pScrn, restore);
+ RADEONRestorePLLRegisters(pScrn, restore);
+ RADEONRestoreRMXRegisters(pScrn, restore);
+ RADEONRestoreFPRegisters(pScrn, restore);
+ RADEONRestoreFP2Registers(pScrn, restore);
+ RADEONRestoreLVDSRegisters(pScrn, restore);
- RADEONRestoreBIOSRegisters(pScrn, restore);
- RADEONRestoreCrtcRegisters(pScrn, restore);
- RADEONRestorePLLRegisters(pScrn, restore);
- RADEONRestoreRMXRegisters(pScrn, restore);
- RADEONRestoreFPRegisters(pScrn, restore);
- RADEONRestoreFP2Registers(pScrn, restore);
- RADEONRestoreLVDSRegisters(pScrn, restore);
+ if (info->InternalTVOut)
+ RADEONRestoreTVRegisters(pScrn, restore);
- if (info->InternalTVOut)
- RADEONRestoreTVRegisters(pScrn, restore);
+ }
RADEONRestoreSurfaces(pScrn, restore);
@@ -5662,7 +6060,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2)
crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
#endif
if (info->tilingEnabled) {
- if (IS_R300_VARIANT) {
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
/* On r300/r400 when tiling is enabled crtc_offset is set to the address of
* the surface. the x/y offsets are handled by the X_Y tile reg for each crtc
* Makes tiling MUCH easier.
@@ -5719,7 +6117,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2)
}
#endif
- if (IS_R300_VARIANT) {
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
OUTREG(xytilereg, crtcxytile);
} else {
OUTREG(regcntl, crtcoffsetcntl);
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index d68a956..5253cd7 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -192,6 +192,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA },
{ PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA },
{ PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
commit 0abfe3150ce3eed4db93ccc2975bd4622dfa54a7
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 6 18:47:00 2007 -0500
Add atombios files
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
new file mode 100644
index 0000000..8c0f5c1
--- /dev/null
+++ b/src/atombios_crtc.c
@@ -0,0 +1,536 @@
+/*
+ * Copyright © 2007 Dave Airlie
+ *
+ */
+/*
+ * avivo crtc handling functions.
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+/* DPMS */
+#define DPMS_SERVER
+#include <X11/extensions/dpms.h>
+
+#include "radeon.h"
+#include "radeon_reg.h"
+#include "avivo_reg.h"
+#include "radeon_macros.h"
+#include "radeon_atombios.h"
+
+
+AtomBiosResult
+atombios_enable_crtc(atomBIOSHandlePtr atomBIOS, int crtc, int state)
+{
+ ENABLE_CRTC_PS_ALLOCATION crtc_data;
+ AtomBIOSArg data;
+ unsigned char *space;
+
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucEnable = state;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Enable":"Disable", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Enable CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+AtomBiosResult
+atombios_blank_crtc(atomBIOSHandlePtr atomBIOS, int crtc, int state)
+{
+ BLANK_CRTC_PS_ALLOCATION crtc_data;
+ unsigned char *space;
+ AtomBIOSArg data;
+
+ memset(&crtc_data, 0, sizeof(crtc_data));
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucBlanking = state;
+
+ data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Blank":"Unblank", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Blank CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+static void
+atombios_crtc_enable(xf86CrtcPtr crtc, int enable)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ int scan_enable, cntl;
+ AtomBiosResult res;
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable);
+
+ //TODOavivo_wait_idle(avivo);
+}
+
+void
+atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ switch (mode) {
+ case DPMSModeOn:
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ case DPMSModeOff:
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ }
+}
+
+static void
+atombios_set_crtc_source(xf86CrtcPtr crtc)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ AtomBIOSArg data;
+ unsigned char *space;
+ SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
+ int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
+ int major, minor;
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ ErrorF("select crtc source table is %d %d\n", major, minor);
+
+ switch(major) {
+ case 1: {
+ switch(minor) {
+ case 0:
+ case 1:
+ default:
+ crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
+ crtc_src_param.ucDevice = radeon_crtc->crtc_id? 0: 3;
+ break;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_src_param;
+
+ if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC Source success\n");
+ return;
+ }
+
+ ErrorF("Set CRTC Source failed\n");
+ return;
+}
+
+static AtomBiosResult
+atombios_set_crtc_timing(atomBIOSHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
+{
+ AtomBIOSArg data;
+ unsigned char *space;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = crtc_param;
+
+ if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC Timing success\n");
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Set CRTC Timing failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+#define USE_RADEONHD_CODE_FOR_PLL 1
+#if USE_RADEONHD_CODE_FOR_PLL
+
+struct rhdPLL {
+ int scrnIndex;
+
+/* also used as an index to rhdPtr->PLLs */
+#define PLL_ID_PLL1 0
+#define PLL_ID_PLL2 1
+#define PLL_ID_NONE -1
+ int Id;
+
+ CARD32 CurrentClock;
+ Bool Active;
+
+ /* from defaults or from atom */
+ CARD32 RefClock;
+ CARD32 InMin;
+ CARD32 InMax;
+ CARD32 OutMin;
+ CARD32 OutMax;
+ CARD32 PixMin;
+ CARD32 PixMax;
+};
+
+static struct rhdPLL mypll = {
+ 0, 0, 0, 0,
+ 27000,
+ 1000, 13500,
+ 600000, 1100000,
+ 16000, 400000
+};
+/*
+ * Calculate the PLL parameters for a given dotclock.
+ */
+static Bool
+PLLCalculate(CARD32 PixelClock,
+ CARD16 *RefDivider, CARD16 *FBDivider, CARD8 *PostDivider)
+{
+/* limited by the number of bits available */
+#define FB_DIV_LIMIT 1024 /* rv6x0 doesn't like 2048 */
+#define REF_DIV_LIMIT 1024
+#define POST_DIV_LIMIT 128
+ struct rhdPLL *PLL = &mypll;
+ CARD32 FBDiv, RefDiv, PostDiv, BestDiff = 0xFFFFFFFF;
+ float Ratio;
+
+ Ratio = ((float) PixelClock) / ((float) PLL->RefClock);
+
+ for (PostDiv = 2; PostDiv < POST_DIV_LIMIT; PostDiv++) {
+ CARD32 VCOOut = PixelClock * PostDiv;
+
+ /* we are conservative and avoid the limits */
+ if (VCOOut <= PLL->OutMin)
+ continue;
+ if (VCOOut >= PLL->OutMax)
+ break;
+
+ for (RefDiv = 1; RefDiv <= REF_DIV_LIMIT; RefDiv++)
+ {
+ CARD32 Diff;
+
+ FBDiv = (CARD32) ((Ratio * PostDiv * RefDiv) + 0.5);
+
+ if (FBDiv >= FB_DIV_LIMIT)
+ break;
+
+ if (FBDiv > (500 + (13 * RefDiv))) /* rv6x0 limit */
+ break;
+
+ Diff = abs( PixelClock - (FBDiv * PLL->RefClock) / (PostDiv * RefDiv) );
+
+ if (Diff < BestDiff) {
+ *FBDivider = FBDiv;
+ *RefDivider = RefDiv;
+ *PostDivider = PostDiv;
+ BestDiff = Diff;
+ }
+
+ if (BestDiff == 0)
+ break;
+ }
+ if (BestDiff == 0)
+ break;
+ }
+
+ if (BestDiff != 0xFFFFFFFF) {
+ ErrorF("PLL Calculation: %dkHz = "
+ "(((0x%X / 0x%X) * 0x%X) / 0x%X) (%dkHz off)\n",
+ (int) PixelClock, (unsigned int) PLL->RefClock, *RefDivider,
+ *FBDivider, *PostDivider, (int) BestDiff);
+ xf86DrvMsg(PLL->scrnIndex, X_INFO, "PLL for %dkHz uses %dkHz internally.\n",
+ (int) PixelClock,
+ (int) (PLL->RefClock * *FBDivider) / *RefDivider);
+ return TRUE;
+ } else { /* Should never happen */
+ xf86DrvMsg(PLL->scrnIndex, X_ERROR,
+ "%s: Failed to get a valid PLL setting for %dkHz\n",
+ __func__, (int) PixelClock);
+ return FALSE;
+ }
+}
+#else // avivo code
+
+
+#endif
+
+void
+atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ double c;
+ int div1, div2, clock;
+ int sclock;
+ uint16_t ref_div, fb_div;
+ uint8_t post_div;
+ int mul;
+ int major, minor;
+ SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
+ void *ptr;
+ AtomBIOSArg data;
+ unsigned char *space;
+ RADEONSavePtr save = &info->ModeReg;
+
+ PLLCalculate(mode->Clock, &ref_div, &fb_div, &post_div);
+
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) Clock: mode %d, PLL %d\n",
+ radeon_crtc->crtc_id, mode->Clock, sclock);
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) PLL : refdiv %d, fbdiv 0x%X(%d), pdiv %d\n",
+ radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
+
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "AGD: crtc(%d) PLL : refdiv %d, fbdiv 0x%X(%d), pdiv %d\n",
+ radeon_crtc->crtc_id, save->ppll_ref_div, save->feedback_div, save->feedback_div, save->post_div);
+
+ if (1) {
+ fb_div = save->feedback_div;
+ post_div = save->post_div;
+ ref_div = save->ppll_ref_div;
+ }
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ ErrorF("table is %d %d\n", major, minor);
+ switch(major) {
+ case 1:
+ switch(minor) {
+ case 1:
+ case 2: {
+ spc_param.sPCLKInput.usPixelClock = sclock / 10;
+ spc_param.sPCLKInput.usRefDiv = ref_div;
+ spc_param.sPCLKInput.usFbDiv = fb_div;
+ spc_param.sPCLKInput.ucPostDiv = post_div;
+ spc_param.sPCLKInput.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+ spc_param.sPCLKInput.ucCRTC = radeon_crtc->crtc_id;
+ spc_param.sPCLKInput.ucRefDivSrc = 1;
+
+ ptr = &spc_param;
+ break;
+ }
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = ptr;
+
+ if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC PLL success\n");
+ return;
+ }
+
+ ErrorF("Set CRTC PLL failed\n");
+ return;
+}
+
+
+void
+atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode,
+ int x, int y)
+{
+ ScrnInfoPtr screen_info = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
+ int regval;
+ AtomBiosResult atom_res;
+ RADEONSavePtr restore = &info->ModeReg;
+
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
+
+ memset(&crtc_timing, 0, sizeof(crtc_timing));
+
+ crtc_timing.ucCRTC = radeon_crtc->crtc_id;
+ crtc_timing.usH_Total = adjusted_mode->CrtcHTotal;
+ crtc_timing.usH_Disp = adjusted_mode->CrtcHDisplay;
+ crtc_timing.usH_SyncStart = adjusted_mode->CrtcHSyncStart;
+ crtc_timing.usH_SyncWidth = adjusted_mode->CrtcHSyncEnd - adjusted_mode->CrtcHSyncStart;
+
+ crtc_timing.usV_Total = adjusted_mode->CrtcVTotal;
+ crtc_timing.usV_Disp = adjusted_mode->CrtcVDisplay;
+ crtc_timing.usV_SyncStart = adjusted_mode->CrtcVSyncStart;
+ crtc_timing.usV_SyncWidth = adjusted_mode->CrtcVSyncEnd - adjusted_mode->CrtcVSyncStart;
+
+ if (adjusted_mode->Flags & V_NVSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
+
+ if (adjusted_mode->Flags & V_NHSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
+
+ ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
+ adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
+
+ if (0) {
+ radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_height = screen_info->virtualY;
+ radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4;
+ switch (crtc->scrn->bitsPerPixel) {
+ case 15:
+ radeon_crtc->fb_format = AVIVO_CRTC_FORMAT_ARGB15;
+ break;
+ case 16:
+ radeon_crtc->fb_format = AVIVO_CRTC_FORMAT_ARGB16;
+ break;
+ case 24:
+ case 32:
+ radeon_crtc->fb_format = AVIVO_CRTC_FORMAT_ARGB32;
+ break;
+ default:
+ FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
+ }
+ if (info->tilingEnabled) {
+ radeon_crtc->fb_format |= AVIVO_CRTC_MACRO_ADDRESS_MODE;
+ }
+ /* setup fb format and location
+ */
+ OUTREG(AVIVO_CRTC1_EXPANSION_SOURCE + radeon_crtc->crtc_offset,
+ (mode->HDisplay << 16) | mode->VDisplay);
+
+ OUTREG(AVIVO_CRTC1_FB_LOCATION + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_CRTC1_FB_END + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_CRTC1_FB_FORMAT + radeon_crtc->crtc_offset,
+ radeon_crtc->fb_format);
+
+ OUTREG(AVIVO_CRTC1_X_LENGTH + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualX);
+ OUTREG(AVIVO_CRTC1_Y_LENGTH + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualY);
+ OUTREG(AVIVO_CRTC1_PITCH + radeon_crtc->crtc_offset,
+ crtc->scrn->displayWidth);
+
+ OUTREG(AVIVO_CRTC1_SCAN_ENABLE + radeon_crtc->crtc_offset, 1);
+
+ }
+
+ atombios_set_crtc_source(crtc);
+
+ atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
+
+ atombios_crtc_set_pll(crtc, adjusted_mode);
+
+}
+
+
+
+static void
+atombios_setup_cursor(ScrnInfoPtr pScrn, int id, int enable)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ if (id == 0) {
+ OUTREG(AVIVO_CURSOR1_CNTL, 0);
+
+ if (enable) {
+ OUTREG(AVIVO_CURSOR1_LOCATION, info->fbLocation +
+ info->cursor_offset);
+ OUTREG(AVIVO_CURSOR1_SIZE, ((info->cursor_width -1) << 16) |
+ (info->cursor_height-1));
+ OUTREG(AVIVO_CURSOR1_CNTL, AVIVO_CURSOR_EN |
+ (AVIVO_CURSOR_FORMAT_ARGB <<
+ AVIVO_CURSOR_FORMAT_SHIFT));
+ }
+ }
+}
+
+void
+atombios_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ int crtc_id = radeon_crtc->crtc_id;
+
+ if (x < 0)
+ x = 0;
+ if (y < 0)
+ y = 0;
+
+ OUTREG(AVIVO_CURSOR1_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
+ radeon_crtc->cursor_x = x;
+ radeon_crtc->cursor_y = y;
+}
+
+
+void
+atombios_crtc_show_cursor(xf86CrtcPtr crtc)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+#ifdef XF86DRI
+ if (info->CPStarted && crtc->scrn->pScreen) DRILock(crtc->scrn->pScreen, 0);
+#endif
+
+ RADEON_SYNC(info, crtc->scrn);
+
+ OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset,
+ INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset)
+ | AVIVO_CURSOR_EN);
+ atombios_setup_cursor(crtc->scrn, radeon_crtc->crtc_id, 1);
+
+#ifdef XF86DRI
+ if (info->CPStarted && crtc->scrn->pScreen) DRIUnlock(crtc->scrn->pScreen);
+#endif
+}
+
+void
+atombios_crtc_hide_cursor(xf86CrtcPtr crtc)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+#ifdef XF86DRI
+ if (info->CPStarted && crtc->scrn->pScreen) DRILock(crtc->scrn->pScreen, 0);
+#endif
+
+ RADEON_SYNC(info, crtc->scrn);
+
+ OUTREG(AVIVO_CURSOR1_CNTL+ radeon_crtc->crtc_offset,
+ INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset)
+ & ~(AVIVO_CURSOR_EN));
+ atombios_setup_cursor(crtc->scrn, radeon_crtc->crtc_id, 0);
+
+#ifdef XF86DRI
+ if (info->CPStarted && crtc->scrn->pScreen) DRIUnlock(crtc->scrn->pScreen);
+#endif
+}
+
+static void
+atombios_crtc_destroy(xf86CrtcPtr crtc)
+{
+ if (crtc->driver_private)
+ xfree(crtc->driver_private);
+}
diff --git a/src/atombios_output.c b/src/atombios_output.c
new file mode 100644
index 0000000..18e6d3c
--- /dev/null
+++ b/src/atombios_output.c
@@ -0,0 +1,1188 @@
+/*
+ * Copyright © 2007 Dave Airlie
+ */
+/*
+ * avivo output handling functions.
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+/* DPMS */
+#define DPMS_SERVER
+#include <X11/extensions/dpms.h>
+#include <unistd.h>
+
+#include "radeon.h"
+#include "radeon_reg.h"
+#include "radeon_macros.h"
+#include "radeon_atombios.h"
+
+static
+Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state);
+
+static AtomBiosResult atom_bios_display_device_control(atomBIOSHandlePtr atomBIOS, int device, Bool state)
+{
+ DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data;
+ AtomBIOSArg data;
+ unsigned char *space;
+ AtomBiosResult ret;
+
+ disp_data.ucAction = state;
+ data.exec.index = device;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+
+ if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output %d enable success\n", device);
+ return ATOM_SUCCESS;
+ }
+
+ ErrorF("Output %d enable failed\n", device);
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+static void
+atom_bios_enable_crt(atomBIOSHandlePtr atomBIOS, int dac, Bool state)
+{
+ int output;
+ if (dac == DAC_PRIMARY)
+ output = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
+ else
+ output = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
+
+ atom_bios_display_device_control(atomBIOS, output, state);
+}
+
+static int
+atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
+ AtomBIOSArg data;
+ unsigned char *space;
+ AtomBiosResult ret;
+
+ disp_data.ucAction = 1;
+ disp_data.ucDacStandard = 1;
+ disp_data.usPixelClock = mode->Clock / 10;
+ if (radeon_output->DACType == DAC_PRIMARY)
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
+ else
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+
+ if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output DAC %d enable success\n", radeon_output->DACType);
+ return ATOM_SUCCESS;
+ }
+
+ ErrorF("Output DAC %d enable failed\n", radeon_output->DACType);
+ return ATOM_NOT_IMPLEMENTED;
+
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, CRT1OutputControl), ATOM_TRANSMITTER_ACTION_INIT);
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, CRT1OutputControl), ATOM_TRANSMITTER_ACTION_SETUP);
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, CRT1OutputControl), ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT);
+ return ATOM_SUCCESS;
+
+}
+
+
+static int
+atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned int tmp;
+ TMDS1_ENCODER_CONTROL_PS_ALLOCATION disp_data;
+ AtomBIOSArg data;
+ unsigned char *space;
+ AtomBiosResult ret;
+
+ disp_data.ucAction = 1;
+ if (mode->Clock > 165000)
+ disp_data.ucMisc = 1;
+ else
+ disp_data.ucMisc = 0;
+ disp_data.usPixelClock = mode->Clock / 10;
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+
+ if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output TMDS1 enable success\n");
+ return ATOM_SUCCESS;
+ }
+
+ ErrorF("Output TMDS1 enable failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, DFP1OutputControl), ATOM_TRANSMITTER_ACTION_INIT);
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, DFP1OutputControl), ATOM_TRANSMITTER_ACTION_SETUP);
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, DFP1OutputControl), ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT);
+ return ATOM_SUCCESS;
+}
+
+static void
+atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ unsigned int tmp;
+ TMDS2_ENCODER_CONTROL_PS_ALLOCATION disp_data;
+ AtomBIOSArg data;
+ unsigned char *space;
+ AtomBiosResult ret;
+
+ disp_data.ucAction = 1;
+ if (mode->Clock > 165000)
+ disp_data.ucMisc = 1;
+ else
+ disp_data.ucMisc = 0;
+ disp_data.usPixelClock = mode->Clock / 10;
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+
+ if (RHDAtomBIOSFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output TMDS2 enable success\n");
+ return ATOM_SUCCESS;
+ }
+
+ ErrorF("Output TMDS2 enable failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+static void
+atombios_output_dac_dpms(xf86OutputPtr output, int mode)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+
+ switch(mode) {
+ case DPMSModeOn:
+ atom_bios_enable_crt(info->atomBIOS, radeon_output->DACType, ATOM_ENABLE);
+ break;
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ case DPMSModeOff:
+ atom_bios_enable_crt(info->atomBIOS, radeon_output->DACType, ATOM_DISABLE);
+ break;
+ }
+}
+
+static void
+atombios_output_tmds1_dpms(xf86OutputPtr output, int mode)
+{
+ RADEONOutputPrivatePtr avivo_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+
+ switch(mode) {
+ case DPMSModeOn:
+ /* TODO */
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl), ATOM_ENABLE);
+
+ break;
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ case DPMSModeOff:
+ /* TODO */
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl), ATOM_DISABLE);
+ break;
+ }
+}
+
+static void
+atombios_output_tmds2_dpms(xf86OutputPtr output, int mode)
+{
+ RADEONOutputPrivatePtr avivo_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ switch(mode) {
+ case DPMSModeOn:
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl), ATOM_ENABLE);
+ /* TODO */
+ break;
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ case DPMSModeOff:
+ atom_bios_display_device_control(info->atomBIOS, GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl), ATOM_DISABLE);
+ /* TODO */
+ break;
+ }
+}
+
+static void
+atombios_output_lvds_dpms(xf86OutputPtr output, int mode)
+{
+ atombios_output_tmds2_dpms(output, mode);
+}
+
+void
+atombios_output_dpms(xf86OutputPtr output, int mode)
+{
+ RADEONOutputPrivatePtr avivo_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ int tmp, count;
+
+#if 1
+ /* try to grab card lock or at least somethings that looks like a lock
+ * if it fails more than 5 times with 1000ms wait btw each try than we
+ * assume we can process.
+ */
+ count = 0;
+ tmp = INREG(0x0028);
+ while((tmp & 0x100) && (count < 5)) {
+ tmp = INREG(0x0028);
+ count++;
+ usleep(1000);
+ }
+ if (count >= 5) {
+ xf86DrvMsg(output->scrn->scrnIndex, X_INFO,
+ "%s (WARNING) failed to grab card lock process anyway.\n",
+ __func__);
+ }
+ OUTREG(0x0028, tmp | 0x100);
+#endif
+
+ ErrorF("AGD: output dpms\n");
+
+ if (avivo_output->MonType == MT_LCD) {
+ atombios_output_tmds2_dpms(output, mode);
+ } else if (avivo_output->MonType == MT_DFP) {
+ ErrorF("AGD: tmds dpms\n");
+ atombios_output_tmds1_dpms(output, mode);
+ } else if (avivo_output->MonType == MT_CRT) {
+ ErrorF("AGD: dac dpms\n");
+ atombios_output_dac_dpms(output, mode);
+ }
+
+#if 1
+ /* release card lock */
+ tmp = INREG(0x0028);
+ OUTREG(0x0028, tmp & (~0x100));
+#endif
+}
+
+static int
+atombios_output_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
+{
+ if (pMode->Flags & V_DBLSCAN)
+ return MODE_NO_DBLESCAN;
+
+ if (pMode->Clock > 400000 || pMode->Clock < 25000)
+ return MODE_CLOCK_RANGE;
+
+ return MODE_OK;
+}
+
+static Bool
+atombios_output_mode_fixup(xf86OutputPtr output,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode)
+{
+ return TRUE;
+}
+
+static void
+atombios_output_prepare(xf86OutputPtr output)
+{
+ output->funcs->dpms(output, DPMSModeOff);
+}
+
+
+
+void
+atombios_output_mode_set(xf86OutputPtr output,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode)
+{
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ ErrorF("AGD: atom dac setup\n");
+ atombios_output_dac_setup(output, adjusted_mode);
+ }
+ } else if (radeon_output->MonType == MT_DFP) {
+ ErrorF("AGD: atom tmds setup\n");
+ if (radeon_output->TMDSType == TMDS_INT)
+ atombios_output_tmds1_setup(output, adjusted_mode);
+ else
+ atombios_output_tmds2_setup(output, adjusted_mode);
+ } else if (radeon_output->MonType == MT_LCD) {
+ atombios_output_tmds2_setup(output, adjusted_mode);
+ }
+}
+
+static void
+atombios_output_commit(xf86OutputPtr output)
+{
+ output->funcs->dpms(output, DPMSModeOn);
+}
+
+DisplayModePtr
+atombios_output_get_modes(xf86OutputPtr output)
+{
+ RADEONOutputPrivatePtr atombios_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ xf86MonPtr edid_mon;
+ DisplayModePtr modes;
+
+ modes = RADEONProbeOutputModes(output);
+ return modes;
+}
+
+static void
+atombios_output_destroy(xf86OutputPtr output)
+{
+ RADEONOutputPrivatePtr avivo_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ if (avivo_output == NULL)
+ return;
+ xf86DestroyI2CBusRec(avivo_output->pI2CBus, TRUE, TRUE);
+ xfree(avivo_output->name);
+ xfree(avivo_output);
+}
+
+
+Bool
+atombios_output_lfp_mode_fixup(xf86OutputPtr output,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode)
+{
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+
+#if 0
+ if (avivo->lfp_fixed_mode) {
+ adjusted_mode->HDisplay = info->lfp_fixed_mode->HDisplay;
+ adjusted_mode->HSyncStart = info->lfp_fixed_mode->HSyncStart;
+ adjusted_mode->HSyncEnd = info->lfp_fixed_mode->HSyncEnd;
+ adjusted_mode->HTotal = info->lfp_fixed_mode->HTotal;
+ adjusted_mode->VDisplay = info->lfp_fixed_mode->VDisplay;
+ adjusted_mode->VSyncStart = info->lfp_fixed_mode->VSyncStart;
+ adjusted_mode->VSyncEnd = info->lfp_fixed_mode->VSyncEnd;
+ adjusted_mode->VTotal = info->lfp_fixed_mode->VTotal;
+ adjusted_mode->Clock = info->lfp_fixed_mode->Clock;
+ xf86SetModeCrtc(adjusted_mode, 0);
+ }
+#endif
+ return TRUE;
+}
+
+DisplayModePtr
+atombios_output_lfp_get_modes(xf86OutputPtr output)
+{
+ ScrnInfoPtr screen_info = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ DisplayModePtr modes = NULL;
+
+ modes = atombios_output_get_modes(output);
+ if (modes == NULL) {
+ /* DDC EDID failed try to get timing from BIOS */
+ xf86DrvMsg(screen_info->scrnIndex, X_WARNING,
+ "Failed to get EDID over i2c for LFP try BIOS timings.\n");
+ modes = atombios_bios_get_lfp_timing(screen_info);
+ }
+#if 0
+ if (modes) {
+ xf86DeleteMode(&info->lfp_fixed_mode, info->lfp_fixed_mode);
+ info->lfp_fixed_mode = xf86DuplicateMode(modes);
+ }
+#endif
+ return modes;
+}
+
+
+
+void
+atombios_i2c_gpio0_get_bits(I2CBusPtr b, int *Clock, int *data)
+{
+ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(screen_info);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long val;
+
+ ErrorF("INREG %08x\n", INREG(b->DriverPrivate.uval));
+ /* Get the result */
+ val = INREG(b->DriverPrivate.uval + 0xC);
+ *Clock = (val & (1<<19)) != 0;
+ *data = (val & (1<<18)) != 0;
+}
+
+void
+atombios_i2c_gpio0_put_bits(I2CBusPtr b, int Clock, int data)
+{
+ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(screen_info);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long val;
+
+ val = 0;
+ val |= (Clock ? 0:(1<<19));
+ val |= (data ? 0:(1<<18));
+ OUTREG(b->DriverPrivate.uval + 0x8, val);
+ /* read back to improve reliability on some cards. */
+ val = INREG(b->DriverPrivate.uval + 0x8);
+}
+
+void
+atombios_i2c_gpio123_get_bits(I2CBusPtr b, int *Clock, int *data)
+{
+ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(screen_info);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long val;
+
+ if (INREG(b->DriverPrivate.uval) == 0)
+ OUTREG(b->DriverPrivate.uval, (1<<0) | (1<<8));
+
+ /* Get the result */
+ val = INREG(b->DriverPrivate.uval + 0xC);
+ *Clock = (val & (1<<0)) != 0;
+ *data = (val & (1<<8)) != 0;
+}
+
+void
+atombios_i2c_gpio123_put_bits(I2CBusPtr b, int Clock, int data)
+{
+ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(screen_info);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long val;
+
+ val = 0;
+ val |= (Clock ? 0:(1<<0));
+ val |= (data ? 0:(1<<8));
+ OUTREG(b->DriverPrivate.uval + 0x8, val);
+ /* read back to improve reliability on some cards. */
+ val = INREG(b->DriverPrivate.uval + 0x8);
+}
+
+static xf86OutputStatus
+atombios_output_detect(xf86OutputPtr output)
+{
+ RADEONOutputPrivatePtr avivo_output = output->driver_private;
+ ScrnInfoPtr screen_info = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ AtomBiosResult ret;
+ uint32_t bios_0_scratch;
+
+ return radeon_detect(output);
+}
+
+static const xf86OutputFuncsRec atombios_output_dac_funcs = {
+ .dpms = atombios_output_dpms,
+ .save = NULL,
+ .restore = NULL,
+ .mode_valid = atombios_output_mode_valid,
+ .mode_fixup = atombios_output_mode_fixup,
+ .prepare = atombios_output_prepare,
+ .mode_set = atombios_output_mode_set,
+ .commit = atombios_output_commit,
+ .detect = atombios_output_detect,
+ .get_modes = atombios_output_get_modes,
+ .destroy = atombios_output_destroy
+};
+
+static const xf86OutputFuncsRec atombios_output_tmds_funcs = {
+ .dpms = atombios_output_dpms,
+ .save = NULL,
+ .restore = NULL,
+ .mode_valid = atombios_output_mode_valid,
+ .mode_fixup = atombios_output_mode_fixup,
+ .prepare = atombios_output_prepare,
+ .mode_set = atombios_output_mode_set,
+ .commit = atombios_output_commit,
+ .detect = atombios_output_detect,
+ .get_modes = atombios_output_get_modes,
+ .destroy = atombios_output_destroy
+};
+
+static const xf86OutputFuncsRec atombios_output_lfp_funcs = {
+ .dpms = atombios_output_dpms,
+ .save = NULL,
+ .restore = NULL,
+ .mode_valid = atombios_output_mode_valid,
+ .mode_fixup = atombios_output_lfp_mode_fixup,
+ .prepare = atombios_output_prepare,
+ .mode_set = atombios_output_mode_set,
+ .commit = atombios_output_commit,
+ .detect = atombios_output_detect,
+ .get_modes = atombios_output_get_modes,
+ .destroy = atombios_output_destroy
+};
+
+Bool
+atombios_output_exist(ScrnInfoPtr screen_info, xf86ConnectorType type,
+ int number, unsigned long ddc_reg)
+{
+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(screen_info);
+ int i;
+
+ for (i = 0; i < config->num_output; i++) {
+ xf86OutputPtr output = config->output[i];
+ RADEONOutputPrivatePtr avivo_output = output->driver_private;
+ if (avivo_output->num == number && avivo_output->type == type)
+ return TRUE;
+ /* LVTMA is shared by LFP & DVI-I */
+ if (avivo_output->type == XF86ConnectorLFP && number >= 1)
+ return TRUE;
+ if (type == XF86ConnectorLFP && avivo_output->num >= 1) {
+ avivo_output->type = type;
+ avivo_output->pI2CBus->DriverPrivate.uval = ddc_reg;
+ return TRUE;
+ }
+ }
+ return FALSE;
+}
+
+#if 0
+Bool
+avivo_output_init(ScrnInfoPtr screen_info, xf86ConnectorType type,
+ int number, unsigned long ddc_reg)
+{
+ xf86OutputPtr output = {0,};
+ RADEONOutputPrivateRec *avivo_output;
+ int name_size;
+
+ /* allocate & initialize private output structure */
+ avivo_output = xcalloc(sizeof(RADEONOutputPrivateRec), 1);
+ if (avivo_output == NULL)
+ return FALSE;
+ name_size = snprintf(NULL, 0, "%s connector %d",
+ xf86ConnectorGetName(type), number);
+ avivo_output->name = xcalloc(name_size + 1, 1);
+ if (avivo_output->name == NULL) {
+ xfree(avivo_output);
+ xf86DrvMsg(screen_info->scrnIndex, X_ERROR,
+ "Failed to allocate memory for I2C bus name\n");
+ return FALSE;
+ }
+ snprintf(avivo_output->name, name_size + 1, "%s connector %d",
+ xf86ConnectorGetName(type), number);
+ avivo_output->pI2CBus = xf86CreateI2CBusRec();
+ if (!avivo_output->pI2CBus) {
+ xfree(avivo_output);
+ xf86DrvMsg(screen_info->scrnIndex, X_ERROR,
+ "Couldn't create I2C bus for %s connector %d\n",
+ xf86ConnectorGetName(type), number);
+ return FALSE;
+ }
+ avivo_output->pI2CBus->BusName = avivo_output->name;
+ avivo_output->pI2CBus->scrnIndex = screen_info->scrnIndex;
+ if (ddc_reg == AVIVO_GPIO_0) {
+ avivo_output->pI2CBus->I2CPutBits = atombios_i2c_gpio0_put_bits;
+ avivo_output->pI2CBus->I2CGetBits = atombios_i2c_gpio0_get_bits;
+ } else {
+ avivo_output->pI2CBus->I2CPutBits = avivo_i2c_gpio123_put_bits;
+ avivo_output->pI2CBus->I2CGetBits = avivo_i2c_gpio123_get_bits;
+ }
+ avivo_output->pI2CBus->AcknTimeout = 5;
+ avivo_output->pI2CBus->DriverPrivate.uval = ddc_reg;
+ if (!xf86I2CBusInit(avivo_output->pI2CBus)) {
+ xf86DrvMsg(screen_info->scrnIndex, X_ERROR,
+ "Couldn't initialise I2C bus for %s connector %d\n",
+ xf86ConnectorGetName(type), number);
+ return FALSE;
+ }
+ avivo_output->gpio = ddc_reg;
+ avivo_output->type = type;
+ avivo_output->num = number;
+ switch (avivo_output->type) {
+ case XF86ConnectorVGA:
+ avivo_output->setup = avivo_output_dac_setup;
+ avivo_output->dpms = avivo_output_dac_dpms;
+ output = xf86OutputCreate (screen_info,
+ &avivo_output_dac_funcs,
+ xf86ConnectorGetName(type));
+ break;
+ case XF86ConnectorLFP:
+ avivo_output->setup = avivo_output_tmds2_setup;
+ avivo_output->dpms = avivo_output_lvds_dpms;
+ output = xf86OutputCreate (screen_info,
+ &avivo_output_lfp_funcs,
+ xf86ConnectorGetName(type));
+ break;
+ case XF86ConnectorDVI_I:
+ case XF86ConnectorDVI_D:
+ case XF86ConnectorDVI_A:
+ if (!number) {
+ avivo_output->setup = avivo_output_tmds1_setup;
+ avivo_output->dpms = avivo_output_tmds1_dpms;
+ } else {
+ avivo_output->setup = avivo_output_tmds2_setup;
+ avivo_output->dpms = avivo_output_tmds2_dpms;
+ }
+ output = xf86OutputCreate (screen_info,
+ &avivo_output_tmds_funcs,
+ xf86ConnectorGetName(type));
+ break;
+ default:
+ avivo_output->setup = NULL;
+ break;
+ }
+
+ if (output == NULL) {
+ xf86DestroyI2CBusRec(avivo_output->pI2CBus, TRUE, TRUE);
+ xfree(avivo_output);
+ return FALSE;
+ }
+ output->driver_private = avivo_output;
+ output->interlaceAllowed = FALSE;
+ output->doubleScanAllowed = FALSE;
+ xf86DrvMsg(screen_info->scrnIndex, X_INFO,
+ "added %s connector %d (0x%04lX)\n",
+ xf86ConnectorGetName(type), number, ddc_reg);
+
+ return TRUE;
+}
+#endif
+extern void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output);
+extern void RADEONInitConnector(xf86OutputPtr output);
+extern const char *OutputType[], *DDCTypeName[];
+
+
+static
+Bool AVIVOI2CReset(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ OUTREG(AVIVO_I2C_STOP, 1);
+ INREG(AVIVO_I2C_STOP);
+ OUTREG(AVIVO_I2C_STOP, 0x0);
+ return TRUE;
+}
+
+static
+Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CARD32 temp;
+ int count=0;
+
+ switch(lock_state) {
+ case 0:
+ temp = INREG(AVIVO_I2C_CNTL);
+ OUTREG(AVIVO_I2C_CNTL, temp | 0x100);
+ /* enable hdcp block */
+ OUTREG(R520_PCLK_HDCP_CNTL, 0x0);
+ break;
+ case 1:
+ /* disable hdcp block */
+ OUTREG(R520_PCLK_HDCP_CNTL, 0x1);
+ usleep(1);
+ OUTREG(AVIVO_I2C_CNTL, 0x1);
+ usleep(1);
+ temp = INREG(AVIVO_I2C_CNTL);
+ if (!(temp & 0x2)) {
+ ErrorF("Lock failed %08X\n", temp);
+ return FALSE;
+ }
+ break;
+ }
+ return TRUE;
+}
+
+#if 0
+static Bool
+AVIVOI2CSendData(I2CDevPtr d, int address, int nWrite, I2CByte *data)
+{
+ I2CBusPtr b = d->pI2CBus;
+ ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CARD32 temp;
+ int count, i;
+
+ OUTREG(AVIVO_I2C_STATUS, (AVIVO_I2C_STATUS_DONE | AVIVO_I2C_STATUS_NACK | AVIVO_I2C_STATUS_HALT));
+ temp = INREG(AVIVO_I2C_START_CNTL);
+ temp |= R520_I2C_START | R520_I2C_STOP | R520_I2C_RX | R520_I2C_EN;
+
+ temp &= ~R520_I2C_DDC_MASK;
+
+ switch(b->DriverPrivate.uval)
+ {
+ case 0x7e40:
+ temp |= R520_I2C_DDC1;
+ break;
+ case 0x7e50:
+ default:
+ temp |= R520_I2C_DDC2;
+ break;
+ }
+
+ OUTREG(AVIVO_I2C_START_CNTL, temp);
+
+ temp = INREG(AVIVO_I2C_CONTROL2);
+ temp &= ~R520_I2C_DATA_COUNT_MASK;
+ temp |= 1 << R520_I2C_DATA_COUNT_SHIFT;
+ temp &= ~R520_I2C_ADDR_COUNT_MASK;
+ temp |= 1;
+ OUTREG(AVIVO_I2C_CONTROL2, temp);
+
+ temp = INREG(AVIVO_I2C_CONTROL3);
+ OUTREG(AVIVO_I2C_CONTROL3, temp);
+
+ OUTREG(AVIVO_I2C_DATA, address);
+ for (i=0; i<nWrite; i++)
+ OUTREG(AVIVO_I2C_DATA, data[i]);
+
+ /* set to i2c tx mode */
+ temp = INREG(AVIVO_I2C_START_CNTL);
+ temp &= ~R520_I2C_RX;
+ OUTREG(AVIVO_I2C_START_CNTL, temp);
+
+ /* set go flag */
+ OUTREG(AVIVO_I2C_STATUS, AVIVO_I2C_STATUS_GO);
+
+ count = 0;
+ do {
+ temp = INREG(AVIVO_I2C_STATUS);
+ if (temp & AVIVO_I2C_STATUS_DONE)
+ break;
+ usleep(1);
+ count++;
+ } while(count<10);
+
+ if (count == 10)
+ return FALSE;
+ OUTREG(AVIVO_I2C_STATUS, temp);
+
+ return TRUE;
+}
+static Bool
+AVIVOI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite,
+ I2CByte *ReadBuffer, int nRead)
+{
+ I2CBusPtr b = d->pI2CBus;
+ ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CARD32 temp;
+ int i, count;
+ int sofar, thisread;
+ I2CByte offbuf[1];
+ Bool ret;
+
+ AVIVOI2CReset(pScrn);
+
+ /* set the control1 flags */
+ if (nWrite > 1)
+ {
+ ret = AVIVOI2CSendData(d, d->SlaveAddr, nWrite, WriteBuffer);
+ if (ret==FALSE)
+ return FALSE;
+ }
+
+ if (nRead > 0 && nWrite == 1)
+ {
+ /* okay this is a standard read - the i2c hw can only do 15 bytes */
+ sofar = 0;
+ do {
+ thisread = nRead - sofar;
+ if (thisread > 15)
+ thisread = 15;
+
+ offbuf[0] = sofar;
+ ret = AVIVOI2CSendData(d, d->SlaveAddr, 1, offbuf);
+ if (ret==FALSE)
+ return FALSE;
+
+ OUTREG(AVIVO_I2C_DATA, d->SlaveAddr | 0x1);
+
+ temp = INREG(AVIVO_I2C_START_CNTL);
+ temp |= R520_I2C_RX;
+ OUTREG(AVIVO_I2C_START_CNTL, temp);
+
+ temp = INREG(AVIVO_I2C_CONTROL2);
+ temp &= ~R520_I2C_DATA_COUNT_MASK;
+ temp |= thisread << R520_I2C_DATA_COUNT_SHIFT;
+ temp &= ~R520_I2C_ADDR_COUNT_MASK;
+ temp |= 1;
+ OUTREG(AVIVO_I2C_CONTROL2, temp);
+
+ OUTREG(AVIVO_I2C_STATUS, AVIVO_I2C_STATUS_GO);
+ count = 0;
+ do {
+ temp = INREG(AVIVO_I2C_STATUS);
+ if (temp & AVIVO_I2C_STATUS_DONE)
+ break;
+ usleep(1);
+ count++;
+ } while(count<100);
+ if (count == 100)
+ return FALSE;
+
+ OUTREG(AVIVO_I2C_STATUS, temp);
+
+ for (i=0; i<thisread; i++)
+ {
+ temp = INREG(AVIVO_I2C_DATA);
+ ReadBuffer[sofar+i] = (I2CByte)(temp & 0xff);
+ }
+ sofar += thisread;
+ } while(sofar < nRead);
+ }
+ return TRUE;
+}
+
+
+Bool atombios_i2c_init(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ I2CBusPtr pI2CBus;
+
+ pI2CBus = xf86CreateI2CBusRec();
+ if (!pI2CBus)
+ return FALSE;
+
+ pI2CBus->BusName = name;
+ pI2CBus->scrnIndex = pScrn->scrnIndex;
+ pI2CBus->I2CWriteRead = AVIVOI2CWriteRead;
+ pI2CBus->DriverPrivate.uval = i2c_reg;
+
+ ErrorF("uval is %04X\n", i2c_reg);
+ if (!xf86I2CBusInit(pI2CBus))
+ return FALSE;
+
+ *bus_ptr = pI2CBus;
+ return TRUE;
+}
+
+#else
+Bool
+atom_bios_i2c_init(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
+{
+ I2CBusPtr pI2CBus;
+
+ pI2CBus = xf86CreateI2CBusRec();
+ if (!pI2CBus) return FALSE;
+
+ pI2CBus->BusName = name;
+ pI2CBus->scrnIndex = pScrn->scrnIndex;
+ if (i2c_reg == AVIVO_GPIO_0) {
+ pI2CBus->I2CPutBits = atombios_i2c_gpio0_put_bits;
+ pI2CBus->I2CGetBits = atombios_i2c_gpio0_get_bits;
+ } else {
+ pI2CBus->I2CPutBits = atombios_i2c_gpio123_put_bits;
+ pI2CBus->I2CGetBits = atombios_i2c_gpio123_get_bits;
+ }
+ pI2CBus->AcknTimeout = 5;
+ pI2CBus->DriverPrivate.uval = i2c_reg;
+
+ if (!xf86I2CBusInit(pI2CBus)) return FALSE;
+
+ *bus_ptr = pI2CBus;
+ return TRUE;
+}
+#endif
+
+void atombios_init_connector(xf86OutputPtr output)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ int DDCReg = 0;
+ char* name = (char*) DDCTypeName[radeon_output->DDCType];
+
+ if (radeon_output->gpio) {
+ radeon_output->DDCReg = radeon_output->gpio;
+ if (IS_AVIVO_VARIANT)
+ atom_bios_i2c_init(pScrn, &radeon_output->pI2CBus, radeon_output->gpio, output->name);
+ else
+ RADEONI2CInit(pScrn, &radeon_output->pI2CBus, radeon_output->DDCReg, name);
+ }
+
+ if (radeon_output->type == OUTPUT_LVDS) {
+ RADEONGetLVDSInfo(output);
+ }
+
+ if (radeon_output->type == OUTPUT_DVI) {
+ // RADEONGetTMDSInfo(output);
+ }
+
+ if (radeon_output->type == OUTPUT_STV ||
+ radeon_output->type == OUTPUT_CTV) {
+ // RADEONGetTVInfo(output);
+ }
+
+ if (radeon_output->DACType == DAC_TVDAC) {
+ radeon_output->tv_on = FALSE;
+ // RADEONGetTVDacAdjInfo(output);
+ }
+
+}
+
+Bool atombios_setup_outputs(ScrnInfoPtr pScrn, int num_vga, int num_dvi)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ xf86OutputPtr output;
+ int i;
+
+ for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
+ if (info->BiosConnector[i].valid) {
+ RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
+ if (!radeon_output) {
+ return FALSE;
+ }
+ radeon_output->MonType = MT_UNKNOWN;
+ radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType;
+ radeon_output->DDCType = info->BiosConnector[i].DDCType;
+ radeon_output->gpio = info->BiosConnector[i].gpio;
+ if (info->IsAtomBios) {
+ if (radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM)
+ radeon_output->DACType = DAC_NONE;
+ else
+ radeon_output->DACType = info->BiosConnector[i].DACType;
+
+ if (radeon_output->ConnectorType == CONNECTOR_VGA_ATOM)
+ radeon_output->TMDSType = TMDS_NONE;
+ else
+ radeon_output->TMDSType = info->BiosConnector[i].TMDSType;
+ } else {
+ if (radeon_output->ConnectorType == CONNECTOR_DVI_D)
+ radeon_output->DACType = DAC_NONE;
+ else
+ radeon_output->DACType = info->BiosConnector[i].DACType;
+
+ if (radeon_output->ConnectorType == CONNECTOR_CRT)
+ radeon_output->TMDSType = TMDS_NONE;
+ else
+ radeon_output->TMDSType = info->BiosConnector[i].TMDSType;
+ }
+ RADEONSetOutputType(pScrn, radeon_output);
+ fprintf(stderr,"output type is %d\n", radeon_output->type);
+ if (info->IsAtomBios) {
+ if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D_ATOM) ||
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I_ATOM) ||
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A_ATOM)) {
+ if (num_dvi > 1) {
+ output = xf86OutputCreate(pScrn, &atombios_output_tmds_funcs, "DVI-1");
+ num_dvi--;
+ } else {
+ output = xf86OutputCreate(pScrn, &atombios_output_tmds_funcs, "DVI-0");
+ }
+ } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA_ATOM) {
+ if (num_vga > 1) {
+ output = xf86OutputCreate(pScrn, &atombios_output_dac_funcs, "VGA-1");
+ num_vga--;
+ } else {
+ output = xf86OutputCreate(pScrn, &atombios_output_dac_funcs, "VGA-0");
+ }
+ } else if (info->BiosConnector[i].ConnectorType != CONNECTOR_STV)
+ output = xf86OutputCreate(pScrn, &atombios_output_lfp_funcs, OutputType[radeon_output->type]);
+ } else {
+ if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
+ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I)) {
+ if (num_dvi > 1) {
+ output = xf86OutputCreate(pScrn, &atombios_output_tmds_funcs, "DVI-1");
+ num_dvi--;
+ } else {
+ output = xf86OutputCreate(pScrn, &atombios_output_tmds_funcs, "DVI-0");
+ }
+ } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT) {
+ if (num_vga > 1) {
+ output = xf86OutputCreate(pScrn, &atombios_output_dac_funcs, "VGA-1");
+ num_vga--;
+ } else {
+ output = xf86OutputCreate(pScrn, &atombios_output_dac_funcs, "VGA-0");
+ }
+ } else
+ output = xf86OutputCreate(pScrn, &atombios_output_lfp_funcs, OutputType[radeon_output->type]);
+ }
+
+ if (!output) {
+ return FALSE;
+ }
+ output->driver_private = radeon_output;
+ output->possible_crtcs = 1;
+ /* crtc2 can drive LVDS, it just doesn't have RMX */
+ if (radeon_output->type != OUTPUT_LVDS)
+ output->possible_crtcs |= 2;
+
+ /* we can clone the DACs, and probably TV-out,
+ but I'm not sure it's worth the trouble */
+ output->possible_clones = 0;
+
+ atombios_init_connector(output);
+ }
+ }
+ return TRUE;
+}
+
+static AtomBiosResult
+atom_bios_dac_load_detect(atomBIOSHandlePtr atomBIOS, int dac)
+{
+ DAC_LOAD_DETECTION_PS_ALLOCATION dac_data;
+ AtomBIOSArg data;
+ unsigned char *space;
+
+ dac_data.sDacload.usDeviceID = 0;
+ dac_data.sDacload.ucDacType = 0;
+ dac_data.sDacload.ucMisc = 0;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &dac_data;
+
+ if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+
+ ErrorF("Dac detection success\n");
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("DAC detection failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+static RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONMonitorType MonType = MT_NONE;
+ AtomBiosResult ret;
+ uint32_t bios_0_scratch;
+
+ ret = atom_bios_dac_load_detect(info->atomBIOS, radeon_output->DACType);
+ if (ret == ATOM_SUCCESS) {
+ ErrorF("DAC connect %08X\n", INREG(0x10));
+ bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH);
+
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ if (bios_0_scratch & ATOM_S0_CRT1_COLOR)
+ MonType = MT_CRT;
+ } else {
+ if (bios_0_scratch & ATOM_S0_CRT2_COLOR)
+ MonType = MT_CRT;
+ }
+ }
+ return MonType;
+}
+
+static RADEONMonitorType atombios_port_check_nonddc(ScrnInfoPtr pScrn, xf86OutputPtr output)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONMonitorType MonType = MT_NONE;
+ uint32_t bios_0_scratch;
+ int ret;
+ if (radeon_output->type == OUTPUT_LVDS) {
+ MonType = MT_LCD;
+ }
+#if 0
+ else if (radeon_output->type == OUTPUT_DVI) {
+ if (radeon_output->TMDSType == TMDS_INT) {
+ if (INREG(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
+ MonType = MT_DFP;
+ } else if (radeon_output->TMDSType == TMDS_EXT) {
+ if (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
+ MonType = MT_DFP;
+ }
+ }
+#endif
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Detected Monitor Type: %d\n", MonType);
+
+ return MonType;
+
+}
+
+
+static RADEONMonitorType
+atombios_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned long DDCReg;
+ RADEONMonitorType MonType = MT_NONE;
+ xf86MonPtr* MonInfo = &output->MonInfo;
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONDDCType DDCType = radeon_output->DDCType;
+ int i, j;
+
+ if (!IS_AVIVO_VARIANT) {
+ ErrorF("AGD: DDCConnected\n");
+ return RADEONDisplayDDCConnected(pScrn, output);
+ }
+
+ AVIVOI2CDoLock(output->scrn, 1);
+ *MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
+ AVIVOI2CDoLock(output->scrn, 0);
+ if (*MonInfo) {
+ if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_LVDS_ATOM) ||
+ (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_PROPRIETARY)) {
+ MonType = MT_LCD;
+ } else if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM) ||
+ (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D)) {
+ MonType = MT_DFP;
+ } else if (radeon_output->type == OUTPUT_DVI &&
+ ((*MonInfo)->rawData[0x14] & 0x80)) { /* if it's digital and DVI */
+ MonType = MT_DFP;
+ } else {
+ MonType = MT_CRT;
+ }
+ } else MonType = MT_NONE;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DDC Type: %d[%04x], Detected Monitor Type: %d\n", DDCType, radeon_output->gpio, MonType);
+
+ return MonType;
+}
+
+extern const char *ConnectorTypeNameATOM[];
+extern const char *ConnectorTypeName[];
+
+void atombios_connector_find_monitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+
+ ErrorF("AGD: atom connector find monitor\n");
+
+ if (radeon_output->MonType == MT_UNKNOWN) {
+ radeon_output->MonType = atombios_display_ddc_connected(pScrn, output);
+ if (!radeon_output->MonType) {
+ ErrorF("AGD: No DDC\n");
+ if (radeon_output->type == OUTPUT_LVDS || radeon_output->type == OUTPUT_DVI)
+ radeon_output->MonType = atombios_port_check_nonddc(pScrn, output);
+#if 0
+ if (!radeon_output->MonType) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ radeon_output->MonType = atombios_dac_detect(pScrn, output);
+ }
+ }
+#endif
+ if (!radeon_output->MonType) {
+ radeon_output->MonType = MT_NONE;
+ }
+ }
+ }
+ /* update panel info for RMX */
+ // if (radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP)
+ // RADEONUpdatePanelSize(output);
+
+ if (output->MonInfo) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on connector: %s ----------------------\n",
+ info->IsAtomBios ?
+ ConnectorTypeNameATOM[radeon_output->ConnectorType]:
+ ConnectorTypeName[radeon_output->ConnectorType]
+ );
+ xf86PrintEDID( output->MonInfo );
+ }
+}
commit 20f01950e42babc308b4470df6a3c6628c932003
Author: Alex Deucher <alex at botch2.(none)>
Date: Tue Nov 6 18:04:43 2007 -0500
for r4xx ATOM cards, just use ATOM for PLL
while crtc timing and pll seem to work fine, output setup
and routing don't seem to work too reliably with atom.
AMD claims ATOM was still pretty new with r4xx so
it's probably better to stick with direct programming for
some things.
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 5530713..4a017c0 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -70,10 +70,10 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
-#if 1
+#if 0
if (info->IsAtomBios) {
atombios_crtc_dpms(crtc, mode);
- //return;
+ return;
}
#endif
@@ -132,12 +132,7 @@ radeon_crtc_mode_prepare(xf86CrtcPtr crtc)
ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
-#if 1
- if (info->IsAtomBios)
- atombios_crtc_dpms(crtc, DPMSModeOff);
- else
-#endif
- radeon_crtc_dpms(crtc, DPMSModeOff);
+ radeon_crtc_dpms(crtc, DPMSModeOff);
}
/* Define common registers for requested video mode */
@@ -916,26 +911,24 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
ErrorF("restore common\n");
RADEONRestoreCommonRegisters(pScrn, &info->ModeReg);
-#if 1
- if (info->IsAtomBios) {
- //RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
- atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
- return;
- }
-#endif
-
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("restore crtc1\n");
RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
ErrorF("restore pll1\n");
- RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
+ if (info->IsAtomBios)
+ atombios_crtc_set_pll(crtc, adjusted_mode);
+ else
+ RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
break;
case 1:
ErrorF("restore crtc2\n");
RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg);
ErrorF("restore pll2\n");
- RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
+ if (info->IsAtomBios)
+ atombios_crtc_set_pll(crtc, adjusted_mode);
+ else
+ RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
break;
}
@@ -960,13 +953,6 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
/* reset ecp_div for Xv */
info->ecp_div = -1;
-#if 0
- if (info->IsAtomBios) {
- atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
- //return;
- }
-#endif
-
}
static void
@@ -975,12 +961,7 @@ radeon_crtc_mode_commit(xf86CrtcPtr crtc)
ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
-#if 1
- if (info->IsAtomBios)
- atombios_crtc_dpms(crtc, DPMSModeOn);
- //else
-#endif
- radeon_crtc_dpms(crtc, DPMSModeOn);
+ radeon_crtc_dpms(crtc, DPMSModeOn);
}
void radeon_crtc_load_lut(xf86CrtcPtr crtc)
diff --git a/src/radeon_output.c b/src/radeon_output.c
index d00908b..be542a4 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -160,6 +160,7 @@ extern void atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr adjusted_mode);
extern void atombios_output_dpms(xf86OutputPtr output, int mode);
#endif
+
Bool
RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch)
{
@@ -714,7 +715,7 @@ radeon_dpms(xf86OutputPtr output, int mode)
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
-#if 1
+#if 0
if (info->IsAtomBios) {
atombios_output_dpms(output, mode);
return;
@@ -1224,10 +1225,10 @@ radeon_mode_commit(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
-#if 1
+#if 0
if (info->IsAtomBios)
atombios_output_dpms(output, DPMSModeOn);
- //else
+ else
#endif
RADEONEnableDisplay(output, TRUE);
}
commit 78a3eabff382e8ebe33df2039076fb083bcc361b
Author: Alex Deucher <alex at botch2.(none)>
Date: Sun Nov 4 14:11:26 2007 -0500
WIP: get ATOM crtc stuff working on r4xx
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index ec30218..972001b 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -151,7 +151,7 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->FbFreeStart = atomBiosArg.fb.start;
info->FbFreeSize = atomBiosArg.fb.size;
}
- rhdTestAtomBIOS(info->atomBIOS);
+ //rhdTestAtomBIOS(info->atomBIOS);
#endif
info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32);
}
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index de24273..5530713 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -54,7 +54,13 @@
#endif
void radeon_crtc_load_lut(xf86CrtcPtr crtc);
-
+#if 0
+extern void atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode,
+ int x, int y);
+extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode);
+#endif
static void
radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
{
@@ -63,7 +69,14 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
-
+
+#if 1
+ if (info->IsAtomBios) {
+ atombios_crtc_dpms(crtc, mode);
+ //return;
+ }
+#endif
+
mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS);
@@ -116,7 +129,15 @@ radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
static void
radeon_crtc_mode_prepare(xf86CrtcPtr crtc)
{
- radeon_crtc_dpms(crtc, DPMSModeOff);
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+#if 1
+ if (info->IsAtomBios)
+ atombios_crtc_dpms(crtc, DPMSModeOff);
+ else
+#endif
+ radeon_crtc_dpms(crtc, DPMSModeOff);
}
/* Define common registers for requested video mode */
@@ -168,7 +189,7 @@ RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save)
}
-static Bool
+Bool
RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
int x, int y)
{
@@ -286,7 +307,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
}
/* Define CRTC registers for requested video mode */
-static Bool
+Bool
RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
DisplayModePtr mode)
{
@@ -399,7 +420,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
return TRUE;
}
-static Bool
+Bool
RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
int x, int y)
{
@@ -512,7 +533,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
}
/* Define CRTC2 registers for requested video mode */
-static Bool
+Bool
RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
DisplayModePtr mode)
{
@@ -812,6 +833,13 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
#endif
}
+#if 0
+ if (info->IsAtomBios) {
+ atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
+ return;
+ }
+#endif
+
for (i = 0; i < xf86_config->num_output; i++) {
xf86OutputPtr output = xf86_config->output[i];
RADEONOutputPrivatePtr radeon_output = output->driver_private;
@@ -888,6 +916,14 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
ErrorF("restore common\n");
RADEONRestoreCommonRegisters(pScrn, &info->ModeReg);
+#if 1
+ if (info->IsAtomBios) {
+ //RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
+ atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
+ return;
+ }
+#endif
+
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("restore crtc1\n");
@@ -924,12 +960,27 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
/* reset ecp_div for Xv */
info->ecp_div = -1;
+#if 0
+ if (info->IsAtomBios) {
+ atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
+ //return;
+ }
+#endif
+
}
static void
radeon_crtc_mode_commit(xf86CrtcPtr crtc)
{
- radeon_crtc_dpms(crtc, DPMSModeOn);
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+#if 1
+ if (info->IsAtomBios)
+ atombios_crtc_dpms(crtc, DPMSModeOn);
+ //else
+#endif
+ radeon_crtc_dpms(crtc, DPMSModeOn);
}
void radeon_crtc_load_lut(xf86CrtcPtr crtc)
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 9cfc2c4..d00908b 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -154,7 +154,12 @@ static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color
static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color);
static RADEONMonitorType radeon_detect_ext_dac(ScrnInfoPtr pScrn);
static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output);
-
+#if 0
+extern void atombios_output_mode_set(xf86OutputPtr output,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode);
+extern void atombios_output_dpms(xf86OutputPtr output, int mode);
+#endif
Bool
RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch)
{
@@ -706,6 +711,16 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr
static void
radeon_dpms(xf86OutputPtr output, int mode)
{
+ ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+#if 1
+ if (info->IsAtomBios) {
+ atombios_output_dpms(output, mode);
+ return;
+ }
+#endif
+
switch(mode) {
case DPMSModeOn:
RADEONEnableDisplay(output, TRUE);
@@ -1153,6 +1168,15 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
xf86CrtcPtr crtc = output->crtc;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+#if 0
+ if (info->IsAtomBios) {
+ ErrorF("AGD: output mode set start\n");
+ atombios_output_mode_set(output, mode, adjusted_mode);
+ ErrorF("AGD: output mode set end\n");
+ return;
+ }
+#endif
+
RADEONInitOutputRegisters(pScrn, &info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id);
if (radeon_crtc->crtc_id == 0)
@@ -1184,12 +1208,28 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
RADEONRestoreDACRegisters(pScrn, &info->ModeReg);
}
+#if 0
+ if (info->IsAtomBios) {
+ ErrorF("AGD: output mode set start\n");
+ atombios_output_mode_set(output, mode, adjusted_mode);
+ ErrorF("AGD: output mode set end\n");
+ //return;
+ }
+#endif
+
}
static void
radeon_mode_commit(xf86OutputPtr output)
{
- RADEONEnableDisplay(output, TRUE);
+ ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+#if 1
+ if (info->IsAtomBios)
+ atombios_output_dpms(output, DPMSModeOn);
+ //else
+#endif
+ RADEONEnableDisplay(output, TRUE);
}
/* the following functions are based on the load detection code
commit 5e9ebd8e496b72b051053d637c63b2956b7861d3
Author: Alex Deucher <alex at botch2.(none)>
Date: Sat Nov 3 20:46:17 2007 -0400
Initial support for r4xx
- add r3xx/r4xx MC access macros and functions
diff --git a/src/Makefile.am b/src/Makefile.am
index bcc6637..9bad63d 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -100,7 +100,7 @@ radeon_drv_la_SOURCES = \
radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \
radeon_vip.c radeon_misc.c radeon_probe.c radeon_display.c \
radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \
- $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c\
+ $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \
$(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c
theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 12af4eb..009df2f 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -386,7 +386,7 @@ rhdInitAtomBIOS(int scrnIndex)
#if ATOM_BIOS_PARSER
/* Try to find out if BIOS has been posted (either by system or int10 */
- if (1 || !rhdBIOSGetFbBaseAndSize(scrnIndex, handle, &dummy, &dummy)) {
+ if (!rhdBIOSGetFbBaseAndSize(scrnIndex, handle, &dummy, &dummy)) {
/* run AsicInit */
if (!rhdASICInit(handle))
xf86DrvMsg(scrnIndex, X_WARNING,
@@ -849,7 +849,7 @@ CailReadMC(VOID *CAIL, ULONG Address)
ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
CAILFUNC(CAIL);
- ret = AVIVOINMC(pScrn, Address);
+ ret = INMC(pScrn, Address);
DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));
return ret;
}
@@ -860,7 +860,7 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data)
CAILFUNC(CAIL);
ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data));
- AVIVOOUTMC(pScrn, Address, data);
+ OUTMC(pScrn, Address, data);
}
VOID
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 3965263..ec30218 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -132,12 +132,16 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
else
info->IsAtomBios = FALSE;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n",
+ info->IsAtomBios ? "ATOM":"Legacy");
+
if (info->IsAtomBios) {
+#if 1
AtomBIOSArg atomBiosArg;
- if (RHDAtomBIOSFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) == ATOM_SUCCESS) {
+ if (RHDAtomBIOSFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) == ATOM_SUCCESS) {
info->atomBIOS = atomBiosArg.ptr;
- }
+ }
atomBiosArg.fb.start = info->FbFreeStart;
atomBiosArg.fb.size = info->FbFreeSize;
@@ -148,12 +152,10 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->FbFreeSize = atomBiosArg.fb.size;
}
rhdTestAtomBIOS(info->atomBIOS);
+#endif
info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32);
}
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n",
- info->IsAtomBios ? "ATOM":"Legacy");
-
return TRUE;
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index a243c9f..04a117b 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -716,6 +716,29 @@ void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data)
RADEONPllErrataAfterData(info);
}
+/* Read MC register */
+unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CARD32 data;
+
+ OUTREG8(R300_MC_IND_INDEX, addr & 0x3f);
+ data = INREG(R300_MC_IND_DATA);
+
+ return data;
+}
+
+/* Write PLL information */
+void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ OUTREG8(R300_MC_IND_INDEX, (((addr) & 0x3f) |
+ R300_MC_IND_WR_EN));
+ OUTREG(R300_MC_IND_DATA, data);
+}
#if 0
/* Read PAL information (only used for debugging) */
diff --git a/src/radeon_macros.h b/src/radeon_macros.h
index efc9e82..4359eb8 100644
--- a/src/radeon_macros.h
+++ b/src/radeon_macros.h
@@ -129,4 +129,8 @@ do { \
} \
} while (0)
+#define INMC(pScrn, addr) RADEONINMC(pScrn, addr)
+
+#define OUTMC(pScrn, addr, val) RADEONOUTMC(pScrn, addr, val)
+
#endif
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 2653339..1122f13 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -996,6 +996,7 @@
#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
#define R300_MC_IND_INDEX 0x01f8
# define R300_MC_IND_ADDR_MASK 0x3f
+# define R300_MC_IND_WR_EN (1 << 8)
#define R300_MC_IND_DATA 0x01fc
#define R300_MC_READ_CNTL_AB 0x017c
# define R300_MEM_RBS_POSITION_A_MASK 0x03
@@ -3270,4 +3271,6 @@
#define RADEON_RS480_UNK_e38 0xe38
#define RADEON_RS480_UNK_e3c 0xe3c
+#include "avivo_reg.h"
+
#endif
commit c106075ccb81ca2ee4894743e676fd37653c8dce
Author: Alex Deucher <alex at botch2.(none)>
Date: Sat Nov 3 18:29:20 2007 -0400
More of Dave's ATOM init code.
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 1b46746..3965263 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -39,6 +39,7 @@
#include "radeon_reg.h"
#include "radeon_macros.h"
#include "radeon_probe.h"
+#include "radeon_atombios.h"
#include "vbe.h"
/* Read the Video BIOS block and the FP registers (if applicable). */
@@ -131,8 +132,24 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
else
info->IsAtomBios = FALSE;
- if (info->IsAtomBios)
+ if (info->IsAtomBios) {
+ AtomBIOSArg atomBiosArg;
+
+ if (RHDAtomBIOSFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) == ATOM_SUCCESS) {
+ info->atomBIOS = atomBiosArg.ptr;
+ }
+
+ atomBiosArg.fb.start = info->FbFreeStart;
+ atomBiosArg.fb.size = info->FbFreeSize;
+ if (RHDAtomBIOSFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH,
+ &atomBiosArg) == ATOM_SUCCESS) {
+
+ info->FbFreeStart = atomBiosArg.fb.start;
+ info->FbFreeSize = atomBiosArg.fb.size;
+ }
+ rhdTestAtomBIOS(info->atomBIOS);
info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32);
+ }
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n",
info->IsAtomBios ? "ATOM":"Legacy");
commit e18f5d61806b445ad77d93e258fbce9422b52bb6
Author: Alex Deucher <alex at botch2.(none)>
Date: Sat Nov 3 18:20:55 2007 -0400
Initial integration of Atom code and some of Dave's code.
ATOM builds, but it's not hooked up yet.
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
new file mode 100644
index 0000000..1e48f81
--- /dev/null
+++ b/src/AtomBios/CD_Operations.c
@@ -0,0 +1,954 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+
+Module Name:
+
+ CD_Operations.c
+
+Abstract:
+
+ Functions Implementing Command Operations and other common functions
+
+Revision History:
+
+ NEG:27.09.2002 Initiated.
+--*/
+#define __SW_4
+
+#include "Decoder.h"
+#include "atombios.h"
+
+
+
+VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData);
+UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable);
+
+
+WRITE_IO_FUNCTION WritePCIFunctions[8] = {
+ WritePCIReg32,
+ WritePCIReg16, WritePCIReg16, WritePCIReg16,
+ WritePCIReg8,WritePCIReg8,WritePCIReg8,WritePCIReg8
+};
+WRITE_IO_FUNCTION WriteIOFunctions[8] = {
+ WriteSysIOReg32,
+ WriteSysIOReg16,WriteSysIOReg16,WriteSysIOReg16,
+ WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8
+};
+READ_IO_FUNCTION ReadPCIFunctions[8] = {
+ (READ_IO_FUNCTION)ReadPCIReg32,
+ (READ_IO_FUNCTION)ReadPCIReg16,
+ (READ_IO_FUNCTION)ReadPCIReg16,
+ (READ_IO_FUNCTION)ReadPCIReg16,
+ (READ_IO_FUNCTION)ReadPCIReg8,
+ (READ_IO_FUNCTION)ReadPCIReg8,
+ (READ_IO_FUNCTION)ReadPCIReg8,
+ (READ_IO_FUNCTION)ReadPCIReg8
+};
+READ_IO_FUNCTION ReadIOFunctions[8] = {
+ (READ_IO_FUNCTION)ReadSysIOReg32,
+ (READ_IO_FUNCTION)ReadSysIOReg16,
+ (READ_IO_FUNCTION)ReadSysIOReg16,
+ (READ_IO_FUNCTION)ReadSysIOReg16,
+ (READ_IO_FUNCTION)ReadSysIOReg8,
+ (READ_IO_FUNCTION)ReadSysIOReg8,
+ (READ_IO_FUNCTION)ReadSysIOReg8,
+ (READ_IO_FUNCTION)ReadSysIOReg8
+};
+READ_IO_FUNCTION GetParametersDirectArray[8]={
+ GetParametersDirect32,
+ GetParametersDirect16,GetParametersDirect16,GetParametersDirect16,
+ GetParametersDirect8,GetParametersDirect8,GetParametersDirect8,
+ GetParametersDirect8
+};
+
+COMMANDS_DECODER PutDataFunctions[6] = {
+ PutDataRegister,
+ PutDataPS,
+ PutDataWS,
+ PutDataFB,
+ PutDataPLL,
+ PutDataMC
+};
+CD_GET_PARAMETERS GetDestination[6] = {
+ GetParametersRegister,
+ GetParametersPS,
+ GetParametersWS,
+ GetParametersFB,
+ GetParametersPLL,
+ GetParametersMC
+};
+
+COMMANDS_DECODER SkipDestination[6] = {
+ SkipParameters16,
+ SkipParameters8,
+ SkipParameters8,
+ SkipParameters8,
+ SkipParameters8,
+ SkipParameters8
+};
+
+CD_GET_PARAMETERS GetSource[8] = {
+ GetParametersRegister,
+ GetParametersPS,
+ GetParametersWS,
+ GetParametersFB,
+ GetParametersIndirect,
+ GetParametersDirect,
+ GetParametersPLL,
+ GetParametersMC
+};
+
+UINT32 AlignmentMask[8] = {0xFFFFFFFF,0xFFFF,0xFFFF,0xFFFF,0xFF,0xFF,0xFF,0xFF};
+UINT8 SourceAlignmentShift[8] = {0,0,8,16,0,8,16,24};
+UINT8 DestinationAlignmentShift[4] = {0,8,16,24};
+
+#define INDIRECTIO_ID 1
+#define INDIRECTIO_END_OF_ID 9
+
+VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_MOVE(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT32 temp);
+VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+
+INDIRECT_IO_PARSER_COMMANDS IndirectIOParserCommands[10]={
+ {IndirectIOCommand,1},
+ {IndirectIOCommand,2},
+ {ReadIndReg32,3},
+ {WriteIndReg32,3},
+ {IndirectIOCommand_CLEAR,3},
+ {IndirectIOCommand_SET,3},
+ {IndirectIOCommand_MOVE_INDEX,4},
+ {IndirectIOCommand_MOVE_ATTR,4},
+ {IndirectIOCommand_MOVE_DATA,4},
+ {IndirectIOCommand,3}
+};
+
+
+VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+}
+
+
+VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
+ pParserTempData->IndirectData |=(((pParserTempData->Index >> pParserTempData->IndirectIOTablePointer[2]) &
+ (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
+}
+
+VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
+ pParserTempData->IndirectData |=(((pParserTempData->AttributesData >> pParserTempData->IndirectIOTablePointer[2])
+ & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
+}
+
+VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
+ pParserTempData->IndirectData |=(((pParserTempData->DestData32 >> pParserTempData->IndirectIOTablePointer[2])
+ & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
+}
+
+
+VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->IndirectData |= ((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]);
+}
+
+VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]);
+}
+
+
+UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ // if ((pParserTempData->IndirectData & 0x7f)==INDIRECT_IO_MM) pParserTempData->IndirectData|=pParserTempData->CurrentPortID;
+// pParserTempData->IndirectIOTablePointer=pParserTempData->IndirectIOTable;
+ while (*pParserTempData->IndirectIOTablePointer)
+ {
+ if ((pParserTempData->IndirectIOTablePointer[0] == INDIRECTIO_ID) &&
+ (pParserTempData->IndirectIOTablePointer[1] == pParserTempData->IndirectData))
+ {
+ pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
+ while (*pParserTempData->IndirectIOTablePointer != INDIRECTIO_END_OF_ID)
+ {
+ IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData);
+ pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
+ }
+ pParserTempData->IndirectIOTablePointer-=*(UINT16*)(pParserTempData->IndirectIOTablePointer+1);
+ pParserTempData->IndirectIOTablePointer++;
+ return pParserTempData->IndirectData;
+ } else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
+ }
+ return 0;
+}
+
+
+
+VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.WordXX.PA_Destination;
+ pParserTempData->Index+=pParserTempData->CurrentRegBlock;
+ switch(pParserTempData->Multipurpose.CurrentPort){
+ case ATI_RegsPort:
+ if (pParserTempData->CurrentPortID == INDIRECT_IO_MM)
+ {
+ if (pParserTempData->Index==0) pParserTempData->DestData32 <<= 2;
+ WriteReg32( pParserTempData);
+ } else
+ {
+ pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_WRITE;
+ IndirectInputOutput(pParserTempData);
+ }
+ break;
+ case PCI_Port:
+ WritePCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
+ break;
+ case SystemIO_Port:
+ WriteIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
+ break;
+ }
+}
+
+VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)=
+ pParserTempData->DestData32;
+}
+
+VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C)
+ *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32;
+ else
+ switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)
+ {
+ case WS_REMINDER_C:
+ pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32;
+ break;
+ case WS_QUOTIENT_C:
+ pParserTempData->MultiplicationOrDivision.Division.Quotient32=pParserTempData->DestData32;
+ break;
+ case WS_DATAPTR_C:
+#ifndef UEFI_BUILD
+ pParserTempData->CurrentDataBlock=(UINT16)pParserTempData->DestData32;
+#else
+ pParserTempData->CurrentDataBlock=(UINTN)pParserTempData->DestData32;
+#endif
+ break;
+ case WS_SHIFT_C:
+ pParserTempData->Shift2MaskConverter=(UINT8)pParserTempData->DestData32;
+ break;
+ case WS_FB_WINDOW_C:
+ pParserTempData->CurrentFB_Window=pParserTempData->DestData32;
+ break;
+ case WS_ATTRIBUTES_C:
+ pParserTempData->AttributesData=(UINT16)pParserTempData->DestData32;
+ break;
+ }
+
+}
+
+VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination;
+ //Make an Index from address first, then add to the Index
+ pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2);
+ WriteFrameBuffer32(pParserTempData);
+}
+
+VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination;
+ WritePLL32( pParserTempData );
+}
+
+VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination;
+ WriteMC32( pParserTempData );
+}
+
+
+VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
+}
+
+VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
+}
+
+
+UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
+ pParserTempData->Index+=pParserTempData->CurrentRegBlock;
+ switch(pParserTempData->Multipurpose.CurrentPort)
+ {
+ case PCI_Port:
+ return ReadPCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
+ case SystemIO_Port:
+ return ReadIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
+ case ATI_RegsPort:
+ default:
+ if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) return ReadReg32( pParserTempData );
+ else
+ {
+ pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_READ;
+ return IndirectInputOutput(pParserTempData);
+ }
+ }
+}
+
+UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
+ return *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index);
+}
+
+UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
+ if (pParserTempData->Index < WS_QUOTIENT_C)
+ return *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->Index);
+ else
+ switch (pParserTempData->Index)
+ {
+ case WS_REMINDER_C:
+ return pParserTempData->MultiplicationOrDivision.Division.Reminder32;
+ case WS_QUOTIENT_C:
+ return pParserTempData->MultiplicationOrDivision.Division.Quotient32;
+ case WS_DATAPTR_C:
+ return (UINT32)pParserTempData->CurrentDataBlock;
+ case WS_OR_MASK_C:
+ return ((UINT32)1) << pParserTempData->Shift2MaskConverter;
+ case WS_AND_MASK_C:
+ return ~(((UINT32)1) << pParserTempData->Shift2MaskConverter);
+ case WS_FB_WINDOW_C:
+ return pParserTempData->CurrentFB_Window;
+ case WS_ATTRIBUTES_C:
+ return pParserTempData->AttributesData;
+ }
+ return 0;
+
+}
+
+UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
+ pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2);
+ return ReadFrameBuffer32(pParserTempData);
+}
+
+UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
+ return ReadPLL32( pParserTempData );
+}
+
+UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
+ return ReadMC32( pParserTempData );
+}
+
+
+UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
+ return *(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock);
+}
+
+UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->CD_Mask.SrcAlignment=alignmentByte0;
+ pParserTempData->Index=*(UINT8*)pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
+ return pParserTempData->Index;
+}
+
+UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord;
+ pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
+ return pParserTempData->Index;
+}
+
+UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->CD_Mask.SrcAlignment=alignmentDword;
+ pParserTempData->Index=*(UINT32*)pParserTempData->pWorkingTableData->IP;
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT32);
+ return pParserTempData->Index;
+}
+
+
+UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ return GetParametersDirectArray[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
+}
+
+
+VOID CommonSourceDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
+}
+
+VOID CommonOperationDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->DestData32 >>= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
+ pParserTempData->DestData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
+}
+
+VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword)
+ {
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ } else
+ {
+ SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ }
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+
+ if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword)
+ {
+ pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
+ CommonSourceDataTransformation(pParserTempData);
+ pParserTempData->DestData32 |= pParserTempData->SourceData32;
+ } else
+ {
+ pParserTempData->DestData32=pParserTempData->SourceData32;
+ }
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+VOID ProcessMask(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetParametersDirect(pParserTempData);
+ pParserTempData->Index=GetParametersDirect(pParserTempData);
+ pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
+ pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
+ pParserTempData->DestData32 &= pParserTempData->SourceData32;
+ pParserTempData->Index &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->Index <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
+ pParserTempData->DestData32 |= pParserTempData->Index;
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+VOID ProcessAnd(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
+ pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
+ pParserTempData->DestData32 &= pParserTempData->SourceData32;
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+VOID ProcessOr(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ CommonSourceDataTransformation(pParserTempData);
+ pParserTempData->DestData32 |= pParserTempData->SourceData32;
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+VOID ProcessXor(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ CommonSourceDataTransformation(pParserTempData);
+ pParserTempData->DestData32 ^= pParserTempData->SourceData32;
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+VOID ProcessShl(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ CommonSourceDataTransformation(pParserTempData);
+ pParserTempData->DestData32 <<= pParserTempData->SourceData32;
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+VOID ProcessShr(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ CommonSourceDataTransformation(pParserTempData);
+ pParserTempData->DestData32 >>= pParserTempData->SourceData32;
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+
+VOID ProcessADD(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ CommonSourceDataTransformation(pParserTempData);
+ pParserTempData->DestData32 += pParserTempData->SourceData32;
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+VOID ProcessSUB(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ CommonSourceDataTransformation(pParserTempData);
+ pParserTempData->DestData32 -= pParserTempData->SourceData32;
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+VOID ProcessMUL(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ CommonOperationDataTransformation(pParserTempData);
+ pParserTempData->MultiplicationOrDivision.Multiplication.Low32Bit=pParserTempData->DestData32 * pParserTempData->SourceData32;
+}
+
+VOID ProcessDIV(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+
+ CommonOperationDataTransformation(pParserTempData);
+ pParserTempData->MultiplicationOrDivision.Division.Quotient32=
+ pParserTempData->DestData32 / pParserTempData->SourceData32;
+ pParserTempData->MultiplicationOrDivision.Division.Reminder32=
+ pParserTempData->DestData32 % pParserTempData->SourceData32;
+}
+
+
+VOID ProcessCompare(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+
+ CommonOperationDataTransformation(pParserTempData);
+
+ // Here we just set flags based on evaluation
+ if (pParserTempData->DestData32==pParserTempData->SourceData32)
+ pParserTempData->CompareFlags = Equal;
+ else
+ pParserTempData->CompareFlags =
+ (UINT8)((pParserTempData->DestData32<pParserTempData->SourceData32) ? Below : Above);
+
+}
+
+VOID ProcessClear(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]);
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+
+}
+
+VOID ProcessShift(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ UINT32 mask = AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetParametersDirect8(pParserTempData);
+
+ // save original value of the destination
+ pParserTempData->Index = pParserTempData->DestData32 & ~mask;
+ pParserTempData->DestData32 &= mask;
+
+ if (pParserTempData->pCmd->Header.Opcode < SHIFT_RIGHT_REG_OPCODE)
+ pParserTempData->DestData32 <<= pParserTempData->SourceData32; else
+ pParserTempData->DestData32 >>= pParserTempData->SourceData32;
+
+ // Clear any bits shifted out of masked area...
+ pParserTempData->DestData32 &= mask;
+ // ... and restore the area outside of masked with original values
+ pParserTempData->DestData32 |= pParserTempData->Index;
+
+ // write data back
+ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
+}
+
+VOID ProcessTest(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ CommonOperationDataTransformation(pParserTempData);
+ pParserTempData->CompareFlags =
+ (UINT8)((pParserTempData->DestData32 & pParserTempData->SourceData32) ? NotEqual : Equal);
+
+}
+
+VOID ProcessSetFB_Base(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->CurrentFB_Window=pParserTempData->SourceData32;
+}
+
+VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
+ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
+ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
+ pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
+ while ( *(UINT16*)pParserTempData->pWorkingTableData->IP != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
+ {
+ if (*pParserTempData->pWorkingTableData->IP == 'c')
+ {
+ pParserTempData->pWorkingTableData->IP++;
+ pParserTempData->DestData32=GetParametersDirect(pParserTempData);
+ pParserTempData->Index=GetParametersDirect16(pParserTempData);
+ if (pParserTempData->SourceData32 == pParserTempData->DestData32)
+ {
+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index);
+ return;
+ }
+ }
+ }
+ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
+}
+
+
+VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ UINT8 value;
+ UINT16* pMasterDataTable;
+ value=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
+ if (value == 0) pParserTempData->CurrentDataBlock=0; else
+ {
+ if (value == DB_CURRENT_COMMAND_TABLE)
+ {
+ pParserTempData->CurrentDataBlock= (UINT16)(pParserTempData->pWorkingTableData->pTableHead-pParserTempData->pDeviceData->pBIOS_Image);
+ } else
+ {
+ pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData);
+ pParserTempData->CurrentDataBlock= (TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value];
+ }
+ }
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
+}
+
+VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort;
+ pParserTempData->CurrentPortID = (UINT8)((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination;
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
+}
+
+VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->CurrentRegBlock = ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination;
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
+}
+
+
+//Atavism!!! Review!!!
+VOID cmdSet_X_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
+ pParserTempData->Multipurpose.CurrentPort=pParserTempData->ParametersType.Destination;
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_ONLY);
+
+}
+
+VOID cmdDelay_Millisec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
+ pParserTempData->SourceData32 =
+ ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
+ DelayMilliseconds(pParserTempData);
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
+}
+VOID cmdDelay_Microsec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
+ pParserTempData->SourceData32 =
+ ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
+ DelayMicroseconds(pParserTempData);
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
+}
+
+VOID ProcessPostChar(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->SourceData32 =
+ ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
+ PostCharOutput(pParserTempData);
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
+}
+
+VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->SourceData32 =
+ ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
+ CallerDebugFunc(pParserTempData);
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
+}
+
+
+VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->pWorkingTableData->IP+=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination+sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
+}
+
+
+VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
+ UINT16* MasterTableOffset;
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
+ MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData);
+ if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO
+ {
+ pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value);
+ pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable =
+ (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pParserTempData->pWorkingTableData->pTableHead)->TableAttribute.PS_SizeInBytes>>2);
+ pParserTempData->pDeviceData->pParameterSpace+=
+ pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable;
+ pParserTempData->Status=CD_CALL_TABLE;
+ pParserTempData->pCmd=(GENERIC_ATTRIBUTE_COMMAND*)MasterTableOffset;
+ }
+}
+
+
+VOID cmdNOP_(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+}
+
+
+static VOID NotImplemented(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->Status = CD_NOT_IMPLEMENTED;
+}
+
+
+VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ if ((pParserTempData->ParametersType.Destination == NoCondition) ||
+ (pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags ))
+ {
+
+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16);
+ } else
+ {
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
+ }
+}
+
+VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ if ((pParserTempData->CompareFlags == Equal) ||
+ (pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination))
+ {
+
+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16);
+ } else
+ {
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
+ }
+}
+
+VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ if (pParserTempData->CompareFlags != Equal)
+ {
+
+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16);
+ } else
+ {
+ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
+ }
+}
+
+
+
+COMMANDS_PROPERTIES CallTable[] =
+{
+ { NULL, 0,0},
+ { ProcessMove, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessMove, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessMove, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessMove, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessMove, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessMove, destMC, sizeof(COMMAND_HEADER)},
+ { ProcessAnd, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessAnd, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessAnd, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessAnd, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessAnd, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessAnd, destMC, sizeof(COMMAND_HEADER)},
+ { ProcessOr, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessOr, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessOr, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessOr, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessOr, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessOr, destMC, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destMC, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessShift, destMC, sizeof(COMMAND_HEADER)},
+ { ProcessMUL, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessMUL, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessMUL, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessMUL, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessMUL, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessMUL, destMC, sizeof(COMMAND_HEADER)},
+ { ProcessDIV, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessDIV, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessDIV, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessDIV, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessDIV, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessDIV, destMC, sizeof(COMMAND_HEADER)},
+ { ProcessADD, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessADD, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessADD, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessADD, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessADD, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessADD, destMC, sizeof(COMMAND_HEADER)},
+ { ProcessSUB, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessSUB, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessSUB, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessSUB, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessSUB, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessSUB, destMC, sizeof(COMMAND_HEADER)},
+ { cmdSet_ATI_Port, ATI_RegsPort, 0},
+ { cmdSet_X_Port, PCI_Port, 0},
+ { cmdSet_X_Port, SystemIO_Port, 0},
+ { cmdSet_Reg_Block, 0, 0},
+ { ProcessSetFB_Base,0, sizeof(COMMAND_HEADER)},
+ { ProcessCompare, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessCompare, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessCompare, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessCompare, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessCompare, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessCompare, destMC, sizeof(COMMAND_HEADER)},
+ { ProcessSwitch, 0, sizeof(COMMAND_HEADER)},
+ { ProcessJump, NoCondition, 0},
+ { ProcessJump, Equal, 0},
+ { ProcessJump, Below, 0},
+ { ProcessJump, Above, 0},
+ { ProcessJumpE, Below, 0},
+ { ProcessJumpE, Above, 0},
+ { ProcessJumpNE, 0, 0},
+ { ProcessTest, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessTest, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessTest, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessTest, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessTest, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessTest, destMC, sizeof(COMMAND_HEADER)},
+ { cmdDelay_Millisec,0, 0},
+ { cmdDelay_Microsec,0, 0},
+ { cmdCall_Table, 0, 0},
+ /*cmdRepeat*/ { NotImplemented, 0, 0},
+ { ProcessClear, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessClear, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessClear, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessClear, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessClear, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessClear, destMC, sizeof(COMMAND_HEADER)},
+ { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)},
+ /*cmdEOT*/ { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)},
+ { ProcessMask, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessMask, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessMask, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessMask, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessMask, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessMask, destMC, sizeof(COMMAND_HEADER)},
+ /*cmdPost_Card*/ { ProcessPostChar, 0, 0},
+ /*cmdBeep*/ { NotImplemented, 0, 0},
+ /*cmdSave_Reg*/ { NotImplemented, 0, 0},
+ /*cmdRestore_Reg*/{ NotImplemented, 0, 0},
+ { cmdSetDataBlock, 0, 0},
+ { ProcessXor, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessXor, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessXor, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessXor, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessXor, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessXor, destMC, sizeof(COMMAND_HEADER)},
+
+ { ProcessShl, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessShl, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessShl, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessShl, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessShl, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessShl, destMC, sizeof(COMMAND_HEADER)},
+
+ { ProcessShr, destRegister, sizeof(COMMAND_HEADER)},
+ { ProcessShr, destParamSpace, sizeof(COMMAND_HEADER)},
+ { ProcessShr, destWorkSpace, sizeof(COMMAND_HEADER)},
+ { ProcessShr, destFrameBuffer, sizeof(COMMAND_HEADER)},
+ { ProcessShr, destPLL, sizeof(COMMAND_HEADER)},
+ { ProcessShr, destMC, sizeof(COMMAND_HEADER)},
+ /*cmdDebug*/ { ProcessDebug, 0, 0},
+ { ProcessDS, 0, 0},
+
+};
+
+// EOF
diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c
new file mode 100644
index 0000000..95908d5
--- /dev/null
+++ b/src/AtomBios/Decoder.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+
+Module Name:
+
+ Decoder.c
+
+Abstract:
+
+ Commands Decoder
+
+Revision History:
+
+ NEG:24.09.2002 Initiated.
+--*/
+//#include "AtomBios.h"
+#include "Decoder.h"
+#include "atombios.h"
+#include "CD_binding.h"
+#include "CD_Common_Types.h"
+
+#ifndef DISABLE_EASF
+ #include "easf.h"
+#endif
+
+
+
+#define INDIRECT_IO_TABLE (((UINT16)&((ATOM_MASTER_LIST_OF_DATA_TABLES*)0)->IndirectIOAccess)/sizeof(TABLE_UNIT_TYPE) )
+extern COMMANDS_PROPERTIES CallTable[];
+
+
+UINT8 ProcessCommandProperties(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ UINT8 opcode=((COMMAND_HEADER*)pParserTempData->pWorkingTableData->IP)->Opcode;
+ pParserTempData->pWorkingTableData->IP+=CallTable[opcode].headersize;
+ pParserTempData->ParametersType.Destination=CallTable[opcode].destination;
+ pParserTempData->ParametersType.Source = pParserTempData->pCmd->Header.Attribute.Source;
+ pParserTempData->CD_Mask.SrcAlignment=pParserTempData->pCmd->Header.Attribute.SourceAlignment;
+ pParserTempData->CD_Mask.DestAlignment=pParserTempData->pCmd->Header.Attribute.DestinationAlignment;
+ return opcode;
+}
+
+UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData)
+{
+ UINT16 *MasterTableOffset;
+#ifndef DISABLE_EASF
+ if (pDeviceData->format == TABLE_FORMAT_EASF)
+ {
+ /*
+ make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize.
+ */
+ MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset);
+ } else
+#endif
+ {
+#ifndef UEFI_BUILD
+ MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image);
+ MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset + pDeviceData->pBIOS_Image );
+ MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables);
+#else
+ MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables));
+#endif
+ }
+ return MasterTableOffset;
+}
+
+UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData)
+{
+ UINT16 *MasterTableOffset;
+
+#ifndef UEFI_BUILD
+ MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image);
+ MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset + pDeviceData->pBIOS_Image );
+ MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables);
+#else
+ MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables));
+#endif
+ return MasterTableOffset;
+}
+
+
+UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable)
+{
+#ifndef DISABLE_EASF
+ UINT16 i;
+ if ( pParserTempData->pDeviceData->format == TABLE_FORMAT_EASF)
+ {
+/*
+ Consider EASF_ASIC_SETUP_TABLE structure pointed by pParserTempData->pCmd as UINT16[]
+ ((UINT16*)pParserTempData->pCmd)[0] = EASF_ASIC_SETUP_TABLE.usSize;
+ ((UINT16*)pParserTempData->pCmd)[1+n*4] = usFunctionID;
+ usFunctionID has to be shifted left by 2 before compare it to the value provided by caller.
+*/
+ for (i=1; (i < ((UINT16*)pParserTempData->pCmd)[0] >> 1);i+=4)
+ if ((UINT8)(((UINT16*)pParserTempData->pCmd)[i] << 2)==(IndexInMasterTable & EASF_TABLE_INDEX_MASK)) return (i+1+(IndexInMasterTable & EASF_TABLE_ATTR_MASK));
+ return 1;
+ } else
+#endif
+ {
+ return IndexInMasterTable;
+ }
+}
+
+CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable)
+{
+ PARSER_TEMP_DATA ParserTempData;
+ WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData;
+
+ ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData;
+#ifndef DISABLE_EASF
+ if (pDeviceData->format == TABLE_FORMAT_EASF)
+ {
+ ParserTempData.IndirectIOTablePointer = 0;
+ } else
+#endif
+ {
+ ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData);
+ ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE]) + pDeviceData->pBIOS_Image);
+ ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER);
+ }
+
+ ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetCommandMasterTablePointer(pDeviceData);
+ IndexInMasterTable=GetTrueIndexInMasterTable((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData,IndexInMasterTable);
+ if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0 ) // if the offset is not ZERO
+ {
+ ParserTempData.CommandSpecific.IndexInMasterTable=IndexInMasterTable;
+ ParserTempData.Multipurpose.CurrentPort=ATI_RegsPort;
+ ParserTempData.CurrentPortID=INDIRECT_IO_MM;
+ ParserTempData.CurrentRegBlock=0;
+ ParserTempData.CurrentFB_Window=0;
+ prevWorkingTableData=NULL;
+ ParserTempData.Status=CD_CALL_TABLE;
+
+ do{
+
+ if (ParserTempData.Status==CD_CALL_TABLE)
+ {
+ IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable;
+ if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO
+ {
+#ifndef UEFI_BUILD
+ ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData,
+ ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
+#else
+ ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData,
+ ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
+#endif
+ if (ParserTempData.pWorkingTableData!=NULL)
+ {
+ ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA));
+#ifndef UEFI_BUILD
+ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image);
+#else
+ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]);
+#endif
+ ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER);
+ ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData;
+ prevWorkingTableData=ParserTempData.pWorkingTableData;
+ ParserTempData.Status = CD_SUCCESS;
+ } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR;
+ } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND;
+ }
+ if (!CD_ERROR(ParserTempData.Status))
+ {
+ ParserTempData.Status = CD_SUCCESS;
+ while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status))
+ {
+
+ if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
+ {
+ ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP;
+
+ if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
+ {
+ ParserTempData.Status=CD_COMPLETED;
+ prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData;
+
+ FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData);
+ ParserTempData.pWorkingTableData=prevWorkingTableData;
+ if (prevWorkingTableData!=NULL)
+ {
+ ParserTempData.pDeviceData->pParameterSpace-=
+ (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)ParserTempData.pWorkingTableData->
+ pTableHead)->TableAttribute.PS_SizeInBytes>>2);
+ }
+ // if there is a parent table where to return, then restore PS_pointer to the original state
+ }
+ else
+ {
+ IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData);
+ (*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData);
+#if (PARSER_TYPE!=DRIVER_TYPE_PARSER)
+ BIOS_STACK_MODIFIER();
+#endif
+ }
+ }
+ else
+ {
+ ParserTempData.Status=CD_INVALID_OPCODE;
+ break;
+ }
+
+ } // while
+ } // if
+ else
+ break;
+ } while (prevWorkingTableData!=NULL);
+ if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS;
+ return ParserTempData.Status;
+ } else return CD_SUCCESS;
+}
+
+// EOF
+
diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c
new file mode 100644
index 0000000..a5f5a5b
--- /dev/null
+++ b/src/AtomBios/hwserv_drv.c
@@ -0,0 +1,348 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+
+Module Name:
+
+ hwserv_drv.c
+
+Abstract:
+
+ Functions defined in the Command Decoder Specification document
+
+Revision History:
+
+ NEG:27.09.2002 Initiated.
+--*/
+#include "CD_binding.h"
+#include "CD_hw_services.h"
+
+//trace settings
+#if DEBUG_OUTPUT_DEVICE & 1
+ #define TRACE_USING_STDERR //define it to use stderr as trace output,
+#endif
+#if DEBUG_OUTPUT_DEVICE & 2
+ #define TRACE_USING_RS232
+#endif
+#if DEBUG_OUTPUT_DEVICE & 4
+ #define TRACE_USING_LPT
+#endif
+
+
+#if DEBUG_PARSER == 4
+ #define IO_TRACE //IO access trace switch, undefine it to turn off
+ #define PCI_TRACE //PCI access trace switch, undefine it to turn off
+ #define MEM_TRACE //MEM access trace switch, undefine it to turn off
+#endif
+
+UINT32 CailReadATIRegister(VOID*,UINT32);
+VOID CailWriteATIRegister(VOID*,UINT32,UINT32);
+VOID* CailAllocateMemory(VOID*,UINT16);
+VOID CailReleaseMemory(VOID *,VOID *);
+VOID CailDelayMicroSeconds(VOID *,UINT32 );
+VOID CailReadPCIConfigData(VOID*,VOID*,UINT32,UINT16);
+VOID CailWritePCIConfigData(VOID*,VOID*,UINT32,UINT16);
+UINT32 CailReadFBData(VOID*,UINT32);
+VOID CailWriteFBData(VOID*,UINT32,UINT32);
+ULONG CailReadPLL(VOID *Context ,ULONG Address);
+VOID CailWritePLL(VOID *Context,ULONG Address,ULONG Data);
+ULONG CailReadMC(VOID *Context ,ULONG Address);
+VOID CailWriteMC(VOID *Context ,ULONG Address,ULONG Data);
+
+
+#if DEBUG_PARSER>0
+VOID CailVideoDebugPrint(VOID*,ULONG_PTR, UINT16);
+#endif
+// Delay function
+#if ( defined ENABLE_PARSER_DELAY || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+
+VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32*1000);
+}
+
+VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32);
+}
+#endif
+
+VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+}
+
+VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+}
+
+
+// PCI READ Access
+
+#if ( defined ENABLE_PARSER_PCIREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ UINT8 rvl;
+ CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT8));
+ return rvl;
+}
+#endif
+
+
+#if ( defined ENABLE_PARSER_PCIREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+
+ UINT16 rvl;
+ CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT16));
+ return rvl;
+
+}
+#endif
+
+
+
+#if ( defined ENABLE_PARSER_PCIREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+UINT32 ReadPCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+
+ UINT32 rvl;
+ CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT32));
+ return rvl;
+}
+#endif
+
+
+// PCI WRITE Access
+
+#if ( defined ENABLE_PARSER_PCIWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+VOID WritePCIReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+
+ CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT8));
+
+}
+
+#endif
+
+
+#if ( defined ENABLE_PARSER_PCIWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+VOID WritePCIReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+
+ CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT16));
+}
+
+#endif
+
+
+#if ( defined ENABLE_PARSER_PCIWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+VOID WritePCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT32));
+}
+#endif
+
+
+
+
+// System IO Access
+#if ( defined ENABLE_PARSER_SYS_IOREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+UINT8 ReadSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ UINT8 rvl;
+ rvl=0;
+ //rvl= (UINT8) ReadGenericPciCfg(dev,reg,sizeof(UINT8));
+ return rvl;
+}
+#endif
+
+
+#if ( defined ENABLE_PARSER_SYS_IOREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+
+ UINT16 rvl;
+ rvl=0;
+ //rvl= (UINT16) ReadGenericPciCfg(dev,reg,sizeof(UINT16));
+ return rvl;
+
+}
+#endif
+
+
+
+#if ( defined ENABLE_PARSER_SYS_IOREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+UINT32 ReadSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+
+ UINT32 rvl;
+ rvl=0;
+ //rvl= (UINT32) ReadGenericPciCfg(dev,reg,sizeof(UINT32));
+ return rvl;
+}
+#endif
+
+
+// PCI WRITE Access
+
+#if ( defined ENABLE_PARSER_SYS_IOWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+VOID WriteSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+
+ //WriteGenericPciCfg(dev,reg,sizeof(UINT8),(UINT32)value);
+}
+
+#endif
+
+
+#if ( defined ENABLE_PARSER_SYS_IOWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+VOID WriteSysIOReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+
+ //WriteGenericPciCfg(dev,reg,sizeof(UINT16),(UINT32)value);
+}
+
+#endif
+
+
+#if ( defined ENABLE_PARSER_SYS_IOWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+VOID WriteSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ //WriteGenericPciCfg(dev,reg,sizeof(UINT32),(UINT32)value);
+}
+#endif
+
+// ATI Registers Memory Mapped Access
+
+#if ( defined ENABLE_PARSER_REGISTERS_MEMORY_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS)
+
+UINT32 ReadReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
+}
+
+VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,(UINT16)pWorkingTableData->Index,pWorkingTableData->DestData32 );
+}
+
+
+VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1));
+}
+
+VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1),pWorkingTableData->IndirectData );
+}
+
+#endif
+
+// ATI Registers IO Mapped Access
+
+#if ( defined ENABLE_PARSER_REGISTERS_IO_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS )
+UINT32 ReadRegIO (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ //return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
+ return 0;
+}
+VOID WriteRegIO(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ // return CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32 );
+}
+#endif
+
+// access to Frame buffer, dummy function, need more information to implement it
+UINT32 ReadFrameBuffer32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+
+ return CailReadFBData(pWorkingTableData->pDeviceData->CAIL, (pWorkingTableData->Index <<2 ));
+
+}
+
+VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ CailWriteFBData(pWorkingTableData->pDeviceData->CAIL,(pWorkingTableData->Index <<2), pWorkingTableData->DestData32);
+
+}
+
+
+VOID *AllocateMemory(DEVICE_DATA *pDeviceData , UINT16 MemSize)
+{
+ if(MemSize)
+ return(CailAllocateMemory(pDeviceData->CAIL,MemSize));
+ else
+ return NULL;
+}
+
+
+VOID ReleaseMemory(DEVICE_DATA *pDeviceData , WORKING_TABLE_DATA* pWorkingTableData)
+{
+ if( pWorkingTableData)
+ CailReleaseMemory(pDeviceData->CAIL, pWorkingTableData);
+}
+
+
+UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ UINT32 ReadData;
+ ReadData=(UINT32)CailReadMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
+ return ReadData;
+}
+
+VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ CailWriteMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32);
+}
+
+UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ UINT32 ReadData;
+ ReadData=(UINT32)CailReadPLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
+ return ReadData;
+
+}
+
+VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
+{
+ CailWritePLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32);
+
+}
+
+
+
+#if DEBUG_PARSER>0
+VOID CD_print_string (DEVICE_DATA *pDeviceData, UINT8 *str)
+{
+ CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR) str, PARSER_STRINGS);
+}
+
+VOID CD_print_value (DEVICE_DATA *pDeviceData, ULONG_PTR value, UINT16 value_type )
+{
+ CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR)value, value_type);
+}
+
+#endif
+
+// EOF
diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h
new file mode 100644
index 0000000..7a0f27f
--- /dev/null
+++ b/src/AtomBios/includes/CD_Common_Types.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*++
+
+Module Name:
+
+ CD_Common_Types.h
+
+Abstract:
+
+ Defines common data types to use across platforms/SW components
+
+Revision History:
+
+ NEG:17.09.2002 Initiated.
+--*/
+#ifndef _COMMON_TYPES_H_
+ #define _COMMON_TYPES_H_
+
+ #ifndef LINUX
+ #if _MSC_EXTENSIONS
+
+ //
+ // use Microsoft* C complier dependent interger width types
+ //
+ // typedef unsigned __int64 uint64_t;
+ // typedef __int64 int64_t;
+ typedef unsigned __int32 uint32_t;
+ typedef __int32 int32_t;
+#elif defined (linux) || defined (__NetBSD__)
+ typedef unsigned int uint32_t;
+ typedef int int32_t;
+ #else
+ typedef unsigned long uint32_t;
+ typedef signed long int32_t;
+ #endif
+ typedef unsigned char uint8_t;
+ typedef signed char int8_t;
+ typedef unsigned short uint16_t;
+ typedef signed short int16_t;
+ #endif
+#ifndef UEFI_BUILD
+ typedef signed int intn_t;
+ typedef unsigned int uintn_t;
+#else
+#ifndef EFIX64
+ typedef signed int intn_t;
+ typedef unsigned int uintn_t;
+#endif
+#endif
+#ifndef FGL_LINUX
+#pragma warning ( disable : 4142 )
+#endif
+
+
+#ifndef VOID
+typedef void VOID;
+#endif
+#ifndef UEFI_BUILD
+ typedef intn_t INTN;
+ typedef uintn_t UINTN;
+#else
+#ifndef EFIX64
+ typedef intn_t INTN;
+ typedef uintn_t UINTN;
+#endif
+#endif
+#ifndef BOOLEAN
+typedef uint8_t BOOLEAN;
+#endif
+#ifndef INT8
+typedef int8_t INT8;
+#endif
+#ifndef UINT8
+typedef uint8_t UINT8;
+#endif
+#ifndef INT16
+typedef int16_t INT16;
+#endif
+#ifndef UINT16
+typedef uint16_t UINT16;
+#endif
+#ifndef INT32
+typedef int32_t INT32;
+#endif
+#ifndef UINT32
+typedef uint32_t UINT32;
+#endif
+//typedef int64_t INT64;
+//typedef uint64_t UINT64;
+typedef uint8_t CHAR8;
+typedef uint16_t CHAR16;
+#ifndef USHORT
+typedef UINT16 USHORT;
+#endif
+#ifndef UCHAR
+typedef UINT8 UCHAR;
+#endif
+#ifndef ULONG
+typedef UINT32 ULONG;
+#endif
+
+#ifndef _WIN64
+#ifndef ULONG_PTR
+typedef unsigned long ULONG_PTR;
+#endif // ULONG_PTR
+#endif // _WIN64
+
+//#define FAR __far
+#ifndef TRUE
+ #define TRUE ((BOOLEAN) 1 == 1)
+#endif
+
+#ifndef FALSE
+ #define FALSE ((BOOLEAN) 0 == 1)
+#endif
+
+#ifndef NULL
+ #define NULL ((VOID *) 0)
+#endif
+
+//typedef UINTN CD_STATUS;
+
+
+#ifndef FGL_LINUX
+#pragma warning ( default : 4142 )
+#endif
+#endif // _COMMON_TYPES_H_
+
+// EOF
diff --git a/src/AtomBios/includes/CD_Definitions.h b/src/AtomBios/includes/CD_Definitions.h
new file mode 100644
index 0000000..98fd495
--- /dev/null
+++ b/src/AtomBios/includes/CD_Definitions.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*++
+
+Module Name:
+
+CD_Definitions.h
+
+Abstract:
+
+Defines Script Language commands
+
+Revision History:
+
+NEG:27.08.2002 Initiated.
+--*/
+
+#include "CD_Structs.h"
+#ifndef _CD_DEFINITIONS_H
+#define _CD_DEFINITIONS_H_
+#ifdef DRIVER_PARSER
+VOID *AllocateMemory(VOID *, UINT16);
+VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* );
+#endif
+CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable);
+//CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData);
+CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable);
+UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData);
+#endif //CD_DEFINITIONS
diff --git a/src/AtomBios/includes/CD_Opcodes.h b/src/AtomBios/includes/CD_Opcodes.h
new file mode 100644
index 0000000..2f3bec5
--- /dev/null
+++ b/src/AtomBios/includes/CD_Opcodes.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*++
+
+Module Name:
+
+CD_OPCODEs.h
+
+Abstract:
+
+Defines Command Decoder OPCODEs
+
+Revision History:
+
+NEG:24.09.2002 Initiated.
+--*/
+#ifndef _CD_OPCODES_H_
+#define _CD_OPCODES_H_
+
+typedef enum _OPCODE {
+ Reserved_00= 0, // 0 = 0x00
+ // MOVE_ group
+ MOVE_REG_OPCODE, // 1 = 0x01
+ FirstValidCommand=MOVE_REG_OPCODE,
+ MOVE_PS_OPCODE, // 2 = 0x02
+ MOVE_WS_OPCODE, // 3 = 0x03
+ MOVE_FB_OPCODE, // 4 = 0x04
+ MOVE_PLL_OPCODE, // 5 = 0x05
+ MOVE_MC_OPCODE, // 6 = 0x06
+ // Logic group
+ AND_REG_OPCODE, // 7 = 0x07
+ AND_PS_OPCODE, // 8 = 0x08
+ AND_WS_OPCODE, // 9 = 0x09
+ AND_FB_OPCODE, // 10 = 0x0A
+ AND_PLL_OPCODE, // 11 = 0x0B
+ AND_MC_OPCODE, // 12 = 0x0C
+ OR_REG_OPCODE, // 13 = 0x0D
+ OR_PS_OPCODE, // 14 = 0x0E
+ OR_WS_OPCODE, // 15 = 0x0F
+ OR_FB_OPCODE, // 16 = 0x10
+ OR_PLL_OPCODE, // 17 = 0x11
+ OR_MC_OPCODE, // 18 = 0x12
+ SHIFT_LEFT_REG_OPCODE, // 19 = 0x13
+ SHIFT_LEFT_PS_OPCODE, // 20 = 0x14
+ SHIFT_LEFT_WS_OPCODE, // 21 = 0x15
+ SHIFT_LEFT_FB_OPCODE, // 22 = 0x16
+ SHIFT_LEFT_PLL_OPCODE, // 23 = 0x17
+ SHIFT_LEFT_MC_OPCODE, // 24 = 0x18
+ SHIFT_RIGHT_REG_OPCODE, // 25 = 0x19
+ SHIFT_RIGHT_PS_OPCODE, // 26 = 0x1A
+ SHIFT_RIGHT_WS_OPCODE, // 27 = 0x1B
+ SHIFT_RIGHT_FB_OPCODE, // 28 = 0x1C
+ SHIFT_RIGHT_PLL_OPCODE, // 29 = 0x1D
+ SHIFT_RIGHT_MC_OPCODE, // 30 = 0x1E
+ // Arithmetic group
+ MUL_REG_OPCODE, // 31 = 0x1F
+ MUL_PS_OPCODE, // 32 = 0x20
+ MUL_WS_OPCODE, // 33 = 0x21
+ MUL_FB_OPCODE, // 34 = 0x22
+ MUL_PLL_OPCODE, // 35 = 0x23
+ MUL_MC_OPCODE, // 36 = 0x24
+ DIV_REG_OPCODE, // 37 = 0x25
+ DIV_PS_OPCODE, // 38 = 0x26
+ DIV_WS_OPCODE, // 39 = 0x27
+ DIV_FB_OPCODE, // 40 = 0x28
+ DIV_PLL_OPCODE, // 41 = 0x29
+ DIV_MC_OPCODE, // 42 = 0x2A
+ ADD_REG_OPCODE, // 43 = 0x2B
+ ADD_PS_OPCODE, // 44 = 0x2C
+ ADD_WS_OPCODE, // 45 = 0x2D
+ ADD_FB_OPCODE, // 46 = 0x2E
+ ADD_PLL_OPCODE, // 47 = 0x2F
+ ADD_MC_OPCODE, // 48 = 0x30
+ SUB_REG_OPCODE, // 49 = 0x31
+ SUB_PS_OPCODE, // 50 = 0x32
+ SUB_WS_OPCODE, // 51 = 0x33
+ SUB_FB_OPCODE, // 52 = 0x34
+ SUB_PLL_OPCODE, // 53 = 0x35
+ SUB_MC_OPCODE, // 54 = 0x36
+ // Control grouop
+ SET_ATI_PORT_OPCODE, // 55 = 0x37
+ SET_PCI_PORT_OPCODE, // 56 = 0x38
+ SET_SYS_IO_PORT_OPCODE, // 57 = 0x39
+ SET_REG_BLOCK_OPCODE, // 58 = 0x3A
+ SET_FB_BASE_OPCODE, // 59 = 0x3B
+ COMPARE_REG_OPCODE, // 60 = 0x3C
+ COMPARE_PS_OPCODE, // 61 = 0x3D
+ COMPARE_WS_OPCODE, // 62 = 0x3E
+ COMPARE_FB_OPCODE, // 63 = 0x3F
+ COMPARE_PLL_OPCODE, // 64 = 0x40
+ COMPARE_MC_OPCODE, // 65 = 0x41
+ SWITCH_OPCODE, // 66 = 0x42
+ JUMP__OPCODE, // 67 = 0x43
+ JUMP_EQUAL_OPCODE, // 68 = 0x44
+ JUMP_BELOW_OPCODE, // 69 = 0x45
+ JUMP_ABOVE_OPCODE, // 70 = 0x46
+ JUMP_BELOW_OR_EQUAL_OPCODE, // 71 = 0x47
+ JUMP_ABOVE_OR_EQUAL_OPCODE, // 72 = 0x48
+ JUMP_NOT_EQUAL_OPCODE, // 73 = 0x49
+ TEST_REG_OPCODE, // 74 = 0x4A
+ TEST_PS_OPCODE, // 75 = 0x4B
+ TEST_WS_OPCODE, // 76 = 0x4C
+ TEST_FB_OPCODE, // 77 = 0x4D
+ TEST_PLL_OPCODE, // 78 = 0x4E
+ TEST_MC_OPCODE, // 79 = 0x4F
+ DELAY_MILLISEC_OPCODE, // 80 = 0x50
+ DELAY_MICROSEC_OPCODE, // 81 = 0x51
+ CALL_TABLE_OPCODE, // 82 = 0x52
+ REPEAT_OPCODE, // 83 = 0x53
+ // Miscellaneous group
+ CLEAR_REG_OPCODE, // 84 = 0x54
+ CLEAR_PS_OPCODE, // 85 = 0x55
+ CLEAR_WS_OPCODE, // 86 = 0x56
+ CLEAR_FB_OPCODE, // 87 = 0x57
+ CLEAR_PLL_OPCODE, // 88 = 0x58
+ CLEAR_MC_OPCODE, // 89 = 0x59
+ NOP_OPCODE, // 90 = 0x5A
+ EOT_OPCODE, // 91 = 0x5B
+ MASK_REG_OPCODE, // 92 = 0x5C
+ MASK_PS_OPCODE, // 93 = 0x5D
+ MASK_WS_OPCODE, // 94 = 0x5E
+ MASK_FB_OPCODE, // 95 = 0x5F
+ MASK_PLL_OPCODE, // 96 = 0x60
+ MASK_MC_OPCODE, // 97 = 0x61
+ // BIOS dedicated group
+ POST_CARD_OPCODE, // 98 = 0x62
+ BEEP_OPCODE, // 99 = 0x63
+ SAVE_REG_OPCODE, // 100 = 0x64
+ RESTORE_REG_OPCODE, // 101 = 0x65
+ SET_DATA_BLOCK_OPCODE, // 102 = 0x66
+
+ XOR_REG_OPCODE, // 103 = 0x67
+ XOR_PS_OPCODE, // 104 = 0x68
+ XOR_WS_OPCODE, // 105 = 0x69
+ XOR_FB_OPCODE, // 106 = 0x6a
+ XOR_PLL_OPCODE, // 107 = 0x6b
+ XOR_MC_OPCODE, // 108 = 0x6c
+
+ SHL_REG_OPCODE, // 109 = 0x6d
+ SHL_PS_OPCODE, // 110 = 0x6e
+ SHL_WS_OPCODE, // 111 = 0x6f
+ SHL_FB_OPCODE, // 112 = 0x70
+ SHL_PLL_OPCODE, // 113 = 0x71
+ SHL_MC_OPCODE, // 114 = 0x72
+
+ SHR_REG_OPCODE, // 115 = 0x73
+ SHR_PS_OPCODE, // 116 = 0x74
+ SHR_WS_OPCODE, // 117 = 0x75
+ SHR_FB_OPCODE, // 118 = 0x76
+ SHR_PLL_OPCODE, // 119 = 0x77
+ SHR_MC_OPCODE, // 120 = 0x78
+
+ DEBUG_OPCODE, // 121 = 0x79
+ CTB_DS_OPCODE, // 122 = 0x7A
+
+ LastValidCommand = CTB_DS_OPCODE,
+ // Extension specificaTOR
+ Extension = 0x80, // 128 = 0x80 // Next byte is an OPCODE as well
+ Reserved_FF = 255 // 255 = 0xFF
+}OPCODE;
+#endif // _CD_OPCODES_H_
diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h
new file mode 100644
index 0000000..c43f81d
--- /dev/null
+++ b/src/AtomBios/includes/CD_Structs.h
@@ -0,0 +1,464 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*++
+
+Module Name:
+
+CD_Struct.h
+
+Abstract:
+
+Defines Script Language commands
+
+Revision History:
+
+NEG:26.08.2002 Initiated.
+--*/
+
+#include "CD_binding.h"
+#ifndef _CD_STRUCTS_H_
+#define _CD_STRUCTS_H_
+
+#ifdef UEFI_BUILD
+typedef UINT16** PTABLE_UNIT_TYPE;
+typedef UINTN TABLE_UNIT_TYPE;
+#else
+typedef UINT16* PTABLE_UNIT_TYPE;
+typedef UINT16 TABLE_UNIT_TYPE;
+#endif
+
+#include <regsdef.h> //This important file is dynamically generated based on the ASIC!!!!
+
+#define PARSER_MAJOR_REVISION 5
+#define PARSER_MINOR_REVISION 0
+
+//#include "atombios.h"
+#if (PARSER_TYPE==DRIVER_TYPE_PARSER)
+#ifdef FGL_LINUX
+#pragma pack(push,1)
+#else
+#pragma pack(push)
+#pragma pack(1)
+#endif
+#endif
+
+#include "CD_Common_Types.h"
+#include "CD_Opcodes.h"
+typedef UINT16 WORK_SPACE_SIZE;
+typedef enum _CD_STATUS{
+ CD_SUCCESS,
+ CD_CALL_TABLE,
+ CD_COMPLETED=0x10,
+ CD_GENERAL_ERROR=0x80,
+ CD_INVALID_OPCODE,
+ CD_NOT_IMPLEMENTED,
+ CD_EXEC_TABLE_NOT_FOUND,
+ CD_EXEC_PARAMETER_ERROR,
+ CD_EXEC_PARSER_ERROR,
+ CD_INVALID_DESTINATION_TYPE,
+ CD_UNEXPECTED_BEHAVIOR,
+ CD_INVALID_SWITCH_OPERAND_SIZE
+}CD_STATUS;
+
+#define PARSER_STRINGS 0
+#define PARSER_DEC 1
+#define PARSER_HEX 2
+
+#define DB_CURRENT_COMMAND_TABLE 0xFF
+
+#define TABLE_FORMAT_BIOS 0
+#define TABLE_FORMAT_EASF 1
+
+#define EASF_TABLE_INDEX_MASK 0xfc
+#define EASF_TABLE_ATTR_MASK 0x03
+
+#define CD_ERROR(a) (((INTN) (a)) > CD_COMPLETED)
+#define CD_ERROR_OR_COMPLETED(a) (((INTN) (a)) > CD_SUCCESS)
+
+
+#if (BIOS_PARSER==1)
+#ifdef _H2INC
+#define STACK_BASED
+#else
+extern __segment farstack;
+#define STACK_BASED __based(farstack)
+#endif
+#else
+#define STACK_BASED
+#endif
+
+typedef enum _COMPARE_FLAGS{
+ Below,
+ Equal,
+ Above,
+ NotEqual,
+ Overflow,
+ NoCondition
+}COMPARE_FLAGS;
+
+typedef UINT16 IO_BASE_ADDR;
+
+typedef struct _BUS_DEV_FUNC_PCI_ADDR{
+ UINT8 Register;
+ UINT8 Function;
+ UINT8 Device;
+ UINT8 Bus;
+} BUS_DEV_FUNC_PCI_ADDR;
+
+typedef struct _BUS_DEV_FUNC{
+ UINT8 Function : 3;
+ UINT8 Device : 5;
+ UINT8 Bus;
+} BUS_DEV_FUNC;
+
+#ifndef UEFI_BUILD
+typedef struct _PCI_CONFIG_ACCESS_CF8{
+ UINT32 Reg : 8;
+ UINT32 Func : 3;
+ UINT32 Dev : 5;
+ UINT32 Bus : 8;
+ UINT32 Reserved: 7;
+ UINT32 Enable : 1;
+} PCI_CONFIG_ACCESS_CF8;
+#endif
+
+typedef enum _MEM_RESOURCE {
+ Stack_Resource,
+ FrameBuffer_Resource,
+ BIOS_Image_Resource
+}MEM_RESOURCE;
+
+typedef enum _PORTS{
+ ATI_RegsPort,
+ PCI_Port,
+ SystemIO_Port
+}PORTS;
+
+typedef enum _OPERAND_TYPE {
+ typeRegister,
+ typeParamSpace,
+ typeWorkSpace,
+ typeFrameBuffer,
+ typeIndirect,
+ typeDirect,
+ typePLL,
+ typeMC
+}OPERAND_TYPE;
+
+typedef enum _DESTINATION_OPERAND_TYPE {
+ destRegister,
+ destParamSpace,
+ destWorkSpace,
+ destFrameBuffer,
+ destPLL,
+ destMC
+}DESTINATION_OPERAND_TYPE;
+
+typedef enum _SOURCE_OPERAND_TYPE {
+ sourceRegister,
+ sourceParamSpace,
+ sourceWorkSpace,
+ sourceFrameBuffer,
+ sourceIndirect,
+ sourceDirect,
+ sourcePLL,
+ sourceMC
+}SOURCE_OPERAND_TYPE;
+
+typedef enum _ALIGNMENT_TYPE {
+ alignmentDword,
+ alignmentLowerWord,
+ alignmentMiddleWord,
+ alignmentUpperWord,
+ alignmentByte0,
+ alignmentByte1,
+ alignmentByte2,
+ alignmentByte3
+}ALIGNMENT_TYPE;
+
+
+#define INDIRECT_IO_READ 0
+#define INDIRECT_IO_WRITE 0x80
+#define INDIRECT_IO_MM 0
+#define INDIRECT_IO_PLL 1
+#define INDIRECT_IO_MC 2
+
+typedef struct _PARAMETERS_TYPE{
+ UINT8 Destination;
+ UINT8 Source;
+}PARAMETERS_TYPE;
+/* The following structures don't used to allocate any type of objects(variables).
+ they are serve the only purpose: Get proper access to data(commands), found in the tables*/
+typedef struct _PA_BYTE_BYTE{
+ UINT8 PA_Destination;
+ UINT8 PA_Source;
+ UINT8 PA_Padding[8];
+}PA_BYTE_BYTE;
+typedef struct _PA_BYTE_WORD{
+ UINT8 PA_Destination;
+ UINT16 PA_Source;
+ UINT8 PA_Padding[7];
+}PA_BYTE_WORD;
+typedef struct _PA_BYTE_DWORD{
+ UINT8 PA_Destination;
+ UINT32 PA_Source;
+ UINT8 PA_Padding[5];
+}PA_BYTE_DWORD;
+typedef struct _PA_WORD_BYTE{
+ UINT16 PA_Destination;
+ UINT8 PA_Source;
+ UINT8 PA_Padding[7];
+}PA_WORD_BYTE;
+typedef struct _PA_WORD_WORD{
+ UINT16 PA_Destination;
+ UINT16 PA_Source;
+ UINT8 PA_Padding[6];
+}PA_WORD_WORD;
+typedef struct _PA_WORD_DWORD{
+ UINT16 PA_Destination;
+ UINT32 PA_Source;
+ UINT8 PA_Padding[4];
+}PA_WORD_DWORD;
+typedef struct _PA_WORD_XX{
+ UINT16 PA_Destination;
+ UINT8 PA_Padding[8];
+}PA_WORD_XX;
+typedef struct _PA_BYTE_XX{
+ UINT8 PA_Destination;
+ UINT8 PA_Padding[9];
+}PA_BYTE_XX;
+/*The following 6 definitions used for Mask operation*/
+typedef struct _PA_BYTE_BYTE_BYTE{
+ UINT8 PA_Destination;
+ UINT8 PA_AndMaskByte;
+ UINT8 PA_OrMaskByte;
+ UINT8 PA_Padding[7];
+}PA_BYTE_BYTE_BYTE;
+typedef struct _PA_BYTE_WORD_WORD{
+ UINT8 PA_Destination;
+ UINT16 PA_AndMaskWord;
+ UINT16 PA_OrMaskWord;
+ UINT8 PA_Padding[5];
+}PA_BYTE_WORD_WORD;
+typedef struct _PA_BYTE_DWORD_DWORD{
+ UINT8 PA_Destination;
+ UINT32 PA_AndMaskDword;
+ UINT32 PA_OrMaskDword;
+ UINT8 PA_Padding;
+}PA_BYTE_DWORD_DWORD;
+typedef struct _PA_WORD_BYTE_BYTE{
+ UINT16 PA_Destination;
+ UINT8 PA_AndMaskByte;
+ UINT8 PA_OrMaskByte;
+ UINT8 PA_Padding[6];
+}PA_WORD_BYTE_BYTE;
+typedef struct _PA_WORD_WORD_WORD{
+ UINT16 PA_Destination;
+ UINT16 PA_AndMaskWord;
+ UINT16 PA_OrMaskWord;
+ UINT8 PA_Padding[4];
+}PA_WORD_WORD_WORD;
+typedef struct _PA_WORD_DWORD_DWORD{
+ UINT16 PA_Destination;
+ UINT32 PA_AndMaskDword;
+ UINT32 PA_OrMaskDword;
+}PA_WORD_DWORD_DWORD;
+
+
+typedef union _PARAMETER_ACCESS {
+ PA_BYTE_XX ByteXX;
+ PA_BYTE_BYTE ByteByte;
+ PA_BYTE_WORD ByteWord;
+ PA_BYTE_DWORD ByteDword;
+ PA_WORD_BYTE WordByte;
+ PA_WORD_WORD WordWord;
+ PA_WORD_DWORD WordDword;
+ PA_WORD_XX WordXX;
+/*The following 6 definitions used for Mask operation*/
+ PA_BYTE_BYTE_BYTE ByteByteAndByteOr;
+ PA_BYTE_WORD_WORD ByteWordAndWordOr;
+ PA_BYTE_DWORD_DWORD ByteDwordAndDwordOr;
+ PA_WORD_BYTE_BYTE WordByteAndByteOr;
+ PA_WORD_WORD_WORD WordWordAndWordOr;
+ PA_WORD_DWORD_DWORD WordDwordAndDwordOr;
+}PARAMETER_ACCESS;
+
+typedef struct _COMMAND_ATTRIBUTE {
+ UINT8 Source:3;
+ UINT8 SourceAlignment:3;
+ UINT8 DestinationAlignment:2;
+}COMMAND_ATTRIBUTE;
+
+typedef struct _SOURCE_DESTINATION_ALIGNMENT{
+ UINT8 DestAlignment;
+ UINT8 SrcAlignment;
+}SOURCE_DESTINATION_ALIGNMENT;
+typedef struct _MULTIPLICATION_RESULT{
+ UINT32 Low32Bit;
+ UINT32 High32Bit;
+}MULTIPLICATION_RESULT;
+typedef struct _DIVISION_RESULT{
+ UINT32 Quotient32;
+ UINT32 Reminder32;
+}DIVISION_RESULT;
+typedef union _DIVISION_MULTIPLICATION_RESULT{
+ MULTIPLICATION_RESULT Multiplication;
+ DIVISION_RESULT Division;
+}DIVISION_MULTIPLICATION_RESULT;
+typedef struct _COMMAND_HEADER {
+ UINT8 Opcode;
+ COMMAND_ATTRIBUTE Attribute;
+}COMMAND_HEADER;
+
+typedef struct _GENERIC_ATTRIBUTE_COMMAND{
+ COMMAND_HEADER Header;
+ PARAMETER_ACCESS Parameters;
+} GENERIC_ATTRIBUTE_COMMAND;
+
+typedef struct _COMMAND_TYPE_1{
+ UINT8 Opcode;
+ PARAMETER_ACCESS Parameters;
+} COMMAND_TYPE_1;
+
+typedef struct _COMMAND_TYPE_OPCODE_OFFSET16{
+ UINT8 Opcode;
+ UINT16 CD_Offset16;
+} COMMAND_TYPE_OPCODE_OFFSET16;
+
+typedef struct _COMMAND_TYPE_OPCODE_OFFSET32{
+ UINT8 Opcode;
+ UINT32 CD_Offset32;
+} COMMAND_TYPE_OPCODE_OFFSET32;
+
+typedef struct _COMMAND_TYPE_OPCODE_VALUE_BYTE{
+ UINT8 Opcode;
+ UINT8 Value;
+} COMMAND_TYPE_OPCODE_VALUE_BYTE;
+
+typedef union _COMMAND_SPECIFIC_UNION{
+ UINT8 ContinueSwitch;
+ UINT8 ControlOperandSourcePosition;
+ UINT8 IndexInMasterTable;
+} COMMAND_SPECIFIC_UNION;
+
+
+typedef struct _CD_GENERIC_BYTE{
+ UINT16 CommandType:3;
+ UINT16 CurrentParameterSize:3;
+ UINT16 CommandAccessType:3;
+ UINT16 CurrentPort:2;
+ UINT16 PS_SizeInDwordsUsedByCallingTable:5;
+}CD_GENERIC_BYTE;
+
+typedef UINT8 COMMAND_TYPE_OPCODE_ONLY;
+
+typedef UINT8 COMMAND_HEADER_POINTER;
+
+
+#if (PARSER_TYPE==BIOS_TYPE_PARSER)
+
+typedef struct _DEVICE_DATA {
+ UINT32 STACK_BASED *pParameterSpace;
+ UINT8 *pBIOS_Image;
+ UINT8 format;
+#if (IO_INTERFACE==PARSER_INTERFACE)
+ IO_BASE_ADDR IOBase;
+#endif
+} DEVICE_DATA;
+
+#else
+
+typedef struct _DEVICE_DATA {
+ UINT32 *pParameterSpace;
+ VOID *CAIL;
+ UINT8 *pBIOS_Image;
+ UINT32 format;
+} DEVICE_DATA;
+
+#endif
+
+struct _PARSER_TEMP_DATA;
+typedef UINT32 WORKSPACE_POINTER;
+
+struct _WORKING_TABLE_DATA{
+ UINT8 * pTableHead;
+ COMMAND_HEADER_POINTER * IP; // Commands pointer
+ WORKSPACE_POINTER STACK_BASED * pWorkSpace;
+ struct _WORKING_TABLE_DATA STACK_BASED * prevWorkingTableData;
+};
+
+
+
+typedef struct _PARSER_TEMP_DATA{
+ DEVICE_DATA STACK_BASED *pDeviceData;
+ struct _WORKING_TABLE_DATA STACK_BASED *pWorkingTableData;
+ UINT32 SourceData32;
+ UINT32 DestData32;
+ DIVISION_MULTIPLICATION_RESULT MultiplicationOrDivision;
+ UINT32 Index;
+ UINT32 CurrentFB_Window;
+ UINT32 IndirectData;
+ UINT16 CurrentRegBlock;
+ TABLE_UNIT_TYPE CurrentDataBlock;
+ UINT16 AttributesData;
+// UINT8 *IndirectIOTable;
+ UINT8 *IndirectIOTablePointer;
+ GENERIC_ATTRIBUTE_COMMAND *pCmd; //CurrentCommand;
+ SOURCE_DESTINATION_ALIGNMENT CD_Mask;
+ PARAMETERS_TYPE ParametersType;
+ CD_GENERIC_BYTE Multipurpose;
+ UINT8 CompareFlags;
+ COMMAND_SPECIFIC_UNION CommandSpecific;
+ CD_STATUS Status;
+ UINT8 Shift2MaskConverter;
+ UINT8 CurrentPortID;
+} PARSER_TEMP_DATA;
+
+
+typedef struct _WORKING_TABLE_DATA WORKING_TABLE_DATA;
+
+
+
+typedef VOID (*COMMANDS_DECODER)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+typedef VOID (*WRITE_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+typedef UINT32 (*READ_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+typedef UINT32 (*CD_GET_PARAMETERS)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+typedef struct _COMMANDS_PROPERTIES
+{
+ COMMANDS_DECODER function;
+ UINT8 destination;
+ UINT8 headersize;
+} COMMANDS_PROPERTIES;
+
+typedef struct _INDIRECT_IO_PARSER_COMMANDS
+{
+ COMMANDS_DECODER func;
+ UINT8 csize;
+} INDIRECT_IO_PARSER_COMMANDS;
+
+#if (PARSER_TYPE==DRIVER_TYPE_PARSER)
+#pragma pack(pop)
+#endif
+
+#endif
diff --git a/src/AtomBios/includes/CD_binding.h b/src/AtomBios/includes/CD_binding.h
new file mode 100644
index 0000000..7b021d3
--- /dev/null
+++ b/src/AtomBios/includes/CD_binding.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef NT_BUILD
+#ifdef LH_BUILD
+#include <ntddk.h>
+#else
+#include <miniport.h>
+#endif // LH_BUILD
+#endif // NT_BUILD
+
+
+#if ((defined DBG) || (defined DEBUG))
+#define DEBUG_PARSER 1 // enable parser debug output
+#endif
+
+#define USE_SWITCH_COMMAND 1
+#define DRIVER_TYPE_PARSER 0x48
+
+#define PARSER_TYPE DRIVER_TYPE_PARSER
+
+#define AllocateWorkSpace(x,y) AllocateMemory(pDeviceData,y)
+#define FreeWorkSpace(x,y) ReleaseMemory(x,y)
+
+#define RELATIVE_TO_BIOS_IMAGE( x ) ((ULONG_PTR)x + (ULONG_PTR)((DEVICE_DATA*)pParserTempData->pDeviceData->pBIOS_Image))
+#define RELATIVE_TO_TABLE( x ) (x + (UCHAR *)(pParserTempData->pWorkingTableData->pTableHead))
+
diff --git a/src/AtomBios/includes/CD_hw_services.h b/src/AtomBios/includes/CD_hw_services.h
new file mode 100644
index 0000000..529fde5
--- /dev/null
+++ b/src/AtomBios/includes/CD_hw_services.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _HW_SERVICES_INTERFACE_
+#define _HW_SERVICES_INTERFACE_
+
+#include "CD_Common_Types.h"
+#include "CD_Structs.h"
+
+
+// CD - from Command Decoder
+typedef UINT16 CD_REG_INDEX;
+typedef UINT8 CD_PCI_OFFSET;
+typedef UINT16 CD_FB_OFFSET;
+typedef UINT16 CD_SYS_IO_PORT;
+typedef UINT8 CD_MEM_TYPE;
+typedef UINT8 CD_MEM_SIZE;
+
+typedef VOID * CD_VIRT_ADDR;
+typedef UINT32 CD_PHYS_ADDR;
+typedef UINT32 CD_IO_ADDR;
+
+/***********************ATI Registers access routines**************************/
+
+ VOID ReadIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ UINT32 ReadReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+/************************PCI Registers access routines*************************/
+
+ UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ UINT32 ReadPCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WritePCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WritePCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WritePCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+/***************************Frame buffer access routines************************/
+
+ UINT32 ReadFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+/******************System IO Registers access routines********************/
+
+ UINT8 ReadSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ UINT32 ReadSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WriteSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WriteSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID WriteSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+/****************************Delay routines****************************************/
+
+ VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); // take WORKING_TABLE_DATA->SourceData32 as a delay value
+
+ VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+ VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+
+//************************Tracing/Debugging routines and macroses******************/
+#define KEYPRESSED -1
+
+#if (DEBUG_PARSER != 0)
+
+#ifdef DRIVER_PARSER
+
+VOID CD_print_string (DEVICE_DATA STACK_BASED *pDeviceData, UINT8 *str);
+VOID CD_print_value (DEVICE_DATA STACK_BASED *pDeviceData, ULONG_PTR value, UINT16 value_type );
+
+// Level 1 : can use WorkingTableData or pDeviceData
+#define CD_TRACE_DL1(string) CD_print_string(pDeviceData, string);
+#define CD_TRACETAB_DL1(string) CD_TRACE_DL1("\n");CD_TRACE_DL1(string)
+#define CD_TRACEDEC_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_DEC);
+#define CD_TRACEHEX_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_HEX);
+
+// Level 2:can use pWorkingTableData
+#define CD_TRACE_DL2(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string);
+#define CD_TRACETAB_DL2(string) CD_TRACE_DL2("\n");CD_TRACE_DL2(string)
+#define CD_TRACEDEC_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_DEC);
+#define CD_TRACEHEX_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_HEX);
+
+// Level 3:can use pWorkingTableData
+#define CD_TRACE_DL3(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string);
+#define CD_TRACETAB_DL3(string) CD_TRACE_DL3("\n");CD_TRACE_DL3(string)
+#define CD_TRACEDEC_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_DEC);
+#define CD_TRACEHEX_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_HEX);
+
+#define CD_TRACE(string)
+#define CD_WAIT(what)
+#define CD_BREAKPOINT()
+
+#else
+
+
+VOID CD_assert (UINT8 *file, INTN lineno); //output file/line to debug console
+VOID CD_postcode(UINT8 value); //output post code to debug console
+VOID CD_print (UINT8 *str); //output text to debug console
+VOID CD_print_dec(UINTN value); //output value in decimal format to debug console
+VOID CD_print_hex(UINT32 value, UINT8 len); //output value in hexadecimal format to debug console
+VOID CD_print_buf(UINT8 *p, UINTN len); //output dump of memory to debug console
+VOID CD_wait(INT32 what); //wait for KEYPRESSED=-1 or Delay value expires
+VOID CD_breakpoint(); //insert int3 opcode or 0xF1 (for American Arium)
+
+#define CD_ASSERT(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
+#define CD_POSTCODE(value) CD_postcode(value)
+#define CD_TRACE(string) CD_print(string)
+#define CD_TRACETAB(string) CD_print(string)
+#define CD_TRACEDEC(value) CD_print_dec( (UINTN)(value))
+#define CD_TRACEHEX(value) CD_print_hex( (UINT32)(value), sizeof(value) )
+#define CD_TRACEBUF(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
+#define CD_WAIT(what) CD_wait((INT32)what)
+#define CD_BREAKPOINT() CD_breakpoint()
+
+#if (DEBUG_PARSER == 4)
+#define CD_ASSERT_DL4(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
+#define CD_POSTCODE_DL4(value) CD_postcode(value)
+#define CD_TRACE_DL4(string) CD_print(string)
+#define CD_TRACETAB_DL4(string) CD_print("\n\t\t");CD_print(string)
+#define CD_TRACEDEC_DL4(value) CD_print_dec( (UINTN)(value))
+#define CD_TRACEHEX_DL4(value) CD_print_hex( (UINT32)(value), sizeof(value) )
+#define CD_TRACEBUF_DL4(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
+#define CD_WAIT_DL4(what) CD_wait((INT32)what)
+#define CD_BREAKPOINT_DL4() CD_breakpoint()
+#else
+#define CD_ASSERT_DL4(condition)
+#define CD_POSTCODE_DL4(value)
+#define CD_TRACE_DL4(string)
+#define CD_TRACETAB_DL4(string)
+#define CD_TRACEDEC_DL4(value)
+#define CD_TRACEHEX_DL4(value)
+#define CD_TRACEBUF_DL4(pointer, len)
+#define CD_WAIT_DL4(what)
+#define CD_BREAKPOINT_DL4()
+#endif
+
+#if (DEBUG_PARSER >= 3)
+#define CD_ASSERT_DL3(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
+#define CD_POSTCODE_DL3(value) CD_postcode(value)
+#define CD_TRACE_DL3(string) CD_print(string)
+#define CD_TRACETAB_DL3(string) CD_print("\n\t\t");CD_print(string)
+#define CD_TRACEDEC_DL3(value) CD_print_dec( (UINTN)(value))
+#define CD_TRACEHEX_DL3(value) CD_print_hex( (UINT32)(value), sizeof(value) )
+#define CD_TRACEBUF_DL3(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
+#define CD_WAIT_DL3(what) CD_wait((INT32)what)
+#define CD_BREAKPOINT_DL3() CD_breakpoint()
+#else
+#define CD_ASSERT_DL3(condition)
+#define CD_POSTCODE_DL3(value)
+#define CD_TRACE_DL3(string)
+#define CD_TRACETAB_DL3(string)
+#define CD_TRACEDEC_DL3(value)
+#define CD_TRACEHEX_DL3(value)
+#define CD_TRACEBUF_DL3(pointer, len)
+#define CD_WAIT_DL3(what)
+#define CD_BREAKPOINT_DL3()
+#endif
+
+
+#if (DEBUG_PARSER >= 2)
+#define CD_ASSERT_DL2(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
+#define CD_POSTCODE_DL2(value) CD_postcode(value)
+#define CD_TRACE_DL2(string) CD_print(string)
+#define CD_TRACETAB_DL2(string) CD_print("\n\t");CD_print(string)
+#define CD_TRACEDEC_DL2(value) CD_print_dec( (UINTN)(value))
+#define CD_TRACEHEX_DL2(value) CD_print_hex( (UINT32)(value), sizeof(value) )
+#define CD_TRACEBUF_DL2(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
+#define CD_WAIT_DL2(what) CD_wait((INT32)what)
+#define CD_BREAKPOINT_DL2() CD_breakpoint()
+#else
+#define CD_ASSERT_DL2(condition)
+#define CD_POSTCODE_DL2(value)
+#define CD_TRACE_DL2(string)
+#define CD_TRACETAB_DL2(string)
+#define CD_TRACEDEC_DL2(value)
+#define CD_TRACEHEX_DL2(value)
+#define CD_TRACEBUF_DL2(pointer, len)
+#define CD_WAIT_DL2(what)
+#define CD_BREAKPOINT_DL2()
+#endif
+
+
+#if (DEBUG_PARSER >= 1)
+#define CD_ASSERT_DL1(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
+#define CD_POSTCODE_DL1(value) CD_postcode(value)
+#define CD_TRACE_DL1(string) CD_print(string)
+#define CD_TRACETAB_DL1(string) CD_print("\n");CD_print(string)
+#define CD_TRACEDEC_DL1(value) CD_print_dec( (UINTN)(value))
+#define CD_TRACEHEX_DL1(value) CD_print_hex( (UINT32)(value), sizeof(value) )
+#define CD_TRACEBUF_DL1(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
+#define CD_WAIT_DL1(what) CD_wait((INT32)what)
+#define CD_BREAKPOINT_DL1() CD_breakpoint()
+#else
+#define CD_ASSERT_DL1(condition)
+#define CD_POSTCODE_DL1(value)
+#define CD_TRACE_DL1(string)
+#define CD_TRACETAB_DL1(string)
+#define CD_TRACEDEC_DL1(value)
+#define CD_TRACEHEX_DL1(value)
+#define CD_TRACEBUF_DL1(pointer, len)
+#define CD_WAIT_DL1(what)
+#define CD_BREAKPOINT_DL1()
+#endif
+
+#endif //#ifdef DRIVER_PARSER
+
+
+#else
+
+#define CD_ASSERT(condition)
+#define CD_POSTCODE(value)
+#define CD_TRACE(string)
+#define CD_TRACEDEC(value)
+#define CD_TRACEHEX(value)
+#define CD_TRACEBUF(pointer, len)
+#define CD_WAIT(what)
+#define CD_BREAKPOINT()
+
+#define CD_ASSERT_DL4(condition)
+#define CD_POSTCODE_DL4(value)
+#define CD_TRACE_DL4(string)
+#define CD_TRACETAB_DL4(string)
+#define CD_TRACEDEC_DL4(value)
+#define CD_TRACEHEX_DL4(value)
+#define CD_TRACEBUF_DL4(pointer, len)
+#define CD_WAIT_DL4(what)
+#define CD_BREAKPOINT_DL4()
+
+#define CD_ASSERT_DL3(condition)
+#define CD_POSTCODE_DL3(value)
+#define CD_TRACE_DL3(string)
+#define CD_TRACETAB_DL3(string)
+#define CD_TRACEDEC_DL3(value)
+#define CD_TRACEHEX_DL3(value)
+#define CD_TRACEBUF_DL3(pointer, len)
+#define CD_WAIT_DL3(what)
+#define CD_BREAKPOINT_DL3()
+
+#define CD_ASSERT_DL2(condition)
+#define CD_POSTCODE_DL2(value)
+#define CD_TRACE_DL2(string)
+#define CD_TRACETAB_DL2(string)
+#define CD_TRACEDEC_DL2(value)
+#define CD_TRACEHEX_DL2(value)
+#define CD_TRACEBUF_DL2(pointer, len)
+#define CD_WAIT_DL2(what)
+#define CD_BREAKPOINT_DL2()
+
+#define CD_ASSERT_DL1(condition)
+#define CD_POSTCODE_DL1(value)
+#define CD_TRACE_DL1(string)
+#define CD_TRACETAB_DL1(string)
+#define CD_TRACEDEC_DL1(value)
+#define CD_TRACEHEX_DL1(value)
+#define CD_TRACEBUF_DL1(pointer, len)
+#define CD_WAIT_DL1(what)
+#define CD_BREAKPOINT_DL1()
+
+
+#endif //#if (DEBUG_PARSER > 0)
+
+
+#ifdef CHECKSTACK
+VOID CD_fillstack(UINT16 size);
+UINT16 CD_checkstack(UINT16 size);
+#define CD_CHECKSTACK(stacksize) CD_checkstack(stacksize)
+#define CD_FILLSTACK(stacksize) CD_fillstack(stacksize)
+#else
+#define CD_CHECKSTACK(stacksize) 0
+#define CD_FILLSTACK(stacksize)
+#endif
+
+
+#endif
diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h
new file mode 100644
index 0000000..24c25fc
--- /dev/null
+++ b/src/AtomBios/includes/Decoder.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*++
+
+Module Name:
+
+Decoder.h
+
+Abstract:
+
+Includes all helper headers
+
+Revision History:
+
+NEG:27.08.2002 Initiated.
+--*/
+#ifndef _DECODER_H_
+#define _DECODER_H_
+#define WS_QUOTIENT_C 64
+#define WS_REMINDER_C (WS_QUOTIENT_C+1)
+#define WS_DATAPTR_C (WS_REMINDER_C+1)
+#define WS_SHIFT_C (WS_DATAPTR_C+1)
+#define WS_OR_MASK_C (WS_SHIFT_C+1)
+#define WS_AND_MASK_C (WS_OR_MASK_C+1)
+#define WS_FB_WINDOW_C (WS_AND_MASK_C+1)
+#define WS_ATTRIBUTES_C (WS_FB_WINDOW_C+1)
+#define PARSER_VERSION_MAJOR 0x00000000
+#define PARSER_VERSION_MINOR 0x0000000E
+#define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR)
+#include "CD_binding.h"
+#include "CD_Common_Types.h"
+#include "CD_hw_services.h"
+#include "CD_Structs.h"
+#include "CD_Definitions.h"
+#include "CD_Opcodes.h"
+
+#define SOURCE_ONLY_CMD_TYPE 0//0xFE
+#define SOURCE_DESTINATION_CMD_TYPE 1//0xFD
+#define DESTINATION_ONLY_CMD_TYPE 2//0xFC
+
+#define ACCESS_TYPE_BYTE 0//0xF9
+#define ACCESS_TYPE_WORD 1//0xF8
+#define ACCESS_TYPE_DWORD 2//0xF7
+#define SWITCH_TYPE_ACCESS 3//0xF6
+
+#define CD_CONTINUE 0//0xFB
+#define CD_STOP 1//0xFA
+
+
+#define IS_END_OF_TABLE(cmd) ((cmd) == EOT_OPCODE)
+#define IS_COMMAND_VALID(cmd) (((cmd)<=LastValidCommand)&&((cmd)>=FirstValidCommand))
+#define IS_IT_SHIFT_COMMAND(Opcode) ((Opcode<=SHIFT_RIGHT_MC_OPCODE)&&(Opcode>=SHIFT_LEFT_REG_OPCODE))
+#define IS_IT_XXXX_COMMAND(Group, Opcode) ((Opcode<=Group##_MC_OPCODE)&&(Opcode>=Group##_REG_OPCODE))
+#define CheckCaseAndAdjustIP_Macro(size) \
+ if (pParserTempData->SourceData32==(UINT32)((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.Value){\
+ pParserTempData->CommandSpecific.ContinueSwitch = CD_STOP;\
+ pParserTempData->pWorkingTableData->IP =(COMMAND_HEADER_POINTER *) RELATIVE_TO_TABLE(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.JumpOffset);\
+ }else{\
+ pParserTempData->pWorkingTableData->IP+=(sizeof (CASE_##size##ACCESS)\
+ +sizeof(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->CaseSignature));\
+ }
+
+#endif
+/* pWorkingTableData->pCmd->Header.Attribute.SourceAlignment=alignmentLowerWord;\*/
+
+// EOF
diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h
new file mode 100644
index 0000000..3eb5f77
--- /dev/null
+++ b/src/AtomBios/includes/atombios.h
@@ -0,0 +1,4306 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+
+/****************************************************************************/
+/*Portion I: Definitions shared between VBIOS and Driver */
+/****************************************************************************/
+
+
+#ifndef _ATOMBIOS_H
+#define _ATOMBIOS_H
+
+#define ATOM_VERSION_MAJOR 0x00020000
+#define ATOM_VERSION_MINOR 0x00000002
+
+#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
+
+
+#ifdef _H2INC
+ #ifndef ULONG
+ typedef unsigned long ULONG;
+ #endif
+
+ #ifndef UCHAR
+ typedef unsigned char UCHAR;
+ #endif
+
+ #ifndef USHORT
+ typedef unsigned short USHORT;
+ #endif
+#endif
+
+#define ATOM_DAC_A 0
+#define ATOM_DAC_B 1
+#define ATOM_EXT_DAC 2
+
+#define ATOM_CRTC1 0
+#define ATOM_CRTC2 1
+
+#define ATOM_DIGA 0
+#define ATOM_DIGB 1
+
+#define ATOM_PPLL1 0
+#define ATOM_PPLL2 1
+
+#define ATOM_SCALER1 0
+#define ATOM_SCALER2 1
+
+#define ATOM_SCALER_DISABLE 0
+#define ATOM_SCALER_CENTER 1
+#define ATOM_SCALER_EXPANSION 2
+#define ATOM_SCALER_MULTI_EX 3
+
+#define ATOM_DISABLE 0
+#define ATOM_ENABLE 1
+#define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
+#define ATOM_LCD_BLON (ATOM_ENABLE+2)
+#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
+#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
+#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
+#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
+
+#define ATOM_BLANKING 1
+#define ATOM_BLANKING_OFF 0
+
+#define ATOM_CURSOR1 0
+#define ATOM_CURSOR2 1
+
+#define ATOM_ICON1 0
+#define ATOM_ICON2 1
+
+#define ATOM_CRT1 0
+#define ATOM_CRT2 1
+
+#define ATOM_TV_NTSC 1
+#define ATOM_TV_NTSCJ 2
+#define ATOM_TV_PAL 3
+#define ATOM_TV_PALM 4
+#define ATOM_TV_PALCN 5
+#define ATOM_TV_PALN 6
+#define ATOM_TV_PAL60 7
+#define ATOM_TV_SECAM 8
+#define ATOM_TV_CV 16
+
+#define ATOM_DAC1_PS2 1
+#define ATOM_DAC1_CV 2
+#define ATOM_DAC1_NTSC 3
+#define ATOM_DAC1_PAL 4
+
+#define ATOM_DAC2_PS2 ATOM_DAC1_PS2
+#define ATOM_DAC2_CV ATOM_DAC1_CV
+#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
+#define ATOM_DAC2_PAL ATOM_DAC1_PAL
+
+#define ATOM_PM_ON 0
+#define ATOM_PM_STANDBY 1
+#define ATOM_PM_SUSPEND 2
+#define ATOM_PM_OFF 3
+
+/* Bit0:{=0:single, =1:dual},
+ Bit1 {=0:666RGB, =1:888RGB},
+ Bit2:3:{Grey level}
+ Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
+
+#define ATOM_PANEL_MISC_DUAL 0x00000001
+#define ATOM_PANEL_MISC_888RGB 0x00000002
+#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
+#define ATOM_PANEL_MISC_FPDI 0x00000010
+#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
+#define ATOM_PANEL_MISC_SPATIAL 0x00000020
+#define ATOM_PANEL_MISC_TEMPORAL 0x00000040
+#define ATOM_PANEL_MISC_API_ENABLED 0x00000080
+
+
+#define MEMTYPE_DDR1 "DDR1"
+#define MEMTYPE_DDR2 "DDR2"
+#define MEMTYPE_DDR3 "DDR3"
+#define MEMTYPE_DDR4 "DDR4"
+
+#define ASIC_BUS_TYPE_PCI "PCI"
+#define ASIC_BUS_TYPE_AGP "AGP"
+#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
+
+/* Maximum size of that FireGL flag string */
+
+#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
+#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
+
+#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
+#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
+
+#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
+#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
+
+#define HW_ASSISTED_I2C_STATUS_FAILURE 2
+#define HW_ASSISTED_I2C_STATUS_SUCCESS 1
+
+#pragma pack(1) /* BIOS data must use byte aligment */
+
+/* Define offset to location of ROM header. */
+
+#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
+#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
+
+#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
+#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */
+#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
+#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
+
+/* Common header for all ROM Data tables.
+ Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
+ And the pointer actually points to this header. */
+
+typedef struct _ATOM_COMMON_TABLE_HEADER
+{
+ USHORT usStructureSize;
+ UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */
+ UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */
+ /*Image can't be updated, while Driver needs to carry the new table! */
+}ATOM_COMMON_TABLE_HEADER;
+
+typedef struct _ATOM_ROM_HEADER
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
+ atombios should init it as "ATOM", don't change the position */
+ USHORT usBiosRuntimeSegmentAddress;
+ USHORT usProtectedModeInfoOffset;
+ USHORT usConfigFilenameOffset;
+ USHORT usCRC_BlockOffset;
+ USHORT usBIOS_BootupMessageOffset;
+ USHORT usInt10Offset;
+ USHORT usPciBusDevInitCode;
+ USHORT usIoBaseAddress;
+ USHORT usSubsystemVendorID;
+ USHORT usSubsystemID;
+ USHORT usPCI_InfoOffset;
+ USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
+ USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
+ UCHAR ucExtendedFunctionCode;
+ UCHAR ucReserved;
+}ATOM_ROM_HEADER;
+
+/*==============================Command Table Portion==================================== */
+
+#ifdef UEFI_BUILD
+ #define UTEMP USHORT
+ #define USHORT void*
+#endif
+
+typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
+ USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
+ USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
+ USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
+ USHORT VRAM_BlockVenderDetection;
+ USHORT SetClocksRatio;
+ USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
+ USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
+ USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
+ USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
+ USHORT GPIOPinControl; //Atomic Table, only used by Bios
+ USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
+ USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
+ USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
+ USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
+ USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
+ USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
+ USHORT MemoryPLLInit;
+ USHORT AdjustDisplayPll; //only used by Bios
+ USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
+ USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
+ USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios
+ USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
+ USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
+ USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT CV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT GetConditionalGoldenSetting; //only used by Bios
+ USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
+ USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3
+ USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3
+ USHORT TV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT EnableScaler; //Atomic Table, used only by Bios
+ USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
+ USHORT EnableVGA_Access; //Obsolete , only used by Bios
+ USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
+ USHORT SetCRTC_Replication; //Atomic Table, used only by Bios
+ USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
+ USHORT UpdateCRTC_DoubleBufferRegisters;
+ USHORT LUT_AutoFill; //Atomic Table, only used by Bios
+ USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios
+ USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
+ USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT VRAM_BlockDetectionByStrap;
+ USHORT MemoryCleanUp; //Atomic Table, only used by Bios
+ USHORT ReadEDIDFromHWAssistedI2C; //Function Table,only used by Bios
+ USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
+ USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
+ USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
+ USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
+ USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
+ USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
+ USHORT VRAM_GetCurrentInfoBlock;
+ USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
+ USHORT MemoryTraining;
+ USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
+ USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
+ USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
+ USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
+ USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
+ USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
+ USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
+ USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
+ USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
+ USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
+ USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
+ USHORT DPEncoderService; //Function Table,only used by Bios
+}ATOM_MASTER_LIST_OF_COMMAND_TABLES;
+
+#define UNIPHYTransmitterControl DIG1TransmitterControl
+#define LVTMATransmitterControl DIG2TransmitterControl
+#define SetCRTC_DPM_State GetConditionalGoldenSetting
+
+typedef struct _ATOM_MASTER_COMMAND_TABLE
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
+}ATOM_MASTER_COMMAND_TABLE;
+
+typedef struct _ATOM_TABLE_ATTRIBUTE
+{
+ USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
+ USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
+ USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
+}ATOM_TABLE_ATTRIBUTE;
+
+// Common header for all command tables.
+//Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
+//And the pointer actually points to this header.
+
+typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
+{
+ ATOM_COMMON_TABLE_HEADER CommonHeader;
+ ATOM_TABLE_ATTRIBUTE TableAttribute;
+}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
+
+
+typedef struct _ASIC_INIT_PARAMETERS
+{
+ ULONG ulDefaultEngineClock; //In 10Khz unit
+ ULONG ulDefaultMemoryClock; //In 10Khz unit
+}ASIC_INIT_PARAMETERS;
+
+#define COMPUTE_MEMORY_PLL_PARAM 1
+#define COMPUTE_ENGINE_PLL_PARAM 2
+
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
+{
+ ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
+ UCHAR ucAction; //0:reserved //1:Memory //2:Engine
+ UCHAR ucReserved; //may expand to return larger Fbdiv later
+ UCHAR ucFbDiv; //return value
+ UCHAR ucPostDiv; //return value
+}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
+
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
+{
+ ULONG ulClock; //When return, [23:0] return real clock
+ UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
+ USHORT usFbDiv; //return Feedback value to be written to register
+ UCHAR ucPostDiv; //return post div to be written to register
+}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
+#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
+
+
+#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
+#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
+#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
+#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
+#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
+#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
+#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
+
+#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
+#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
+#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
+#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
+#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
+
+typedef struct _SET_ENGINE_CLOCK_PARAMETERS
+{
+ ULONG ulTargetEngineClock; //In 10Khz unit
+}SET_ENGINE_CLOCK_PARAMETERS;
+
+typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
+{
+ ULONG ulTargetEngineClock; //In 10Khz unit
+ COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
+}SET_ENGINE_CLOCK_PS_ALLOCATION;
+
+
+typedef struct _SET_MEMORY_CLOCK_PARAMETERS
+{
+ ULONG ulTargetMemoryClock; //In 10Khz unit
+}SET_MEMORY_CLOCK_PARAMETERS;
+
+typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
+{
+ ULONG ulTargetMemoryClock; //In 10Khz unit
+ COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
+}SET_MEMORY_CLOCK_PS_ALLOCATION;
+
+typedef struct _ASIC_INIT_PS_ALLOCATION
+{
+ ASIC_INIT_PARAMETERS sASICInitClocks;
+ SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
+}ASIC_INIT_PS_ALLOCATION;
+
+
+typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
+{
+ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
+ UCHAR ucPadding[3];
+}DYNAMIC_CLOCK_GATING_PARAMETERS;
+#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
+
+
+typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
+{
+ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
+ UCHAR ucPadding[3];
+}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
+#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
+
+
+typedef struct _DAC_LOAD_DETECTION_PARAMETERS
+{
+ USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
+ UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
+ UCHAR ucMisc; //Valid only when table revision =1.3 and above
+}DAC_LOAD_DETECTION_PARAMETERS;
+
+// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
+#define DAC_LOAD_MISC_YPrPb 0x01
+
+
+typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
+{
+ DAC_LOAD_DETECTION_PARAMETERS sDacload;
+ ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
+}DAC_LOAD_DETECTION_PS_ALLOCATION;
+
+
+typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
+{
+ USHORT usPixelClock; // in 10KHz; for bios convenient
+ UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx
+ // 1: PS2
+ UCHAR ucAction; // 0: turn off encoder
+ // 1: setup and turn on encoder
+}DAC_ENCODER_CONTROL_PARAMETERS;
+
+#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
+
+typedef struct _TV_ENCODER_CONTROL_PARAMETERS
+{
+ USHORT usPixelClock; // in 10KHz; for bios convenient
+ UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
+ UCHAR ucAction; // 0: turn off encoder
+ // 1: setup and turn on encoder
+}TV_ENCODER_CONTROL_PARAMETERS;
+
+typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
+{
+ USHORT usPixelClock; // in 10KHz; for bios convenient
+ UCHAR ucConfig;
+ // [2] Link Select:
+ // =0: PHY linkA if bfLane<3
+ // =1: PHY linkB if bfLanes<3
+ // =0: PHY linkA+B if bfLanes=3
+ // [3] Transmitter Sel
+ // =0: UNIPHY or PCIEPHY
+ // =1: LVTMA
+ UCHAR ucAction; // =0: turn off encoder
+ // =1: turn on encoder
+ union{
+ UCHAR ucEncoderMode;
+ // =0: DP encoder
+ // =1: LVDS encoder
+ // =2: DVI encoder
+ // =3: HDMI encoder
+ // =4: SDVO encoder
+ UCHAR ucEncoderType;
+ };
+ UCHAR ucLaneNum; // how many lanes to enable
+ UCHAR ucReserved[2];
+}DIG_ENCODER_CONTROL_PARAMETERS;
+#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
+#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
+#define EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PS_ALLOCATION
+
+//ucConfig
+#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
+#define ATOM_ENCODER_CONFIG_LINKA 0x00
+#define ATOM_ENCODER_CONFIG_LINKB 0x04
+#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
+#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
+#define ATOM_ENCODER_CONFIG_UNIPHY 0x00
+#define ATOM_ENCODER_CONFIG_LVTMA 0x08
+#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
+#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
+#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
+// ucAction
+// ATOM_ENABLE: Enable Encoder
+// ATOM_DISABLE: Disable Encoder
+
+//ucEncoderMode
+#define ATOM_ENCODER_MODE_DP 0
+#define ATOM_ENCODER_MODE_LVDS 1
+#define ATOM_ENCODER_MODE_DVI 2
+#define ATOM_ENCODER_MODE_HDMI 3
+#define ATOM_ENCODER_MODE_SDVO 4
+#define ATOM_ENCODER_MODE_TV 13
+#define ATOM_ENCODER_MODE_CV 14
+#define ATOM_ENCODER_MODE_CRT 15
+
+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
+{
+ union
+ {
+ USHORT usPixelClock; // in 10KHz; for bios convenient
+ USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
+ };
+ UCHAR ucConfig;
+ // [0]=0: 4 lane Link,
+ // =1: 8 lane Link ( Dual Links TMDS )
+ // [1]=0: InCoherent mode
+ // =1: Coherent Mode
+ // [2] Link Select:
+ // =0: PHY linkA if bfLane<3
+ // =1: PHY linkB if bfLanes<3
+ // =0: PHY linkA+B if bfLanes=3
+ // [5:4]PCIE lane Sel
+ // =0: lane 0~3 or 0~7
+ // =1: lane 4~7
+ // =2: lane 8~11 or 8~15
+ // =3: lane 12~15
+ UCHAR ucAction; // =0: turn off encoder
+ // =1: turn on encoder
+ UCHAR ucReserved[4];
+}DIG_TRANSMITTER_CONTROL_PARAMETERS;
+
+#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
+
+//ucInitInfo
+#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
+
+//ucConfig
+#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
+#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
+#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
+#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
+#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
+#define ATOM_TRANSMITTER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
+#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
+#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
+#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
+#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
+#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
+#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
+#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
+
+//ucAction
+#define ATOM_TRANSMITTER_ACTION_DISABLE 0
+#define ATOM_TRANSMITTER_ACTION_ENABLE 1
+#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
+#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
+#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
+#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
+#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
+#define ATOM_TRANSMITTER_ACTION_INIT 7
+#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 8
+#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 9
+#define ATOM_TRANSMITTER_ACTION_SETUP 10
+
+
+/****************************Device Output Control Command Table Definitions**********************/
+typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+{
+ UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
+ // When the display is LCD, in addition to above:
+ // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
+ // ATOM_LCD_SELFTEST_STOP
+
+ UCHAR aucPadding[3]; // padding to DWORD aligned
+}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
+
+#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+
+
+#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
+#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
+
+/**************************************************************************/
+typedef struct _BLANK_CRTC_PARAMETERS
+{
+ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
+ UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
+ USHORT usBlackColorRCr;
+ USHORT usBlackColorGY;
+ USHORT usBlackColorBCb;
+}BLANK_CRTC_PARAMETERS;
+#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
+
+
+typedef struct _ENABLE_CRTC_PARAMETERS
+{
+ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
+ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
+ UCHAR ucPadding[2];
+}ENABLE_CRTC_PARAMETERS;
+#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
+
+
+typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
+{
+ USHORT usOverscanRight; // right
+ USHORT usOverscanLeft; // left
+ USHORT usOverscanBottom; // bottom
+ USHORT usOverscanTop; // top
+ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
+ UCHAR ucPadding[3];
+}SET_CRTC_OVERSCAN_PARAMETERS;
+#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
+
+
+typedef struct _SET_CRTC_REPLICATION_PARAMETERS
+{
+ UCHAR ucH_Replication; // horizontal replication
+ UCHAR ucV_Replication; // vertical replication
+ UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
+ UCHAR ucPadding;
+}SET_CRTC_REPLICATION_PARAMETERS;
+#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
+
+
+typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
+{
+ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
+ UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
+ UCHAR ucPadding[2];
+}SELECT_CRTC_SOURCE_PARAMETERS;
+#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
+
+typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
+{
+ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
+ UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
+ UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
+ UCHAR ucPadding;
+}SELECT_CRTC_SOURCE_PARAMETERS_V2;
+
+//ucEncoderID
+//#define ASIC_INT_DAC1_ENCODER_ID 0x00
+//#define ASIC_INT_TV_ENCODER_ID 0x02
+//#define ASIC_INT_DIG1_ENCODER_ID 0x03
+//#define ASIC_INT_DAC2_ENCODER_ID 0x04
+//#define ASIC_EXT_TV_ENCODER_ID 0x06
+//#define ASIC_INT_DVO_ENCODER_ID 0x07
+//#define ASIC_INT_DIG2_ENCODER_ID 0x09
+//#define ASIC_EXT_DIG_ENCODER_ID 0x05
+
+//ucEncodeMode
+//#define ATOM_ENCODER_MODE_DP 0
+//#define ATOM_ENCODER_MODE_LVDS 1
+//#define ATOM_ENCODER_MODE_DVI 2
+//#define ATOM_ENCODER_MODE_HDMI 3
+//#define ATOM_ENCODER_MODE_SDVO 4
+//#define ATOM_ENCODER_MODE_TV 13
+//#define ATOM_ENCODER_MODE_CV 14
+//#define ATOM_ENCODER_MODE_CRT 15
+
+//Major revision=1., Minor revision=1
+typedef struct _PIXEL_CLOCK_PARAMETERS
+{
+ USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
+ // 0 means disable PPLL
+ USHORT usRefDiv; // Reference divider
+ USHORT usFbDiv; // feedback divider
+ UCHAR ucPostDiv; // post divider
+ UCHAR ucFracFbDiv; // fractional feedback divider
+ UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
+ UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
+ UCHAR ucCRTC; // Which CRTC uses this Ppll
+ UCHAR ucPadding;
+}PIXEL_CLOCK_PARAMETERS;
+
+
+//Major revision=1., Minor revision=2, add ucMiscIfno
+//ucMiscInfo:
+#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
+#define MISC_DEVICE_INDEX_MASK 0xF0
+#define MISC_DEVICE_INDEX_SHIFT 4
+
+typedef struct _PIXEL_CLOCK_PARAMETERS_V2
+{
+ USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
+ // 0 means disable PPLL
+ USHORT usRefDiv; // Reference divider
+ USHORT usFbDiv; // feedback divider
+ UCHAR ucPostDiv; // post divider
+ UCHAR ucFracFbDiv; // fractional feedback divider
+ UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
+ UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
+ UCHAR ucCRTC; // Which CRTC uses this Ppll
+ UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
+}PIXEL_CLOCK_PARAMETERS_V2;
+
+//Major revision=1., Minor revision=3, structure/definition change
+//ucEncoderMode:
+//ATOM_ENCODER_MODE_DP
+//ATOM_ENOCDER_MODE_LVDS
+//ATOM_ENOCDER_MODE_DVI
+//ATOM_ENOCDER_MODE_HDMI
+//ATOM_ENOCDER_MODE_SDVO
+//ATOM_ENCODER_MODE_TV 13
+//ATOM_ENCODER_MODE_CV 14
+//ATOM_ENCODER_MODE_CRT 15
+
+//ucMiscInfo: also changed, see below
+#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
+#define PIXEL_CLOCK_MISC_VGA_MODE 0x02
+#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
+#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
+#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
+
+typedef struct _PIXEL_CLOCK_PARAMETERS_V3
+{
+ USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
+ // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
+ USHORT usRefDiv; // Reference divider
+ USHORT usFbDiv; // feedback divider
+ UCHAR ucPostDiv; // post divider
+ UCHAR ucFracFbDiv; // fractional feedback divider
+ UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
+ UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
+ UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
+ UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
+}PIXEL_CLOCK_PARAMETERS_V3;
+
+#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
+#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
+
+typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
+{
+ USHORT usPixelClock;
+ UCHAR ucTransmitterID;
+ UCHAR ucEncodeMode;
+ union
+ {
+ UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
+ UCHAR ucConfig; //if none DVO, not defined yet
+ };
+ UCHAR ucReserved[3];
+}ADJUST_DISPLAY_PLL_PARAMETERS;
+
+#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
+
+typedef struct _ENABLE_YUV_PARAMETERS
+{
+ UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
+ UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
+ UCHAR ucPadding[2];
+}ENABLE_YUV_PARAMETERS;
+#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
+
+typedef struct _GET_MEMORY_CLOCK_PARAMETERS
+{
+ ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
+} GET_MEMORY_CLOCK_PARAMETERS;
+#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
+
+
+typedef struct _GET_ENGINE_CLOCK_PARAMETERS
+{
+ ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
+} GET_ENGINE_CLOCK_PARAMETERS;
+#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
+
+
+//Maxium 8 bytes,the data read in will be placed in the parameter space.
+//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
+typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
+{
+ USHORT usPrescale; //Ratio between Engine clock and I2C clock
+ USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
+ USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
+ //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
+ UCHAR ucSlaveAddr; //Read from which slave
+ UCHAR ucLineNumber; //Read from which HW assisted line
+}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
+#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
+
+
+#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
+#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
+#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
+#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
+#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
+
+typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+{
+ USHORT usPrescale; //Ratio between Engine clock and I2C clock
+ USHORT usByteOffset; //Write to which byte
+ //Upper portion of usByteOffset is Format of data
+ //1bytePS+offsetPS
+ //2bytesPS+offsetPS
+ //blockID+offsetPS
+ //blockID+offsetID
+ //blockID+counterID+offsetID
+ UCHAR ucData; //PS data1
+ UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
+ UCHAR ucSlaveAddr; //Write to which slave
+ UCHAR ucLineNumber; //Write from which HW assisted line
+}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
+
+#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+
+typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
+{
+ USHORT usPrescale; //Ratio between Engine clock and I2C clock
+ UCHAR ucSlaveAddr; //Write to which slave
+ UCHAR ucLineNumber; //Write from which HW assisted line
+}SET_UP_HW_I2C_DATA_PARAMETERS;
+
+
+/**************************************************************************/
+#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+
+typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
+{
+ UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
+ UCHAR ucPwrBehaviorId;
+ USHORT usPwrBudget; //how much power currently boot to in unit of watt
+}POWER_CONNECTOR_DETECTION_PARAMETERS;
+
+typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
+{
+ UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
+ UCHAR ucReserved;
+ USHORT usPwrBudget; //how much power currently boot to in unit of watt
+ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
+}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
+
+/****************************LVDS SS Command Table Definitions**********************/
+typedef struct _ENABLE_LVDS_SS_PARAMETERS
+{
+ USHORT usSpreadSpectrumPercentage;
+ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
+ UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
+ UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
+ UCHAR ucPadding[3];
+}ENABLE_LVDS_SS_PARAMETERS;
+
+//ucTableFormatRevision=1,ucTableContentRevision=2
+typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
+{
+ USHORT usSpreadSpectrumPercentage;
+ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
+ UCHAR ucSpreadSpectrumStep; //
+ UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
+ UCHAR ucSpreadSpectrumDelay;
+ UCHAR ucSpreadSpectrumRange;
+ UCHAR ucPadding;
+}ENABLE_LVDS_SS_PARAMETERS_V2;
+
+//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
+typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
+{
+ USHORT usSpreadSpectrumPercentage;
+ UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
+ UCHAR ucSpreadSpectrumStep; //
+ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
+ UCHAR ucSpreadSpectrumDelay;
+ UCHAR ucSpreadSpectrumRange;
+ UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
+}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
+
+#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
+
+/**************************************************************************/
+
+typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
+{
+ PIXEL_CLOCK_PARAMETERS sPCLKInput;
+ ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
+}SET_PIXEL_CLOCK_PS_ALLOCATION;
+
+#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
+
+typedef struct _MEMORY_TRAINING_PARAMETERS
+{
+ ULONG ulTargetMemoryClock; //In 10Khz unit
+}MEMORY_TRAINING_PARAMETERS;
+#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
+
+
+
+/****************************LVDS and other encoder command table definitions **********************/
+typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
+{
+ USHORT usPixelClock; // in 10KHz; for bios convenient
+ UCHAR ucMisc; // bit0=0: Enable single link
+ // =1: Enable dual link
+ // Bit1=0: 666RGB
+ // =1: 888RGB
+ UCHAR ucAction; // 0: turn off encoder
+ // 1: setup and turn on encoder
+}LVDS_ENCODER_CONTROL_PARAMETERS;
+
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
+
+typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
+{
+ UCHAR ucEnable; // Enable or Disable External TMDS encoder
+ UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
+ UCHAR ucPadding[2];
+}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
+
+typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
+{
+ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
+ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
+}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
+
+
+//ucTableFormatRevision=1,ucTableContentRevision=2
+typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
+{
+ USHORT usPixelClock; // in 10KHz; for bios convenient
+ UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
+ UCHAR ucAction; // 0: turn off encoder
+ // 1: setup and turn on encoder
+ UCHAR ucTruncate; // bit0=0: Disable truncate
+ // =1: Enable truncate
+ // bit4=0: 666RGB
+ // =1: 888RGB
+ UCHAR ucSpatial; // bit0=0: Disable spatial dithering
+ // =1: Enable spatial dithering
+ // bit4=0: 666RGB
+ // =1: 888RGB
+ UCHAR ucTemporal; // bit0=0: Disable temporal dithering
+ // =1: Enable temporal dithering
+ // bit4=0: 666RGB
+ // =1: 888RGB
+ // bit5=0: Gray level 2
+ // =1: Gray level 4
+ UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
+ // =1: 25FRC_SEL pattern F
+ // bit6:5=0: 50FRC_SEL pattern A
+ // =1: 50FRC_SEL pattern B
+ // =2: 50FRC_SEL pattern C
+ // =3: 50FRC_SEL pattern D
+ // bit7=0: 75FRC_SEL pattern E
+ // =1: 75FRC_SEL pattern F
+}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
+
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
+#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
+
+typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
+{
+ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
+ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
+}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
+
+
+//ucTableFormatRevision=1,ucTableContentRevision=3
+
+//ucDVOConfig:
+#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
+#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
+#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
+#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
+#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
+#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
+#define DVO_ENCODER_CONFIG_24BIT 0x08
+
+typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
+{
+ USHORT usPixelClock;
+ UCHAR ucDVOConfig;
+ UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
+ UCHAR ucReseved[4];
+}DVO_ENCODER_CONTROL_PARAMETERS_V3;
+#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
+
+//ucTableFormatRevision=1
+//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
+// bit1=0: non-coherent mode
+// =1: coherent mode
+
+#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
+
+//==========================================================================================
+//Only change is here next time when changing encoder parameter definitions again!
+#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
+
+#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
+#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
+
+//==========================================================================================
+#define PANEL_ENCODER_MISC_DUAL 0x01
+#define PANEL_ENCODER_MISC_COHERENT 0x02
+#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
+#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
+
+#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
+#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
+#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
+
+#define PANEL_ENCODER_TRUNCATE_EN 0x01
+#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
+#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
+#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
+#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
+#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
+#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
+#define PANEL_ENCODER_25FRC_MASK 0x10
+#define PANEL_ENCODER_25FRC_E 0x00
+#define PANEL_ENCODER_25FRC_F 0x10
+#define PANEL_ENCODER_50FRC_MASK 0x60
+#define PANEL_ENCODER_50FRC_A 0x00
+#define PANEL_ENCODER_50FRC_B 0x20
+#define PANEL_ENCODER_50FRC_C 0x40
+#define PANEL_ENCODER_50FRC_D 0x60
+#define PANEL_ENCODER_75FRC_MASK 0x80
+#define PANEL_ENCODER_75FRC_E 0x00
+#define PANEL_ENCODER_75FRC_F 0x80
+
+/**************************************************************************/
+
+#define SET_VOLTAGE_TYPE_ASIC_VDDC 1
+#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
+#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
+#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
+
+#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
+#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
+#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
+
+#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
+#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
+#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
+
+typedef struct _SET_VOLTAGE_PARAMETERS
+{
+ UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
+ UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
+ UCHAR ucVoltageIndex; // An index to tell which voltage level
+ UCHAR ucReserved;
+}SET_VOLTAGE_PARAMETERS;
+
+
+typedef struct _SET_VOLTAGE_PARAMETERS_V2
+{
+ UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
+ UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
+ USHORT usVoltageLevel; // real voltage level
+}SET_VOLTAGE_PARAMETERS_V2;
+
+
+typedef struct _SET_VOLTAGE_PS_ALLOCATION
+{
+ SET_VOLTAGE_PARAMETERS sASICSetVoltage;
+ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
+}SET_VOLTAGE_PS_ALLOCATION;
+
+typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
+{
+ TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
+ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
+}TV_ENCODER_CONTROL_PS_ALLOCATION;
+
+//==============================Data Table Portion====================================
+
+#ifdef UEFI_BUILD
+ #define UTEMP USHORT
+ #define USHORT void*
+#endif
+
+typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
+{
+ USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
+ USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
+ USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
+ USHORT StandardVESA_Timing; // Only used by Bios
+ USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
+ USHORT DAC_Info; // Will be obsolete from R600
+ USHORT LVDS_Info; // Shared by various SW components,latest version 1.1
+ USHORT TMDS_Info; // Will be obsolete from R600
+ USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
+ USHORT SupportedDevicesInfo; // Will be obsolete from R600
+ USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
+ USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
+ USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
+ USHORT VESA_ToInternalModeLUT; // Only used by Bios
+ USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
+ USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
+ USHORT CompassionateData; // Will be obsolete from R600
+ USHORT SaveRestoreInfo; // Only used by Bios
+ USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
+ USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
+ USHORT XTMDS_Info; // Will be obsolete from R600
+ USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
+ USHORT Object_Header; // Shared by various SW components,latest version 1.1
+ USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
+ USHORT MC_InitParameter; // Only used by command table
+ USHORT ASIC_VDDC_Info; // Will be obsolete from R600
+ USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
+ USHORT TV_VideoMode; // Only used by command table
+ USHORT VRAM_Info; // Only used by command table, latest version 1.3
+ USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
+ USHORT IntegratedSystemInfo; // Shared by various SW components
+ USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
+ USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
+ USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
+}ATOM_MASTER_LIST_OF_DATA_TABLES;
+
+#ifdef UEFI_BUILD
+ #define USHORT UTEMP
+#endif
+
+
+typedef struct _ATOM_MASTER_DATA_TABLE
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
+}ATOM_MASTER_DATA_TABLE;
+
+
+typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulSignature; // HW info table signature string "$ATI"
+ UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
+ UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
+ UCHAR ucVideoPortInfo; // Provides the video port capabilities
+ UCHAR ucHostPortInfo; // Provides host port configuration information
+}ATOM_MULTIMEDIA_CAPABILITY_INFO;
+
+
+typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulSignature; // MM info table signature sting "$MMT"
+ UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
+ UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
+ UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
+ UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
+ UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
+ UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
+ UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
+ UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+ UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+ UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+ UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+ UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+}ATOM_MULTIMEDIA_CONFIG_INFO;
+
+/****************************Firmware Info Table Definitions**********************/
+
+// usBIOSCapability Defintion:
+// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
+// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
+// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
+// Others: Reserved
+#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
+#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
+#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
+#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008
+#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010
+#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
+#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
+#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
+#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
+#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
+#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
+#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
+
+
+#ifndef _H2INC
+
+//Please don't add or expand this bitfield structure below, this one will retire soon.!
+typedef struct _ATOM_FIRMWARE_CAPABILITY
+{
+ USHORT FirmwarePosted:1;
+ USHORT DualCRTC_Support:1;
+ USHORT ExtendedDesktopSupport:1;
+ USHORT MemoryClockSS_Support:1;
+ USHORT EngineClockSS_Support:1;
+ USHORT GPUControlsBL:1;
+ USHORT WMI_SUPPORT:1;
+ USHORT PPMode_Assigned:1;
+ USHORT HyperMemory_Support:1;
+ USHORT HyperMemory_Size:4;
+ USHORT Reserved:3;
+}ATOM_FIRMWARE_CAPABILITY;
+
+typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
+{
+ ATOM_FIRMWARE_CAPABILITY sbfAccess;
+ USHORT susAccess;
+}ATOM_FIRMWARE_CAPABILITY_ACCESS;
+
+#else
+
+typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
+{
+ USHORT susAccess;
+}ATOM_FIRMWARE_CAPABILITY_ACCESS;
+
+#endif
+
+typedef struct _ATOM_FIRMWARE_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulFirmwareRevision;
+ ULONG ulDefaultEngineClock; //In 10Khz unit
+ ULONG ulDefaultMemoryClock; //In 10Khz unit
+ ULONG ulDriverTargetEngineClock; //In 10Khz unit
+ ULONG ulDriverTargetMemoryClock; //In 10Khz unit
+ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
+ ULONG ulASICMaxEngineClock; //In 10Khz unit
+ ULONG ulASICMaxMemoryClock; //In 10Khz unit
+ UCHAR ucASICMaxTemperature;
+ UCHAR ucPadding[3]; //Don't use them
+ ULONG aulReservedForBIOS[3]; //Don't use them
+ USHORT usMinEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMinEngineClockPLL_Output; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
+ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
+ USHORT usMinPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
+ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+ USHORT usReferenceClock; //In 10Khz unit
+ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
+ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
+ UCHAR ucDesign_ID; //Indicate what is the board design
+ UCHAR ucMemoryModule_ID; //Indicate what is the board design
+}ATOM_FIRMWARE_INFO;
+
+typedef struct _ATOM_FIRMWARE_INFO_V1_2
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulFirmwareRevision;
+ ULONG ulDefaultEngineClock; //In 10Khz unit
+ ULONG ulDefaultMemoryClock; //In 10Khz unit
+ ULONG ulDriverTargetEngineClock; //In 10Khz unit
+ ULONG ulDriverTargetMemoryClock; //In 10Khz unit
+ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
+ ULONG ulASICMaxEngineClock; //In 10Khz unit
+ ULONG ulASICMaxMemoryClock; //In 10Khz unit
+ UCHAR ucASICMaxTemperature;
+ UCHAR ucMinAllowedBL_Level;
+ UCHAR ucPadding[2]; //Don't use them
+ ULONG aulReservedForBIOS[2]; //Don't use them
+ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
+ USHORT usMinEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMinEngineClockPLL_Output; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
+ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
+ USHORT usMinPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
+ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+ USHORT usReferenceClock; //In 10Khz unit
+ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
+ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
+ UCHAR ucDesign_ID; //Indicate what is the board design
+ UCHAR ucMemoryModule_ID; //Indicate what is the board design
+}ATOM_FIRMWARE_INFO_V1_2;
+
+typedef struct _ATOM_FIRMWARE_INFO_V1_3
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulFirmwareRevision;
+ ULONG ulDefaultEngineClock; //In 10Khz unit
+ ULONG ulDefaultMemoryClock; //In 10Khz unit
+ ULONG ulDriverTargetEngineClock; //In 10Khz unit
+ ULONG ulDriverTargetMemoryClock; //In 10Khz unit
+ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
+ ULONG ulASICMaxEngineClock; //In 10Khz unit
+ ULONG ulASICMaxMemoryClock; //In 10Khz unit
+ UCHAR ucASICMaxTemperature;
+ UCHAR ucMinAllowedBL_Level;
+ UCHAR ucPadding[2]; //Don't use them
+ ULONG aulReservedForBIOS; //Don't use them
+ ULONG ul3DAccelerationEngineClock;//In 10Khz unit
+ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
+ USHORT usMinEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMinEngineClockPLL_Output; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
+ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
+ USHORT usMinPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
+ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+ USHORT usReferenceClock; //In 10Khz unit
+ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
+ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
+ UCHAR ucDesign_ID; //Indicate what is the board design
+ UCHAR ucMemoryModule_ID; //Indicate what is the board design
+}ATOM_FIRMWARE_INFO_V1_3;
+
+typedef struct _ATOM_FIRMWARE_INFO_V1_4
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulFirmwareRevision;
+ ULONG ulDefaultEngineClock; //In 10Khz unit
+ ULONG ulDefaultMemoryClock; //In 10Khz unit
+ ULONG ulDriverTargetEngineClock; //In 10Khz unit
+ ULONG ulDriverTargetMemoryClock; //In 10Khz unit
+ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
+ ULONG ulASICMaxEngineClock; //In 10Khz unit
+ ULONG ulASICMaxMemoryClock; //In 10Khz unit
+ UCHAR ucASICMaxTemperature;
+ UCHAR ucMinAllowedBL_Level;
+ USHORT usBootUpVDDCVoltage; //In MV unit
+ USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
+ USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
+ ULONG ul3DAccelerationEngineClock;//In 10Khz unit
+ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
+ USHORT usMinEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMinEngineClockPLL_Output; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
+ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
+ USHORT usMinPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
+ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+ USHORT usReferenceClock; //In 10Khz unit
+ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
+ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
+ UCHAR ucDesign_ID; //Indicate what is the board design
+ UCHAR ucMemoryModule_ID; //Indicate what is the board design
+}ATOM_FIRMWARE_INFO_V1_4;
+
+#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4
+
+#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
+#define IGP_CAP_FLAG_AC_CARD 0x4
+#define IGP_CAP_FLAG_SDVO_CARD 0x8
+#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
+
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulBootUpEngineClock; //in 10kHz unit
+ ULONG ulBootUpMemoryClock; //in 10kHz unit
+ ULONG ulMaxSystemMemoryClock; //in 10kHz unit
+ ULONG ulMinSystemMemoryClock; //in 10kHz unit
+ UCHAR ucNumberOfCyclesInPeriodHi;
+ UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
+ USHORT usReserved1;
+ USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
+ USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
+ ULONG ulReserved[2];
+
+ USHORT usFSBClock; //In MHz unit
+ USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
+ //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
+ //Bit[4]==1: P/2 mode, ==0: P/1 mode
+ USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
+ USHORT usK8MemoryClock; //in MHz unit
+ USHORT usK8SyncStartDelay; //in 0.01 us unit
+ USHORT usK8DataReturnTime; //in 0.01 us unit
+ UCHAR ucMaxNBVoltage;
+ UCHAR ucMinNBVoltage;
+ UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
+ UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
+ UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
+ UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
+ UCHAR ucMaxNBVoltageHigh;
+ UCHAR ucMinNBVoltageHigh;
+}ATOM_INTEGRATED_SYSTEM_INFO;
+
+/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
+ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
+ For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
+ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
+ For AMD IGP,for now this can be 0
+ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
+ For AMD IGP,for now this can be 0
+
+usFSBClock: For Intel IGP,it's FSB Freq
+ For AMD IGP,it's HT Link Speed
+
+usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
+usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
+usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
+
+VC:Voltage Control
+ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
+ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
+
+ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
+ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
+
+ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
+ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
+
+
+usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
+usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
+*/
+
+
+/*
+The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
+Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
+The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
+
+SW components can access the IGP system infor structure in the same way as before
+*/
+
+
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulBootUpEngineClock; //in 10kHz unit
+ ULONG ulReserved1[2]; //must be 0x0 for the reserved
+ ULONG ulBootUpUMAClock; //in 10kHz unit
+ ULONG ulBootUpSidePortClock; //in 10kHz unit
+ ULONG ulReserved2[8]; //must be 0x0 for the reserved
+ ULONG ulBootUpReqDisplayVector;
+ ULONG ulOtherDisplayMisc;
+ ULONG ulDDISlot1Config;
+ ULONG ulDDISlot2Config;
+ UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
+ UCHAR ucReserved; //must be 0x0 for the reserved
+ UCHAR ucDockingPinBit;
+ UCHAR ucDockingPinPolarity;
+ ULONG ulDockingPinCFGInfo;
+ ULONG ulCPUCapInfo;
+ ULONG ulReserved3[107]; //must be 0x0
+}ATOM_INTEGRATED_SYSTEM_INFO_V2;
+
+/*
+ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
+ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
+ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present
+
+
+ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
+
+ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
+ [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
+
+ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
+ [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
+ [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
+ [15:8] - Lane configuration attribute;
+ [31:16]- Reserved
+
+ulDDISlot2Config: Same as Slot1
+
+ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
+ucDockingPinBit: which bit in this register to read the pin status;
+ucDockingPinPolarity:Polarity of the pin when docked;
+
+ulCPUCapInfo: TBD
+
+*/
+
+#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
+#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
+#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
+#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
+#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
+#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
+#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
+#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
+#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
+#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
+#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
+#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
+#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
+#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
+
+// define ASIC internal encoder id ( bit vector )
+#define ASIC_INT_DAC1_ENCODER_ID 0x00
+#define ASIC_INT_TV_ENCODER_ID 0x02
+#define ASIC_INT_DIG1_ENCODER_ID 0x03
+#define ASIC_INT_DAC2_ENCODER_ID 0x04
+#define ASIC_EXT_TV_ENCODER_ID 0x06
+#define ASIC_INT_DVO_ENCODER_ID 0x07
+#define ASIC_INT_DIG2_ENCODER_ID 0x09
+#define ASIC_EXT_DIG_ENCODER_ID 0x05
+
+//define Encoder attribute
+#define ATOM_ANALOG_ENCODER 0
+#define ATOM_DIGITAL_ENCODER 1
+
+#define ATOM_DEVICE_CRT1_INDEX 0x00000000
+#define ATOM_DEVICE_LCD1_INDEX 0x00000001
+#define ATOM_DEVICE_TV1_INDEX 0x00000002
+#define ATOM_DEVICE_DFP1_INDEX 0x00000003
+#define ATOM_DEVICE_CRT2_INDEX 0x00000004
+#define ATOM_DEVICE_LCD2_INDEX 0x00000005
+#define ATOM_DEVICE_TV2_INDEX 0x00000006
+#define ATOM_DEVICE_DFP2_INDEX 0x00000007
+#define ATOM_DEVICE_CV_INDEX 0x00000008
+#define ATOM_DEVICE_DFP3_INDEX 0x00000009
+#define ATOM_DEVICE_RESERVEDA_INDEX 0x0000000A
+#define ATOM_DEVICE_RESERVEDB_INDEX 0x0000000B
+#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
+#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
+#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
+#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
+#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_CV_INDEX+2)
+#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
+#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
+
+#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
+#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
+#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
+#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX)
+#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
+#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
+#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX )
+#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX)
+#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
+#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
+
+#define ATOM_DEVICE_CRT_SUPPORT ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT
+#define ATOM_DEVICE_DFP_SUPPORT ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT
+#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT
+#define ATOM_DEVICE_LCD_SUPPORT ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT
+
+#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
+#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
+#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
+#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
+#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
+#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
+#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
+#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
+#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
+#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
+#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
+#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
+#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
+#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
+#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
+
+
+#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
+#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
+#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
+#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
+#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
+#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
+
+#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
+
+#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
+#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
+
+#define ATOM_DEVICE_I2C_ID_MASK 0x00000070
+#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
+#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
+#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
+#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
+#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
+
+#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
+#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
+#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
+#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
+
+// usDeviceSupport:
+// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
+// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
+// Bit 2 = 0 - no TV1 support= 1- TV1 is supported
+// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
+// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
+// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
+// Bit 6 = 0 - no TV2 support= 1- TV2 is supported
+// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
+// Bit 8 = 0 - no CV support= 1- CV is supported
+// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
+// Byte1 (Supported Device Info)
+// Bit 0 = = 0 - no CV support= 1- CV is supported
+//
+//
+
+// ucI2C_ConfigID
+// [7:0] - I2C LINE Associate ID
+// = 0 - no I2C
+// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
+// = 0, [6:0]=SW assisted I2C ID
+// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
+// = 2, HW engine for Multimedia use
+// = 3-7 Reserved for future I2C engines
+// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
+
+
+typedef struct _ATOM_I2C_ID_CONFIG
+{
+ UCHAR bfI2C_LineMux:4;
+ UCHAR bfHW_EngineID:3;
+ UCHAR bfHW_Capable:1;
+}ATOM_I2C_ID_CONFIG;
+
+typedef union _ATOM_I2C_ID_CONFIG_ACCESS
+{
+ ATOM_I2C_ID_CONFIG sbfAccess;
+ UCHAR ucAccess;
+}ATOM_I2C_ID_CONFIG_ACCESS;
+
+
+typedef struct _ATOM_GPIO_I2C_ASSIGMENT
+{
+ USHORT usClkMaskRegisterIndex;
+ USHORT usClkEnRegisterIndex;
+ USHORT usClkY_RegisterIndex;
+ USHORT usClkA_RegisterIndex;
+ USHORT usDataMaskRegisterIndex;
+ USHORT usDataEnRegisterIndex;
+ USHORT usDataY_RegisterIndex;
+ USHORT usDataA_RegisterIndex;
+ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
+ UCHAR ucClkMaskShift;
+ UCHAR ucClkEnShift;
+ UCHAR ucClkY_Shift;
+ UCHAR ucClkA_Shift;
+ UCHAR ucDataMaskShift;
+ UCHAR ucDataEnShift;
+ UCHAR ucDataY_Shift;
+ UCHAR ucDataA_Shift;
+ UCHAR ucReserved1;
+ UCHAR ucReserved2;
+}ATOM_GPIO_I2C_ASSIGMENT;
+
+typedef struct _ATOM_GPIO_I2C_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
+}ATOM_GPIO_I2C_INFO;
+
+
+#ifndef _H2INC
+
+//Please don't add or expand this bitfield structure below, this one will retire soon.!
+typedef struct _ATOM_MODE_MISC_INFO
+{
+ USHORT HorizontalCutOff:1;
+ USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
+ USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
+ USHORT VerticalCutOff:1;
+ USHORT H_ReplicationBy2:1;
+ USHORT V_ReplicationBy2:1;
+ USHORT CompositeSync:1;
+ USHORT Interlace:1;
+ USHORT DoubleClock:1;
+ USHORT RGB888:1;
+ USHORT Reserved:6;
+}ATOM_MODE_MISC_INFO;
+
+typedef union _ATOM_MODE_MISC_INFO_ACCESS
+{
+ ATOM_MODE_MISC_INFO sbfAccess;
+ USHORT usAccess;
+}ATOM_MODE_MISC_INFO_ACCESS;
+
+#else
+
+typedef union _ATOM_MODE_MISC_INFO_ACCESS
+{
+ USHORT usAccess;
+}ATOM_MODE_MISC_INFO_ACCESS;
+
+#endif
+
+// usModeMiscInfo-
+#define ATOM_H_CUTOFF 0x01
+#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
+#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
+#define ATOM_V_CUTOFF 0x08
+#define ATOM_H_REPLICATIONBY2 0x10
+#define ATOM_V_REPLICATIONBY2 0x20
+#define ATOM_COMPOSITESYNC 0x40
+#define ATOM_INTERLACE 0x80
+#define ATOM_DOUBLE_CLOCK_MODE 0x100
+#define ATOM_RGB888_MODE 0x200
+
+//usRefreshRate-
+#define ATOM_REFRESH_43 43
+#define ATOM_REFRESH_47 47
+#define ATOM_REFRESH_56 56
+#define ATOM_REFRESH_60 60
+#define ATOM_REFRESH_65 65
+#define ATOM_REFRESH_70 70
+#define ATOM_REFRESH_72 72
+#define ATOM_REFRESH_75 75
+#define ATOM_REFRESH_85 85
+
+// ATOM_MODE_TIMING data are exactly the same as VESA timing data.
+// Translation from EDID to ATOM_MODE_TIMING, use the following formula.
+//
+// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
+// = EDID_HA + EDID_HBL
+// VESA_HDISP = VESA_ACTIVE = EDID_HA
+// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
+// = EDID_HA + EDID_HSO
+// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
+// VESA_BORDER = EDID_BORDER
+
+
+typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
+{
+ USHORT usH_Size;
+ USHORT usH_Blanking_Time;
+ USHORT usV_Size;
+ USHORT usV_Blanking_Time;
+ USHORT usH_SyncOffset;
+ USHORT usH_SyncWidth;
+ USHORT usV_SyncOffset;
+ USHORT usV_SyncWidth;
+ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
+ UCHAR ucH_Border; // From DFP EDID
+ UCHAR ucV_Border;
+ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
+ UCHAR ucPadding[3];
+}SET_CRTC_USING_DTD_TIMING_PARAMETERS;
+
+typedef struct _SET_CRTC_TIMING_PARAMETERS
+{
+ USHORT usH_Total; // horizontal total
+ USHORT usH_Disp; // horizontal display
+ USHORT usH_SyncStart; // horozontal Sync start
+ USHORT usH_SyncWidth; // horizontal Sync width
+ USHORT usV_Total; // vertical total
+ USHORT usV_Disp; // vertical display
+ USHORT usV_SyncStart; // vertical Sync start
+ USHORT usV_SyncWidth; // vertical Sync width
+ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
+ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
+ UCHAR ucOverscanRight; // right
+ UCHAR ucOverscanLeft; // left
+ UCHAR ucOverscanBottom; // bottom
+ UCHAR ucOverscanTop; // top
+ UCHAR ucReserved;
+}SET_CRTC_TIMING_PARAMETERS;
+#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
+
+
+typedef struct _ATOM_MODE_TIMING
+{
+ USHORT usCRTC_H_Total;
+ USHORT usCRTC_H_Disp;
+ USHORT usCRTC_H_SyncStart;
+ USHORT usCRTC_H_SyncWidth;
+ USHORT usCRTC_V_Total;
+ USHORT usCRTC_V_Disp;
+ USHORT usCRTC_V_SyncStart;
+ USHORT usCRTC_V_SyncWidth;
+ USHORT usPixelClock; //in 10Khz unit
+ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
+ USHORT usCRTC_OverscanRight;
+ USHORT usCRTC_OverscanLeft;
+ USHORT usCRTC_OverscanBottom;
+ USHORT usCRTC_OverscanTop;
+ USHORT usReserve;
+ UCHAR ucInternalModeNumber;
+ UCHAR ucRefreshRate;
+}ATOM_MODE_TIMING;
+
+
+typedef struct _ATOM_DTD_FORMAT
+{
+ USHORT usPixClk;
+ USHORT usHActive;
+ USHORT usHBlanking_Time;
+ USHORT usVActive;
+ USHORT usVBlanking_Time;
+ USHORT usHSyncOffset;
+ USHORT usHSyncWidth;
+ USHORT usVSyncOffset;
+ USHORT usVSyncWidth;
+ USHORT usImageHSize;
+ USHORT usImageVSize;
+ UCHAR ucHBorder;
+ UCHAR ucVBorder;
+ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
+ UCHAR ucReserved1;
+ UCHAR ucReserved2;
+}ATOM_DTD_FORMAT;
+
+#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
+#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
+#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
+#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
+
+/****************************LVDS Info Table Definitions **********************/
+//ucTableFormatRevision=1
+//ucTableContentRevision=1
+typedef struct _ATOM_LVDS_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_DTD_FORMAT sLCDTiming;
+ USHORT usModePatchTableOffset;
+ USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
+ USHORT usOffDelayInMs;
+ UCHAR ucPowerSequenceDigOntoDEin10Ms;
+ UCHAR ucPowerSequenceDEtoBLOnin10Ms;
+ UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
+ // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
+ // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
+ // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
+ UCHAR ucPanelDefaultRefreshRate;
+ UCHAR ucPanelIdentification;
+ UCHAR ucSS_Id;
+}ATOM_LVDS_INFO;
+
+//ucTableFormatRevision=1
+//ucTableContentRevision=2
+typedef struct _ATOM_LVDS_INFO_V12
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_DTD_FORMAT sLCDTiming;
+ USHORT usExtInfoTableOffset;
+ USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
+ USHORT usOffDelayInMs;
+ UCHAR ucPowerSequenceDigOntoDEin10Ms;
+ UCHAR ucPowerSequenceDEtoBLOnin10Ms;
+ UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
+ // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
+ // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
+ // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
+ UCHAR ucPanelDefaultRefreshRate;
+ UCHAR ucPanelIdentification;
+ UCHAR ucSS_Id;
+ USHORT usLCDVenderID;
+ USHORT usLCDProductID;
+ UCHAR ucLCDPanel_SpecialHandlingCap;
+ UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
+ UCHAR ucReserved[2];
+}ATOM_LVDS_INFO_V12;
+
+#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12
+
+typedef struct _ATOM_PATCH_RECORD_MODE
+{
+ UCHAR ucRecordType;
+ USHORT usHDisp;
+ USHORT usVDisp;
+}ATOM_PATCH_RECORD_MODE;
+
+typedef struct _ATOM_LCD_RTS_RECORD
+{
+ UCHAR ucRecordType;
+ UCHAR ucRTSValue;
+}ATOM_LCD_RTS_RECORD;
+
+//!! If the record below exits, it shoud always be the first record for easy use in command table!!!
+typedef struct _ATOM_LCD_MODE_CONTROL_CAP
+{
+ UCHAR ucRecordType;
+ USHORT usLCDCap;
+}ATOM_LCD_MODE_CONTROL_CAP;
+
+#define LCD_MODE_CAP_BL_OFF 1
+#define LCD_MODE_CAP_CRTC_OFF 2
+#define LCD_MODE_CAP_PANEL_OFF 4
+
+typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
+{
+ UCHAR ucRecordType;
+ UCHAR ucFakeEDIDLength;
+ UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
+} ATOM_FAKE_EDID_PATCH_RECORD;
+
+typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
+{
+ UCHAR ucRecordType;
+ USHORT usHSize;
+ USHORT usVSize;
+}ATOM_PANEL_RESOLUTION_PATCH_RECORD;
+
+#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
+#define LCD_RTS_RECORD_TYPE 2
+#define LCD_CAP_RECORD_TYPE 3
+#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
+#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
+#define ATOM_RECORD_END_TYPE 0xFF
+
+/****************************Spread Spectrum Info Table Definitions **********************/
+
+//ucTableFormatRevision=1
+//ucTableContentRevision=2
+typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
+{
+ USHORT usSpreadSpectrumPercentage;
+ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
+ UCHAR ucSS_Step;
+ UCHAR ucSS_Delay;
+ UCHAR ucSS_Id;
+ UCHAR ucRecommandedRef_Div;
+ UCHAR ucSS_Range; //it was reserved for V11
+}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
+
+#define ATOM_MAX_SS_ENTRY 16
+#define ATOM_DP_SS_ID1 0x0f1 // SS modulation freq=30k
+#define ATOM_DP_SS_ID2 0x0f2 // SS modulation freq=33k
+
+
+#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
+#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
+#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
+#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
+#define ATOM_INTERNAL_SS_MASK 0x00000000
+#define ATOM_EXTERNAL_SS_MASK 0x00000002
+#define EXEC_SS_STEP_SIZE_SHIFT 2
+#define EXEC_SS_DELAY_SHIFT 4
+#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
+
+typedef struct _ATOM_SPREAD_SPECTRUM_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
+}ATOM_SPREAD_SPECTRUM_INFO;
+
+
+
+
+//ucTVBootUpDefaultStd definiton:
+
+//ATOM_TV_NTSC 1
+//ATOM_TV_NTSCJ 2
+//ATOM_TV_PAL 3
+//ATOM_TV_PALM 4
+//ATOM_TV_PALCN 5
+//ATOM_TV_PALN 6
+//ATOM_TV_PAL60 7
+//ATOM_TV_SECAM 8
+
+
+//ucTVSuppportedStd definition:
+#define NTSC_SUPPORT 0x1
+#define NTSCJ_SUPPORT 0x2
+
+#define PAL_SUPPORT 0x4
+#define PALM_SUPPORT 0x8
+#define PALCN_SUPPORT 0x10
+#define PALN_SUPPORT 0x20
+#define PAL60_SUPPORT 0x40
+#define SECAM_SUPPORT 0x80
+
+#define MAX_SUPPORTED_TV_TIMING 2
+
+typedef struct _ATOM_ANALOG_TV_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR ucTV_SuppportedStandard;
+ UCHAR ucTV_BootUpDefaultStandard;
+ UCHAR ucExt_TV_ASIC_ID;
+ UCHAR ucExt_TV_ASIC_SlaveAddr;
+ ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
+}ATOM_ANALOG_TV_INFO;
+
+
+/**************************************************************************/
+// VRAM usage and their defintions
+
+// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
+// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
+// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
+// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
+// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
+
+#ifndef VESA_MEMORY_IN_64K_BLOCK
+#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
+#endif
+
+#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes
+#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes
+#define ATOM_HWICON_INFOTABLE_SIZE 32
+#define MAX_DTD_MODE_IN_VRAM 6
+#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
+#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
+#define DFP_ENCODER_TYPE_OFFSET 0x80
+#define DP_ENCODER_LANE_NUMBER 0x84
+#define DP_ENCODER_LINK_RATE 0x88
+
+#define ATOM_HWICON1_SURFACE_ADDR 0
+#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
+#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
+#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
+#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256)
+#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512
+
+//The size below is in Kb!
+#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
+
+#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
+#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
+#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
+#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
+
+#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
+
+typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
+{
+ ULONG ulStartAddrUsedByFirmware;
+ USHORT usFirmwareUseInKb;
+ USHORT usReserved;
+}ATOM_FIRMWARE_VRAM_RESERVE_INFO;
+
+typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
+}ATOM_VRAM_USAGE_BY_FIRMWARE;
+
+/**************************************************************************/
+//GPIO Pin lut table definition
+typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
+{
+ USHORT usGpioPin_AIndex;
+ UCHAR ucGpioPinBitShift;
+ UCHAR ucGPIO_ID;
+}ATOM_GPIO_PIN_ASSIGNMENT;
+
+typedef struct _ATOM_GPIO_PIN_LUT
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
+}ATOM_GPIO_PIN_LUT;
+
+/**************************************************************************/
+
+
+#define GPIO_PIN_ACTIVE_HIGH 0x1
+
+#define MAX_SUPPORTED_CV_STANDARDS 5
+
+// definitions for ATOM_D_INFO.ucSettings
+#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
+#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out
+#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
+
+typedef struct _ATOM_GPIO_INFO
+{
+ USHORT usAOffset;
+ UCHAR ucSettings;
+ UCHAR ucReserved;
+}ATOM_GPIO_INFO;
+
+// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
+#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
+
+// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
+#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
+#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]
+
+// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
+//Line 3 out put 5V.
+#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9
+#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
+#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
+
+//Line 3 out put 2.2V
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
+
+//Line 3 out put 0V
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
+
+#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
+
+#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
+
+//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
+#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
+#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
+
+
+typedef struct _ATOM_COMPONENT_VIDEO_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usMask_PinRegisterIndex;
+ USHORT usEN_PinRegisterIndex;
+ USHORT usY_PinRegisterIndex;
+ USHORT usA_PinRegisterIndex;
+ UCHAR ucBitShift;
+ UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
+ ATOM_DTD_FORMAT sReserved; // must be zeroed out
+ UCHAR ucMiscInfo;
+ UCHAR uc480i;
+ UCHAR uc480p;
+ UCHAR uc720p;
+ UCHAR uc1080i;
+ UCHAR ucLetterBoxMode;
+ UCHAR ucReserved[3];
+ UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
+ ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
+ ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
+}ATOM_COMPONENT_VIDEO_INFO;
+
+//ucTableFormatRevision=2
+//ucTableContentRevision=1
+typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR ucMiscInfo;
+ UCHAR uc480i;
+ UCHAR uc480p;
+ UCHAR uc720p;
+ UCHAR uc1080i;
+ UCHAR ucReserved;
+ UCHAR ucLetterBoxMode;
+ UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
+ ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
+ ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
+}ATOM_COMPONENT_VIDEO_INFO_V21;
+
+#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21
+
+/**************************************************************************/
+//Object table starts here
+typedef struct _ATOM_OBJECT_HEADER
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usDeviceSupport;
+ USHORT usConnectorObjectTableOffset;
+ USHORT usRouterObjectTableOffset;
+ USHORT usEncoderObjectTableOffset;
+ USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
+ USHORT usDisplayPathTableOffset;
+}ATOM_OBJECT_HEADER;
+
+
+typedef struct _ATOM_DISPLAY_OBJECT_PATH
+{
+ USHORT usDeviceTag; //supported device
+ USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
+ USHORT usConnObjectId; //Connector Object ID
+ USHORT usGPUObjectId; //GPU ID
+ USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
+}ATOM_DISPLAY_OBJECT_PATH;
+
+typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
+{
+ UCHAR ucNumOfDispPath;
+ UCHAR ucVersion;
+ UCHAR ucPadding[2];
+ ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
+}ATOM_DISPLAY_OBJECT_PATH_TABLE;
+
+
+typedef struct _ATOM_OBJECT //each object has this structure
+{
+ USHORT usObjectID;
+ USHORT usSrcDstTableOffset;
+ USHORT usRecordOffset; //this pointing to a bunch of records defined below
+ USHORT usReserved;
+}ATOM_OBJECT;
+
+typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure
+{
+ UCHAR ucNumberOfObjects;
+ UCHAR ucPadding[3];
+ ATOM_OBJECT asObjects[1];
+}ATOM_OBJECT_TABLE;
+
+typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
+{
+ UCHAR ucNumberOfSrc;
+ USHORT usSrcObjectID[1];
+ UCHAR ucNumberOfDst;
+ USHORT usDstObjectID[1];
+}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
+
+
+//Related definitions, all records are differnt but they have a commond header
+typedef struct _ATOM_COMMON_RECORD_HEADER
+{
+ UCHAR ucRecordType; //An emun to indicate the record type
+ UCHAR ucRecordSize; //The size of the whole record in byte
+}ATOM_COMMON_RECORD_HEADER;
+
+
+#define ATOM_I2C_RECORD_TYPE 1
+#define ATOM_HPD_INT_RECORD_TYPE 2
+#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3
+#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
+#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
+#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
+#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
+#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
+#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9
+#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10
+#define ATOM_CONNECTOR_CF_RECORD_TYPE 11
+#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
+#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
+#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
+#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
+
+//Must be updated when new record type is added,equal to that record definition!
+#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE
+
+typedef struct _ATOM_I2C_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ ATOM_I2C_ID_CONFIG sucI2cId;
+ UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
+}ATOM_I2C_RECORD;
+
+typedef struct _ATOM_HPD_INT_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
+ UCHAR ucPluggged_PinState;
+}ATOM_HPD_INT_RECORD;
+
+
+typedef struct _ATOM_OUTPUT_PROTECTION_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucProtectionFlag;
+ UCHAR ucReserved;
+}ATOM_OUTPUT_PROTECTION_RECORD;
+
+typedef struct _ATOM_CONNECTOR_DEVICE_TAG
+{
+ ULONG ulACPIDeviceEnum; //Reserved for now
+ USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
+ USHORT usPadding;
+}ATOM_CONNECTOR_DEVICE_TAG;
+
+typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucNumberOfDevice;
+ UCHAR ucReserved;
+ ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
+}ATOM_CONNECTOR_DEVICE_TAG_RECORD;
+
+
+typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucConfigGPIOID;
+ UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
+ UCHAR ucFlowinGPIPID;
+ UCHAR ucExtInGPIPID;
+}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
+
+typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucCTL1GPIO_ID;
+ UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
+ UCHAR ucCTL2GPIO_ID;
+ UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
+ UCHAR ucCTL3GPIO_ID;
+ UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
+ UCHAR ucCTLFPGA_IN_ID;
+ UCHAR ucPadding[3];
+}ATOM_ENCODER_FPGA_CONTROL_RECORD;
+
+typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
+ UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
+}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
+
+typedef struct _ATOM_JTAG_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucTMSGPIO_ID;
+ UCHAR ucTMSGPIOState; //Set to 1 when it's active high
+ UCHAR ucTCKGPIO_ID;
+ UCHAR ucTCKGPIOState; //Set to 1 when it's active high
+ UCHAR ucTDOGPIO_ID;
+ UCHAR ucTDOGPIOState; //Set to 1 when it's active high
+ UCHAR ucTDIGPIO_ID;
+ UCHAR ucTDIGPIOState; //Set to 1 when it's active high
+ UCHAR ucPadding[2];
+}ATOM_JTAG_RECORD;
+
+
+//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
+typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
+{
+ UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
+ UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
+}ATOM_GPIO_PIN_CONTROL_PAIR;
+
+typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucFlags; // Future expnadibility
+ UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
+ ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
+}ATOM_OBJECT_GPIO_CNTL_RECORD;
+
+//Definitions for GPIO pin state
+#define GPIO_PIN_TYPE_INPUT 0x00
+#define GPIO_PIN_TYPE_OUTPUT 0x10
+#define GPIO_PIN_TYPE_HW_CONTROL 0x20
+
+//For GPIO_PIN_TYPE_OUTPUT the following is defined
+#define GPIO_PIN_OUTPUT_STATE_MASK 0x01
+#define GPIO_PIN_OUTPUT_STATE_SHIFT 0
+#define GPIO_PIN_STATE_ACTIVE_LOW 0x0
+#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
+
+typedef struct _ATOM_ENCODER_DVO_CF_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ ULONG ulStrengthControl; // DVOA strength control for CF
+ UCHAR ucPadding[2];
+}ATOM_ENCODER_DVO_CF_RECORD;
+
+// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
+#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
+#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
+
+typedef struct _ATOM_CONNECTOR_CF_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ USHORT usMaxPixClk;
+ UCHAR ucFlowCntlGpioId;
+ UCHAR ucSwapCntlGpioId;
+ UCHAR ucConnectedDvoBundle;
+ UCHAR ucPadding;
+}ATOM_CONNECTOR_CF_RECORD;
+
+typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ ATOM_DTD_FORMAT asTiming;
+}ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
+
+typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
+ UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
+ UCHAR ucReserved;
+}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
+
+
+typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
+ UCHAR ucMuxControlPin;
+ UCHAR ucMuxState[2]; //for alligment purpose
+}ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
+
+typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucMuxType;
+ UCHAR ucMuxControlPin;
+ UCHAR ucMuxState[2]; //for alligment purpose
+}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
+
+// define ucMuxType
+#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
+#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
+
+/**************************************************************************/
+//ASIC voltage data table starts here
+
+typedef struct _ATOM_VOLTAGE_INFO_HEADER
+{
+ USHORT usVDDCBaseLevel; //In number of 50mv unit
+ USHORT usReserved; //For possible extension table offset
+ UCHAR ucNumOfVoltageEntries;
+ UCHAR ucBytesPerVoltageEntry;
+ UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
+ UCHAR ucDefaultVoltageEntry;
+ UCHAR ucVoltageControlI2cLine;
+ UCHAR ucVoltageControlAddress;
+ UCHAR ucVoltageControlOffset;
+}ATOM_VOLTAGE_INFO_HEADER;
+
+typedef struct _ATOM_VOLTAGE_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_VOLTAGE_INFO_HEADER viHeader;
+ UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
+}ATOM_VOLTAGE_INFO;
+
+
+typedef struct _ATOM_VOLTAGE_FORMULA
+{
+ USHORT usVoltageBaseLevel; // In number of 1mv unit
+ USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
+ UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
+ UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
+ UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
+ UCHAR ucReserved;
+ UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
+}ATOM_VOLTAGE_FORMULA;
+
+typedef struct _ATOM_VOLTAGE_CONTROL
+{
+ UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
+ UCHAR ucVoltageControlI2cLine;
+ UCHAR ucVoltageControlAddress;
+ UCHAR ucVoltageControlOffset;
+ USHORT usGpioPin_AIndex; //GPIO_PAD register index
+ UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
+ UCHAR ucReserved;
+}ATOM_VOLTAGE_CONTROL;
+
+// Define ucVoltageControlId
+#define VOLTAGE_CONTROLLED_BY_HW 0x00
+#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F
+#define VOLTAGE_CONTROLLED_BY_GPIO 0x80
+#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage
+#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
+#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage
+#define VOLTAGE_CONTROL_ID_DS4402 0x04
+
+typedef struct _ATOM_VOLTAGE_OBJECT
+{
+ UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
+ UCHAR ucSize; //Size of Object
+ ATOM_VOLTAGE_CONTROL asControl; //describ how to control
+ ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
+}ATOM_VOLTAGE_OBJECT;
+
+typedef struct _ATOM_VOLTAGE_OBJECT_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
+}ATOM_VOLTAGE_OBJECT_INFO;
+
+typedef struct _ATOM_LEAKID_VOLTAGE
+{
+ UCHAR ucLeakageId;
+ UCHAR ucReserved;
+ USHORT usVoltage;
+}ATOM_LEAKID_VOLTAGE;
+
+typedef struct _ATOM_ASIC_PROFILE_VOLTAGE
+{
+ UCHAR ucProfileId;
+ UCHAR ucReserved;
+ USHORT usSize;
+ USHORT usEfuseSpareStartAddr;
+ USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
+ ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
+}ATOM_ASIC_PROFILE_VOLTAGE;
+
+//ucProfileId
+#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
+#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
+#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
+
+typedef struct _ATOM_ASIC_PROFILING_INFO
+{
+ ATOM_COMMON_TABLE_HEADER asHeader;
+ ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
+}ATOM_ASIC_PROFILING_INFO;
+
+typedef struct _ATOM_POWER_SOURCE_OBJECT
+{
+ UCHAR ucPwrSrcId; // Power source
+ UCHAR ucPwrSensorType; // GPIO, I2C or none
+ UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
+ UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
+ UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
+ UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
+ UCHAR ucPwrSensActiveState; // high active or low active
+ UCHAR ucReserve[3]; // reserve
+ USHORT usSensPwr; // in unit of watt
+}ATOM_POWER_SOURCE_OBJECT;
+
+typedef struct _ATOM_POWER_SOURCE_INFO
+{
+ ATOM_COMMON_TABLE_HEADER asHeader;
+ UCHAR asPwrbehave[16];
+ ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
+}ATOM_POWER_SOURCE_INFO;
+
+
+//Define ucPwrSrcId
+#define POWERSOURCE_PCIE_ID1 0x00
+#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01
+#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02
+#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04
+#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08
+
+//define ucPwrSensorId
+#define POWER_SENSOR_ALWAYS 0x00
+#define POWER_SENSOR_GPIO 0x01
+#define POWER_SENSOR_I2C 0x02
+
+/**************************************************************************/
+// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
+//Memory SS Info Table
+//Define Memory Clock SS chip ID
+#define ICS91719 1
+#define ICS91720 2
+
+//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
+typedef struct _ATOM_I2C_DATA_RECORD
+{
+ UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
+ UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
+}ATOM_I2C_DATA_RECORD;
+
+
+//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
+typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
+{
+ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
+ UCHAR ucSSChipID; //SS chip being used
+ UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
+ UCHAR ucNumOfI2CDataRecords; //number of data block
+ ATOM_I2C_DATA_RECORD asI2CData[1];
+}ATOM_I2C_DEVICE_SETUP_INFO;
+
+//==========================================================================================
+typedef struct _ATOM_ASIC_MVDD_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
+}ATOM_ASIC_MVDD_INFO;
+
+//==========================================================================================
+#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO
+
+//==========================================================================================
+/**************************************************************************/
+
+typedef struct _ATOM_ASIC_SS_ASSIGNMENT
+{
+ ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
+ USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
+ USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
+ UCHAR ucClockIndication; //Indicate which clock source needs SS
+ UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
+ UCHAR ucReserved[2];
+}ATOM_ASIC_SS_ASSIGNMENT;
+
+//Define ucSpreadSpectrumType
+#define ASIC_INTERNAL_MEMORY_SS 1
+#define ASIC_INTERNAL_ENGINE_SS 2
+#define ASIC_INTERNAL_UVD_SS 3
+
+typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
+}ATOM_ASIC_INTERNAL_SS_INFO;
+
+//==============================Scratch Pad Definition Portion===============================
+#define ATOM_DEVICE_CONNECT_INFO_DEF 0
+#define ATOM_ROM_LOCATION_DEF 1
+#define ATOM_TV_STANDARD_DEF 2
+#define ATOM_ACTIVE_INFO_DEF 3
+#define ATOM_LCD_INFO_DEF 4
+#define ATOM_DOS_REQ_INFO_DEF 5
+#define ATOM_ACC_CHANGE_INFO_DEF 6
+#define ATOM_DOS_MODE_INFO_DEF 7
+#define ATOM_I2C_CHANNEL_STATUS_DEF 8
+#define ATOM_I2C_CHANNEL_STATUS1_DEF 9
+
+
+// BIOS_0_SCRATCH Definition
+#define ATOM_S0_CRT1_MONO 0x00000001L
+#define ATOM_S0_CRT1_COLOR 0x00000002L
+#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
+
+#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L
+#define ATOM_S0_TV1_SVIDEO_A 0x00000008L
+#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
+
+#define ATOM_S0_CV_A 0x00000010L
+#define ATOM_S0_CV_DIN_A 0x00000020L
+#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
+
+
+#define ATOM_S0_CRT2_MONO 0x00000100L
+#define ATOM_S0_CRT2_COLOR 0x00000200L
+#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
+
+#define ATOM_S0_TV1_COMPOSITE 0x00000400L
+#define ATOM_S0_TV1_SVIDEO 0x00000800L
+#define ATOM_S0_TV1_SCART 0x00004000L
+#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
+
+#define ATOM_S0_CV 0x00001000L
+#define ATOM_S0_CV_DIN 0x00002000L
+#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)
+
+
+#define ATOM_S0_DFP1 0x00010000L
+#define ATOM_S0_DFP2 0x00020000L
+#define ATOM_S0_LCD1 0x00040000L
+#define ATOM_S0_LCD2 0x00080000L
+#define ATOM_S0_TV2 0x00100000L
+#define ATOM_S0_DFP3 0x00200000L
+
+#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with
+ // the FAD/HDP reg access bug. Bit is read by DAL
+
+#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
+#define ATOM_S0_THERMAL_STATE_SHIFT 26
+
+#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
+#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
+
+#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
+#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
+#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
+
+//Byte aligned defintion for BIOS usage
+#define ATOM_S0_CRT1_MONOb0 0x01
+#define ATOM_S0_CRT1_COLORb0 0x02
+#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
+
+#define ATOM_S0_TV1_COMPOSITEb0 0x04
+#define ATOM_S0_TV1_SVIDEOb0 0x08
+#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
+
+#define ATOM_S0_CVb0 0x10
+#define ATOM_S0_CV_DINb0 0x20
+#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
+
+#define ATOM_S0_CRT2_MONOb1 0x01
+#define ATOM_S0_CRT2_COLORb1 0x02
+#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
+
+#define ATOM_S0_TV1_COMPOSITEb1 0x04
+#define ATOM_S0_TV1_SVIDEOb1 0x08
+#define ATOM_S0_TV1_SCARTb1 0x40
+#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
+
+#define ATOM_S0_CVb1 0x10
+#define ATOM_S0_CV_DINb1 0x20
+#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
+
+#define ATOM_S0_DFP1b2 0x01
+#define ATOM_S0_DFP2b2 0x02
+#define ATOM_S0_LCD1b2 0x04
+#define ATOM_S0_LCD2b2 0x08
+#define ATOM_S0_TV2b2 0x10
+#define ATOM_S0_DFP3b2 0x20
+
+#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
+#define ATOM_S0_THERMAL_STATE_SHIFTb3 2
+
+#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
+#define ATOM_S0_LCD1_SHIFT 18
+
+// BIOS_1_SCRATCH Definition
+#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL
+#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L
+
+
+// BIOS_2_SCRATCH Definition
+#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL
+#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
+#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
+
+#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
+#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L
+#define ATOM_S2_TV1_DPMS_STATE 0x00040000L
+#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L
+#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L
+#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L
+#define ATOM_S2_TV2_DPMS_STATE 0x00400000L
+#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L
+#define ATOM_S2_CV_DPMS_STATE 0x01000000L
+#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L
+
+#define ATOM_S2_DEVICE_DPMS_STATE (ATOM_S2_CRT1_DPMS_STATE+ATOM_S2_LCD1_DPMS_STATE+ATOM_S2_TV1_DPMS_STATE+\
+ ATOM_S2_DFP1I_DPMS_STATE+ATOM_S2_CRT2_DPMS_STATE+ATOM_S2_LCD2_DPMS_STATE+\
+ ATOM_S2_TV2_DPMS_STATE+ATOM_S2_DFP1X_DPMS_STATE+ATOM_S2_CV_DPMS_STATE+\
+ ATOM_S2_DFP3_DPMS_STATE)
+
+
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
+
+#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
+
+#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
+#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1
+#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2
+#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3
+#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
+#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
+
+
+//Byte aligned defintion for BIOS usage
+#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
+#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
+#define ATOM_S2_CRT1_DPMS_STATEb2 0x01
+#define ATOM_S2_LCD1_DPMS_STATEb2 0x02
+#define ATOM_S2_TV1_DPMS_STATEb2 0x04
+#define ATOM_S2_DFP1_DPMS_STATEb2 0x08
+#define ATOM_S2_CRT2_DPMS_STATEb2 0x10
+#define ATOM_S2_LCD2_DPMS_STATEb2 0x20
+#define ATOM_S2_TV2_DPMS_STATEb2 0x40
+#define ATOM_S2_DFP2_DPMS_STATEb2 0x80
+#define ATOM_S2_CV_DPMS_STATEb3 0x01
+#define ATOM_S2_DFP3_DPMS_STATEb3 0x02
+
+#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10
+#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20
+#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0
+
+
+// BIOS_3_SCRATCH Definition
+#define ATOM_S3_CRT1_ACTIVE 0x00000001L
+#define ATOM_S3_LCD1_ACTIVE 0x00000002L
+#define ATOM_S3_TV1_ACTIVE 0x00000004L
+#define ATOM_S3_DFP1_ACTIVE 0x00000008L
+#define ATOM_S3_CRT2_ACTIVE 0x00000010L
+#define ATOM_S3_LCD2_ACTIVE 0x00000020L
+#define ATOM_S3_TV2_ACTIVE 0x00000040L
+#define ATOM_S3_DFP2_ACTIVE 0x00000080L
+#define ATOM_S3_CV_ACTIVE 0x00000100L
+#define ATOM_S3_DFP3_ACTIVE 0x00000200L
+
+#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL
+
+#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L
+#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L
+#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L
+#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
+#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
+#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
+#define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L
+#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
+#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
+#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
+
+#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x03FF0000L
+#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
+#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
+#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
+
+//Byte aligned defintion for BIOS usage
+#define ATOM_S3_CRT1_ACTIVEb0 0x01
+#define ATOM_S3_LCD1_ACTIVEb0 0x02
+#define ATOM_S3_TV1_ACTIVEb0 0x04
+#define ATOM_S3_DFP1_ACTIVEb0 0x08
+#define ATOM_S3_CRT2_ACTIVEb0 0x10
+#define ATOM_S3_LCD2_ACTIVEb0 0x20
+#define ATOM_S3_TV2_ACTIVEb0 0x40
+#define ATOM_S3_DFP2_ACTIVEb0 0x80
+#define ATOM_S3_CV_ACTIVEb1 0x01
+#define ATOM_S3_DFP3_ACTIVEb1 0x02
+
+#define ATOM_S3_ACTIVE_CRTC1w0 0x3FF
+
+#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01
+#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02
+#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04
+#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
+#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
+#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
+#define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40
+#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
+#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
+#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
+
+#define ATOM_S3_ACTIVE_CRTC2w1 0x3FF
+
+#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20
+#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
+#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80
+
+// BIOS_4_SCRATCH Definition
+#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
+#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
+#define ATOM_S4_LCD1_REFRESH_SHIFT 8
+
+
+//Byte aligned defintion for BIOS usage
+#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
+#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
+#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
+
+
+// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
+#define ATOM_S5_DOS_REQ_CRT1b0 0x01
+#define ATOM_S5_DOS_REQ_LCD1b0 0x02
+#define ATOM_S5_DOS_REQ_TV1b0 0x04
+#define ATOM_S5_DOS_REQ_DFP1b0 0x08
+#define ATOM_S5_DOS_REQ_CRT2b0 0x10
+#define ATOM_S5_DOS_REQ_LCD2b0 0x20
+#define ATOM_S5_DOS_REQ_TV2b0 0x40
+#define ATOM_S5_DOS_REQ_DFP2b0 0x80
+#define ATOM_S5_DOS_REQ_CVb1 0x01
+#define ATOM_S5_DOS_REQ_DFP3b1 0x02
+
+#define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF
+
+#define ATOM_S5_DOS_REQ_CRT1 0x0001
+#define ATOM_S5_DOS_REQ_LCD1 0x0002
+#define ATOM_S5_DOS_REQ_TV1 0x0004
+#define ATOM_S5_DOS_REQ_DFP1 0x0008
+#define ATOM_S5_DOS_REQ_CRT2 0x0010
+#define ATOM_S5_DOS_REQ_LCD2 0x0020
+#define ATOM_S5_DOS_REQ_TV2 0x0040
+#define ATOM_S5_DOS_REQ_DFP2 0x0080
+#define ATOM_S5_DOS_REQ_CV 0x0100
+#define ATOM_S5_DOS_REQ_DFP3 0x0200
+
+#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
+#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
+#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0
+#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1
+#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
+ (ATOM_S5_DOS_FORCE_CVb3<<8))
+
+// BIOS_6_SCRATCH Definition
+#define ATOM_S6_DEVICE_CHANGE 0x00000001L
+#define ATOM_S6_SCALER_CHANGE 0x00000002L
+#define ATOM_S6_LID_CHANGE 0x00000004L
+#define ATOM_S6_DOCKING_CHANGE 0x00000008L
+#define ATOM_S6_ACC_MODE 0x00000010L
+#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L
+#define ATOM_S6_LID_STATE 0x00000040L
+#define ATOM_S6_DOCK_STATE 0x00000080L
+#define ATOM_S6_CRITICAL_STATE 0x00000100L
+#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L
+#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L
+#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L
+#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
+#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD
+
+#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
+#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
+
+
+#define ATOM_S6_ACC_REQ_CRT1 0x00010000L
+#define ATOM_S6_ACC_REQ_LCD1 0x00020000L
+#define ATOM_S6_ACC_REQ_TV1 0x00040000L
+#define ATOM_S6_ACC_REQ_DFP1 0x00080000L
+#define ATOM_S6_ACC_REQ_CRT2 0x00100000L
+#define ATOM_S6_ACC_REQ_LCD2 0x00200000L
+#define ATOM_S6_ACC_REQ_TV2 0x00400000L
+#define ATOM_S6_ACC_REQ_DFP2 0x00800000L
+#define ATOM_S6_ACC_REQ_CV 0x01000000L
+#define ATOM_S6_ACC_REQ_DFP3 0x02000000L
+
+#define ATOM_S6_ACC_REQ_MASK 0x03FF0000L
+#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L
+#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L
+#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
+#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
+
+//Byte aligned defintion for BIOS usage
+#define ATOM_S6_DEVICE_CHANGEb0 0x01
+#define ATOM_S6_SCALER_CHANGEb0 0x02
+#define ATOM_S6_LID_CHANGEb0 0x04
+#define ATOM_S6_DOCKING_CHANGEb0 0x08
+#define ATOM_S6_ACC_MODEb0 0x10
+#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20
+#define ATOM_S6_LID_STATEb0 0x40
+#define ATOM_S6_DOCK_STATEb0 0x80
+#define ATOM_S6_CRITICAL_STATEb1 0x01
+#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02
+#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04
+#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
+#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10
+#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
+
+#define ATOM_S6_ACC_REQ_CRT1b2 0x01
+#define ATOM_S6_ACC_REQ_LCD1b2 0x02
+#define ATOM_S6_ACC_REQ_TV1b2 0x04
+#define ATOM_S6_ACC_REQ_DFP1b2 0x08
+#define ATOM_S6_ACC_REQ_CRT2b2 0x10
+#define ATOM_S6_ACC_REQ_LCD2b2 0x20
+#define ATOM_S6_ACC_REQ_TV2b2 0x40
+#define ATOM_S6_ACC_REQ_DFP2b2 0x80
+#define ATOM_S6_ACC_REQ_CVb3 0x01
+#define ATOM_S6_ACC_REQ_DFP3b3 0x02
+
+#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
+#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
+#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
+#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40
+#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80
+
+#define ATOM_S6_DEVICE_CHANGE_SHIFT 0
+#define ATOM_S6_SCALER_CHANGE_SHIFT 1
+#define ATOM_S6_LID_CHANGE_SHIFT 2
+#define ATOM_S6_DOCKING_CHANGE_SHIFT 3
+#define ATOM_S6_ACC_MODE_SHIFT 4
+#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5
+#define ATOM_S6_LID_STATE_SHIFT 6
+#define ATOM_S6_DOCK_STATE_SHIFT 7
+#define ATOM_S6_CRITICAL_STATE_SHIFT 8
+#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9
+#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10
+#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
+#define ATOM_S6_REQ_SCALER_SHIFT 12
+#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13
+#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14
+#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15
+#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28
+#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29
+#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
+#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31
+
+// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
+#define ATOM_S7_DOS_MODE_TYPEb0 0x03
+#define ATOM_S7_DOS_MODE_VGAb0 0x00
+#define ATOM_S7_DOS_MODE_VESAb0 0x01
+#define ATOM_S7_DOS_MODE_EXTb0 0x02
+#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
+#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
+#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
+#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
+
+#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
+
+// BIOS_8_SCRATCH Definition
+#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF
+#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000
+
+#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0
+#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16
+
+// BIOS_9_SCRATCH Definition
+#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
+#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF
+#endif
+#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
+#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000
+#endif
+#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
+#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
+#endif
+#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
+#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16
+#endif
+
+
+#define ATOM_FLAG_SET 0x20
+#define ATOM_FLAG_CLEAR 0
+#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
+#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
+
+#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
+
+#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
+
+#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
+
+#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
+
+#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
+
+#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
+#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
+
+#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
+
+#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
+
+#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
+#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
+#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
+
+/****************************************************************************/
+//Portion II: Definitinos only used in Driver
+/****************************************************************************/
+
+// Macros used by driver
+
+#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
+
+#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
+#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
+
+#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
+#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
+
+/****************************************************************************/
+//Portion III: Definitinos only used in VBIOS
+/****************************************************************************/
+#define ATOM_DAC_SRC 0x80
+#define ATOM_SRC_DAC1 0
+#define ATOM_SRC_DAC2 0x80
+
+
+#ifdef UEFI_BUILD
+ #define USHORT UTEMP
+#endif
+
+typedef struct _MEMORY_PLLINIT_PARAMETERS
+{
+ ULONG ulTargetMemoryClock; //In 10Khz unit
+ UCHAR ucAction; //not define yet
+ UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
+ UCHAR ucFbDiv; //FB value
+ UCHAR ucPostDiv; //Post div
+}MEMORY_PLLINIT_PARAMETERS;
+
+#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS
+
+
+#define GPIO_PIN_WRITE 0x01
+#define GPIO_PIN_READ 0x00
+
+typedef struct _GPIO_PIN_CONTROL_PARAMETERS
+{
+ UCHAR ucGPIO_ID; //return value, read from GPIO pins
+ UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
+ UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
+ UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
+}GPIO_PIN_CONTROL_PARAMETERS;
+
+typedef struct _ENABLE_SCALER_PARAMETERS
+{
+ UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
+ UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
+ UCHAR ucPadding[2];
+}ENABLE_SCALER_PARAMETERS;
+#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
+
+//ucEnable:
+#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
+#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
+#define SCALER_ENABLE_2TAP_ALPHA_MODE 2
+#define SCALER_ENABLE_MULTITAP_MODE 3
+
+typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
+{
+ ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
+ UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
+ UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
+ UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
+ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
+}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
+
+typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
+{
+ ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
+ ENABLE_CRTC_PARAMETERS sReserved;
+}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
+
+typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
+{
+ USHORT usHight; // Image Hight
+ USHORT usWidth; // Image Width
+ UCHAR ucSurface; // Surface 1 or 2
+ UCHAR ucPadding[3];
+}ENABLE_GRAPH_SURFACE_PARAMETERS;
+
+typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
+{
+ ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
+ ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
+}ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
+
+typedef struct _MEMORY_CLEAN_UP_PARAMETERS
+{
+ USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address
+ USHORT usMemorySize; //8Kb blocks aligned
+}MEMORY_CLEAN_UP_PARAMETERS;
+#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
+
+typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
+{
+ USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
+ USHORT usY_Size;
+}GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
+
+typedef struct _INDIRECT_IO_ACCESS
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR IOAccessSequence[256];
+} INDIRECT_IO_ACCESS;
+
+#define INDIRECT_READ 0x00
+#define INDIRECT_WRITE 0x80
+
+#define INDIRECT_IO_MM 0
+#define INDIRECT_IO_PLL 1
+#define INDIRECT_IO_MC 2
+#define INDIRECT_IO_PCIE 3
+#define INDIRECT_IO_PCIEP 4
+
+#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ
+#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE
+#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ
+#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE
+#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ
+#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE
+#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ
+#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE
+
+typedef struct _ATOM_OEM_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
+}ATOM_OEM_INFO;
+
+typedef struct _ATOM_TV_MODE
+{
+ UCHAR ucVMode_Num; //Video mode number
+ UCHAR ucTV_Mode_Num; //Internal TV mode number
+}ATOM_TV_MODE;
+
+typedef struct _ATOM_BIOS_INT_TVSTD_MODE
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
+ USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
+ USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
+ USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
+ USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
+}ATOM_BIOS_INT_TVSTD_MODE;
+
+
+typedef struct _ATOM_TV_MODE_SCALER_PTR
+{
+ USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
+ USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
+ UCHAR ucTV_Mode_Num;
+}ATOM_TV_MODE_SCALER_PTR;
+
+typedef struct _ATOM_STANDARD_VESA_TIMING
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_MODE_TIMING aModeTimings[16]; // 16 is not the real array number, just for initial allocation
+}ATOM_STANDARD_VESA_TIMING;
+
+
+typedef struct _ATOM_STD_FORMAT
+{
+ USHORT usSTD_HDisp;
+ USHORT usSTD_VDisp;
+ USHORT usSTD_RefreshRate;
+ USHORT usReserved;
+}ATOM_STD_FORMAT;
+
+typedef struct _ATOM_VESA_TO_EXTENDED_MODE
+{
+ USHORT usVESA_ModeNumber;
+ USHORT usExtendedModeNumber;
+}ATOM_VESA_TO_EXTENDED_MODE;
+
+typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
+}ATOM_VESA_TO_INTENAL_MODE_LUT;
+
+/*************** ATOM Memory Related Data Structure ***********************/
+typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
+ UCHAR ucMemoryType;
+ UCHAR ucMemoryVendor;
+ UCHAR ucAdjMCId;
+ UCHAR ucDynClkId;
+ ULONG ulDllResetClkRange;
+}ATOM_MEMORY_VENDOR_BLOCK;
+
+
+typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
+ ULONG ulMemClockRange:24;
+ ULONG ucMemBlkId:8;
+}ATOM_MEMORY_SETTING_ID_CONFIG;
+
+typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
+{
+ ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
+ ULONG ulAccess;
+}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
+
+
+typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
+ ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
+ ULONG aulMemData[1];
+}ATOM_MEMORY_SETTING_DATA_BLOCK;
+
+
+typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
+ USHORT usRegIndex; // MC register index
+ UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
+}ATOM_INIT_REG_INDEX_FORMAT;
+
+
+typedef struct _ATOM_INIT_REG_BLOCK{
+ USHORT usRegIndexTblSize; //size of asRegIndexBuf
+ USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
+ ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
+ ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
+}ATOM_INIT_REG_BLOCK;
+
+#define END_OF_REG_INDEX_BLOCK 0x0ffff
+#define END_OF_REG_DATA_BLOCK 0x00000000
+#define ATOM_INIT_REG_MASK_FLAG 0x80
+#define CLOCK_RANGE_HIGHEST 0x00ffffff
+
+#define VALUE_DWORD SIZEOF ULONG
+#define VALUE_SAME_AS_ABOVE 0
+#define VALUE_MASK_DWORD 0x84
+
+typedef struct _ATOM_MC_INIT_PARAM_TABLE
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usAdjustARB_SEQDataOffset;
+ USHORT usMCInitMemTypeTblOffset;
+ USHORT usMCInitCommonTblOffset;
+ USHORT usMCInitPowerDownTblOffset;
+ ULONG ulARB_SEQDataBuf[32];
+ ATOM_INIT_REG_BLOCK asMCInitMemType;
+ ATOM_INIT_REG_BLOCK asMCInitCommon;
+}ATOM_MC_INIT_PARAM_TABLE;
+
+
+#define _4Mx16 0x2
+#define _4Mx32 0x3
+#define _8Mx16 0x12
+#define _8Mx32 0x13
+#define _16Mx16 0x22
+#define _16Mx32 0x23
+#define _32Mx16 0x32
+
+#define SAMSUNG 0x1
+#define INFINEON 0x2
+#define ELPIDA 0x3
+#define ETRON 0x4
+#define NANYA 0x5
+#define HYNIX 0x6
+#define MOSEL 0x7
+#define WINBOND 0x8
+#define ESMT 0x9
+#define MICRO 0xF
+
+#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
+
+#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
+typedef struct _ATOM_VRAM_MODULE_V1
+{
+ ULONG ulReserved;
+ USHORT usEMRSValue;
+ USHORT usMRSValue;
+ USHORT usReserved;
+ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
+ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
+ UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
+ UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
+ UCHAR ucRow; // Number of Row,in power of 2;
+ UCHAR ucColumn; // Number of Column,in power of 2;
+ UCHAR ucBank; // Nunber of Bank;
+ UCHAR ucRank; // Number of Rank, in power of 2
+ UCHAR ucChannelNum; // Number of channel;
+ UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
+ UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
+ UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
+ UCHAR ucReserved[2];
+}ATOM_VRAM_MODULE_V1;
+
+
+typedef struct _ATOM_VRAM_MODULE_V2
+{
+ ULONG ulReserved;
+ ULONG ulFlags; // To enable/disable functionalities based on memory type
+ ULONG ulEngineClock; // Override of default engine clock for particular memory type
+ ULONG ulMemoryClock; // Override of default memory clock for particular memory type
+ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
+ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
+ USHORT usEMRSValue;
+ USHORT usMRSValue;
+ USHORT usReserved;
+ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
+ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
+ UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
+ UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
+ UCHAR ucRow; // Number of Row,in power of 2;
+ UCHAR ucColumn; // Number of Column,in power of 2;
+ UCHAR ucBank; // Nunber of Bank;
+ UCHAR ucRank; // Number of Rank, in power of 2
+ UCHAR ucChannelNum; // Number of channel;
+ UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
+ UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
+ UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
+ UCHAR ucRefreshRateFactor;
+ UCHAR ucReserved[3];
+}ATOM_VRAM_MODULE_V2;
+
+
+typedef struct _ATOM_MEMORY_TIMING_FORMAT
+{
+ ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
+ USHORT usMRS; // mode register
+ USHORT usEMRS; // extended mode register
+ UCHAR ucCL; // CAS latency
+ UCHAR ucWL; // WRITE Latency
+ UCHAR uctRAS; // tRAS
+ UCHAR uctRC; // tRC
+ UCHAR uctRFC; // tRFC
+ UCHAR uctRCDR; // tRCDR
+ UCHAR uctRCDW; // tRCDW
+ UCHAR uctRP; // tRP
+ UCHAR uctRRD; // tRRD
+ UCHAR uctWR; // tWR
+ UCHAR uctWTR; // tWTR
+ UCHAR uctPDIX; // tPDIX
+ UCHAR uctFAW; // tFAW
+ UCHAR uctAOND; // tAOND
+ UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
+ UCHAR ucReserved; //
+}ATOM_MEMORY_TIMING_FORMAT;
+
+#define MEM_TIMING_FLAG_APP_MODE 0x01 // =0 mid clock range =1 high clock range
+
+typedef struct _ATOM_MEMORY_FORMAT
+{
+ ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
+ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
+ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
+ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
+ UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
+ UCHAR ucRow; // Number of Row,in power of 2;
+ UCHAR ucColumn; // Number of Column,in power of 2;
+ UCHAR ucBank; // Nunber of Bank;
+ UCHAR ucRank; // Number of Rank, in power of 2
+ UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
+ UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
+ UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
+ UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
+ UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
+ UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
+ ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock
+}ATOM_MEMORY_FORMAT;
+
+
+typedef struct _ATOM_VRAM_MODULE_V3
+{
+ ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
+ USHORT usSize; // size of ATOM_VRAM_MODULE_V3
+ USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
+ USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
+ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
+ UCHAR ucChannelNum; // board dependent parameter:Number of channel;
+ UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
+ UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
+ UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
+ UCHAR ucFlag; // To enable/disable functionalities based on memory type
+ ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
+}ATOM_VRAM_MODULE_V3;
+
+//ATOM_VRAM_MODULE_V3.ucFlag
+#define Mx_FLAG_RDBI_ENABLE 0x01
+#define Mx_FLAG_WDBI_ENABLE 0x02
+#define Mx_FLAG_DQ_QS_AUTO_CALI 0x04
+#define Mx_FLAG_STROBE_SINGLE_END 0x08
+#define Mx_FLAG_DIS_MEM_TRAINING 0x10
+
+//ATOM_VRAM_MODULE_V3.ucNPL_RT
+#define NPL_RT_MASK 0x0f
+#define BATTERY_ODT_MASK 0xc0
+
+#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
+
+typedef struct _ATOM_VRAM_INFO_V2
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR ucNumOfVRAMModule;
+ ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
+}ATOM_VRAM_INFO_V2;
+
+typedef struct _ATOM_VRAM_INFO_V3
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
+ USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
+ USHORT usRerseved;
+ UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
+ UCHAR ucNumOfVRAMModule;
+ ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
+ ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
+ // ATOM_INIT_REG_BLOCK aMemAdjust;
+}ATOM_VRAM_INFO_V3;
+
+#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
+
+typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
+}ATOM_VRAM_GPIO_DETECTION_INFO;
+
+
+typedef struct _ATOM_MEMORY_TRAINING_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR ucTrainingLoop;
+ UCHAR ucReserved[3];
+ ATOM_INIT_REG_BLOCK asMemTrainingSetting;
+}ATOM_MEMORY_TRAINING_INFO;
+
+
+typedef struct SW_I2C_CNTL_DATA_PARAMETERS
+{
+ UCHAR ucControl;
+ UCHAR ucData;
+ UCHAR ucSatus;
+ UCHAR ucTemp;
+} SW_I2C_CNTL_DATA_PARAMETERS;
+
+#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS
+
+typedef struct _SW_I2C_IO_DATA_PARAMETERS
+{
+ USHORT GPIO_Info;
+ UCHAR ucAct;
+ UCHAR ucData;
+ } SW_I2C_IO_DATA_PARAMETERS;
+
+#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS
+
+/****************************SW I2C CNTL DEFINITIONS**********************/
+#define SW_I2C_IO_RESET 0
+#define SW_I2C_IO_GET 1
+#define SW_I2C_IO_DRIVE 2
+#define SW_I2C_IO_SET 3
+#define SW_I2C_IO_START 4
+
+#define SW_I2C_IO_CLOCK 0
+#define SW_I2C_IO_DATA 0x80
+
+#define SW_I2C_IO_ZERO 0
+#define SW_I2C_IO_ONE 0x100
+
+#define SW_I2C_CNTL_READ 0
+#define SW_I2C_CNTL_WRITE 1
+#define SW_I2C_CNTL_START 2
+#define SW_I2C_CNTL_STOP 3
+#define SW_I2C_CNTL_OPEN 4
+#define SW_I2C_CNTL_CLOSE 5
+#define SW_I2C_CNTL_WRITE1BIT 6
+
+//==============================VESA definition Portion===============================
+#define VESA_OEM_PRODUCT_REV '01.00'
+#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support
+#define VESA_MODE_WIN_ATTRIBUTE 7
+#define VESA_WIN_SIZE 64
+
+typedef struct _PTR_32_BIT_STRUCTURE
+{
+ USHORT Offset16;
+ USHORT Segment16;
+} PTR_32_BIT_STRUCTURE;
+
+typedef union _PTR_32_BIT_UNION
+{
+ PTR_32_BIT_STRUCTURE SegmentOffset;
+ ULONG Ptr32_Bit;
+} PTR_32_BIT_UNION;
+
+typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
+{
+ UCHAR VbeSignature[4];
+ USHORT VbeVersion;
+ PTR_32_BIT_UNION OemStringPtr;
+ UCHAR Capabilities[4];
+ PTR_32_BIT_UNION VideoModePtr;
+ USHORT TotalMemory;
+} VBE_1_2_INFO_BLOCK_UPDATABLE;
+
+
+typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
+{
+ VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
+ USHORT OemSoftRev;
+ PTR_32_BIT_UNION OemVendorNamePtr;
+ PTR_32_BIT_UNION OemProductNamePtr;
+ PTR_32_BIT_UNION OemProductRevPtr;
+} VBE_2_0_INFO_BLOCK_UPDATABLE;
+
+typedef union _VBE_VERSION_UNION
+{
+ VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
+ VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
+} VBE_VERSION_UNION;
+
+typedef struct _VBE_INFO_BLOCK
+{
+ VBE_VERSION_UNION UpdatableVBE_Info;
+ UCHAR Reserved[222];
+ UCHAR OemData[256];
+} VBE_INFO_BLOCK;
+
+typedef struct _VBE_FP_INFO
+{
+ USHORT HSize;
+ USHORT VSize;
+ USHORT FPType;
+ UCHAR RedBPP;
+ UCHAR GreenBPP;
+ UCHAR BlueBPP;
+ UCHAR ReservedBPP;
+ ULONG RsvdOffScrnMemSize;
+ ULONG RsvdOffScrnMEmPtr;
+ UCHAR Reserved[14];
+} VBE_FP_INFO;
+
+typedef struct _VESA_MODE_INFO_BLOCK
+{
+// Mandatory information for all VBE revisions
+ USHORT ModeAttributes; // dw ? ; mode attributes
+ UCHAR WinAAttributes; // db ? ; window A attributes
+ UCHAR WinBAttributes; // db ? ; window B attributes
+ USHORT WinGranularity; // dw ? ; window granularity
+ USHORT WinSize; // dw ? ; window size
+ USHORT WinASegment; // dw ? ; window A start segment
+ USHORT WinBSegment; // dw ? ; window B start segment
+ ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
+ USHORT BytesPerScanLine;// dw ? ; bytes per scan line
+
+//; Mandatory information for VBE 1.2 and above
+ USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
+ USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
+ UCHAR XCharSize; // db ? ; character cell width in pixels
+ UCHAR YCharSize; // db ? ; character cell height in pixels
+ UCHAR NumberOfPlanes; // db ? ; number of memory planes
+ UCHAR BitsPerPixel; // db ? ; bits per pixel
+ UCHAR NumberOfBanks; // db ? ; number of banks
+ UCHAR MemoryModel; // db ? ; memory model type
+ UCHAR BankSize; // db ? ; bank size in KB
+ UCHAR NumberOfImagePages;// db ? ; number of images
+ UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
+
+//; Direct Color fields(required for direct/6 and YUV/7 memory models)
+ UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
+ UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
+ UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
+ UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
+ UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
+ UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
+ UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
+ UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
+ UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
+
+//; Mandatory information for VBE 2.0 and above
+ ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
+ ULONG Reserved_1; // dd 0 ; reserved - always set to 0
+ USHORT Reserved_2; // dw 0 ; reserved - always set to 0
+
+//; Mandatory information for VBE 3.0 and above
+ USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
+ UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
+ UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
+ UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
+ UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
+ UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
+ UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
+ UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
+ UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
+ UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
+ UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
+ ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
+ UCHAR Reserved; // db 190 dup (0)
+} VESA_MODE_INFO_BLOCK;
+
+// BIOS function CALLS
+#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code
+#define ATOM_BIOS_FUNCTION_COP_MODE 0x00
+#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04
+#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05
+#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06
+#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B
+#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E
+#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F
+#define ATOM_BIOS_FUNCTION_STV_STD 0x16
+#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17
+#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18
+
+#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82
+#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83
+#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84
+#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A
+#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B
+#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80
+#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80
+
+#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D
+#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E
+#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F
+#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03
+#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
+#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state
+#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state
+#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85
+#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
+#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported
+
+
+#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS
+#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01
+#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02
+#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.
+#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY
+#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND
+#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF
+#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
+
+#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L
+#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L
+#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL
+
+// structure used for VBIOS only
+
+//DispOutInfoTable
+typedef struct _ASIC_TRANSMITTER_INFO
+{
+ USHORT usTransmitterObjId;
+ USHORT usSupportDevice;
+ UCHAR ucTransmitterCmdTblId;
+ UCHAR ucConfig;
+ UCHAR ucEncoderID; //available 1st encoder ( default )
+ UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
+ UCHAR uc2ndEncoderID;
+ UCHAR ucReserved;
+}ASIC_TRANSMITTER_INFO;
+
+typedef struct _ASIC_ENCODER_INFO
+{
+ UCHAR ucEncoderID;
+ UCHAR ucEncoderConfig;
+ USHORT usEncoderCmdTblId;
+}ASIC_ENCODER_INFO;
+
+typedef struct _ATOM_DISP_OUT_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT ptrTransmitterInfo;
+ USHORT ptrEncoderInfo;
+ ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
+ ASIC_ENCODER_INFO asEncoderInfo[1];
+}ATOM_DISP_OUT_INFO;
+
+// DispDevicePriorityInfo
+typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT asDevicePriority[16];
+}ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
+
+//ProcessAuxChannelTransactionTable
+typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
+{
+ USHORT lpAuxRequest;
+ USHORT lpDataOut;
+ UCHAR ucChannelID;
+ union
+ {
+ UCHAR ucReplyStatus;
+ UCHAR ucDelay;
+ };
+ UCHAR ucDataOutLen;
+ UCHAR ucReserved;
+}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
+
+#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
+
+//GetSinkType
+
+typedef struct _DP_ENCODER_SERVICE_PARAMETERS
+{
+ USHORT ucLinkClock;
+ union
+ {
+ UCHAR ucConfig; // for DP training command
+ UCHAR ucI2cId; // use for GET_SINK_TYPE command
+ };
+ UCHAR ucAction;
+ UCHAR ucStatus;
+ UCHAR ucLaneNum;
+ UCHAR ucReserved[2];
+}DP_ENCODER_SERVICE_PARAMETERS;
+
+// ucAction
+#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
+#define ATOM_DP_ACTION_TRAINING_START 0x02
+#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03
+#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04
+#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05
+#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06
+
+// ucConfig
+#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03
+#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00
+#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01
+#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02
+#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04
+#define ATOM_DP_CONFIG_LINK_A 0x00
+#define ATOM_DP_CONFIG_LINK_B 0x04
+
+#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+
+// DP_TRAINING_TABLE
+#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
+#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
+#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 )
+#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 )
+#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)
+#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)
+#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)
+#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)
+#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
+#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
+#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
+#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
+
+
+/****************************************************************************/
+//Portion VI: Definitinos being oboselete
+/****************************************************************************/
+
+//==========================================================================================
+//Remove the definitions below when driver is ready!
+typedef struct _ATOM_DAC_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usMaxFrequency; // in 10kHz unit
+ USHORT usReserved;
+}ATOM_DAC_INFO;
+
+
+typedef struct _COMPASSIONATE_DATA
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+
+ //============================== DAC1 portion
+ UCHAR ucDAC1_BG_Adjustment;
+ UCHAR ucDAC1_DAC_Adjustment;
+ USHORT usDAC1_FORCE_Data;
+ //============================== DAC2 portion
+ UCHAR ucDAC2_CRT2_BG_Adjustment;
+ UCHAR ucDAC2_CRT2_DAC_Adjustment;
+ USHORT usDAC2_CRT2_FORCE_Data;
+ USHORT usDAC2_CRT2_MUX_RegisterIndex;
+ UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
+ UCHAR ucDAC2_NTSC_BG_Adjustment;
+ UCHAR ucDAC2_NTSC_DAC_Adjustment;
+ USHORT usDAC2_TV1_FORCE_Data;
+ USHORT usDAC2_TV1_MUX_RegisterIndex;
+ UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
+ UCHAR ucDAC2_CV_BG_Adjustment;
+ UCHAR ucDAC2_CV_DAC_Adjustment;
+ USHORT usDAC2_CV_FORCE_Data;
+ USHORT usDAC2_CV_MUX_RegisterIndex;
+ UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
+ UCHAR ucDAC2_PAL_BG_Adjustment;
+ UCHAR ucDAC2_PAL_DAC_Adjustment;
+ USHORT usDAC2_TV2_FORCE_Data;
+}COMPASSIONATE_DATA;
+
+/****************************Supported Device Info Table Definitions**********************/
+// ucConnectInfo:
+// [7:4] - connector type
+// = 1 - VGA connector
+// = 2 - DVI-I
+// = 3 - DVI-D
+// = 4 - DVI-A
+// = 5 - SVIDEO
+// = 6 - COMPOSITE
+// = 7 - LVDS
+// = 8 - DIGITAL LINK
+// = 9 - SCART
+// = 0xA - HDMI_type A
+// = 0xB - HDMI_type B
+// = 0xE - Special case1 (DVI+DIN)
+// Others=TBD
+// [3:0] - DAC Associated
+// = 0 - no DAC
+// = 1 - DACA
+// = 2 - DACB
+// = 3 - External DAC
+// Others=TBD
+//
+
+typedef struct _ATOM_CONNECTOR_INFO
+{
+ UCHAR bfAssociatedDAC:4;
+ UCHAR bfConnectorType:4;
+}ATOM_CONNECTOR_INFO;
+
+typedef union _ATOM_CONNECTOR_INFO_ACCESS
+{
+ ATOM_CONNECTOR_INFO sbfAccess;
+ UCHAR ucAccess;
+}ATOM_CONNECTOR_INFO_ACCESS;
+
+typedef struct _ATOM_CONNECTOR_INFO_I2C
+{
+ ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
+ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
+}ATOM_CONNECTOR_INFO_I2C;
+
+
+typedef struct _ATOM_SUPPORTED_DEVICES_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usDeviceSupport;
+ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
+}ATOM_SUPPORTED_DEVICES_INFO;
+
+#define NO_INT_SRC_MAPPED 0xFF
+
+typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
+{
+ UCHAR ucIntSrcBitmap;
+}ATOM_CONNECTOR_INC_SRC_BITMAP;
+
+typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usDeviceSupport;
+ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
+ ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
+}ATOM_SUPPORTED_DEVICES_INFO_2;
+
+typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usDeviceSupport;
+ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
+ ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
+}ATOM_SUPPORTED_DEVICES_INFO_2d1;
+
+#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
+
+
+
+typedef struct _ATOM_MISC_CONTROL_INFO
+{
+ USHORT usFrequency;
+ UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
+ UCHAR ucPLL_DutyCycle; // PLL duty cycle control
+ UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
+ UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
+}ATOM_MISC_CONTROL_INFO;
+
+
+#define ATOM_MAX_MISC_INFO 4
+
+typedef struct _ATOM_TMDS_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usMaxFrequency; // in 10Khz
+ ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
+}ATOM_TMDS_INFO;
+
+
+typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
+{
+ UCHAR ucTVStandard; //Same as TV standards defined above,
+ UCHAR ucPadding[1];
+}ATOM_ENCODER_ANALOG_ATTRIBUTE;
+
+typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
+{
+ UCHAR ucAttribute; //Same as other digital encoder attributes defined above
+ UCHAR ucPadding[1];
+}ATOM_ENCODER_DIGITAL_ATTRIBUTE;
+
+typedef union _ATOM_ENCODER_ATTRIBUTE
+{
+ ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
+ ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
+}ATOM_ENCODER_ATTRIBUTE;
+
+
+typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
+{
+ USHORT usPixelClock;
+ USHORT usEncoderID;
+ UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
+ UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
+ ATOM_ENCODER_ATTRIBUTE usDevAttr;
+}DVO_ENCODER_CONTROL_PARAMETERS;
+
+typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
+{
+ DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
+ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
+}DVO_ENCODER_CONTROL_PS_ALLOCATION;
+
+
+#define ATOM_XTMDS_ASIC_SI164_ID 1
+#define ATOM_XTMDS_ASIC_SI178_ID 2
+#define ATOM_XTMDS_ASIC_TFP513_ID 3
+#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
+#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002
+#define ATOM_XTMDS_MVPU_FPGA 0x00000004
+
+
+typedef struct _ATOM_XTMDS_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usSingleLinkMaxFrequency;
+ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip
+ UCHAR ucXtransimitterID;
+ UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
+ UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
+ // due to design. This ID is used to alert driver that the sequence is not "standard"!
+ UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
+ UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
+}ATOM_XTMDS_INFO;
+
+typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
+{
+ UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
+ UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
+ UCHAR ucPadding[2];
+}DFP_DPMS_STATUS_CHANGE_PARAMETERS;
+
+/****************************Legacy Power Play Table Definitions **********************/
+
+//Definitions for ulPowerPlayMiscInfo
+#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L
+#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L
+#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L
+
+#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L
+#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L
+
+#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L
+
+#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L
+#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L
+#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
+
+#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L
+#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L
+#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L
+#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L
+#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L
+#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
+#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L
+
+#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L
+#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L
+#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L
+#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L
+#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L
+
+#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
+#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20
+
+#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L
+#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L
+#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L
+#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic
+#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic
+#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
+
+#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
+#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28
+#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
+
+#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L
+#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L
+#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L
+#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L
+#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L
+#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L
+#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
+ //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
+#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L
+#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L
+#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
+
+//ucTableFormatRevision=1
+//ucTableContentRevision=1
+typedef struct _ATOM_POWERMODE_INFO
+{
+ ULONG ulMiscInfo; //The power level should be arranged in ascending order
+ ULONG ulReserved1; // must set to 0
+ ULONG ulReserved2; // must set to 0
+ USHORT usEngineClock;
+ USHORT usMemoryClock;
+ UCHAR ucVoltageDropIndex; // index to GPIO table
+ UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
+ UCHAR ucMinTemperature;
+ UCHAR ucMaxTemperature;
+ UCHAR ucNumPciELanes; // number of PCIE lanes
+}ATOM_POWERMODE_INFO;
+
+//ucTableFormatRevision=2
+//ucTableContentRevision=1
+typedef struct _ATOM_POWERMODE_INFO_V2
+{
+ ULONG ulMiscInfo; //The power level should be arranged in ascending order
+ ULONG ulMiscInfo2;
+ ULONG ulEngineClock;
+ ULONG ulMemoryClock;
+ UCHAR ucVoltageDropIndex; // index to GPIO table
+ UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
+ UCHAR ucMinTemperature;
+ UCHAR ucMaxTemperature;
+ UCHAR ucNumPciELanes; // number of PCIE lanes
+}ATOM_POWERMODE_INFO_V2;
+
+//ucTableFormatRevision=2
+//ucTableContentRevision=2
+typedef struct _ATOM_POWERMODE_INFO_V3
+{
+ ULONG ulMiscInfo; //The power level should be arranged in ascending order
+ ULONG ulMiscInfo2;
+ ULONG ulEngineClock;
+ ULONG ulMemoryClock;
+ UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
+ UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
+ UCHAR ucMinTemperature;
+ UCHAR ucMaxTemperature;
+ UCHAR ucNumPciELanes; // number of PCIE lanes
+ UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
+}ATOM_POWERMODE_INFO_V3;
+
+
+#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
+
+#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01
+#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02
+
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog
+
+
+typedef struct _ATOM_POWERPLAY_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR ucOverdriveThermalController;
+ UCHAR ucOverdriveI2cLine;
+ UCHAR ucOverdriveIntBitmap;
+ UCHAR ucOverdriveControllerAddress;
+ UCHAR ucSizeOfPowerModeEntry;
+ UCHAR ucNumOfPowerModeEntries;
+ ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
+}ATOM_POWERPLAY_INFO;
+
+typedef struct _ATOM_POWERPLAY_INFO_V2
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR ucOverdriveThermalController;
+ UCHAR ucOverdriveI2cLine;
+ UCHAR ucOverdriveIntBitmap;
+ UCHAR ucOverdriveControllerAddress;
+ UCHAR ucSizeOfPowerModeEntry;
+ UCHAR ucNumOfPowerModeEntries;
+ ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
+}ATOM_POWERPLAY_INFO_V2;
+
+typedef struct _ATOM_POWERPLAY_INFO_V3
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR ucOverdriveThermalController;
+ UCHAR ucOverdriveI2cLine;
+ UCHAR ucOverdriveIntBitmap;
+ UCHAR ucOverdriveControllerAddress;
+ UCHAR ucSizeOfPowerModeEntry;
+ UCHAR ucNumOfPowerModeEntries;
+ ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
+}ATOM_POWERPLAY_INFO_V3;
+
+
+
+/**************************************************************************/
+
+
+// Following definitions are for compatiblity issue in different SW components.
+#define ATOM_MASTER_DATA_TABLE_REVISION 0x01
+#define Object_Info Object_Header
+#define AdjustARB_SEQ MC_InitParameter
+#define VRAM_GPIO_DetectionInfo VoltageObjectInfo
+#define ASIC_VDDCI_Info ASIC_ProfilingInfo
+#define ASIC_MVDDQ_Info MemoryTrainingInfo
+#define SS_Info PPLL_SS_Info
+#define ASIC_MVDDC_Info ASIC_InternalSS_Info
+#define DispDevicePriorityInfo SaveRestoreInfo
+#define DispOutInfo TV_VideoMode
+
+
+#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE
+#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE
+
+#define ATOM_S3_SCALER2_ACTIVE_H 0x00004000L
+#define ATOM_S3_SCALER2_ACTIVE_V 0x00008000L
+#define ATOM_S6_REQ_SCALER2_H 0x00004000L
+#define ATOM_S6_REQ_SCALER2_V 0x00008000L
+
+#define ATOM_S3_SCALER1_ACTIVE_H 0x00001000L
+#define ATOM_S3_SCALER1_ACTIVE_V 0x00002000L
+
+#define ATOM_S6_REQ_SCALER1_H ATOM_S6_REQ_LCD_EXPANSION_FULL
+#define ATOM_S6_REQ_SCALER1_V ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO
+
+//New device naming, remove them when both DAL/VBIOS is ready
+#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
+#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
+
+#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
+#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
+
+#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS
+#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT
+#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT
+
+#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX
+#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX
+
+#define ATOM_DEVICE_DFP2I_INDEX 0x00000009
+#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)
+
+#define ATOM_S0_DFP1I ATOM_S0_DFP1
+#define ATOM_S0_DFP1X ATOM_S0_DFP2
+
+#define ATOM_S0_DFP2I 0x00200000L
+#define ATOM_S0_DFP2Ib2 0x20
+
+#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE
+#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE
+
+#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L
+#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02
+
+#define ATOM_S3_DFP2I_ACTIVEb1 0x02
+
+#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE
+#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE
+
+#define ATOM_S3_DFP2I_ACTIVE 0x00000200L
+
+#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE
+#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE
+#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L
+
+#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02
+#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02
+
+#define ATOM_S5_DOS_REQ_DFP2I 0x0200
+#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1
+#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2
+
+#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02
+#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L
+
+#define TMDS1XEncoderControl DVOEncoderControl
+#define DFP1XOutputControl DVOOutputControl
+
+#define ExternalDFPOutputControl DFP1XOutputControl
+#define EnableExternalTMDS_Encoder TMDS1XEncoderControl
+
+#define DFP1IOutputControl TMDSAOutputControl
+#define DFP2IOutputControl LVTMAOutputControl
+
+#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
+#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
+
+#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
+#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
+
+#define ucDac1Standard ucDacStandard
+#define ucDac2Standard ucDacStandard
+
+#define TMDS1EncoderControl TMDSAEncoderControl
+#define TMDS2EncoderControl LVTMAEncoderControl
+
+#define DFP1OutputControl TMDSAOutputControl
+#define DFP2OutputControl LVTMAOutputControl
+#define CRT1OutputControl DAC1OutputControl
+#define CRT2OutputControl DAC2OutputControl
+
+//These two lines will be removed for sure in a few days, will follow up with Michael V.
+#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
+#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
+
+/*********************************************************************************/
+
+//==========================================================================================
+
+#pragma pack() // BIOS data must use byte aligment
+
+#endif /* _ATOMBIOS_H */
diff --git a/src/AtomBios/includes/regsdef.h b/src/AtomBios/includes/regsdef.h
new file mode 100644
index 0000000..e557ac0
--- /dev/null
+++ b/src/AtomBios/includes/regsdef.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+//This is a dummy file used by driver-parser during compilation.
+//Without this file, compatibility will be broken among ASICs and BIOs vs. driver
+//James H. Apr. 22/03
diff --git a/src/Makefile.am b/src/Makefile.am
index ff1e225..bcc6637 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -32,6 +32,20 @@ R128_DRI_SRCS = r128_dri.c
RADEON_DRI_SRCS = radeon_dri.c
endif
+RADEON_ATOMBIOS_SOURCES = AtomBios/CD_Operations.c\
+ AtomBios/Decoder.c\
+ AtomBios/hwserv_drv.c \
+ AtomBios/includes/atombios.h \
+ AtomBios/includes/CD_binding.h \
+ AtomBios/includes/CD_Common_Types.h \
+ AtomBios/includes/CD_Definitions.h \
+ AtomBios/includes/CD_hw_services.h \
+ AtomBios/includes/CD_Opcodes.h \
+ AtomBios/includes/CD_Structs.h \
+ AtomBios/includes/Decoder.h \
+ AtomBios/includes/regsdef.h
+
+
if ATIMISC_CPIO
ATIMISC_CPIO_SOURCES = ativga.c ativgaio.c atibank.c atiwonder.c atiwonderio.c
endif
@@ -45,7 +59,8 @@ ATIMISC_EXA_SOURCES = atimach64exa.c
RADEON_EXA_SOURCES = radeon_exa.c
endif
-AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@
+AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER
+INCLUDES = -I$(srcdir)/AtomBios/includes
ati_drv_la_LTLIBRARIES = ati_drv.la
ati_drv_la_LDFLAGS = -module -avoid-version
@@ -85,7 +100,8 @@ radeon_drv_la_SOURCES = \
radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \
radeon_vip.c radeon_misc.c radeon_probe.c radeon_display.c \
radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \
- $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES)
+ $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c\
+ $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c
theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la
theatre_detect_drv_la_LDFLAGS = -module -avoid-version
diff --git a/src/avivo_reg.h b/src/avivo_reg.h
new file mode 100644
index 0000000..f2bdc96
--- /dev/null
+++ b/src/avivo_reg.h
@@ -0,0 +1,503 @@
+/* AVIVO registers are specific to the AVIVO display engine, first
+ * introduced on R5xx.
+ *
+ * CRTCs are the master unit. A CRTC controls scanout, and both the
+ * DACs (be it TV or VGA) and TMDS transmitters take their input from
+ * the CRTC.
+ */
+#define IS_AVIVO_VARIANT 1
+
+/* Core engine. */
+#define AVIVO_ENGINE_STATUS 0x0014
+
+/* Memory mapping. */
+#define AVIVO_MC_INDEX 0x0070
+/* AVIVO_MC_MEMORY_MAP control memory mapping of the video card ram:
+ * base is higher 16bits of the starting address at which card
+ * sees it own memory. end is higher 16bits address at which card
+ * memory should end (might be usefull if you want to use half memory
+ * but don't know what does the card if you address out of bound
+ * memory, likely trigger pci stuff which often end in bad things).
+ */
+# define MC00 0x00
+#define R520_MC_STATUS 0x00
+#define R520_MC_STATUS_IDLE (1<<1)
+# define MC01 0x01
+# define MC02 0x02
+# define MC03 0x03
+# define AVIVO_MC_MEMORY_MAP 0x04
+# define AVIVO_MC_MEMORY_MAP_BASE_MASK (0xFFFF << 0)
+# define AVIVO_MC_MEMORY_MAP_BASE_SHIFT 0
+# define AVIVO_MC_MEMORY_MAP_END_MASK (0xFFFF << 16)
+# define AVIVO_MC_MEMORY_MAP_END_SHIFT 16
+# define MC05 0x05
+# define MC06 0x06
+# define MC07 0x07
+# define MC08 0x08
+#define RV515_MC_STATUS 0x08
+#define RV515_MC_STATUS_IDLE (1<<4)
+# define MC09 0x09
+# define MC0a 0x0a
+# define MC0b 0x0b
+# define MC0c 0x0c
+# define MC0d 0x0d
+# define MC0e 0x0e
+# define MC0f 0x0f
+# define MC10 0x10
+# define MC11 0x11
+# define MC12 0x12
+# define MC13 0x13
+# define MC14 0x14
+# define MC15 0x15
+# define MC16 0x16
+# define MC17 0x17
+# define MC18 0x18
+# define MC19 0x19
+# define MC1a 0x1a
+# define MC1b 0x1b
+# define MC1c 0x1c
+# define MC1d 0x1d
+# define MC1e 0x1e
+# define MC1f 0x1f
+#define AVIVO_MC_DATA 0x0074
+
+/*
+ * You set memory base at which card see its memory (should be the
+ * same as AVIVO_MC_MEMORY_MAP lower 16bits
+ */
+#define AVIVO_VGA_MEMORY_BASE 0x0134
+#define AVIVO_VGA_FB_START 0x0310
+#define AVIVO_VGA1_CONTROL 0x0330
+ #define AVIVO_VGA1_CONTROL_MODE_ENABLE (1<<0)
+ #define AVIVO_VGA1_CONTROL_TIMING_SELECT (1<<8)
+ #define AVIVO_VGA1_CONTROL_SYNC_POLARITY_SELECT (1<<9)
+ #define AVIVO_VGA1_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
+ #define AVIVO_VGA1_CONTROL_OVERSCAN_COLOR_EN (1<<16)
+ #define AVIVO_VGA1_CONTROL_ROTATE (1<<24)
+#define AVIVO_VGA2_CONTROL 0x0338
+ #define AVIVO_VGA2_CONTROL_MODE_ENABLE (1<<0)
+ #define AVIVO_VGA2_CONTROL_TIMING_SELECT (1<<8)
+ #define AVIVO_VGA2_CONTROL_SYNC_POLARITY_SELECT (1<<9)
+ #define AVIVO_VGA2_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
+ #define AVIVO_VGA2_CONTROL_OVERSCAN_COLOR_EN (1<<16)
+ #define AVIVO_VGA2_CONTROL_ROTATE (1<<24)
+
+/*
+ * We believe reference clock is 108Mhz, we likely can change that using
+ * mystery PLL reg spoted below more dump are needed in order to find out.
+ *
+ * The formula we derived so far seems to work for card we have:
+ * (vclk is video mode clock)
+ * vclk = (1080 * AVIVO_PLL_POST_MUL) /
+ * (AVIVO_PLL_DIVIDER * AVIVO_PLL_POST_DIV * 40)
+ * It seems that AVIVO_PLL_DIVIDER * AVIVO_PLL_POST_DIV needs to be
+ * above 40 and that AVIVO_DIVIDER should be greater than AVIVO_PLL_POST_DIV
+ * Try to keep this constraint while computing PLL values.
+ */
+#define AVIVO_PLL1_POST_DIV_CNTL 0x0400 // REF_DIV_SRC
+# define AVIVO_PLL_POST_DIV_EN (1 << 0)
+#define AVIVO_PLL1_POST_DIV 0x0404 // REF_DIV
+#define AVIVO_PLL1_POST_DIV_MYSTERY 0x040C
+# define AVIVO_PLL_POST_DIV_MYSTERY_VALUE 0x10000
+#define AVIVO_PLL2_POST_DIV_CNTL 0x0410
+#define AVIVO_PLL2_POST_DIV 0x0414
+#define AVIVO_PLL2_POST_DIV_MYSTERY 0x041C
+#define AVIVO_PLL1_POST_MUL 0x0430 // FB_DIV
+# define AVIVO_PLL_POST_MUL_SHIFT 16
+#define AVIVO_PLL2_POST_MUL 0x0434 // FB_DIV
+#define AVIVO_PLL1_DIVIDER_CNTL 0x0438 // POST DIV_SRC
+# define AVIVO_PLL_DIVIDER_EN (1 << 0)
+#define AVIVO_PLL1_DIVIDER 0x043C // POST DIV
+#define AVIVO_PLL2_DIVIDER_CNTL 0x0440
+#define AVIVO_PLL2_DIVIDER 0x0444 // POST_DIV
+#define AVIVO_PLL1_MYSTERY0 0x0448 // POST_DIV_SRC
+# define AVIVO_PLL_MYSTERY0_VALUE 0x20704
+#define AVIVO_PLL2_MYSTERY0 0x044C
+#define AVIVO_PLL1_MYSTERY1 0x0450
+# define AVIVO_PLL_MYSTERY1_VALUE 0x4310000
+#define AVIVO_PLL2_MYSTERY1 0x0454
+#define AVIVO_CRTC_PLL_SOURCE 0x0484
+# define AVIVO_CRTC1_PLL_SOURCE_SHIFT 0
+# define AVIVO_CRTC2_PLL_SOURCE_SHIFT 16
+
+/* CRTC controls; these appear to influence the DAC's scanout. */
+#define AVIVO_CRTC1_H_TOTAL 0x6000
+#define AVIVO_CRTC1_H_BLANK 0x6004
+#define AVIVO_CRTC1_H_SYNC_WID 0x6008
+#define AVIVO_CRTC1_H_SYNC_POL 0x600c
+#define AVIVO_CRTC1_V_TOTAL 0x6020
+#define AVIVO_CRTC1_V_BLANK 0x6024
+#define AVIVO_CRTC1_V_SYNC_WID 0x6028
+#define AVIVO_CRTC1_V_SYNC_POL 0x602c
+#define AVIVO_CRTC1_CNTL 0x6080
+# define AVIVO_CRTC_EN (1 << 0)
+#define AVIVO_CRTC1_BLANK_STATUS 0x6084
+#define AVIVO_CRTC1_STEREO_STATUS 0x60c0
+
+/* These all appear to control the scanout from the framebuffer.
+ * Flicking SCAN_ENABLE low results in a black screen -- aside from
+ * the cursor. Messing with PITCH gives you the obvious symptoms,
+ * and messing with X_LENGTH and Y_LENGTH will give you a black
+ * screen beyond those bounds if you make it shorter.
+ *
+ * Messing with the format gives you ... odd results. Setting it
+ * to 3 exactly quadruples my display size, with the next three
+ * panes displaying the next parts of FB memory. BPP?
+ *
+ * FB_LOCATION gives me the obvious result; FB_END is exactly
+ * FB_LOCATION + (xres * yres * 2). FB_END doesn't appear to actually
+ * function as an upper bound.
+ */
+#define AVIVO_CRTC1_SCAN_ENABLE 0x6100
+# define AVIVO_CRTC_SCAN_EN (1 << 0)
+#define AVIVO_CRTC1_FB_FORMAT 0x6104
+# define AVIVO_CRTC_FORMAT_ARGB15 (1 << 0)
+# define AVIVO_CRTC_FORMAT_ARGB16 ((1 << 0) | (1 << 8))
+# define AVIVO_CRTC_FORMAT_ARGB32 (1 << 1)
+# define AVIVO_CRTC_TILED (1 << 20)
+# define AVIVO_CRTC_MACRO_ADDRESS_MODE (1 << 21)
+#define AVIVO_CRTC1_FB_LOCATION 0x6110
+#define AVIVO_CRTC1_FB_END 0x6118
+/* This is in pixels, not bytes. Obviously. */
+#define AVIVO_CRTC1_PITCH 0x6120
+#define AVIVO_CRTC1_X_LENGTH 0x6134
+#define AVIVO_CRTC1_Y_LENGTH 0x6138
+
+#define AVIVO_CRTC1_OFFSET_END 0x6454
+
+#define AVIVO_CRTC1_FB_HEIGHT 0x652c
+#define AVIVO_CRTC1_OFFSET_START 0x6580
+#define AVIVO_CRTC1_EXPANSION_SOURCE 0x6584
+#define AVIVO_CRTC1_EXPANSION_CNTL 0x6590
+# define AVIVO_CRTC_EXPANSION_EN (1 << 0)
+#define AVIVO_CRTC1_6594 0x6594
+# define AVIVO_CRTC1_6594_VALUE ((1 << 8) | (1 << 0))
+#define AVIVO_CRTC1_659C 0x659C
+# define AVIVO_CRTC1_659C_VALUE ((1 << 1))
+#define AVIVO_CRTC1_65A4 0x65a4
+# define AVIVO_CRTC1_65A4_VALUE ((1 << 16) | (1 << 0))
+#define AVIVO_CRTC1_65A8 0x65a8
+# define AVIVO_CRTC1_65A8_VALUE ((1 << 16) | (1 << 14))
+#define AVIVO_CRTC1_65AC 0x65ac
+# define AVIVO_CRTC1_65AC_VALUE ((1 << 15) | (1 << 14) | (1 << 13))
+#define AVIVO_CRTC1_65B0 0x65b0
+# define AVIVO_CRTC1_65B0_VALUE ((1 << 17) | (1 << 16) | (1 << 8))
+#define AVIVO_CRTC1_65B8 0x65b8
+# define AVIVO_CRTC1_65B8_VALUE ((1 << 16))
+#define AVIVO_CRTC1_65BC 0x65bc
+# define AVIVO_CRTC1_65BC_VALUE ((1 << 16))
+#define AVIVO_CRTC1_65C0 0x65c0
+# define AVIVO_CRTC1_65C0_VALUE ((1 << 17) | (1 << 16) | (1 << 8))
+#define AVIVO_CRTC1_65C8 0x65c8
+# define AVIVO_CRTC1_65C8_VALUE ((1 << 16))
+
+#define AVIVO_CRTC2_H_TOTAL 0x6800
+#define AVIVO_CRTC2_H_BLANK 0x6804
+#define AVIVO_CRTC2_H_SYNC_WID 0x6808
+#define AVIVO_CRTC2_H_SYNC_POL 0x680c
+#define AVIVO_CRTC2_V_TOTAL 0x6820
+#define AVIVO_CRTC2_V_BLANK 0x6824
+#define AVIVO_CRTC2_V_SYNC_WID 0x6828
+#define AVIVO_CRTC2_V_SYNC_POL 0x682c
+#define AVIVO_CRTC2_CNTL 0x6880
+#define AVIVO_CRTC2_BLANK_STATUS 0x6884
+
+#define AVIVO_CRTC2_SCAN_ENABLE 0x6900
+#define AVIVO_CRTC2_FB_FORMAT 0x6904
+#define AVIVO_CRTC2_FB_LOCATION 0x6910
+#define AVIVO_CRTC2_FB_END 0x6918
+#define AVIVO_CRTC2_PITCH 0x6920
+#define AVIVO_CRTC2_X_LENGTH 0x6934
+#define AVIVO_CRTC2_Y_LENGTH 0x6938
+
+#define AVIVO_CRTC2_OFFSET_END 0x6c54
+
+#define AVIVO_CRTC2_FB_HEIGHT 0x6d2c
+#define AVIVO_CRTC2_OFFSET_START 0x6d80
+#define AVIVO_CRTC2_EXPANSION_SOURCE 0x6d84
+#define AVIVO_CRTC2_EXPANSION_CNTL 0x6d90
+#define AVIVO_CRTC2_6594 0x6d94
+#define AVIVO_CRTC2_659C 0x6d9C
+#define AVIVO_CRTC2_65A4 0x6da4
+#define AVIVO_CRTC2_65A8 0x6da8
+#define AVIVO_CRTC2_65AC 0x6dac
+#define AVIVO_CRTC2_65B0 0x6db0
+#define AVIVO_CRTC2_65B8 0x6db8
+#define AVIVO_CRTC2_65BC 0x6dbc
+#define AVIVO_CRTC2_65C0 0x6dc0
+#define AVIVO_CRTC2_65C8 0x6dc8
+
+#define AVIVO_DACA_CNTL 0x7800
+#define AVIVO_DACA_CRTC_SOURCE 0x7804
+# define AVIVO_DAC_EN (1 << 0)
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
+#define AVIVO_DACA_POWERDOWN 0x7850
+# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
+# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
+# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
+# define AVIVO_DACA_POWERDOWN_RED (1 << 24)
+
+#define AVIVO_DACB_CNTL 0x7a00
+#define AVIVO_DACB_CRTC_SOURCE 0x7a04
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
+#define AVIVO_DACB_POWERDOWN 0x7a50
+# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
+# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
+# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
+# define AVIVO_DACB_POWERDOWN_RED (1 << 24)
+
+/* Frustratingly, at least on my R580, the DAC and TMDS orders
+ * appear inversed: 7800 and 7a80 enable/disable the same physical
+ * connector; ditto 7a00 and 7880. O brave new world!
+ */
+/* TMDS_CNTL only lower bit of each half bytes matters.
+ * UNK0 seems to have no effect on LVDS but kill the feed of DVI connector
+ * UNK1 really unknow: so far no visible change from setting it or not
+ * UNK2 really unknow: so far no visible change from setting it or not
+ * UNK3 really unknow: so far no visible change from setting it or not
+ * UNK4 seems to switch red & blue encoding
+ * UNK5 is the fun bits on some card people will see their desktop
+ * tiled 4 times but for most cards this will give wrong pictures
+ * UNK6 seems to kill the feed LVDS & DVI
+ */
+#define AVIVO_TMDSA_CNTL 0x7880
+# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
+# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
+# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
+# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
+# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
+# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
+# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
+#define AVIVO_TMDSA_CRTC_SOURCE 0x7884
+/* 78a8 appears to be some kind of (reasonably tolerant) clock?
+ * 78d0 definitely hits the transmitter, definitely clock. */
+/* MYSTERY1 This appears to control dithering? */
+#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
+#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
+#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
+# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
+# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
+#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
+
+/* I don't know any of the bits here, only that enabling (1 << 5)
+ * without (1 << 4) makes things go utterly mental ... seems to be
+ * the transmitter clock again. */
+/* 790c is a clock?
+ * 7910 appears to be some kind of control field, again. (1 << 25)
+ * must be enabled to get a signal on my monitor. */
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
+
+#define AVIVO_LVTMA_CNTL 0x7a80
+# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
+# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
+# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
+# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
+# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
+# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
+# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
+#define AVIVO_LVTMA_CRTC_SOURCE 0x7a84
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
+
+#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
+
+#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
+# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
+# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
+#define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00
+
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
+
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
+
+#define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0
+# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
+# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
+# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
+# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
+# define AVIVO_LVTMA_SYNCEN (1 << 8)
+# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
+# define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
+# define AVIVO_LVTMA_DIGON (1 << 16)
+# define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
+# define AVIVO_LVTMA_DIGON_POL (1 << 18)
+# define AVIVO_LVTMA_BLON (1 << 24)
+# define AVIVO_LVTMA_BLON_OVRD (1 << 25)
+# define AVIVO_LVTMA_BLON_POL (1 << 26)
+
+#define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4
+# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
+# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
+# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
+# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
+# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
+# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
+
+#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
+# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
+# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
+# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
+
+/* The BIOS says so, anyway ... */
+#define AVIVO_GPIO_0 0x7e30
+#define AVIVO_GPIO_1 0x7e40
+#define AVIVO_GPIO_2 0x7e50
+#define AVIVO_GPIO_3 0x7e60
+
+#define AVIVO_TMDS_STATUS 0x7e9c
+# define AVIVO_TMDSA_CONNECTED (1 << 0)
+# define AVIVO_LVTMA_CONNECTED (1 << 8)
+
+/* Cursor registers. */
+#define AVIVO_CURSOR1_CNTL 0x6400
+# define AVIVO_CURSOR_EN (1 << 0)
+# define AVIVO_CURSOR_FORMAT_MASK (3 << 8)
+# define AVIVO_CURSOR_FORMAT_ABGR 0x1
+# define AVIVO_CURSOR_FORMAT_ARGB 0x2
+# define AVIVO_CURSOR_FORMAT_SHIFT 8
+#define AVIVO_CURSOR1_LOCATION 0x6408
+/* x is in the top 16 bits; y in the lower 16. Note that _SIZE does not
+ * impact the in-memory format: it is always 64x64. */
+#define AVIVO_CURSOR1_SIZE 0x6410
+#define AVIVO_CURSOR1_POSITION 0x6414
+
+#define AVIVO_I2C_STATUS 0x7d30
+# define AVIVO_I2C_STATUS_DONE (1 << 0)
+# define AVIVO_I2C_STATUS_NACK (1 << 1)
+# define AVIVO_I2C_STATUS_HALT (1 << 2)
+# define AVIVO_I2C_STATUS_GO (1 << 3)
+# define AVIVO_I2C_STATUS_MASK 0x7
+/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
+ * DONE? */
+# define AVIVO_I2C_STATUS_CMD_RESET 0x7
+# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3)
+#define AVIVO_I2C_STOP 0x7d34
+#define AVIVO_I2C_START_CNTL 0x7d38
+# define AVIVO_I2C_START (1 << 8)
+# define AVIVO_I2C_CONNECTOR0 (0 << 16)
+# define AVIVO_I2C_CONNECTOR1 (1 << 16)
+#define R520_I2C_START (1<<0)
+#define R520_I2C_STOP (1<<1)
+#define R520_I2C_RX (1<<2)
+#define R520_I2C_EN (1<<8)
+#define R520_I2C_DDC1 (0<<16)
+#define R520_I2C_DDC2 (1<<16)
+#define R520_I2C_DDC3 (2<<16)
+#define R520_I2C_DDC_MASK (3<<16)
+#define AVIVO_I2C_CONTROL2 0x7d3c
+# define AVIVO_I2C_7D3C_SIZE_SHIFT 8
+# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8)
+#define AVIVO_I2C_CONTROL3 0x7d40
+/* Reading is done 4 bytes at a time: read the bottom 8 bits from
+ * 7d44, four times in a row.
+ * Writing is a little more complex. First write DATA with
+ * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
+ * magic number, zz is, I think, the slave address, and yy is the byte
+ * you want to write. */
+#define AVIVO_I2C_DATA 0x7d44
+#define R520_I2C_ADDR_COUNT_MASK (0x7)
+#define R520_I2C_DATA_COUNT_SHIFT (8)
+#define R520_I2C_DATA_COUNT_MASK (0xF00)
+#define AVIVO_I2C_CNTL 0x7d50
+# define AVIVO_I2C_EN (1 << 0)
+# define AVIVO_I2C_RESET (1 << 8)
+
+
+#define R520_PCLK_HDCP_CNTL 0x494
+
+#define AVIVO_HDP_FB_LOCATION 0x134
+#define AVIVO_VGA_MEM_BASE 0x310
+#define AVIVO_VGA_SURF_ADDR 0x318
+#define AVIVO_D1VGA_CTRL 0x330
+#define AVIVO_D2VGA_CTRL 0x338
+
+#define AVIVO_DVGA_MODE_ENABLE (1<<0)
+
+
diff --git a/src/radeon.h b/src/radeon.h
index 532f04c..1d2235c 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -443,6 +443,8 @@ typedef enum {
CARD_PCIE
} RADEONCardType;
+typedef struct _atomBIOSHandle *atomBIOSHandlePtr;
+
typedef struct {
EntityInfoPtr pEnt;
pciVideoPtr PciInfo;
@@ -817,6 +819,15 @@ typedef struct {
RADEONMacModel MacModel;
#endif
+ atomBIOSHandlePtr atomBIOS;
+ unsigned long FbFreeStart, FbFreeSize;
+
+ int cursor_width;
+ int cursor_height;
+ int cursor_format;
+ int cursor_x;
+ int cursor_y;
+
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
new file mode 100644
index 0000000..12af4eb
--- /dev/null
+++ b/src/radeon_atombios.c
@@ -0,0 +1,1104 @@
+/*
+ * Copyright 2007 Egbert Eich <eich at novell.com>
+ * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+ * Copyright 2007 Matthias Hopf <mhopf at novell.com>
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+# include "config.h"
+#endif
+#include "xf86.h"
+#include "xf86_OSproc.h"
+#include "radeon.h"
+#include "radeon_atombios.h"
+#include "radeon_macros.h"
+
+#include "xorg-server.h"
+#if XSERVER_LIBPCIACCESS
+#warning pciaccess defined
+#endif
+
+char *AtomBIOSQueryStr[] = {
+ "Default Engine Clock",
+ "Default Memory Clock",
+ "Maximum Pixel ClockPLL Frequency Output",
+ "Minimum Pixel ClockPLL Frequency Output",
+ "Maximum Pixel ClockPLL Frequency Input",
+ "Minimum Pixel ClockPLL Frequency Input",
+ "Minimum Pixel Clock",
+ "Reference Clock",
+ "Start of VRAM area used by Firmware",
+ "Framebuffer space used by Firmware (kb)",
+ "TDMS Frequency",
+ "PLL ChargePump",
+ "PLL DutyCycle",
+ "PLL VCO Gain",
+ "PLL VoltageSwing"
+};
+
+char *AtomBIOSFuncStr[] = {
+ "AtomBIOS Init",
+ "AtomBIOS Teardown",
+ "AtomBIOS Exec",
+ "AtomBIOS Set FB Space"
+};
+
+#define DEBUGP(x) {x;}
+#define LOG_DEBUG 7
+
+#ifdef ATOM_BIOS
+# define LOG_CAIL LOG_DEBUG + 1
+
+#ifdef ATOM_BIOS_PARSER
+static void
+CailDebug(int scrnIndex, const char *format, ...)
+{
+ va_list ap;
+
+ va_start(ap, format);
+ xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_CAIL, format, ap);
+ va_end(ap);
+}
+#endif
+
+# define CAILFUNC(ptr) \
+ CailDebug(((atomBIOSHandlePtr)(ptr))->scrnIndex, "CAIL: %s\n", __func__)
+
+
+enum {
+ legacyBIOSLocation = 0xC0000,
+ legacyBIOSMax = 0x10000
+};
+
+static int
+rhdAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr)
+{
+ if (hdr->usStructureSize == 0xaa55)
+ return FALSE;
+
+ return TRUE;
+}
+
+static int
+rhdAnalyzeRomHdr(unsigned char *rombase,
+ ATOM_ROM_HEADER *hdr,
+ int *data_offset, int *command_offset)
+{
+ if (rhdAnalyzeCommonHdr(&hdr->sHeader) == -1) {
+ return FALSE;
+ }
+ xf86ErrorF("\tSubsysemVendorID: 0x%4.4x SubsystemID: 0x%4.4x\n",
+ hdr->usSubsystemVendorID,hdr->usSubsystemID);
+ xf86ErrorF("\tIOBaseAddress: 0x%4.4x\n",hdr->usIoBaseAddress);
+ xf86ErrorFVerb(3,"\tFilename: %s\n",rombase + hdr->usConfigFilenameOffset);
+ xf86ErrorFVerb(3,"\tBIOS Bootup Message: %s\n",
+ rombase + hdr->usBIOS_BootupMessageOffset);
+
+ *data_offset = hdr->usMasterDataTableOffset;
+ *command_offset = hdr->usMasterCommandTableOffset;
+
+ return TRUE;
+}
+
+static int
+rhdAnalyzeRomDataTable(unsigned char *base, int offset,
+ void *ptr,short *size)
+{
+ ATOM_COMMON_TABLE_HEADER *table = (ATOM_COMMON_TABLE_HEADER *)
+ (base + offset);
+
+ if (!*size || rhdAnalyzeCommonHdr(table) == -1) {
+ if (*size) *size -= 2;
+ *(void **)ptr = NULL;
+ return FALSE;
+ }
+ *size -= 2;
+ *(void **)ptr = (void *)(table);
+ return TRUE;
+}
+
+static Bool
+rhdGetAtomBiosTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr,
+ CARD8 *contentRev,
+ CARD8 *formatRev,
+ short *size)
+{
+ if (!hdr)
+ return FALSE;
+
+ if (contentRev) *contentRev = hdr->ucTableContentRevision;
+ if (formatRev) *formatRev = hdr->ucTableFormatRevision;
+ if (size) *size = (short)hdr->usStructureSize
+ - sizeof(ATOM_COMMON_TABLE_HEADER);
+ return TRUE;
+}
+
+static Bool
+rhdAnalyzeMasterDataTable(unsigned char *base,
+ ATOM_MASTER_DATA_TABLE *table,
+ atomDataTablesPtr data)
+{
+ ATOM_MASTER_LIST_OF_DATA_TABLES *data_table =
+ &table->ListOfDataTables;
+ short size;
+
+ if (!rhdAnalyzeCommonHdr(&table->sHeader))
+ return FALSE;
+ if (!rhdGetAtomBiosTableRevisionAndSize(&table->sHeader,NULL,NULL,&size))
+ return FALSE;
+# define SET_DATA_TABLE(x) {\
+ rhdAnalyzeRomDataTable(base,data_table->x,(void *)(&(data->x)),&size); \
+ }
+
+# define SET_DATA_TABLE_VERS(x) {\
+ rhdAnalyzeRomDataTable(base,data_table->x,&(data->x.base),&size); \
+ }
+
+ SET_DATA_TABLE(UtilityPipeLine);
+ SET_DATA_TABLE(MultimediaCapabilityInfo);
+ SET_DATA_TABLE(MultimediaConfigInfo);
+ SET_DATA_TABLE(StandardVESA_Timing);
+ SET_DATA_TABLE_VERS(FirmwareInfo);
+ SET_DATA_TABLE(DAC_Info);
+ SET_DATA_TABLE_VERS(LVDS_Info);
+ SET_DATA_TABLE(TMDS_Info);
+ SET_DATA_TABLE(AnalogTV_Info);
+ SET_DATA_TABLE_VERS(SupportedDevicesInfo);
+ SET_DATA_TABLE(GPIO_I2C_Info);
+ SET_DATA_TABLE(VRAM_UsageByFirmware);
+ SET_DATA_TABLE(GPIO_Pin_LUT);
+ SET_DATA_TABLE(VESA_ToInternalModeLUT);
+ SET_DATA_TABLE_VERS(ComponentVideoInfo);
+ SET_DATA_TABLE(PowerPlayInfo);
+ SET_DATA_TABLE(CompassionateData);
+ SET_DATA_TABLE(SaveRestoreInfo);
+ SET_DATA_TABLE(PPLL_SS_Info);
+ SET_DATA_TABLE(OemInfo);
+ SET_DATA_TABLE(XTMDS_Info);
+ SET_DATA_TABLE(MclkSS_Info);
+ SET_DATA_TABLE(Object_Header);
+ SET_DATA_TABLE(IndirectIOAccess);
+ SET_DATA_TABLE(MC_InitParameter);
+ SET_DATA_TABLE(ASIC_VDDC_Info);
+ SET_DATA_TABLE(ASIC_InternalSS_Info);
+ SET_DATA_TABLE(TV_VideoMode);
+ SET_DATA_TABLE_VERS(VRAM_Info);
+ SET_DATA_TABLE(MemoryTrainingInfo);
+ SET_DATA_TABLE_VERS(IntegratedSystemInfo);
+ SET_DATA_TABLE(ASIC_ProfilingInfo);
+ SET_DATA_TABLE(VoltageObjectInfo);
+ SET_DATA_TABLE(PowerSourceInfo);
+# undef SET_DATA_TABLE
+
+ return TRUE;
+}
+
+Bool
+rhdGetAtombiosDataTable(int scrnIndex, unsigned char *base, int *cmd_offset,
+ atomDataTables *atomDataPtr)
+{
+ int data_offset;
+ unsigned short atom_romhdr_off = *(unsigned short*)
+ (base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER);
+ ATOM_ROM_HEADER *atom_rom_hdr =
+ (ATOM_ROM_HEADER *)(base + atom_romhdr_off);
+
+ // RHDFUNCI(scrnIndex)
+
+ if (memcmp("ATOM",&atom_rom_hdr->uaFirmWareSignature,4)) {
+ xf86DrvMsg(scrnIndex,X_ERROR,"No AtomBios signature found\n");
+ return FALSE;
+ }
+ xf86DrvMsg(scrnIndex, X_INFO, "ATOM BIOS Rom: \n");
+ if (!rhdAnalyzeRomHdr(base, atom_rom_hdr, &data_offset, cmd_offset)) {
+ xf86DrvMsg(scrnIndex, X_ERROR, "RomHeader invalid\n");
+ return FALSE;
+ }
+ if (!rhdAnalyzeMasterDataTable(base, (ATOM_MASTER_DATA_TABLE *)
+ (base + data_offset),
+ atomDataPtr)) {
+ xf86DrvMsg(scrnIndex, X_ERROR, "ROM Master Table invalid\n");
+ return FALSE;
+ }
+ return TRUE;
+}
+
+static Bool
+rhdBIOSGetFbBaseAndSize(int scrnIndex, atomBIOSHandlePtr handle, unsigned int *base, unsigned int *size)
+{
+ AtomBIOSArg data;
+ if (RHDAtomBIOSFunc(scrnIndex, handle, GET_FW_FB_SIZE, &data)
+ == ATOM_SUCCESS) {
+ if (data.val == 0) {
+ xf86DrvMsg(scrnIndex, X_WARNING, "%s: AtomBIOS specified VRAM "
+ "scratch space size invalid\n", __func__);
+ return FALSE;
+ }
+ *size = (int)data.val;
+ } else
+ return FALSE;
+ if (RHDAtomBIOSFunc(scrnIndex, handle, GET_FW_FB_START, &data)
+ == ATOM_SUCCESS) {
+ if (data.val == 0)
+ return FALSE;
+ *base = (int)data.val;
+ }
+ return TRUE;
+}
+
+/*
+ * Uses videoRam form ScrnInfoRec.
+ */
+static Bool
+rhdAtomBIOSAllocateFbScratch(int scrnIndex, atomBIOSHandlePtr handle,
+ unsigned *start, unsigned int *size)
+{
+ unsigned int fb_base = 0;
+ unsigned int fb_size = 0;
+ handle->scratchBase = NULL;
+ handle->fbBase = 0;
+
+ if (rhdBIOSGetFbBaseAndSize(scrnIndex, handle, &fb_base, &fb_size)) {
+ xf86DrvMsg(scrnIndex, X_INFO, "AtomBIOS requests %ikB"
+ " of VRAM scratch space\n",fb_size);
+ fb_size *= 1024; /* convert to bytes */
+ xf86DrvMsg(scrnIndex, X_INFO, "AtomBIOS VRAM scratch base: 0x%x\n",
+ fb_base);
+ } else {
+ fb_size = 20 * 1024;
+ xf86DrvMsg(scrnIndex, X_INFO, " default to: %i\n",fb_size);
+ }
+ if (fb_base && fb_size && *size) {
+ /* 4k align */
+ fb_size = (fb_size & ~(CARD32)0xfff) + ((fb_size & 0xfff) ? 1 : 0);
+ if ((fb_base + fb_size) > (*start + *size)) {
+ xf86DrvMsg(scrnIndex, X_WARNING,
+ "%s: FW FB scratch area %i (size: %i)"
+ " extends beyond available framebuffer size %i\n",
+ __func__, fb_base, fb_size, *size);
+ } else if ((fb_base + fb_size) < (*start + *size)) {
+ xf86DrvMsg(scrnIndex, X_WARNING,
+ "%s: FW FB scratch area not located "
+ "at the end of VRAM. Scratch End: "
+ "0x%x VRAM End: 0x%x\n", __func__,
+ (unsigned int)(fb_base + fb_size),
+ *size);
+ } else if (fb_base < *start) {
+ xf86DrvMsg(scrnIndex, X_WARNING,
+ "%s: FW FB scratch area extends below "
+ "the base of the free VRAM: 0x%x Base: 0x%x\n",
+ __func__, (unsigned int)(fb_base), *start);
+ } else {
+ *size -= fb_size;
+ handle->fbBase = fb_base;
+ return TRUE;
+ }
+ }
+
+ if (!handle->fbBase) {
+ xf86DrvMsg(scrnIndex, X_INFO,
+ "Cannot get VRAM scratch space. "
+ "Allocating in main memory instead\n");
+ handle->scratchBase = xcalloc(fb_size,1);
+ return TRUE;
+ }
+ return FALSE;
+}
+
+# ifdef ATOM_BIOS_PARSER
+static Bool
+rhdASICInit(atomBIOSHandlePtr handle)
+{
+ ASIC_INIT_PS_ALLOCATION asicInit;
+ AtomBIOSArg data;
+
+ RHDAtomBIOSFunc(handle->scrnIndex, handle,
+ GET_DEFAULT_ENGINE_CLOCK,
+ &data);
+ asicInit.sASICInitClocks.ulDefaultEngineClock = data.val; /* in 10 Khz */
+ RHDAtomBIOSFunc(handle->scrnIndex, handle,
+ GET_DEFAULT_MEMORY_CLOCK,
+ &data);
+ asicInit.sASICInitClocks.ulDefaultMemoryClock = data.val; /* in 10 Khz */
+ data.exec.dataSpace = NULL;
+ data.exec.index = 0x0;
+ data.exec.pspace = &asicInit;
+ xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling ASIC Init\n");
+ if (RHDAtomBIOSFunc(handle->scrnIndex, handle,
+ ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Successful\n");
+ return TRUE;
+ }
+ xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Failed\n");
+ return FALSE;
+}
+# endif
+
+static atomBIOSHandlePtr
+rhdInitAtomBIOS(int scrnIndex)
+{
+ RADEONInfoPtr info = RADEONPTR(xf86Screens[scrnIndex]);
+ unsigned char *ptr = info->VBIOS;
+ atomDataTablesPtr atomDataPtr;
+ atomBIOSHandlePtr handle = NULL;
+ unsigned int dummy;
+ int cmd_offset;
+
+ if (!(atomDataPtr = xcalloc(sizeof(atomDataTables),1))) {
+ xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory for "
+ "ATOM BIOS data tabes\n");
+ goto error;
+ }
+ if (!rhdGetAtombiosDataTable(scrnIndex, ptr, &cmd_offset, atomDataPtr))
+ goto error1;
+ if (!(handle = xcalloc(sizeof(atomBIOSHandle),1))) {
+ xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory\n");
+ goto error1;
+ }
+ handle->cmd_offset = cmd_offset;
+ handle->BIOSBase = ptr;
+ handle->atomDataPtr = atomDataPtr;
+ handle->scrnIndex = scrnIndex;
+#if XSERVER_LIBPCIACCESS
+ handle->device = info->PciInfo;
+#else
+ handle->PciTag = info->PciTag;
+#endif
+
+#if ATOM_BIOS_PARSER
+ /* Try to find out if BIOS has been posted (either by system or int10 */
+ if (1 || !rhdBIOSGetFbBaseAndSize(scrnIndex, handle, &dummy, &dummy)) {
+ /* run AsicInit */
+ if (!rhdASICInit(handle))
+ xf86DrvMsg(scrnIndex, X_WARNING,
+ "%s: AsicInit failed. Won't be able to obtain in VRAM "
+ "FB scratch space\n",__func__);
+ }
+#endif
+ return handle;
+
+ error1:
+ xfree(atomDataPtr);
+ error:
+ xfree(ptr);
+ return NULL;
+}
+
+void
+rhdTearDownAtomBIOS(int scrnIndex, atomBIOSHandlePtr handle)
+{
+ // RHDFUNCI(scrnIndex);
+
+ xfree(handle->BIOSBase);
+ xfree(handle->atomDataPtr);
+ xfree(handle);
+}
+AtomBiosResult
+rhdAtomBIOSVramInfoQuery(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func,
+ CARD32 *val)
+{
+ atomDataTablesPtr atomDataPtr;
+
+ // RHDFUNCI(scrnIndex);
+
+ atomDataPtr = handle->atomDataPtr;
+
+ switch (func) {
+ case GET_FW_FB_START:
+ *val = atomDataPtr->VRAM_UsageByFirmware
+ ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
+ break;
+ case GET_FW_FB_SIZE:
+ *val = atomDataPtr->VRAM_UsageByFirmware
+ ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ return ATOM_SUCCESS;
+}
+
+AtomBiosResult
+rhdAtomBIOSTmdsInfoQuery(int scrnIndex, atomBIOSHandlePtr handle,
+ AtomBiosFunc func, int index, CARD32 *val)
+{
+ atomDataTablesPtr atomDataPtr;
+
+ atomDataPtr = handle->atomDataPtr;
+ if (!rhdGetAtomBiosTableRevisionAndSize(
+ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base),
+ NULL,NULL,NULL)) {
+ return ATOM_FAILED;
+ }
+
+ // RHDFUNCI(scrnIndex);
+
+ switch (func) {
+ case ATOM_TMDS_FREQUENCY:
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[index].usFrequency;
+ break;
+ case ATOM_TMDS_PLL_CHARGE_PUMP:
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_ChargePump;
+ break;
+ case ATOM_TMDS_PLL_DUTY_CYCLE:
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_DutyCycle;
+ break;
+ case ATOM_TMDS_PLL_VCO_GAIN:
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_VCO_Gain;
+ break;
+ case ATOM_TMDS_PLL_VOLTAGE_SWING:
+ *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_VoltageSwing;
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ return ATOM_SUCCESS;
+}
+
+AtomBiosResult
+rhdAtomBIOSFirmwareInfoQuery(int scrnIndex, atomBIOSHandlePtr handle,
+ AtomBiosFunc func, CARD32 *val)
+{
+ atomDataTablesPtr atomDataPtr;
+ CARD8 crev, frev;
+
+ // RHDFUNCI(scrnIndex);
+
+ atomDataPtr = handle->atomDataPtr;
+ if (!rhdGetAtomBiosTableRevisionAndSize(
+ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base),
+ &crev,&frev,NULL)) {
+ return ATOM_FAILED;
+ }
+ switch (crev) {
+ case 1:
+ switch (func) {
+ case GET_DEFAULT_ENGINE_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo->ulDefaultEngineClock;
+ break;
+ case GET_DEFAULT_MEMORY_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo->ulDefaultMemoryClock;
+ break;
+ case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo->ulMaxPixelClockPLL_Output;
+ break;
+ case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo->usMinPixelClockPLL_Output;
+ case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo->usMaxPixelClockPLL_Input;
+ break;
+ case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo->usMinPixelClockPLL_Input;
+ break;
+ case GET_MAX_PIXEL_CLK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo->usMaxPixelClock;
+ break;
+ case GET_REF_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo->usReferenceClock;
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ case 2:
+ switch (func) {
+ case GET_DEFAULT_ENGINE_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_2->ulDefaultEngineClock;
+ break;
+ case GET_DEFAULT_MEMORY_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_2->ulDefaultMemoryClock;
+ break;
+ case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output;
+ break;
+ case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output;
+ break;
+ case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input;
+ break;
+ case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input;
+ break;
+ case GET_MAX_PIXEL_CLK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_2->usMaxPixelClock;
+ break;
+ case GET_REF_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_2->usReferenceClock;
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ break;
+ case 3:
+ switch (func) {
+ case GET_DEFAULT_ENGINE_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_3->ulDefaultEngineClock;
+ break;
+ case GET_DEFAULT_MEMORY_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_3->ulDefaultMemoryClock;
+ break;
+ case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output;
+ break;
+ case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output;
+ break;
+ case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input;
+ break;
+ case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input;
+ break;
+ case GET_MAX_PIXEL_CLK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_3->usMaxPixelClock;
+ break;
+ case GET_REF_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_3->usReferenceClock;
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ break;
+ case 4:
+ switch (func) {
+ case GET_DEFAULT_ENGINE_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_4->ulDefaultEngineClock;
+ break;
+ case GET_DEFAULT_MEMORY_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_4->ulDefaultMemoryClock;
+ break;
+ case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input;
+ break;
+ case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input;
+ break;
+ case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output;
+ break;
+ case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output;
+ break;
+ case GET_MAX_PIXEL_CLK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_4->usMaxPixelClock;
+ break;
+ case GET_REF_CLOCK:
+ *val = atomDataPtr->FirmwareInfo
+ .FirmwareInfo_V_1_4->usReferenceClock;
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ break;
+ default:
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ return ATOM_SUCCESS;
+}
+
+# ifdef ATOM_BIOS_PARSER
+static Bool
+rhdAtomExec (atomBIOSHandlePtr handle, int index, void *pspace, pointer *dataSpace)
+{
+ RADEONInfoPtr info = RADEONPTR (xf86Screens[handle->scrnIndex]);
+ Bool ret = FALSE;
+ char *msg;
+
+ // RHDFUNCI(handle->scrnIndex);
+ if (dataSpace) {
+ if (!handle->fbBase && !handle->scratchBase)
+ return FALSE;
+ if (handle->fbBase) {
+ if (!info->FB) {
+ xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: "
+ "Cannot exec AtomBIOS: framebuffer not mapped\n",
+ __func__);
+ return FALSE;
+ }
+ *dataSpace = (CARD8*)info->FB + handle->fbBase;
+ } else
+ *dataSpace = (CARD8*)handle->scratchBase;
+ }
+ ret = ParseTableWrapper(pspace, index, handle,
+ handle->BIOSBase,
+ &msg);
+ if (!ret)
+ xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s\n",msg);
+ else
+ xf86DrvMsgVerb(handle->scrnIndex, X_INFO, 5, "%s\n",msg);
+
+ return (ret) ? TRUE : FALSE;
+}
+# endif
+
+AtomBiosResult
+RHDAtomBIOSFunc(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func,
+ AtomBIOSArgPtr data)
+{
+ AtomBiosResult ret = ATOM_NOT_IMPLEMENTED;
+ CARD32 val;
+
+# define do_return(x) { \
+ if (func < sizeof(AtomBIOSFuncStr)) \
+ xf86DrvMsgVerb(scrnIndex, (x == ATOM_SUCCESS) ? 7 : 1, \
+ (x == ATOM_SUCCESS) ? X_INFO : X_WARNING, \
+ "Call to %s %s\n", AtomBIOSFuncStr[func], \
+ (x == ATOM_SUCCESS) ? "succeeded" : "FAILED"); \
+ return (x); \
+ }
+ assert (sizeof(AtomBIOSQueryStr) == (FUNC_END - ATOM_QUERY_FUNCS + 1));
+
+ if (func == ATOMBIOS_INIT) {
+ if (!(data->atomp = rhdInitAtomBIOS(scrnIndex)))
+ do_return(ATOM_FAILED);
+ do_return(ATOM_SUCCESS);
+ }
+ if (!handle)
+ do_return(ATOM_FAILED);
+ if (func == ATOMBIOS_ALLOCATE_FB_SCRATCH) {
+ if (rhdAtomBIOSAllocateFbScratch( scrnIndex, handle, &data->fb.start, &data->fb.size)) {
+ do_return(ATOM_SUCCESS);
+ } else {
+ do_return(ATOM_FAILED);
+ }
+ }
+ if (func <= ATOMBIOS_TEARDOWN) {
+ rhdTearDownAtomBIOS(scrnIndex, handle);
+ do_return(ATOM_SUCCESS);
+ }
+# ifdef ATOM_BIOS_PARSER
+ if (func == ATOMBIOS_EXEC) {
+ if (!rhdAtomExec(handle, data->exec.index,
+ data->exec.pspace, data->exec.dataSpace)) {
+ do_return(ATOM_FAILED);
+ } else {
+ do_return(ATOM_SUCCESS);
+ }
+ } else
+# endif
+ if (func >= ATOM_QUERY_FUNCS && func < ATOM_VRAM_QUERIES) {
+ ret = rhdAtomBIOSFirmwareInfoQuery(scrnIndex, handle, func, &val);
+ data->val = val;
+ } else if (func >= ATOM_VRAM_QUERIES && func < FUNC_END) {
+ ret = rhdAtomBIOSVramInfoQuery(scrnIndex, handle, func, &val);
+ data->val = val;
+ } else {
+ xf86DrvMsg(scrnIndex,X_INFO,"%s: Received unknown query\n",__func__);
+ return ATOM_NOT_IMPLEMENTED;
+ }
+ if (ret == ATOM_SUCCESS)
+ xf86DrvMsg(scrnIndex,X_INFO,"%s: %i 0x%08x\n",
+ AtomBIOSQueryStr[func - ATOM_QUERY_FUNCS], (unsigned int)val, (unsigned int)val);
+ else
+ xf86DrvMsg(scrnIndex,X_INFO,"Query for %s: %s\n",
+ AtomBIOSQueryStr[func - ATOM_QUERY_FUNCS],
+ ret == ATOM_FAILED ? "failed" : "not implemented");
+ return ret;
+
+}
+
+# ifdef ATOM_BIOS_PARSER
+VOID*
+CailAllocateMemory(VOID *CAIL,UINT16 size)
+{
+ CAILFUNC(CAIL);
+
+ return malloc(size);
+}
+
+VOID
+CailReleaseMemory(VOID *CAIL, VOID *addr)
+{
+ CAILFUNC(CAIL);
+
+ free(addr);
+}
+
+VOID
+CailDelayMicroSeconds(VOID *CAIL, UINT32 delay)
+{
+ CAILFUNC(CAIL);
+
+ usleep(delay);
+
+ // DEBUGP(xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay));
+}
+
+UINT32
+CailReadATIRegister(VOID* CAIL, UINT32 index)
+{
+ UINT32 ret;
+ ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CAILFUNC(CAIL);
+
+ ret = INREG(index << 2);
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index << 2,ret));
+ return ret;
+}
+
+VOID
+CailWriteATIRegister(VOID *CAIL, UINT32 index, UINT32 data)
+{
+ CAILFUNC(CAIL);
+ ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ OUTREG(index << 2,data);
+ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index << 2,data));
+}
+
+UINT32
+CailReadFBData(VOID* CAIL, UINT32 index)
+{
+ UINT32 ret;
+ ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ CAILFUNC(CAIL);
+
+ if (((atomBIOSHandlePtr)CAIL)->fbBase) {
+ CARD8 *FBBase = (CARD8*)info->FB;
+ ret = *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + index));
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index,ret));
+ } else if (((atomBIOSHandlePtr)CAIL)->scratchBase) {
+ ret = *(CARD32*)((CARD8*)(((atomBIOSHandlePtr)CAIL)->scratchBase) + index);
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index,ret));
+ } else {
+ xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR,
+ "%s: no fbbase set\n",__func__);
+ return 0;
+ }
+ return ret;
+}
+
+VOID
+CailWriteFBData(VOID *CAIL, UINT32 index, UINT32 data)
+{
+ CAILFUNC(CAIL);
+
+ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index,data));
+ if (((atomBIOSHandlePtr)CAIL)->fbBase) {
+ CARD8 *FBBase = (CARD8*)
+ RADEONPTR(xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex])->FB;
+ *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + index)) = data;
+ } else if (((atomBIOSHandlePtr)CAIL)->scratchBase) {
+ *(CARD32*)((CARD8*)(((atomBIOSHandlePtr)CAIL)->scratchBase) + index) = data;
+ } else
+ xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR,
+ "%s: no fbbase set\n",__func__);
+}
+
+ULONG
+CailReadMC(VOID *CAIL, ULONG Address)
+{
+ ULONG ret;
+ ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ CAILFUNC(CAIL);
+
+ ret = AVIVOINMC(pScrn, Address);
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));
+ return ret;
+}
+
+VOID
+CailWriteMC(VOID *CAIL, ULONG Address, ULONG data)
+{
+ CAILFUNC(CAIL);
+ ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data));
+ AVIVOOUTMC(pScrn, Address, data);
+}
+
+VOID
+CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 index,UINT16 size)
+{
+#if !XSERVER_LIBPCIACCESS
+ PCITAG tag = ((atomBIOSHandlePtr)CAIL)->PciTag;
+
+ CAILFUNC(CAIL);
+
+ switch (size) {
+ case 8:
+ *(CARD8*)ret = pciReadByte(tag,index << 2);
+ break;
+ case 16:
+ *(CARD16*)ret = pciReadWord(tag,index << 2);
+ break;
+ case 32:
+ *(CARD32*)ret = pciReadLong(tag,index << 2);
+ break;
+ default:
+ xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,
+ X_ERROR,"%s: Unsupported size: %i\n",
+ __func__,(int)size);
+ return;
+ break;
+ }
+#else
+ struct pci_device *device = ((atomBIOSHandlePtr)CAIL)->device;
+
+ CAILFUNC(CAIL);
+
+ switch (size) {
+ case 8:
+ pci_device_cfg_read_u8(device, (CARD8*)ret, index << 2);
+ break;
+ case 16:
+ pci_device_cfg_read_u16(device, (CARD16*)ret, index << 2);
+ break;
+ case 32:
+ pci_device_cfg_read_u32(device, (uint32_t*)ret, index << 2);
+ break;
+ default:
+ xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,
+ X_ERROR,"%s: Unsupported size: %i\n",
+ __func__,(int)size);
+ return;
+ break;
+ }
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index,*(unsigned int*)ret));
+#endif
+}
+
+VOID
+CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 index,UINT16 size)
+{
+#if !XSERVER_LIBPCIACCESS
+ PCITAG tag = ((atomBIOSHandlePtr)CAIL)->PciTag;
+
+ CAILFUNC(CAIL);
+ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index,(*(unsigned int*)src)));
+ switch (size) {
+ case 8:
+ pciWriteByte(tag,index << 2,*(CARD8*)src);
+ break;
+ case 16:
+ pciWriteWord(tag,index << 2,*(CARD16*)src);
+ break;
+ case 32:
+ pciWriteLong(tag,index << 2,*(CARD32*)src);
+ break;
+ default:
+ xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR,
+ "%s: Unsupported size: %i\n",__func__,(int)size);
+ break;
+ }
+#else
+ struct pci_device *device = ((atomBIOSHandlePtr)CAIL)->device;
+
+ CAILFUNC(CAIL);
+ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index,(*(unsigned int*)src)));
+ switch (size) {
+ case 8:
+ pci_device_cfg_write_u8(device,index << 2,*(CARD8*)src);
+ break;
+ case 16:
+ pci_device_cfg_write_u16(device,index << 2,*(uint16_t *)src);
+ break;
+ case 32:
+ pci_device_cfg_write_u32(device,index << 2,*(uint32_t *)src);
+ break;
+ default:
+ xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR,
+ "%s: Unsupported size: %i\n",__func__,(int)size);
+ break;
+ }
+#endif
+}
+
+ULONG
+CailReadPLL(VOID *CAIL, ULONG Address)
+{
+ ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ ULONG ret;
+
+ CAILFUNC(CAIL);
+
+ ret = RADEONINPLL(pScrn, Address);
+ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));
+ return ret;
+}
+
+VOID
+CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data)
+{
+ ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CAILFUNC(CAIL);
+
+ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data));
+ RADEONOUTPLL(pScrn, Address, Data);
+}
+
+void
+rhdTestAtomBIOS(atomBIOSHandlePtr atomBIOS)
+{
+ READ_EDID_FROM_HW_I2C_DATA_PARAMETERS i2cData;
+ AtomBIOSArg data;
+ int i;
+ unsigned char *space;
+
+ i2cData.usPrescale = 0x7fff;
+ i2cData.usVRAMAddress = 0;
+ i2cData.usStatus = 128;
+ i2cData.ucSlaveAddr = 0xA0;
+
+ data.exec.dataSpace = (void*)&space;
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, ReadEDIDFromHWAssistedI2C);
+ data.exec.pspace = &i2cData;
+
+ for (i = 0; i < 4; i++) {
+ i2cData.ucLineNumber = i;
+ if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ int j;
+ CARD8 chksum = 0;
+ xf86DrvMsg(atomBIOS->scrnIndex, X_INFO,"%s: I2C channel %i STATUS: %x\n",
+ __func__,i,i2cData.usStatus);
+ /* read good ? */
+ if ((i2cData.usStatus >> 8) == HW_ASSISTED_I2C_STATUS_SUCCESS) {
+ /* checksum good? */
+ ErrorF("i2c data ustatus good %04X\n", i2cData.usStatus);
+ if (!(i2cData.usStatus & 0xff)) {
+#if 0
+ RhdDebugDump(atomBIOS->scrnIndex, space, 128);
+#endif
+ for (j = 0; j < 128; j++)
+ chksum += space[i];
+ xf86DrvMsg(atomBIOS->scrnIndex, X_INFO, "DDC Checksum: %i\n",chksum);
+ }
+ }
+ }
+ }
+}
+# endif
+
+#else /* ATOM_BIOS */
+
+AtomBiosResult
+RHDAtomBIOSFunc(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func,
+ AtomBIOSArgPtr data)
+{
+ assert (sizeof(AtomBIOSQueryStr) == (FUNC_END - ATOM_QUERY_FUNCS + 1));
+
+ if (func < ATOM_QUERY_FUNCS) {
+ if (func >= 0 && func < sizeof(AtomBIOSFuncStr))
+ xf86DrvMsgVerb(scrnIndex, 5, X_WARNING,
+ "AtomBIOS support not available, cannot execute %s\n",
+ AtomBIOSFuncStr[func]);
+ else
+ xf86DrvMsg(scrnIndex, X_ERROR,"Invalid AtomBIOS func %x\n",func);
+ } else {
+
+ if (func < FUNC_END)
+ xf86DrvMsgVerb(scrnIndex, 5, X_WARNING,
+ "AtomBIOS not available, cannot get %s\n",
+ AtomBIOSQueryStr[func - ATOM_QUERY_FUNCS]);
+ else
+ xf86DrvMsg(scrnIndex, X_ERROR, "Invalid AtomBIOS query %x\n",func);
+ }
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+#endif /* ATOM_BIOS */
+
+
+AtomBiosResult
+RADEONAtomBIOSSetCrtcSource(atomBIOSHandlePtr atomBIOS, int crtc, int output_mask)
+{
+ SELECT_CRTC_SOURCE_PARAMETERS crtc_data;
+ AtomBIOSArg data;
+ unsigned char *space;
+
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucDevice = ATOM_DEVICE_CRT1_SUPPORT;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC source success\n");
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Set CRTC source failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+void
+atombios_get_command_table_version(atomBIOSHandlePtr atomBIOS, int index, int *major, int *minor)
+{
+ ATOM_MASTER_COMMAND_TABLE *cmd_table = atomBIOS->BIOSBase + atomBIOS->cmd_offset;
+ ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start;
+ ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr;
+
+ unsigned short *ptr;
+ unsigned short offset;
+
+ table_start = &cmd_table->ListOfCommandTables;
+
+ offset = *(((unsigned short *)table_start) + index);
+
+ table_hdr = atomBIOS->BIOSBase + offset;
+
+ *major = table_hdr->CommonHeader.ucTableFormatRevision;
+ *minor = table_hdr->CommonHeader.ucTableContentRevision;
+}
diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h
new file mode 100644
index 0000000..b9ce53a
--- /dev/null
+++ b/src/radeon_atombios.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright 2007 Egbert Eich <eich at novell.com>
+ * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+ * Copyright 2007 Matthias Hopf <mhopf at novell.com>
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef RHD_ATOMBIOS_H_
+# define RHD_ATOMBIOS_H_
+
+#include "radeon.h"
+
+typedef enum {
+ ATOMBIOS_INIT,
+ ATOMBIOS_TEARDOWN,
+ ATOMBIOS_EXEC,
+ ATOMBIOS_ALLOCATE_FB_SCRATCH,
+ ATOM_QUERY_FUNCS = 0x1000,
+ GET_DEFAULT_ENGINE_CLOCK = ATOM_QUERY_FUNCS,
+ GET_DEFAULT_MEMORY_CLOCK,
+ GET_MAX_PIXEL_CLOCK_PLL_OUTPUT,
+ GET_MIN_PIXEL_CLOCK_PLL_OUTPUT,
+ GET_MAX_PIXEL_CLOCK_PLL_INPUT,
+ GET_MIN_PIXEL_CLOCK_PLL_INPUT,
+ GET_MAX_PIXEL_CLK,
+ GET_REF_CLOCK,
+ ATOM_VRAM_QUERIES,
+ GET_FW_FB_START = ATOM_VRAM_QUERIES,
+ GET_FW_FB_SIZE,
+ ATOM_TMDS_QUERIES,
+ ATOM_TMDS_FREQUENCY = ATOM_TMDS_QUERIES,
+ ATOM_TMDS_PLL_CHARGE_PUMP,
+ ATOM_TMDS_PLL_DUTY_CYCLE,
+ ATOM_TMDS_PLL_VCO_GAIN,
+ ATOM_TMDS_PLL_VOLTAGE_SWING,
+ FUNC_END
+} AtomBiosFunc;
+
+typedef enum {
+ ATOM_SUCCESS,
+ ATOM_FAILED,
+ ATOM_NOT_IMPLEMENTED
+} AtomBiosResult;
+
+typedef struct {
+ int index;
+ pointer pspace;
+ pointer *dataSpace;
+} AtomExec, *AtomExecPtr;
+
+typedef struct {
+ unsigned int start;
+ unsigned int size;
+} AtomFb, *AtomFbPtr;
+
+typedef union
+{
+ CARD32 val;
+
+ pointer ptr;
+ atomBIOSHandlePtr atomp;
+ AtomExec exec;
+ AtomFb fb;
+} AtomBIOSArg, *AtomBIOSArgPtr;
+
+
+extern void
+atombios_get_command_table_version(atomBIOSHandlePtr atomBIOS, int index, int *major, int *minor);
+
+extern AtomBiosResult
+RHDAtomBIOSFunc(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func,
+ AtomBIOSArgPtr data);
+
+/* only for testing */
+void rhdTestAtomBIOS(atomBIOSHandlePtr atomBIOS);
+
+#ifdef ATOM_BIOS
+//# include "rhd_atomwrapper.h"
+# include "xf86int10.h"
+# ifdef ATOM_BIOS_PARSER
+# define INT8 INT8
+# define INT16 INT16
+# define INT32 INT32
+# include "CD_Common_Types.h"
+# else
+# ifndef ULONG
+typedef unsigned int ULONG;
+# define ULONG ULONG
+# endif
+# ifndef UCHAR
+typedef unsigned char UCHAR;
+# define UCHAR UCHAR
+# endif
+# ifndef USHORT
+typedef unsigned short USHORT;
+# define USHORT USHORT
+# endif
+# endif
+
+#include "atombios.h"
+
+
+typedef struct _atomDataTables
+{
+ unsigned char *UtilityPipeLine;
+ ATOM_MULTIMEDIA_CAPABILITY_INFO *MultimediaCapabilityInfo;
+ ATOM_MULTIMEDIA_CONFIG_INFO *MultimediaConfigInfo;
+ ATOM_STANDARD_VESA_TIMING *StandardVESA_Timing;
+ union {
+ void *base;
+ ATOM_FIRMWARE_INFO *FirmwareInfo;
+ ATOM_FIRMWARE_INFO_V1_2 *FirmwareInfo_V_1_2;
+ ATOM_FIRMWARE_INFO_V1_3 *FirmwareInfo_V_1_3;
+ ATOM_FIRMWARE_INFO_V1_4 *FirmwareInfo_V_1_4;
+ } FirmwareInfo;
+ ATOM_DAC_INFO *DAC_Info;
+ union {
+ void *base;
+ ATOM_LVDS_INFO *LVDS_Info;
+ ATOM_LVDS_INFO_V12 *LVDS_Info_v12;
+ } LVDS_Info;
+ ATOM_TMDS_INFO *TMDS_Info;
+ ATOM_ANALOG_TV_INFO *AnalogTV_Info;
+ union {
+ void *base;
+ ATOM_SUPPORTED_DEVICES_INFO *SupportedDevicesInfo;
+ ATOM_SUPPORTED_DEVICES_INFO_2 *SupportedDevicesInfo_2;
+ ATOM_SUPPORTED_DEVICES_INFO_2d1 *SupportedDevicesInfo_2d1;
+ } SupportedDevicesInfo;
+ ATOM_GPIO_I2C_INFO *GPIO_I2C_Info;
+ ATOM_VRAM_USAGE_BY_FIRMWARE *VRAM_UsageByFirmware;
+ ATOM_GPIO_PIN_LUT *GPIO_Pin_LUT;
+ ATOM_VESA_TO_INTENAL_MODE_LUT *VESA_ToInternalModeLUT;
+ union {
+ void *base;
+ ATOM_COMPONENT_VIDEO_INFO *ComponentVideoInfo;
+ ATOM_COMPONENT_VIDEO_INFO_V21 *ComponentVideoInfo_v21;
+ } ComponentVideoInfo;
+/**/unsigned char *PowerPlayInfo;
+ COMPASSIONATE_DATA *CompassionateData;
+ ATOM_DISPLAY_DEVICE_PRIORITY_INFO *SaveRestoreInfo;
+/**/unsigned char *PPLL_SS_Info;
+ ATOM_OEM_INFO *OemInfo;
+ ATOM_XTMDS_INFO *XTMDS_Info;
+ ATOM_ASIC_MVDD_INFO *MclkSS_Info;
+ ATOM_OBJECT_HEADER *Object_Header;
+ INDIRECT_IO_ACCESS *IndirectIOAccess;
+ ATOM_MC_INIT_PARAM_TABLE *MC_InitParameter;
+/**/unsigned char *ASIC_VDDC_Info;
+ ATOM_ASIC_INTERNAL_SS_INFO *ASIC_InternalSS_Info;
+/**/unsigned char *TV_VideoMode;
+ union {
+ void *base;
+ ATOM_VRAM_INFO_V2 *VRAM_Info_v2;
+ ATOM_VRAM_INFO_V3 *VRAM_Info_v3;
+ } VRAM_Info;
+ ATOM_MEMORY_TRAINING_INFO *MemoryTrainingInfo;
+ union {
+ void *base;
+ ATOM_INTEGRATED_SYSTEM_INFO *IntegratedSystemInfo;
+ ATOM_INTEGRATED_SYSTEM_INFO_V2 *IntegratedSystemInfo_v2;
+ } IntegratedSystemInfo;
+ ATOM_ASIC_PROFILING_INFO *ASIC_ProfilingInfo;
+ ATOM_VOLTAGE_OBJECT_INFO *VoltageObjectInfo;
+ ATOM_POWER_SOURCE_INFO *PowerSourceInfo;
+} atomDataTables, *atomDataTablesPtr;
+
+typedef struct _atomBIOSHandle {
+ int scrnIndex;
+ unsigned char *BIOSBase;
+ atomDataTablesPtr atomDataPtr;
+ pointer *scratchBase;
+ CARD32 fbBase;
+ int cmd_offset;
+#if XSERVER_LIBPCIACCESS
+ struct pci_device *device;
+#else
+ PCITAG PciTag;
+#endif
+} atomBIOSHandle;
+
+#endif
+#endif /* RHD_ATOMBIOS_H_ */
diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c
new file mode 100644
index 0000000..cdcb532
--- /dev/null
+++ b/src/radeon_atomwrapper.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+ * Copyright 2007 Matthias Hopf <mhopf at novell.com>
+ * Copyright 2007 Egbert Eich <eich at novell.com>
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "radeon_atomwrapper.h"
+
+#define INT32 INT32
+#include "CD_Common_Types.h"
+#include "CD_Definitions.h"
+
+
+int
+ParseTableWrapper(void *pspace, int index, void *handle, void *BIOSBase,
+ char **msg_return)
+{
+ DEVICE_DATA deviceData;
+ int ret = 0;
+
+ /* FILL OUT PARAMETER SPACE */
+ deviceData.pParameterSpace = (UINT32*) pspace;
+ deviceData.CAIL = handle;
+ deviceData.pBIOS_Image = BIOSBase;
+ deviceData.format = TABLE_FORMAT_BIOS;
+
+ switch (ParseTable(&deviceData, index)) { /* IndexInMasterTable */
+ case CD_SUCCESS:
+ ret = 1;
+ *msg_return = "ParseTable said: CD_SUCCESS";
+ break;
+ case CD_CALL_TABLE:
+ ret = 1;
+ *msg_return = "ParseTable said: CD_CALL_TABLE";
+ break;
+ case CD_COMPLETED:
+ ret = 1;
+ *msg_return = "ParseTable said: CD_COMPLETED";
+ break;
+ case CD_GENERAL_ERROR:
+ ret = 0;
+ *msg_return = " ParseTable said: CD_GENERAL_ERROR";
+ break;
+ case CD_INVALID_OPCODE:
+ ret = 0;
+ *msg_return = " ParseTable said: CD_INVALID_OPCODE";
+ break;
+ case CD_NOT_IMPLEMENTED:
+ ret = 0;
+ *msg_return = " ParseTable said: CD_NOT_IMPLEMENTED";
+ break;
+ case CD_EXEC_TABLE_NOT_FOUND:
+ ret = 0;
+ *msg_return = " ParseTable said: CD_EXEC_TABLE_NOT_FOUND";
+ break;
+ case CD_EXEC_PARAMETER_ERROR:
+ ret = 0;
+ *msg_return = " ParseTable said: CD_EXEC_PARAMETER_ERROR";
+ break;
+ case CD_EXEC_PARSER_ERROR:
+ ret = 0;
+ *msg_return = " ParseTable said: CD_EXEC_PARSER_ERROR";
+ break;
+ case CD_INVALID_DESTINATION_TYPE:
+ ret = 0;
+ *msg_return = " ParseTable said: CD_INVALID_DESTINATION_TYPE";
+ break;
+ case CD_UNEXPECTED_BEHAVIOR:
+ ret = 0;
+ *msg_return = " ParseTable said: CD_UNEXPECTED_BEHAVIOR";
+ break;
+ case CD_INVALID_SWITCH_OPERAND_SIZE:
+ ret = 0;
+ *msg_return = " ParseTable said: CD_INVALID_SWITCH_OPERAND_SIZE\n";
+ break;
+ }
+ return ret;
+}
diff --git a/src/radeon_atomwrapper.h b/src/radeon_atomwrapper.h
new file mode 100644
index 0000000..1e7cc77
--- /dev/null
+++ b/src/radeon_atomwrapper.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+ * Copyright 2007 Matthias Hopf <mhopf at novell.com>
+ * Copyright 2007 Egbert Eich <eich at novell.com>
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef RHD_ATOMWRAPPER_H_
+# define RHD_ATOMWRAPPER_H_
+
+extern int ParseTableWrapper(void *pspace, int index, void *CAIL,
+ void *BIOSBase, char **msg_return);
+
+#endif /* RHD_ATOMWRAPPER_H_ */
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 66ece94..78fc9ff 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -168,6 +168,15 @@ typedef struct _RADEONCrtcPrivateRec {
int binding;
/* Lookup table values to be set when the CRTC is enabled */
CARD8 lut_r[256], lut_g[256], lut_b[256];
+
+ uint32_t crtc_offset;
+ int h_total, h_blank, h_sync_wid, h_sync_pol;
+ int v_total, v_blank, v_sync_wid, v_sync_pol;
+ int fb_format, fb_length;
+ int fb_pitch, fb_width, fb_height;
+ INT16 cursor_x;
+ INT16 cursor_y;
+ unsigned long cursor_offset;
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct {
@@ -176,6 +185,7 @@ typedef struct {
RADEONTmdsType TMDSType;
RADEONConnectorType ConnectorType;
Bool valid;
+ int gpio;
} RADEONBIOSConnector;
typedef struct _RADEONOutputPrivateRec {
@@ -221,6 +231,9 @@ typedef struct _RADEONOutputPrivateRec {
int SupportedTVStds;
Bool tv_on;
int load_detection;
+
+ unsigned long gpio;
+ char *name;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
#define RADEON_MAX_CRTC 2
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