xf86-video-ati: Branch 'atombios-support' - 13 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Dec 17 17:20:21 PST 2007
src/atombios_crtc.c | 4
src/radeon.h | 12 ++
src/radeon_bios.c | 2
src/radeon_crtc.c | 71 +++++++----
src/radeon_display.c | 285 ++++++++++++++++++++++++++----------------------
src/radeon_dri.c | 15 --
src/radeon_driver.c | 6 -
src/radeon_exa_render.c | 93 +++++++++------
src/radeon_output.c | 17 ++
src/radeon_reg.h | 1
10 files changed, 297 insertions(+), 209 deletions(-)
New commits:
commit 03b8b49f6f502c45552b018fd8c44d366b2d576f
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Dec 17 20:20:04 2007 -0500
RADEON: fix typo from merge
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index d2271b0..5e9db39 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -625,7 +625,7 @@ static int RADEONDiv(int n, int d)
return (n + (d / 2)) / d;
}
-static void
+void
RADEONComputePLL(RADEONPLLPtr pll,
unsigned long freq,
CARD32 *chosen_dot_clock_freq,
commit 19b9d3708852b7efe2b05249c8359dadb924dd94
Merge: cf685f3... 29706ca...
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Dec 17 20:07:32 2007 -0500
Merge branch 'atombios-support' of git+ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
commit cf685f37ec874f0aacd09e7c4eb0402c6daec1b0
Merge: 2a134af... 44d07c4...
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Dec 17 20:07:07 2007 -0500
Merge branch 'master' of git+ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
merge master and fix conflicts
diff --cc src/atombios_crtc.c
index 6c7828b,0000000..e7ad4a9
mode 100644,000000..100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@@ -1,381 -1,0 +1,381 @@@
+ /*
+ * Copyright © 2007 Red Hat, Inc.
+ *
+ * PLL code is:
+ * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+ * Copyright 2007 Matthias Hopf <mhopf at novell.com>
+ * Copyright 2007 Egbert Eich <eich at novell.com>
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Dave Airlie <airlied at redhat.com>
+ *
+ */
+/*
+ * avivo crtc handling functions.
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+/* DPMS */
+#define DPMS_SERVER
+#include <X11/extensions/dpms.h>
+
+#include "radeon.h"
+#include "radeon_reg.h"
+#include "radeon_macros.h"
+#include "radeon_atombios.h"
+
+#ifdef XF86DRI
+#define _XF86DRI_SERVER_
+#include "radeon_dri.h"
+#include "radeon_sarea.h"
+#include "sarea.h"
+#endif
+
+AtomBiosResult
+atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
+{
+ ENABLE_CRTC_PS_ALLOCATION crtc_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucEnable = state;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Enable":"Disable", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Enable CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+AtomBiosResult
+atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
+{
+ BLANK_CRTC_PS_ALLOCATION crtc_data;
+ unsigned char *space;
+ AtomBiosArgRec data;
+
+ memset(&crtc_data, 0, sizeof(crtc_data));
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucBlanking = state;
+
+ data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Blank":"Unblank", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Blank CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+static void
+atombios_crtc_enable(xf86CrtcPtr crtc, int enable)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable);
+
+ //TODOavivo_wait_idle(avivo);
+}
+
+void
+atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ switch (mode) {
+ case DPMSModeOn:
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ case DPMSModeOff:
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ }
+}
+
+static AtomBiosResult
+atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
+{
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = crtc_param;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC Timing success\n");
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Set CRTC Timing failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+void
+atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ CARD32 sclock = mode->Clock;
+ CARD32 ref_div = 0, fb_div = 0, post_div = 0;
+ int major, minor;
+ SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
+ void *ptr;
+ AtomBiosArgRec data;
+ unsigned char *space;
+ RADEONSavePtr save = info->ModeReg;
+
+ if (IS_AVIVO_VARIANT) {
+ CARD32 temp;
- RADEONComputePLL(&info->pll, mode->Clock * 1000, &temp, &fb_div, &ref_div, &post_div);
- sclock = temp / 10000;
++ RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, 0);
++ sclock = temp;
+
+ /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
+ if (radeon_crtc->crtc_id == 0) {
+ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ } else {
+ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ }
+ } else {
+ sclock = save->dot_clock_freq;
+ fb_div = save->feedback_div;
+ post_div = save->post_div;
+ ref_div = save->ppll_ref_div;
+ }
+
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) Clock: mode %d, PLL %u\n",
+ radeon_crtc->crtc_id, mode->Clock, sclock * 10);
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n",
+ radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ ErrorF("table is %d %d\n", major, minor);
+ switch(major) {
+ case 1:
+ switch(minor) {
+ case 1:
+ case 2: {
+ spc_param.sPCLKInput.usPixelClock = sclock;
+ spc_param.sPCLKInput.usRefDiv = ref_div;
+ spc_param.sPCLKInput.usFbDiv = fb_div;
+ spc_param.sPCLKInput.ucPostDiv = post_div;
+ spc_param.sPCLKInput.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+ spc_param.sPCLKInput.ucCRTC = radeon_crtc->crtc_id;
+ spc_param.sPCLKInput.ucRefDivSrc = 1;
+
+ ptr = &spc_param;
+ break;
+ }
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = ptr;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC PLL success\n");
+ return;
+ }
+
+ ErrorF("Set CRTC PLL failed\n");
+ return;
+}
+
+void
+atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode,
+ int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
+ Bool tilingOld = info->tilingEnabled;
+
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
+
+ memset(&crtc_timing, 0, sizeof(crtc_timing));
+
+ if (info->allowColorTiling) {
+ info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
+#ifdef XF86DRI
+ if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
+ RADEONSAREAPrivPtr pSAREAPriv;
+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "[drm] failed changing tiling status\n");
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
+ info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
+ }
+#endif
+ }
+
+ crtc_timing.ucCRTC = radeon_crtc->crtc_id;
+ crtc_timing.usH_Total = adjusted_mode->CrtcHTotal;
+ crtc_timing.usH_Disp = adjusted_mode->CrtcHDisplay;
+ crtc_timing.usH_SyncStart = adjusted_mode->CrtcHSyncStart;
+ crtc_timing.usH_SyncWidth = adjusted_mode->CrtcHSyncEnd - adjusted_mode->CrtcHSyncStart;
+
+ crtc_timing.usV_Total = adjusted_mode->CrtcVTotal;
+ crtc_timing.usV_Disp = adjusted_mode->CrtcVDisplay;
+ crtc_timing.usV_SyncStart = adjusted_mode->CrtcVSyncStart;
+ crtc_timing.usV_SyncWidth = adjusted_mode->CrtcVSyncEnd - adjusted_mode->CrtcVSyncStart;
+
+ if (adjusted_mode->Flags & V_NVSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
+
+ if (adjusted_mode->Flags & V_NHSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
+
+ ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
+ adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
+
+ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+
+ if (IS_AVIVO_VARIANT) {
+ radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_height = pScrn->virtualY;
+ radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4;
+ switch (crtc->scrn->bitsPerPixel) {
+ case 15:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
+ break;
+ case 16:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
+ break;
+ case 24:
+ case 32:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
+ break;
+ default:
+ FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
+ }
+
+ if (info->tilingEnabled && (crtc->rotatedData == NULL)) {
+ radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
+ }
+
+ if (radeon_crtc->crtc_id == 0)
+ OUTREG(AVIVO_D1VGA_CONTROL, 0);
+ else
+ OUTREG(AVIVO_D2VGA_CONTROL, 0);
+
+ /* setup fb format and location
+ */
+ if (crtc->rotatedData != NULL) {
+ /* x/y offset is already included */
+ x = 0;
+ y = 0;
+ fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB;
+ }
+
+ /* lock the grph regs */
+ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK);
+
+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset,
+ radeon_crtc->fb_format);
+
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualX);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualY);
+ OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
+ crtc->scrn->displayWidth);
+ OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+
+ /* unlock the grph regs */
+ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0);
+
+ /* lock the mode regs */
+ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK);
+
+ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualY);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
+ (mode->HDisplay << 16) | mode->VDisplay);
+ /* unlock the mode regs */
+ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0);
+
+ }
+
+ atombios_crtc_set_pll(crtc, adjusted_mode);
+
+ atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
+
+ if (info->tilingEnabled != tilingOld) {
+ /* need to redraw front buffer, I guess this can be considered a hack ? */
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE);
+ RADEONChangeSurfaces(pScrn);
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE);
+ /* xf86SetRootClip would do, but can't access that here */
+ }
+
+}
+
diff --cc src/radeon.h
index 6cc2b6f,03db360..a5717a0
--- a/src/radeon.h
+++ b/src/radeon.h
@@@ -200,6 -200,176 +200,10 @@@ typedef struct
CARD16 rr4_offset;
} RADEONBIOSInitTable;
-typedef struct {
- /* Common registers */
- CARD32 ovr_clr;
- CARD32 ovr_wid_left_right;
- CARD32 ovr_wid_top_bottom;
- CARD32 ov0_scale_cntl;
- CARD32 mpp_tb_config;
- CARD32 mpp_gp_config;
- CARD32 subpic_cntl;
- CARD32 viph_control;
- CARD32 i2c_cntl_1;
- CARD32 gen_int_cntl;
- CARD32 cap0_trig_cntl;
- CARD32 cap1_trig_cntl;
- CARD32 bus_cntl;
- CARD32 bios_4_scratch;
- CARD32 bios_5_scratch;
- CARD32 bios_6_scratch;
- CARD32 surface_cntl;
- CARD32 surfaces[8][3];
- CARD32 mc_agp_location;
- CARD32 mc_fb_location;
- CARD32 display_base_addr;
- CARD32 display2_base_addr;
- CARD32 ov0_base_addr;
-
- /* Other registers to save for VT switches */
- CARD32 dp_datatype;
- CARD32 rbbm_soft_reset;
- CARD32 clock_cntl_index;
- CARD32 amcgpio_en_reg;
- CARD32 amcgpio_mask;
-
- /* CRTC registers */
- CARD32 crtc_gen_cntl;
- CARD32 crtc_ext_cntl;
- CARD32 dac_cntl;
- CARD32 crtc_h_total_disp;
- CARD32 crtc_h_sync_strt_wid;
- CARD32 crtc_v_total_disp;
- CARD32 crtc_v_sync_strt_wid;
- CARD32 crtc_offset;
- CARD32 crtc_offset_cntl;
- CARD32 crtc_pitch;
- CARD32 disp_merge_cntl;
- CARD32 grph_buffer_cntl;
- CARD32 crtc_more_cntl;
- CARD32 crtc_tile_x0_y0;
-
- /* CRTC2 registers */
- CARD32 crtc2_gen_cntl;
- CARD32 dac_macro_cntl;
- CARD32 dac2_cntl;
- CARD32 disp_output_cntl;
- CARD32 disp_tv_out_cntl;
- CARD32 disp_hw_debug;
- CARD32 disp2_merge_cntl;
- CARD32 grph2_buffer_cntl;
- CARD32 crtc2_h_total_disp;
- CARD32 crtc2_h_sync_strt_wid;
- CARD32 crtc2_v_total_disp;
- CARD32 crtc2_v_sync_strt_wid;
- CARD32 crtc2_offset;
- CARD32 crtc2_offset_cntl;
- CARD32 crtc2_pitch;
- CARD32 crtc2_tile_x0_y0;
-
- /* Flat panel registers */
- CARD32 fp_crtc_h_total_disp;
- CARD32 fp_crtc_v_total_disp;
- CARD32 fp_gen_cntl;
- CARD32 fp2_gen_cntl;
- CARD32 fp_h_sync_strt_wid;
- CARD32 fp_h2_sync_strt_wid;
- CARD32 fp_horz_stretch;
- CARD32 fp_panel_cntl;
- CARD32 fp_v_sync_strt_wid;
- CARD32 fp_v2_sync_strt_wid;
- CARD32 fp_vert_stretch;
- CARD32 lvds_gen_cntl;
- CARD32 lvds_pll_cntl;
- CARD32 tmds_pll_cntl;
- CARD32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- CARD32 dot_clock_freq;
- CARD32 pll_output_freq;
- int feedback_div;
- int reference_div;
- int post_div;
-
- /* PLL registers */
- unsigned ppll_ref_div;
- unsigned ppll_div_3;
- CARD32 htotal_cntl;
- CARD32 vclk_ecp_cntl;
-
- /* Computed values for PLL2 */
- CARD32 dot_clock_freq_2;
- CARD32 pll_output_freq_2;
- int feedback_div_2;
- int reference_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- CARD32 p2pll_ref_div;
- CARD32 p2pll_div_0;
- CARD32 htotal_cntl2;
- CARD32 pixclks_cntl;
-
- /* Pallet */
- Bool palette_valid;
- CARD32 palette[256];
- CARD32 palette2[256];
-
- CARD32 rs480_unk_e30;
- CARD32 rs480_unk_e34;
- CARD32 rs480_unk_e38;
- CARD32 rs480_unk_e3c;
-
- /* TV out registers */
- CARD32 tv_master_cntl;
- CARD32 tv_htotal;
- CARD32 tv_hsize;
- CARD32 tv_hdisp;
- CARD32 tv_hstart;
- CARD32 tv_vtotal;
- CARD32 tv_vdisp;
- CARD32 tv_timing_cntl;
- CARD32 tv_vscaler_cntl1;
- CARD32 tv_vscaler_cntl2;
- CARD32 tv_sync_size;
- CARD32 tv_vrestart;
- CARD32 tv_hrestart;
- CARD32 tv_frestart;
- CARD32 tv_ftotal;
- CARD32 tv_clock_sel_cntl;
- CARD32 tv_clkout_cntl;
- CARD32 tv_data_delay_a;
- CARD32 tv_data_delay_b;
- CARD32 tv_dac_cntl;
- CARD32 tv_pll_cntl;
- CARD32 tv_pll_cntl1;
- CARD32 tv_pll_fine_cntl;
- CARD32 tv_modulator_cntl1;
- CARD32 tv_modulator_cntl2;
- CARD32 tv_frame_lock_cntl;
- CARD32 tv_pre_dac_mux_cntl;
- CARD32 tv_rgb_cntl;
- CARD32 tv_y_saw_tooth_cntl;
- CARD32 tv_y_rise_cntl;
- CARD32 tv_y_fall_cntl;
- CARD32 tv_uv_adr;
- CARD32 tv_upsamp_and_gain_cntl;
- CARD32 tv_gain_limit_settings;
- CARD32 tv_linear_gain_settings;
- CARD32 tv_crc_cntl;
- CARD32 tv_sync_cntl;
- CARD32 gpiopad_a;
- CARD32 pll_test_cntl;
-
- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
-
-} RADEONSaveRec, *RADEONSavePtr;
-
+ #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
+ #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
+ #define RADEON_PLL_USE_REF_DIV (1 << 2)
+
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
@@@ -699,10 -850,14 +703,18 @@@ typedef struct
#endif
RADEONExtTMDSChip ext_tmds_chip;
+ atomBiosHandlePtr atomBIOS;
+ unsigned long FbFreeStart, FbFreeSize;
+ unsigned char* BIOSCopy;
+
+ /* output enable masks for outputs shared across connectors */
+ int output_crt1;
+ int output_crt2;
+ int output_dfp1;
+ int output_dfp2;
+ int output_lcd1;
+ int output_tv1;
+
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
diff --cc src/radeon_bios.c
index 9730119,d150c4b..46a58ca
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@@ -633,13 -473,8 +633,13 @@@ Bool RADEONGetClockInfoFromBIOS (ScrnIn
pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e);
pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10);
- pll->min_pll_freq = RADEON_BIOS32 (pll_info_block + 0x12);
- pll->max_pll_freq = RADEON_BIOS32 (pll_info_block + 0x16);
+ pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12);
+ pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16);
+
+ /* not available in the bios */
+ pll->pll_in_min = 40;
- pll->pll_in_max = 100;
++ pll->pll_in_max = 500;
+
pll->xclk = RADEON_BIOS16 (pll_info_block + 0x08);
info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0;
diff --cc src/radeon_crtc.c
index 611c9ab,41375da..d2271b0
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@@ -637,8 -617,15 +631,11 @@@ RADEONComputePLL(RADEONPLLPtr pll
CARD32 *chosen_dot_clock_freq,
CARD32 *chosen_feedback_div,
CARD32 *chosen_reference_div,
- CARD32 *chosen_post_div)
+ CARD32 *chosen_post_div,
+ int flags)
{
- int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0};
-
- int i;
-
+ CARD32 min_ref_div = pll->min_ref_div;
+ CARD32 max_ref_div = pll->max_ref_div;
CARD32 best_vco = pll->best_vco;
CARD32 best_post_div = 1;
CARD32 best_ref_div = 1;
@@@ -646,18 -633,26 +643,26 @@@
CARD32 best_freq = 1;
CARD32 best_error = 0xffffffff;
CARD32 best_vco_diff = 1;
+ CARD32 post_div;
+ freq = freq / 10;
+
ErrorF("freq: %lu\n", freq);
+ if (flags & RADEON_PLL_USE_REF_DIV)
+ min_ref_div = max_ref_div = pll->reference_div;
+
- for (i = 0; post_divs[i]; i++) {
- int post_div = post_divs[i];
+ for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
CARD32 ref_div;
- CARD32 vco = (freq / 10000) * post_div;
+ CARD32 vco = freq * post_div;
+
+ if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
+ continue;
- if (vco < pll->min_pll_freq || vco > pll->max_pll_freq)
+ if (vco < pll->pll_out_min || vco > pll->pll_out_max)
continue;
- for (ref_div = pll->min_ref_div; ref_div <= pll->max_ref_div; ++ref_div) {
+ for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
CARD32 feedback_div, current_freq, error, vco_diff;
CARD32 pll_in = pll->reference_freq / ref_div;
@@@ -670,8 -665,8 +675,8 @@@
if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div)
continue;
- current_freq = RADEONDiv64((CARD64)pll->reference_freq * 10000 * feedback_div,
- ref_div * post_div);
- current_freq = RADEONDiv(pll->reference_freq * feedback_div,
++ current_freq = RADEONDiv(pll->reference_freq * feedback_div,
+ ref_div * post_div);
error = abs(current_freq - freq);
vco_diff = abs(vco - best_vco);
@@@ -927,11 -934,11 +942,11 @@@ legacy_crtc_mode_set(xf86CrtcPtr crtc,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode);
+ RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags);
} else {
- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
+ info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
+ info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
+ info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl;
}
break;
case 1:
diff --cc src/radeon_driver.c
index 62e7cd0,25b2119..a9756fa
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@@ -1196,15 -1029,11 +1196,15 @@@ static void RADEONGetClockInfo(ScrnInfo
/* Default min/max PLL values */
if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) {
- pll->min_pll_freq = 20000;
- pll->max_pll_freq = 50000;
+ pll->pll_in_min = 100;
+ pll->pll_in_max = 1350;
+ pll->pll_out_min = 20000;
+ pll->pll_out_max = 50000;
} else {
- pll->min_pll_freq = 12500;
- pll->max_pll_freq = 35000;
+ pll->pll_in_min = 40;
- pll->pll_in_max = 100;
++ pll->pll_in_max = 500;
+ pll->pll_out_min = 12500;
+ pll->pll_out_max = 35000;
}
if (RADEONProbePLLParameters(pScrn))
diff --cc src/radeon_output.c
index 02c96ae,c60ece8..519626f
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@@ -1045,9 -985,12 +1049,12 @@@ static void RADEONInitLVDSRegisters(xf8
save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
- save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl;
+ save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl;
save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON |
+ RADEON_LVDS_BLON |
+ RADEON_LVDS_EN |
+ RADEON_LVDS_RST_FM);
if (IS_R300_VARIANT)
save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
commit 44d07c4ccce9acb5bd21a17acb082e91f7225764
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:56:12 2007 -0500
RADEON: typo from last commit
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 95f6b09..6bbd315 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -405,6 +405,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->DACType == DAC_TVDAC) {
info->output_crt2 &= ~(1 << o);
+ tv_dac_change = 1;
if (!info->output_crt2) {
if (info->ChipFamily == CHIP_FAMILY_R200) {
tmp = INREG(RADEON_FP2_GEN_CNTL);
@@ -416,7 +417,6 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
tmp &= ~RADEON_CRTC2_CRT2_ON;
OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
- tv_dac_change = 1;
}
}
}
@@ -462,11 +462,11 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
info->output_tv1 &= ~(1 << o);
+ tv_dac_change = 2;
if (!info->output_tv1) {
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp &= ~RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
radeon_output->tv_on = FALSE;
}
}
commit 4da3782239921eb377216d4de4a9cc5bb55e0e8a
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:51:31 2007 -0500
RADEON: add output enable masks
add output enable masks for outputs that drive
more than one connector. Make sure we don't turn off
an output that's driving another connector.
diff --git a/src/radeon.h b/src/radeon.h
index 67315a2..03db360 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -850,6 +850,14 @@ typedef struct {
#endif
RADEONExtTMDSChip ext_tmds_chip;
+ /* output enable masks for outputs shared across connectors */
+ int output_crt1;
+ int output_crt2;
+ int output_dfp1;
+ int output_dfp2;
+ int output_lcd1;
+ int output_tv1;
+
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 9437ef4..95f6b09 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -322,19 +322,28 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
unsigned char * RADEONMMIO = info->MMIO;
unsigned long tmp;
RADEONOutputPrivatePtr radeon_output;
- int tv_dac_change = 0;
+ int tv_dac_change = 0, o;
radeon_output = output->driver_private;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+
+ for (o = 0; o < xf86_config->num_output; o++) {
+ if (output == xf86_config->output[o]) {
+ break;
+ }
+ }
if (bEnable) {
ErrorF("enable montype: %d\n", radeon_output->MonType);
if (radeon_output->MonType == MT_CRT) {
if (radeon_output->DACType == DAC_PRIMARY) {
+ info->output_crt1 |= (1 << o);
tmp = INREG(RADEON_CRTC_EXT_CNTL);
tmp |= RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
} else if (radeon_output->DACType == DAC_TVDAC) {
+ info->output_crt2 |= (1 << o);
if (info->ChipFamily == CHIP_FAMILY_R200) {
tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
@@ -350,11 +359,13 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->MonType == MT_DFP) {
if (radeon_output->TMDSType == TMDS_INT) {
+ info->output_dfp1 |= (1 << o);
tmp = INREG(RADEON_FP_GEN_CNTL);
tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
OUTREG(RADEON_FP_GEN_CNTL, tmp);
save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
} else if (radeon_output->TMDSType == TMDS_EXT) {
+ info->output_dfp2 |= (1 << o);
tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp &= ~RADEON_FP2_BLANK_EN;
tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
@@ -363,6 +374,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
}
} else if (radeon_output->MonType == MT_LCD) {
+ info->output_lcd1 |= (1 << o);
tmp = INREG(RADEON_LVDS_GEN_CNTL);
tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
@@ -372,6 +384,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
} else if (radeon_output->MonType == MT_STV ||
radeon_output->MonType == MT_CTV) {
+ info->output_tv1 |= (1 << o);
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp |= RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
@@ -382,70 +395,88 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
ErrorF("disable montype: %d\n", radeon_output->MonType);
if (radeon_output->MonType == MT_CRT) {
if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ info->output_crt1 &= ~(1 << o);
+ if (!info->output_crt1) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp &= ~RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ }
} else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ info->output_crt2 &= ~(1 << o);
+ if (!info->output_crt2) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ tv_dac_change = 1;
+ }
}
- tv_dac_change = 1;
}
} else if (radeon_output->MonType == MT_DFP) {
if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ info->output_dfp1 &= ~(1 << o);
+ if (!info->output_dfp1) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ }
} else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= RADEON_FP2_BLANK_EN;
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ info->output_dfp2 &= ~(1 << o);
+ if (!info->output_dfp2) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= RADEON_FP2_BLANK_EN;
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ }
}
} else if (radeon_output->MonType == MT_LCD) {
- unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- if (info->IsMobility || info->IsIGP) {
- /* Asic bug, when turning off LVDS_ON, we have to make sure
- RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
- */
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
- }
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- if (info->IsMobility || info->IsIGP) {
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ info->output_lcd1 &= ~(1 << o);
+ if (!info->output_lcd1) {
+ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ if (info->IsMobility || info->IsIGP) {
+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
}
} else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
- tmp = INREG(RADEON_TV_MASTER_CNTL);
- tmp &= ~RADEON_TV_ON;
- OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
- radeon_output->tv_on = FALSE;
+ info->output_tv1 &= ~(1 << o);
+ if (!info->output_tv1) {
+ tmp = INREG(RADEON_TV_MASTER_CNTL);
+ tmp &= ~RADEON_TV_ON;
+ OUTREG(RADEON_TV_MASTER_CNTL, tmp);
+ tv_dac_change = 2;
+ radeon_output->tv_on = FALSE;
+ }
}
}
if (tv_dac_change) {
if (bEnable)
- info->tv_dac_enable_mask |= tv_dac_change;
+ info->tv_dac_enable_mask |= tv_dac_change;
else
- info->tv_dac_enable_mask &= ~tv_dac_change;
+ info->tv_dac_enable_mask &= ~tv_dac_change;
if (bEnable && info->tv_dac_enable_mask)
RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 9e73c08..c60ece8 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -3207,6 +3207,14 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
}
}
+ /* clear the enable masks */
+ info->output_crt1 = 0;
+ info->output_crt2 = 0;
+ info->output_dfp1 = 0;
+ info->output_dfp2 = 0;
+ info->output_lcd1 = 0;
+ info->output_tv1 = 0;
+
for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
commit 5c5d2d19b2b032a06dd333b4ecc029aac342fb93
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:15:55 2007 -0500
RADEON: whitespace clean-ups
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 999d349..9437ef4 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -163,7 +163,7 @@ void RADEONGetTVDacAdjInfo(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
+
/* Todo: get this setting from BIOS */
radeon_output->tv_dac_adj = default_tvdac_adj[info->ChipFamily];
if (info->IsMobility) { /* some mobility chips may different */
@@ -202,7 +202,7 @@ static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC)
} else {
CARD32 tv_dac_cntl;
CARD32 fp2_gen_cntl;
-
+
switch(info->ChipFamily)
{
case CHIP_FAMILY_R420:
@@ -259,19 +259,19 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) {
/* primary DAC */
tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
+ tmp &= ~RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
RADEONDacPowerSet(pScrn, FALSE, TRUE);
/* Secondary DAC */
if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
} else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
}
RADEONDacPowerSet(pScrn, FALSE, FALSE);
@@ -327,95 +327,95 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
if (bEnable) {
ErrorF("enable montype: %d\n", radeon_output->MonType);
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp |= RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp |= RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
- }
- tv_dac_change = 1;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp |= RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp |= RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+ }
+ tv_dac_change = 1;
+ }
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->TMDSType == TMDS_INT) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ } else if (radeon_output->TMDSType == TMDS_EXT) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp &= ~RADEON_FP2_BLANK_EN;
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
- }
- } else if (radeon_output->MonType == MT_LCD) {
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
+ }
+ } else if (radeon_output->MonType == MT_LCD) {
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
usleep (radeon_output->PanelPwrDly * 1000);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
- } else if (radeon_output->MonType == MT_STV ||
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
+ } else if (radeon_output->MonType == MT_STV ||
radeon_output->MonType == MT_CTV) {
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp |= RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
+ tv_dac_change = 2;
radeon_output->tv_on = TRUE;
}
} else {
ErrorF("disable montype: %d\n", radeon_output->MonType);
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
- }
- tv_dac_change = 1;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp &= ~RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ }
+ tv_dac_change = 1;
+ }
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->TMDSType == TMDS_INT) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ } else if (radeon_output->TMDSType == TMDS_EXT) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp |= RADEON_FP2_BLANK_EN;
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
- }
- } else if (radeon_output->MonType == MT_LCD) {
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ }
+ } else if (radeon_output->MonType == MT_LCD) {
unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
if (info->IsMobility || info->IsIGP) {
/* Asic bug, when turning off LVDS_ON, we have to make sure
@@ -423,20 +423,20 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
*/
OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
}
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
if (info->IsMobility || info->IsIGP) {
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
}
- } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
+ } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp &= ~RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
+ tv_dac_change = 2;
radeon_output->tv_on = FALSE;
}
}
@@ -487,13 +487,13 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
int stop_req, max_stop_req;
float read_return_rate, time_disp1_drop_priority;
- /*
- * Set display0/1 priority up on r3/4xx in the memory controller for
- * high res modes if the user specifies HIGH for displaypriority
+ /*
+ * Set display0/1 priority up on r3/4xx in the memory controller for
+ * high res modes if the user specifies HIGH for displaypriority
* option.
*/
if ((info->DispPriority == 2) && IS_R300_VARIANT) {
- CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
+ CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
if (pRADEONEnt->pCrtc[1]->enabled) {
mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */
} else {
@@ -522,14 +522,14 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
peak_disp_bw += (pix_clk2 * pixel_bytes2);
if (peak_disp_bw >= mem_bw * min_mem_eff) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"You may not have enough display bandwidth for current mode\n"
"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
- }
+ }
/* CRTC1
Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
+ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
*/
stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16;
@@ -540,7 +540,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
max_stop_req = 0x7c;
if (stop_req > max_stop_req)
stop_req = max_stop_req;
-
+
/* Get values from the EXT_MEM_CNTL register...converting its contents. */
temp = INREG(RADEON_MEM_TIMING_CNTL);
if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
@@ -552,8 +552,8 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8];
mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12];
}
-
- /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
+
+ /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
temp = INREG(RADEON_MEM_SDRAM_MODE_REG);
data = (temp & (7<<20)) >> 20;
if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
@@ -625,7 +625,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
}
mc_latency_sclk = sclk_delay / sclk_eff;
-
+
if (info->IsDDR) {
if (info->RamWidth == 32) {
k1 = 40;
@@ -667,7 +667,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
/*
Find the critical point of the display buffer.
*/
- critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5);
+ critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5);
/* ???? */
/*
@@ -682,7 +682,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
The critical point should never be above max_stop_req-4. Setting
GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
*/
- if (max_stop_req - critical_point < 4) critical_point = 0;
+ if (max_stop_req - critical_point < 4) critical_point = 0;
if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) {
/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
@@ -733,7 +733,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
RADEON_GRPH_CRITICAL_AT_SOF |
RADEON_GRPH_STOP_CNTL);
- if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+ if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200))
critical_point2 = 0;
else {
@@ -810,7 +810,7 @@ void RADEONBlank(ScrnInfoPtr pScrn)
for (c = 0; c < xf86_config->num_crtc; c++) {
crtc = xf86_config->crtc[c];
- for (o = 0; o < xf86_config->num_output; o++) {
+ for (o = 0; o < xf86_config->num_output; o++) {
output = xf86_config->output[o];
if (output->crtc != crtc)
continue;
@@ -833,7 +833,7 @@ void RADEONUnblank(ScrnInfoPtr pScrn)
if(!crtc->enabled)
continue;
crtc->funcs->dpms(crtc, DPMSModeOn);
- for (o = 0; o < xf86_config->num_output; o++) {
+ for (o = 0; o < xf86_config->num_output; o++) {
output = xf86_config->output[o];
if (output->crtc != crtc)
continue;
commit 9f1d8220315c8894a17f2cc328025dc682b0c6e0
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:04:05 2007 -0500
RADEON: more PLL fixes
- reduce the calculation accuracy
- certain LVDS panels seem to only like certain ref_divs
- add pll flags to handle special cases
- adjust the pll limits on legacy cards
diff --git a/src/radeon.h b/src/radeon.h
index 960266e..67315a2 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -366,6 +366,10 @@ typedef struct {
} RADEONSaveRec, *RADEONSavePtr;
+#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
+#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
+#define RADEON_PLL_USE_REF_DIV (1 << 2)
+
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index ebb8c52..41375da 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -606,7 +606,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
}
-static CARD32 RADEONDiv64(CARD64 n, CARD32 d)
+static int RADEONDiv(int n, int d)
{
return (n + (d / 2)) / d;
}
@@ -617,12 +617,15 @@ RADEONComputePLL(RADEONPLLPtr pll,
CARD32 *chosen_dot_clock_freq,
CARD32 *chosen_feedback_div,
CARD32 *chosen_reference_div,
- CARD32 *chosen_post_div)
+ CARD32 *chosen_post_div,
+ int flags)
{
int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0};
int i;
+ CARD32 min_ref_div = pll->min_ref_div;
+ CARD32 max_ref_div = pll->max_ref_div;
CARD32 best_vco = pll->best_vco;
CARD32 best_post_div = 1;
CARD32 best_ref_div = 1;
@@ -631,38 +634,46 @@ RADEONComputePLL(RADEONPLLPtr pll,
CARD32 best_error = 0xffffffff;
CARD32 best_vco_diff = 1;
+ freq = freq / 10;
+
ErrorF("freq: %lu\n", freq);
+ if (flags & RADEON_PLL_USE_REF_DIV)
+ min_ref_div = max_ref_div = pll->reference_div;
+
for (i = 0; post_divs[i]; i++) {
int post_div = post_divs[i];
CARD32 ref_div;
- CARD32 vco = (freq / 10000) * post_div;
+ CARD32 vco = freq * post_div;
+
+ if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
+ continue;
if (vco < pll->min_pll_freq || vco > pll->max_pll_freq)
continue;
- for (ref_div = pll->min_ref_div; ref_div <= pll->max_ref_div; ++ref_div) {
+ for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
CARD32 feedback_div, current_freq, error, vco_diff;
CARD32 pll_in = pll->reference_freq / ref_div;
if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
continue;
- feedback_div = RADEONDiv64((CARD64)freq * ref_div * post_div,
- pll->reference_freq * 10000);
+ feedback_div = RADEONDiv(freq * ref_div * post_div,
+ pll->reference_freq);
if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div)
continue;
- current_freq = RADEONDiv64((CARD64)pll->reference_freq * 10000 * feedback_div,
- ref_div * post_div);
+ current_freq = RADEONDiv(pll->reference_freq * feedback_div,
+ ref_div * post_div);
error = abs(current_freq - freq);
vco_diff = abs(vco - best_vco);
if ((best_vco == 0 && error < best_error) ||
(best_vco != 0 &&
- (error < best_error - 100 ||
+ (error < best_error - 1000 ||
(abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) {
best_post_div = post_div;
best_ref_div = ref_div;
@@ -690,7 +701,7 @@ RADEONComputePLL(RADEONPLLPtr pll,
static void
RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
RADEONPLLPtr pll, DisplayModePtr mode,
- Bool UseBiosDividers)
+ int flags)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
CARD32 feedback_div = 0;
@@ -719,14 +730,14 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
};
- if (UseBiosDividers && info->UseBiosDividers) {
+ if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
save->ppll_ref_div = info->RefDivider;
save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
save->htotal_cntl = 0;
return;
}
- RADEONComputePLL(pll, mode->Clock * 1000, &freq, &feedback_div, &reference_div, &post_divider);
+ RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
if (post_div->divider == post_divider)
@@ -738,7 +749,7 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
post_div = &post_divs[0];
}
- save->dot_clock_freq = freq / 10000;
+ save->dot_clock_freq = freq;
save->feedback_div = feedback_div;
save->reference_div = reference_div;
save->post_div = post_divider;
@@ -772,7 +783,7 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
static void
RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
RADEONPLLPtr pll, DisplayModePtr mode,
- Bool UseBiosDividers)
+ int flags)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
CARD32 feedback_div = 0;
@@ -799,14 +810,14 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
{ 0, 0 }
};
- if (UseBiosDividers && info->UseBiosDividers) {
+ if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
save->p2pll_ref_div = info->RefDivider;
save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16);
save->htotal_cntl2 = 0;
return;
}
- RADEONComputePLL(pll, mode->Clock * 1000, &freq, &feedback_div, &reference_div, &post_divider);
+ RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
if (post_div->divider == post_divider)
@@ -818,7 +829,7 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
post_div = &post_divs[0];
}
- save->dot_clock_freq_2 = freq / 10000;
+ save->dot_clock_freq_2 = freq;
save->feedback_div_2 = feedback_div;
save->reference_div_2 = reference_div;
save->post_div_2 = post_divider;
@@ -873,9 +884,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
RADEONInfoPtr info = RADEONPTR(pScrn);
Bool tilingOld = info->tilingEnabled;
int i = 0;
- double dot_clock = 0;
- Bool no_odd_post_div = FALSE;
- Bool use_bios_dividers = FALSE;
+ double dot_clock = 0;
+ int pll_flags = 0;
Bool update_tv_routing = FALSE;
@@ -900,9 +910,9 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
if (output->crtc == crtc) {
if (radeon_output->MonType != MT_CRT)
- no_odd_post_div = TRUE;
+ pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
if (radeon_output->MonType == MT_LCD)
- use_bios_dividers = TRUE;
+ pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV);
}
}
@@ -924,7 +934,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, use_bios_dividers);
+ RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags);
} else {
info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
@@ -938,7 +948,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode, use_bios_dividers);
+ RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags);
}
break;
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 55752d1..25b2119 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1069,7 +1069,7 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
pll->min_feedback_div = 4;
pll->max_feedback_div = 0x7ff;
pll->pll_in_min = 40;
- pll->pll_in_max = 100;
+ pll->pll_in_max = 500;
pll->best_vco = 0;
xf86DrvMsg (pScrn->scrnIndex, X_INFO,
commit 4747c1f3cd4167b6a51d4864a297719ea48b9346
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Sun Dec 16 14:07:29 2007 -0500
RADEON: Make sure LVDS_EN bit is set when enabling LVDS
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 5c4fbfa..999d349 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -304,7 +304,7 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) {
}
tmp = INREG(RADEON_LVDS_GEN_CNTL);
tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
if (info->IsMobility || info->IsIGP) {
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
@@ -364,11 +364,11 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->MonType == MT_LCD) {
tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
usleep (radeon_output->PanelPwrDly * 1000);
OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
} else if (radeon_output->MonType == MT_STV ||
radeon_output->MonType == MT_CTV) {
@@ -425,10 +425,10 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
tmp = INREG(RADEON_LVDS_GEN_CNTL);
tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
if (info->IsMobility || info->IsIGP) {
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
}
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 5dd80fa..9e73c08 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -987,7 +987,10 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl;
save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON |
+ RADEON_LVDS_BLON |
+ RADEON_LVDS_EN |
+ RADEON_LVDS_RST_FM);
if (IS_R300_VARIANT)
save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 2653339..6e4e383 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -916,6 +916,7 @@
# define RADEON_LVDS_DISPLAY_DIS (1 << 1)
# define RADEON_LVDS_PANEL_TYPE (1 << 2)
# define RADEON_LVDS_PANEL_FORMAT (1 << 3)
+# define RADEON_LVDS_RST_FM (1 << 6)
# define RADEON_LVDS_EN (1 << 7)
# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
commit b653e5a628bfa4dfb168e96f93f41eb910f409fb
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Sat Dec 15 00:50:10 2007 +0100
radeon: Default to 1x again with non-v3 AGP cards.
Seems more reliable in general than what was set up by firmware - fingers
crossed...
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 618334e..3190451 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -726,18 +726,9 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
pcie-agp rialto bridge chip - use the one from bridge which must match */
CARD32 agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode;
Bool is_v3 = (agp_status & RADEON_AGPv3_MODE);
- unsigned int defaultMode;
- MessageType from;
-
- if (is_v3) {
- defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
- } else {
- if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4;
- else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2;
- else defaultMode = 1;
- }
-
- from = X_DEFAULT;
+ unsigned int defaultMode = is_v3 ?
+ ((agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4) : 1;
+ MessageType from = X_DEFAULT;
if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->agpMode)) {
if ((info->agpMode < (is_v3 ? 4 : 1)) ||
commit 6229825fa5d6715569098afbb21a40f7a2e7e6be
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Sat Dec 15 00:48:26 2007 +0100
radeon: Warning fixes.
The lid detection code probably wouldn't work on other non-x86 platforms
though...
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index a2603a5..ebb8c52 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -606,12 +606,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
}
-/* Compute n/d with rounding */
-static int RADEONDiv(int n, int d)
-{
- return (n + (d / 2)) / d;
-}
-
static CARD32 RADEONDiv64(CARD64 n, CARD32 d)
{
return (n + (d / 2)) / d;
@@ -680,10 +674,10 @@ RADEONComputePLL(RADEONPLLPtr pll,
}
}
- ErrorF("best_freq: %d\n", best_freq);
- ErrorF("best_feedback_div: %d\n", best_feedback_div);
- ErrorF("best_ref_div: %d\n", best_ref_div);
- ErrorF("best_post_div: %d\n", best_post_div);
+ ErrorF("best_freq: %u\n", (unsigned)best_freq);
+ ErrorF("best_feedback_div: %u\n", (unsigned)best_feedback_div);
+ ErrorF("best_ref_div: %u\n", (unsigned)best_ref_div);
+ ErrorF("best_post_div: %u\n", (unsigned)best_post_div);
*chosen_dot_clock_freq = best_freq;
*chosen_feedback_div = best_feedback_div;
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 12c83aa..5dd80fa 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -684,6 +684,8 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
}
}
+#ifndef __powerpc__
+
static RADEONMonitorType
RADEONDetectLidStatus(ScrnInfoPtr pScrn)
{
@@ -723,6 +725,8 @@ RADEONDetectLidStatus(ScrnInfoPtr pScrn)
return MonType;
}
+#endif /* __powerpc__ */
+
static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
commit 818ccf0fd4b5879171c5f20526d5a58638f8fde5
Author: Fredrik Höglund <fredrik at kde.org>
Date: Fri Dec 14 23:56:12 2007 +0100
RADEON: Fix the vertex coordinates for transformed pictures
This partially fixes transformed pictures on R100/R200 based
cards. The texture still doesn't appear to be clamped correctly,
but since that doesn't matter for rotations at perpendicular
angles, I'm committing this now so randr rotation and reflection
will work properly.
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 9251569..eae69c4 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -736,6 +736,21 @@ do { \
#endif /* !ACCEL_CP */
+#ifdef ONLY_ONCE
+static inline void transformPoint(PictTransform *transform, xPointFixed *point)
+{
+ PictVector v;
+ v.vector[0] = point->x;
+ v.vector[1] = point->y;
+ v.vector[2] = xFixed1;
+ PictureTransformPoint(transform, &v);
+ point->x = v.vector[0];
+ point->y = v.vector[1];
+}
+#endif
+
+#define xFixedToFloat(f) (((float) (f)) / 65536)
+
static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
int srcX, int srcY,
int maskX, int maskY,
@@ -744,7 +759,8 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
{
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
int srcXend, srcYend, maskXend, maskYend;
- PictVector v;
+ xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
+ xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
ACCEL_PREAMBLE();
ENTER_DRAW(0);
@@ -756,33 +772,36 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
srcYend = srcY + h;
maskXend = maskX + w;
maskYend = maskY + h;
+
+ srcTopLeft.x = IntToxFixed(srcX);
+ srcTopLeft.y = IntToxFixed(srcY);
+ srcTopRight.x = IntToxFixed(srcX + w);
+ srcTopRight.y = IntToxFixed(srcY);
+ srcBottomLeft.x = IntToxFixed(srcX);
+ srcBottomLeft.y = IntToxFixed(srcY + h);
+ srcBottomRight.x = IntToxFixed(srcX + w);
+ srcBottomRight.y = IntToxFixed(srcY + h);
+
+ maskTopLeft.x = IntToxFixed(maskX);
+ maskTopLeft.y = IntToxFixed(maskY);
+ maskTopRight.x = IntToxFixed(maskX + w);
+ maskTopRight.y = IntToxFixed(maskY);
+ maskBottomLeft.x = IntToxFixed(maskX);
+ maskBottomLeft.y = IntToxFixed(maskY + h);
+ maskBottomRight.x = IntToxFixed(maskX + w);
+ maskBottomRight.y = IntToxFixed(maskY + h);
+
if (is_transform[0]) {
- v.vector[0] = IntToxFixed(srcX);
- v.vector[1] = IntToxFixed(srcY);
- v.vector[2] = xFixed1;
- PictureTransformPoint(transform[0], &v);
- srcX = xFixedToInt(v.vector[0]);
- srcY = xFixedToInt(v.vector[1]);
- v.vector[0] = IntToxFixed(srcXend);
- v.vector[1] = IntToxFixed(srcYend);
- v.vector[2] = xFixed1;
- PictureTransformPoint(transform[0], &v);
- srcXend = xFixedToInt(v.vector[0]);
- srcYend = xFixedToInt(v.vector[1]);
+ transformPoint(transform[0], &srcTopLeft);
+ transformPoint(transform[0], &srcTopRight);
+ transformPoint(transform[0], &srcBottomLeft);
+ transformPoint(transform[0], &srcBottomRight);
}
if (is_transform[1]) {
- v.vector[0] = IntToxFixed(maskX);
- v.vector[1] = IntToxFixed(maskY);
- v.vector[2] = xFixed1;
- PictureTransformPoint(transform[1], &v);
- maskX = xFixedToInt(v.vector[0]);
- maskY = xFixedToInt(v.vector[1]);
- v.vector[0] = IntToxFixed(maskXend);
- v.vector[1] = IntToxFixed(maskYend);
- v.vector[2] = xFixed1;
- PictureTransformPoint(transform[1], &v);
- maskXend = xFixedToInt(v.vector[0]);
- maskYend = xFixedToInt(v.vector[1]);
+ transformPoint(transform[1], &maskTopLeft);
+ transformPoint(transform[1], &maskTopRight);
+ transformPoint(transform[1], &maskBottomLeft);
+ transformPoint(transform[1], &maskBottomRight);
}
#ifdef ACCEL_CP
@@ -828,18 +847,18 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
VTX_OUT(dstX + w, dstY + h, srcXend, srcYend, maskXend, maskYend);
VTX_OUT(dstX + w, dstY, srcXend, srcY, maskXend, maskY);
} else {
- VTX_OUT((float)dstX, (float)dstY,
- (float)srcX / info->texW[0], (float)srcY / info->texH[0],
- (float)maskX / info->texW[1], (float)maskY / info->texH[1]);
- VTX_OUT((float)dstX, (float)(dstY + h),
- (float)srcX / info->texW[0], (float)srcYend / info->texH[0],
- (float)maskX / info->texW[1], (float)maskYend / info->texH[1]);
- VTX_OUT((float)(dstX + w), (float)(dstY + h),
- (float)srcXend / info->texW[0], (float)srcYend / info->texH[0],
- (float)maskXend / info->texW[1], (float)maskYend / info->texH[1]);
- VTX_OUT((float)(dstX + w), (float)dstY,
- (float)srcXend / info->texW[0], (float)srcY / info->texH[0],
- (float)maskXend / info->texW[1], (float)maskY / info->texH[1]);
+ VTX_OUT((float)dstX, (float)dstY,
+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
+ xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]);
+ VTX_OUT((float)dstX, (float)(dstY + h),
+ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0],
+ xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]);
+ VTX_OUT((float)(dstX + w), (float)(dstY + h),
+ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0],
+ xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]);
+ VTX_OUT((float)(dstX + w), (float)dstY,
+ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0],
+ xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]);
}
#ifdef ACCEL_CP
commit 3cfbcf4cafbdfdb33411d16e51fb1f77cd0f93dd
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Fri Dec 14 17:11:00 2007 -0500
RADEON: Fix PLL set up on certain notebooks
Some LVDS panels require specific PLL dividers as
specified in the bios tables. Make sure to use them
if the output is LVDS.
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 2023f40..a2603a5 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -695,7 +695,8 @@ RADEONComputePLL(RADEONPLLPtr pll,
/* Define PLL registers for requested video mode */
static void
RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
- RADEONPLLPtr pll, DisplayModePtr mode)
+ RADEONPLLPtr pll, DisplayModePtr mode,
+ Bool UseBiosDividers)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
CARD32 feedback_div = 0;
@@ -723,16 +724,15 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
{ 0, 0 }
};
- RADEONComputePLL(pll, mode->Clock * 1000, &freq, &feedback_div, &reference_div, &post_divider);
-#if 0
- if (info->UseBiosDividers) {
+ if (UseBiosDividers && info->UseBiosDividers) {
save->ppll_ref_div = info->RefDivider;
save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
save->htotal_cntl = 0;
return;
}
-#endif
+
+ RADEONComputePLL(pll, mode->Clock * 1000, &freq, &feedback_div, &reference_div, &post_divider);
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
if (post_div->divider == post_divider)
@@ -777,7 +777,8 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
/* Define PLL2 registers for requested video mode */
static void
RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
- RADEONPLLPtr pll, DisplayModePtr mode)
+ RADEONPLLPtr pll, DisplayModePtr mode,
+ Bool UseBiosDividers)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
CARD32 feedback_div = 0;
@@ -804,6 +805,13 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
{ 0, 0 }
};
+ if (UseBiosDividers && info->UseBiosDividers) {
+ save->p2pll_ref_div = info->RefDivider;
+ save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16);
+ save->htotal_cntl2 = 0;
+ return;
+ }
+
RADEONComputePLL(pll, mode->Clock * 1000, &freq, &feedback_div, &reference_div, &post_divider);
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
@@ -873,6 +881,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
int i = 0;
double dot_clock = 0;
Bool no_odd_post_div = FALSE;
+ Bool use_bios_dividers = FALSE;
Bool update_tv_routing = FALSE;
@@ -898,6 +907,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
if (output->crtc == crtc) {
if (radeon_output->MonType != MT_CRT)
no_odd_post_div = TRUE;
+ if (radeon_output->MonType == MT_LCD)
+ use_bios_dividers = TRUE;
}
}
@@ -919,7 +930,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode);
+ RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, use_bios_dividers);
} else {
info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
@@ -933,7 +944,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode);
+ RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode, use_bios_dividers);
}
break;
}
commit a84d446fd301d456bcea8f7abdc52e5a30776412
Author: Alex Deucher <alex at botch2.(none)>
Date: Fri Dec 14 02:17:14 2007 -0500
RADEON: select fb_div0 for LVDS on RV410 (x700) mobility
Fixes bug 8038
I wonder if desktop RV410 need a similar fix.
If your x700 laptop panel has problems after this let me know.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 122c582..55752d1 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4038,6 +4038,10 @@ void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
if (info->IsMobility) {
OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
OUTREG(RADEON_LVDS_PLL_CNTL, restore->lvds_pll_cntl);
+
+ if (info->ChipFamily == CHIP_FAMILY_RV410) {
+ OUTREG(RADEON_CLOCK_CNTL_INDEX, 0);
+ }
}
}
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