xf86-video-ati: Branch 'atombios-support' - 12 commits
Dave Airlie
airlied at kemper.freedesktop.org
Sun Dec 9 21:50:58 PST 2007
Makefile.am | 2
configure.ac | 53 +++++++++
src/Makefile.am | 24 ++++
src/atombios_crtc.c | 6 -
src/radeon.h | 275 +------------------------------------------------
src/radeon_accel.c | 2
src/radeon_atombios.c | 6 -
src/radeon_crtc.c | 138 ++++++++++++------------
src/radeon_cursor.c | 4
src/radeon_display.c | 15 +-
src/radeon_dri.c | 4
src/radeon_driver.c | 181 +++++++++++++++++++++++++-------
src/radeon_output.c | 68 ++++++------
src/radeon_probe.c | 2
src/radeon_probe.h | 279 ++++++++++++++++++++++++++++++++++++++++++++++++++
src/radeon_tv.c | 4
src/radeon_tv.h | 5
src/radeon_video.c | 6 -
18 files changed, 638 insertions(+), 436 deletions(-)
New commits:
commit 731830297f2fc4a416882aacfb0d9b5f8ed32520
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:50:38 2007 +1000
fixup some warnings
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 9d17e47..a04598d 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1443,7 +1443,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
ErrorF("record type %d\n", Record->ucRecordType);
switch (Record->ucRecordType) {
case ATOM_I2C_RECORD_TYPE:
- rhdAtomParseI2CRecord(&info->atomBIOS,
+ rhdAtomParseI2CRecord(info->atomBIOS,
(ATOM_I2C_RECORD *)Record,
&info->BiosConnector[i].ddc_line);
break;
@@ -2604,7 +2604,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data)
void
atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor)
{
- ATOM_MASTER_COMMAND_TABLE *cmd_table = atomBIOS->BIOSBase + atomBIOS->cmd_offset;
+ ATOM_MASTER_COMMAND_TABLE *cmd_table = (void *)(atomBIOS->BIOSBase + atomBIOS->cmd_offset);
ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start;
ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr;
@@ -2615,7 +2615,7 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m
offset = *(((unsigned short *)table_start) + index);
- table_hdr = atomBIOS->BIOSBase + offset;
+ table_hdr = (ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)(atomBIOS->BIOSBase + offset);
*major = table_hdr->CommonHeader.ucTableFormatRevision;
*minor = table_hdr->CommonHeader.ucTableContentRevision;
commit 2818e2b02ca90c9dfa50905b5311b2ae83ac3b0c
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:43:52 2007 +1000
add more to configure.ac for using out-of-tree mode src
diff --git a/configure.ac b/configure.ac
index 71e5e45..b5c694c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -62,6 +62,11 @@ AC_ARG_ENABLE(exa,
[EXA="$enableval"],
[EXA=yes])
+AC_ARG_WITH(xserver-source,AC_HELP_STRING([--with-xserver-source=XSERVER_SOURCE],
+ [Path to X server source tree]),
+ [ XSERVER_SOURCE="$withval" ],
+ [ XSERVER_SOURCE="" ])
+
# Checks for extensions
XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto)
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
@@ -116,22 +121,6 @@ CFLAGS="$XORG_CFLAGS"
AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"])
CFLAGS="$save_CFLAGS"
-AM_CONDITIONAL(XMODES, test "x$XMODES" = xno)
-if test "x$XMODES" = xyes; then
- AC_MSG_NOTICE([X server has new mode code])
- AC_DEFINE(XMODES, 1,[X server has built-in mode code])
- XMODES_CFLAGS=
-else
- if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then
- AC_MSG_NOTICE([X server is missing new mode code, using local copy])
- else
- AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source])
- fi
- XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser'
-fi
-
-AC_SUBST([XMODES_CFLAGS])
-
# Note that this is sort of inverted from drivers/ati/Imakefile in
# the monolith. We test for foo, not for !foo (i.e. ATMISC_CPIO, not
# ATIMISC_AVOID_CPIO), but the defines are negative. So beware. Oh yeah,
@@ -228,6 +217,48 @@ AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
[#include "xorg-server.h"])
+AM_CONDITIONAL(XMODES, test "x$XMODES" = xno)
+
+if test "x$XSERVER_SOURCE" = x; then
+ if test -d ../../xserver; then
+ XSERVER_SOURCE="`cd ../../xserver && pwd`"
+ fi
+fi
+
+if test -d "$XSERVER_SOURCE"; then
+ case "$XSERVER_SOURCE" in
+ /*)
+ ;;
+ *)
+ XSERVER_SOURCE="`cd $XSERVER_SOURCE && pwd`"
+ esac
+ if test -f src/modes/xf86Modes.h; then
+ :
+ else
+ ln -sf $XSERVER_SOURCE/hw/xfree86/modes src/modes
+ fi
+
+ if test -f src/parser/xf86Parser.h; then
+ :
+ else
+ ln -sf $XSERVER_SOURCE/hw/xfree86/parser src/parser
+ fi
+fi
+if test "x$XMODES" = xyes; then
+ AC_MSG_NOTICE([X server has new mode code])
+ AC_DEFINE(XMODES, 1,[X server has built-in mode code])
+ XMODES_CFLAGS=
+else
+ if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then
+ AC_MSG_NOTICE([X server is missing new mode code, using local copy])
+ else
+ AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source])
+ fi
+ XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser'
+fi
+
+AC_SUBST([XMODES_CFLAGS])
+
CPPFLAGS="$SAVE_CPPFLAGS"
AM_CONDITIONAL(USE_EXA, test "x$USE_EXA" = xyes)
commit cc3c36100986f9d8060bc2d433373d4806f8e730
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:25:56 2007 +1000
add support for building against legacy servers similiar to Intel codepaths
diff --git a/configure.ac b/configure.ac
index b3d46a5..71e5e45 100644
--- a/configure.ac
+++ b/configure.ac
@@ -71,7 +71,7 @@ XORG_DRIVER_CHECK_EXT(XF86MISC, xf86miscproto)
XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
# Checks for pkg-config packages
-PKG_CHECK_MODULES(XORG, [xorg-server >= 1.3 xproto fontsproto $REQUIRED_MODULES])
+PKG_CHECK_MODULES(XORG, [xorg-server xproto fontsproto $REQUIRED_MODULES])
sdkdir=$(pkg-config --variable=sdkdir xorg-server)
# Checks for libraries.
@@ -112,6 +112,26 @@ if test "$DRI" = yes; then
fi
fi
+CFLAGS="$XORG_CFLAGS"
+AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"])
+CFLAGS="$save_CFLAGS"
+
+AM_CONDITIONAL(XMODES, test "x$XMODES" = xno)
+if test "x$XMODES" = xyes; then
+ AC_MSG_NOTICE([X server has new mode code])
+ AC_DEFINE(XMODES, 1,[X server has built-in mode code])
+ XMODES_CFLAGS=
+else
+ if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then
+ AC_MSG_NOTICE([X server is missing new mode code, using local copy])
+ else
+ AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source])
+ fi
+ XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser'
+fi
+
+AC_SUBST([XMODES_CFLAGS])
+
# Note that this is sort of inverted from drivers/ati/Imakefile in
# the monolith. We test for foo, not for !foo (i.e. ATMISC_CPIO, not
# ATIMISC_AVOID_CPIO), but the defines are negative. So beware. Oh yeah,
diff --git a/src/Makefile.am b/src/Makefile.am
index fd870c4..3e0352b 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -47,6 +47,22 @@ RADEON_ATOMBIOS_SOURCES = \
AtomBios/includes/ObjectID.h \
AtomBios/includes/regsdef.h
+XMODE_SRCS=\
+ local_xf86Rename.h \
+ parser/xf86Parser.h \
+ parser/xf86Optrec.h \
+ modes/xf86Modes.h \
+ modes/xf86Modes.c \
+ modes/xf86cvt.c \
+ modes/xf86Crtc.h \
+ modes/xf86Crtc.c \
+ modes/xf86Cursors.c \
+ modes/xf86EdidModes.c \
+ modes/xf86RandR12.c \
+ modes/xf86RandR12.h \
+ modes/xf86Rename.h \
+ modes/xf86Rotate.c \
+ modes/xf86DiDGA.c
if ATIMISC_CPIO
ATIMISC_CPIO_SOURCES = ativga.c ativgaio.c atibank.c atiwonder.c atiwonderio.c
@@ -61,7 +77,7 @@ ATIMISC_EXA_SOURCES = atimach64exa.c
RADEON_EXA_SOURCES = radeon_exa.c
endif
-AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER
+AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER
INCLUDES = -I$(srcdir)/AtomBios/includes
ati_drv_la_LTLIBRARIES = ati_drv.la
@@ -105,6 +121,11 @@ radeon_drv_la_SOURCES = \
$(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \
$(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c
+if XMODES
+radeon_drv_la_SOURCES += \
+ $(XMODE_SRCS)
+endif
+
theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la
theatre_detect_drv_la_LDFLAGS = -module -avoid-version
theatre_detect_drv_ladir = @moduledir@/multimedia
@@ -127,6 +148,7 @@ theatre200_drv_la_SOURCES = \
theatre200.c theatre200_module.c
EXTRA_DIST = \
+ $(XMODE_SRCS) \
atimach64render.c \
radeon_render.c \
radeon_accelfuncs.c \
commit 9c278cb7fa7f18d13bde053fd75221cfba9da377
Merge: 6451ea2... cc167b9...
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:18:03 2007 +1000
Merge branch 'zaphod-lolz' of git://git.freedesktop.org/git/xorg/driver/xf86-video-ati into atombios-support
Conflicts:
src/radeon.h
src/radeon_crtc.c
src/radeon_driver.c
src/radeon_output.c
diff --cc src/atombios_crtc.c
index 5c2d261,0000000..3c61ef7
mode 100644,000000..100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@@ -1,433 -1,0 +1,433 @@@
+ /*
+ * Copyright © 2007 Red Hat, Inc.
+ *
+ * PLL code is:
+ * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+ * Copyright 2007 Matthias Hopf <mhopf at novell.com>
+ * Copyright 2007 Egbert Eich <eich at novell.com>
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Dave Airlie <airlied at redhat.com>
+ *
+ */
+/*
+ * avivo crtc handling functions.
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+/* DPMS */
+#define DPMS_SERVER
+#include <X11/extensions/dpms.h>
+
+#include "radeon.h"
+#include "radeon_reg.h"
+#include "radeon_macros.h"
+#include "radeon_atombios.h"
+
+#ifdef XF86DRI
+#define _XF86DRI_SERVER_
+#include "radeon_dri.h"
+#include "radeon_sarea.h"
+#include "sarea.h"
+#endif
+
+AtomBiosResult
+atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
+{
+ ENABLE_CRTC_PS_ALLOCATION crtc_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucEnable = state;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Enable":"Disable", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Enable CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+AtomBiosResult
+atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
+{
+ BLANK_CRTC_PS_ALLOCATION crtc_data;
+ unsigned char *space;
+ AtomBiosArgRec data;
+
+ memset(&crtc_data, 0, sizeof(crtc_data));
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucBlanking = state;
+
+ data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", state? "Blank":"Unblank", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Blank CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+static void
+atombios_crtc_enable(xf86CrtcPtr crtc, int enable)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable);
+
+ //TODOavivo_wait_idle(avivo);
+}
+
+void
+atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ switch (mode) {
+ case DPMSModeOn:
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ case DPMSModeOff:
+ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ break;
+ }
+}
+
+static AtomBiosResult
+atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
+{
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = crtc_param;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC Timing success\n");
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Set CRTC Timing failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
+/*
+ * Calculate the PLL parameters for a given dotclock.
+ */
+#define RADEON_PLL_DEFAULT_PLLOUT_MIN 64800 /* experimental. - taken from rhd divided by 10 */
+
+static Bool
+PLLCalculate(ScrnInfoPtr pScrn, CARD32 PixelClock,
+ CARD16 *RefDivider, CARD16 *FBDivider, CARD8 *PostDivider)
+{
+/* limited by the number of bits available */
+#define FB_DIV_LIMIT 1024 /* rv6x0 doesn't like 2048 */
+#define REF_DIV_LIMIT 1024
+#define POST_DIV_LIMIT 128
+ RADEONInfoPtr info = RADEONPTR (pScrn);
+ RADEONPLLPtr pll = &info->pll;
+ CARD32 FBDiv, RefDiv, PostDiv, BestDiff = 0xFFFFFFFF;
+ float Ratio;
+
+ Ratio = ((float) PixelClock) / ((float) pll->reference_freq * 10);
+
+ if (pll->min_pll_freq == 0)
+ pll->min_pll_freq = RADEON_PLL_DEFAULT_PLLOUT_MIN;
+ for (PostDiv = 2; PostDiv < POST_DIV_LIMIT; PostDiv++) {
+ CARD32 VCOOut = PixelClock * PostDiv;
+
+ /* we are conservative and avoid the limits */
+ if (VCOOut <= pll->min_pll_freq * 10)
+ continue;
+ if (VCOOut >= pll->max_pll_freq * 10)
+ break;
+
+ for (RefDiv = 1; RefDiv <= REF_DIV_LIMIT; RefDiv++)
+ {
+ CARD32 Diff;
+
+ FBDiv = (CARD32) ((Ratio * PostDiv * RefDiv) + 0.5);
+
+ if (FBDiv >= FB_DIV_LIMIT)
+ break;
+
+ if (FBDiv > (500 + (13 * RefDiv))) /* rv6x0 limit */
+ break;
+
+ Diff = abs( PixelClock - (FBDiv * pll->reference_freq * 10) / (PostDiv * RefDiv) );
+
+ if (Diff < BestDiff) {
+ *FBDivider = FBDiv;
+ *RefDivider = RefDiv;
+ *PostDivider = PostDiv;
+ BestDiff = Diff;
+ }
+
+ if (BestDiff == 0)
+ break;
+ }
+ if (BestDiff == 0)
+ break;
+ }
+
+ if (BestDiff != 0xFFFFFFFF) {
+ ErrorF("PLL Calculation: %dkHz = "
+ "(((0x%X / 0x%X) * 0x%X) / 0x%X) (%dkHz off)\n",
+ (int) PixelClock, (unsigned int) pll->reference_freq * 10, *RefDivider,
+ *FBDivider, *PostDivider, (int) BestDiff);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PLL for %dkHz uses %dkHz internally.\n",
+ (int) PixelClock,
+ (int) (pll->reference_freq * 10 * *FBDivider) / *RefDivider);
+ return TRUE;
+ } else { /* Should never happen */
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "%s: Failed to get a valid PLL setting for %dkHz\n",
+ __func__, (int) PixelClock);
+ return FALSE;
+ }
+}
+
+void
+atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ int sclock = mode->Clock;
+ uint16_t ref_div = 0, fb_div = 0;
+ uint8_t post_div = 0;
+ int major, minor;
+ SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
+ void *ptr;
+ AtomBiosArgRec data;
+ unsigned char *space;
- RADEONSavePtr save = &info->ModeReg;
++ RADEONSavePtr save = info->ModeReg;
+
+ if (IS_AVIVO_VARIANT) {
+ CARD32 temp;
+ PLLCalculate(crtc->scrn, sclock, &ref_div, &fb_div, &post_div);
+
+ /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
+ if (radeon_crtc->crtc_id == 0) {
+ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ } else {
+ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ }
+ } else {
+ sclock = save->dot_clock_freq * 10;
+ fb_div = save->feedback_div;
+ post_div = save->post_div;
+ ref_div = save->ppll_ref_div;
+ }
+
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) Clock: mode %d, PLL %d\n",
+ radeon_crtc->crtc_id, mode->Clock, sclock);
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
+ "crtc(%d) PLL : refdiv %d, fbdiv 0x%X(%d), pdiv %d\n",
+ radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ ErrorF("table is %d %d\n", major, minor);
+ switch(major) {
+ case 1:
+ switch(minor) {
+ case 1:
+ case 2: {
+ spc_param.sPCLKInput.usPixelClock = sclock / 10;
+ spc_param.sPCLKInput.usRefDiv = ref_div;
+ spc_param.sPCLKInput.usFbDiv = fb_div;
+ spc_param.sPCLKInput.ucPostDiv = post_div;
+ spc_param.sPCLKInput.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+ spc_param.sPCLKInput.ucCRTC = radeon_crtc->crtc_id;
+ spc_param.sPCLKInput.ucRefDivSrc = 1;
+
+ ptr = &spc_param;
+ break;
+ }
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = ptr;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set CRTC PLL success\n");
+ return;
+ }
+
+ ErrorF("Set CRTC PLL failed\n");
+ return;
+}
+
+void
+atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode,
+ int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
+ Bool tilingOld = info->tilingEnabled;
+
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
+
+ memset(&crtc_timing, 0, sizeof(crtc_timing));
+
+ if (info->allowColorTiling) {
+ info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
+#ifdef XF86DRI
+ if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
+ RADEONSAREAPrivPtr pSAREAPriv;
+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "[drm] failed changing tiling status\n");
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
+ info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
+ }
+#endif
+ }
+
+ crtc_timing.ucCRTC = radeon_crtc->crtc_id;
+ crtc_timing.usH_Total = adjusted_mode->CrtcHTotal;
+ crtc_timing.usH_Disp = adjusted_mode->CrtcHDisplay;
+ crtc_timing.usH_SyncStart = adjusted_mode->CrtcHSyncStart;
+ crtc_timing.usH_SyncWidth = adjusted_mode->CrtcHSyncEnd - adjusted_mode->CrtcHSyncStart;
+
+ crtc_timing.usV_Total = adjusted_mode->CrtcVTotal;
+ crtc_timing.usV_Disp = adjusted_mode->CrtcVDisplay;
+ crtc_timing.usV_SyncStart = adjusted_mode->CrtcVSyncStart;
+ crtc_timing.usV_SyncWidth = adjusted_mode->CrtcVSyncEnd - adjusted_mode->CrtcVSyncStart;
+
+ if (adjusted_mode->Flags & V_NVSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
+
+ if (adjusted_mode->Flags & V_NHSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
+
+ ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
+ adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
+
- RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info);
- RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg);
++ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
++ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+
+ if (IS_AVIVO_VARIANT) {
+ radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_height = pScrn->virtualY;
+ radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay;
+ radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4;
+ switch (crtc->scrn->bitsPerPixel) {
+ case 15:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
+ break;
+ case 16:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
+ break;
+ case 24:
+ case 32:
+ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
+ break;
+ default:
+ FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
+ }
+ if (info->tilingEnabled) {
+ radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
+ }
+
+ if (radeon_crtc->crtc_id == 0)
+ OUTREG(AVIVO_D1VGA_CONTROL, 0);
+ else
+ OUTREG(AVIVO_D2VGA_CONTROL, 0);
+
+ /* setup fb format and location
+ */
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
+ (mode->HDisplay << 16) | mode->VDisplay);
+
+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset,
+ radeon_crtc->fb_format);
+
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualX);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualY);
+ OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
+ crtc->scrn->displayWidth);
+
+ OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+
+ }
+
+ atombios_crtc_set_pll(crtc, adjusted_mode);
+
+ atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
+
+ if (info->tilingEnabled != tilingOld) {
+ /* need to redraw front buffer, I guess this can be considered a hack ? */
+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE);
+ RADEONChangeSurfaces(pScrn);
+ if (pScrn->pScreen)
+ xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE);
+ /* xf86SetRootClip would do, but can't access that here */
+ }
+
+}
+
diff --cc src/radeon.h
index 2870ef5,5c3bf86..10ecd09
--- a/src/radeon.h
+++ b/src/radeon.h
@@@ -200,271 -200,8 +200,6 @@@ typedef struct
CARD16 rr4_offset;
} RADEONBIOSInitTable;
- struct avivo_pll_state {
- CARD32 ref_div_src;
- CARD32 ref_div;
- CARD32 fb_div;
- CARD32 post_div_src;
- CARD32 post_div;
- CARD32 ext_ppll_cntl;
- CARD32 pll_cntl;
- CARD32 int_ss_cntl;
- };
--
- struct avivo_crtc_state {
- CARD32 pll_source;
- CARD32 h_total;
- CARD32 h_blank_start_end;
- CARD32 h_sync_a;
- CARD32 h_sync_a_cntl;
- CARD32 h_sync_b;
- CARD32 h_sync_b_cntl;
- CARD32 v_total;
- CARD32 v_blank_start_end;
- CARD32 v_sync_a;
- CARD32 v_sync_a_cntl;
- CARD32 v_sync_b;
- CARD32 v_sync_b_cntl;
- CARD32 control;
- CARD32 blank_control;
- CARD32 interlace_control;
- CARD32 stereo_control;
- CARD32 cursor_control;
- };
--
- struct avivo_grph_state {
- CARD32 enable;
- CARD32 control;
- CARD32 prim_surf_addr;
- CARD32 sec_surf_addr;
- CARD32 pitch;
- CARD32 x_offset;
- CARD32 y_offset;
- CARD32 x_start;
- CARD32 y_start;
- CARD32 x_end;
- CARD32 y_end;
-
- CARD32 viewport_start;
- CARD32 viewport_size;
- CARD32 scl_enable;
- };
-
- struct avivo_dac_state {
- CARD32 enable;
- CARD32 source_select;
- CARD32 force_output_cntl;
- CARD32 powerdown;
- };
-
- struct avivo_dig_state {
- CARD32 cntl;
- CARD32 bit_depth_cntl;
- CARD32 data_sync;
- CARD32 transmitter_enable;
- CARD32 transmitter_cntl;
- CARD32 source_select;
- };
-
- struct avivo_state
- {
- CARD32 hdp_fb_location;
- CARD32 mc_memory_map;
- CARD32 vga_memory_base;
- CARD32 vga_fb_start;
-
- CARD32 vga1_cntl;
- CARD32 vga2_cntl;
-
- CARD32 crtc_master_en;
- CARD32 crtc_tv_control;
-
- CARD32 lvtma_pwrseq_cntl;
- CARD32 lvtma_pwrseq_state;
-
- struct avivo_pll_state pll1;
- struct avivo_pll_state pll2;
-
- struct avivo_crtc_state crtc1;
- struct avivo_crtc_state crtc2;
-
- struct avivo_grph_state grph1;
- struct avivo_grph_state grph2;
-
- struct avivo_dac_state daca;
- struct avivo_dac_state dacb;
-
- struct avivo_dig_state tmds1;
- struct avivo_dig_state tmds2;
-
- };
-
- typedef struct {
- struct avivo_state avivo;
- /* Common registers */
- CARD32 ovr_clr;
- CARD32 ovr_wid_left_right;
- CARD32 ovr_wid_top_bottom;
- CARD32 ov0_scale_cntl;
- CARD32 mpp_tb_config;
- CARD32 mpp_gp_config;
- CARD32 subpic_cntl;
- CARD32 viph_control;
- CARD32 i2c_cntl_1;
- CARD32 gen_int_cntl;
- CARD32 cap0_trig_cntl;
- CARD32 cap1_trig_cntl;
- CARD32 bus_cntl;
- CARD32 bios_4_scratch;
- CARD32 bios_5_scratch;
- CARD32 bios_6_scratch;
- CARD32 surface_cntl;
- CARD32 surfaces[8][3];
- CARD32 mc_agp_location;
- CARD32 mc_agp_location_hi;
- CARD32 mc_fb_location;
- CARD32 display_base_addr;
- CARD32 display2_base_addr;
- CARD32 ov0_base_addr;
-
- /* Other registers to save for VT switches */
- CARD32 dp_datatype;
- CARD32 rbbm_soft_reset;
- CARD32 clock_cntl_index;
- CARD32 amcgpio_en_reg;
- CARD32 amcgpio_mask;
-
- /* CRTC registers */
- CARD32 crtc_gen_cntl;
- CARD32 crtc_ext_cntl;
- CARD32 dac_cntl;
- CARD32 crtc_h_total_disp;
- CARD32 crtc_h_sync_strt_wid;
- CARD32 crtc_v_total_disp;
- CARD32 crtc_v_sync_strt_wid;
- CARD32 crtc_offset;
- CARD32 crtc_offset_cntl;
- CARD32 crtc_pitch;
- CARD32 disp_merge_cntl;
- CARD32 grph_buffer_cntl;
- CARD32 crtc_more_cntl;
- CARD32 crtc_tile_x0_y0;
-
- /* CRTC2 registers */
- CARD32 crtc2_gen_cntl;
- CARD32 dac_macro_cntl;
- CARD32 dac2_cntl;
- CARD32 disp_output_cntl;
- CARD32 disp_tv_out_cntl;
- CARD32 disp_hw_debug;
- CARD32 disp2_merge_cntl;
- CARD32 grph2_buffer_cntl;
- CARD32 crtc2_h_total_disp;
- CARD32 crtc2_h_sync_strt_wid;
- CARD32 crtc2_v_total_disp;
- CARD32 crtc2_v_sync_strt_wid;
- CARD32 crtc2_offset;
- CARD32 crtc2_offset_cntl;
- CARD32 crtc2_pitch;
- CARD32 crtc2_tile_x0_y0;
-
- /* Flat panel registers */
- CARD32 fp_crtc_h_total_disp;
- CARD32 fp_crtc_v_total_disp;
- CARD32 fp_gen_cntl;
- CARD32 fp2_gen_cntl;
- CARD32 fp_h_sync_strt_wid;
- CARD32 fp_h2_sync_strt_wid;
- CARD32 fp_horz_stretch;
- CARD32 fp_panel_cntl;
- CARD32 fp_v_sync_strt_wid;
- CARD32 fp_v2_sync_strt_wid;
- CARD32 fp_vert_stretch;
- CARD32 lvds_gen_cntl;
- CARD32 lvds_pll_cntl;
- CARD32 tmds_pll_cntl;
- CARD32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- CARD32 dot_clock_freq;
- CARD32 pll_output_freq;
- int feedback_div;
- int post_div;
-
- /* PLL registers */
- unsigned ppll_ref_div;
- unsigned ppll_div_3;
- CARD32 htotal_cntl;
- CARD32 vclk_ecp_cntl;
-
- /* Computed values for PLL2 */
- CARD32 dot_clock_freq_2;
- CARD32 pll_output_freq_2;
- int feedback_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- CARD32 p2pll_ref_div;
- CARD32 p2pll_div_0;
- CARD32 htotal_cntl2;
- CARD32 pixclks_cntl;
-
- /* Pallet */
- Bool palette_valid;
- CARD32 palette[256];
- CARD32 palette2[256];
-
- CARD32 rs480_unk_e30;
- CARD32 rs480_unk_e34;
- CARD32 rs480_unk_e38;
- CARD32 rs480_unk_e3c;
-
- /* TV out registers */
- CARD32 tv_master_cntl;
- CARD32 tv_htotal;
- CARD32 tv_hsize;
- CARD32 tv_hdisp;
- CARD32 tv_hstart;
- CARD32 tv_vtotal;
- CARD32 tv_vdisp;
- CARD32 tv_timing_cntl;
- CARD32 tv_vscaler_cntl1;
- CARD32 tv_vscaler_cntl2;
- CARD32 tv_sync_size;
- CARD32 tv_vrestart;
- CARD32 tv_hrestart;
- CARD32 tv_frestart;
- CARD32 tv_ftotal;
- CARD32 tv_clock_sel_cntl;
- CARD32 tv_clkout_cntl;
- CARD32 tv_data_delay_a;
- CARD32 tv_data_delay_b;
- CARD32 tv_dac_cntl;
- CARD32 tv_pll_cntl;
- CARD32 tv_pll_cntl1;
- CARD32 tv_pll_fine_cntl;
- CARD32 tv_modulator_cntl1;
- CARD32 tv_modulator_cntl2;
- CARD32 tv_frame_lock_cntl;
- CARD32 tv_pre_dac_mux_cntl;
- CARD32 tv_rgb_cntl;
- CARD32 tv_y_saw_tooth_cntl;
- CARD32 tv_y_rise_cntl;
- CARD32 tv_y_fall_cntl;
- CARD32 tv_uv_adr;
- CARD32 tv_upsamp_and_gain_cntl;
- CARD32 tv_gain_limit_settings;
- CARD32 tv_linear_gain_settings;
- CARD32 tv_crc_cntl;
- CARD32 tv_sync_cntl;
- CARD32 gpiopad_a;
- CARD32 pll_test_cntl;
-
- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
-
- } RADEONSaveRec, *RADEONSavePtr;
-
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
diff --cc src/radeon_crtc.c
index e288352,f28bdf7..1ea6d2b
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@@ -905,21 -891,15 +905,21 @@@ legacy_crtc_mode_set(xf86CrtcPtr crtc,
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("restore crtc1\n");
- RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreCrtcRegisters(pScrn, info->ModeReg);
ErrorF("restore pll1\n");
- RADEONRestorePLLRegisters(pScrn, info->ModeReg);
+ /*if (info->IsAtomBios)
+ atombios_crtc_set_pll(crtc, adjusted_mode);
+ else*/
- RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
++ RADEONRestorePLLRegisters(pScrn, info->ModeReg);
break;
case 1:
ErrorF("restore crtc2\n");
- RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg);
+ RADEONRestoreCrtc2Registers(pScrn, info->ModeReg);
ErrorF("restore pll2\n");
- RADEONRestorePLL2Registers(pScrn, info->ModeReg);
+ /*if (info->IsAtomBios)
- atombios_crtc_set_pll(crtc, adjusted_mode);
++ atombios_crtc_set_pll(crtc, adjusted_mode);
+ else*/
- RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
++ RADEONRestorePLL2Registers(pScrn, info->ModeReg);
break;
}
@@@ -1261,39 -1207,41 +1261,43 @@@ Bool RADEONAllocateControllers(ScrnInfo
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- if (pRADEONEnt->Controller[0])
- return TRUE;
-
- pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[0])
- return FALSE;
-
- pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[0])
- return FALSE;
-
- pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
- pRADEONEnt->Controller[0]->crtc_id = 0;
- pRADEONEnt->Controller[0]->crtc_offset = 0;
-
- if (!pRADEONEnt->HasCRTC2)
- return TRUE;
+ if (mask & 1) {
+ if (pRADEONEnt->Controller[0])
+ return TRUE;
+
+ pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
+ if (!pRADEONEnt->pCrtc[0])
+ return FALSE;
+
+ pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
+ if (!pRADEONEnt->Controller[0])
+ return FALSE;
+
+ pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
+ pRADEONEnt->Controller[0]->crtc_id = 0;
-
++ pRADEONEnt->Controller[0]->crtc_offset = 0;
+ }
- pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[1])
- return FALSE;
+ if (mask & 2) {
+ if (!pRADEONEnt->HasCRTC2)
+ return TRUE;
+
+ pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
+ if (!pRADEONEnt->pCrtc[1])
+ return FALSE;
+
+ pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
+ if (!pRADEONEnt->Controller[1])
+ {
+ xfree(pRADEONEnt->Controller[0]);
+ return FALSE;
+ }
- pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[1])
- {
- xfree(pRADEONEnt->Controller[0]);
- return FALSE;
+ pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
+ pRADEONEnt->Controller[1]->crtc_id = 1;
++ pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
}
+
- pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
- pRADEONEnt->Controller[1]->crtc_id = 1;
- pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
-
return TRUE;
}
diff --cc src/radeon_driver.c
index 74dd2a6,35b9a47..4afbee1
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@@ -2287,9 -2118,10 +2314,13 @@@ static void RADEONPreInitColorTiling(Sc
if (!info->allowColorTiling)
return;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ info->allowColorTiling = FALSE;
+
+ /* for zaphod disable tiling for now */
+ if (info->IsPrimary || info->IsSecondary)
+ info->allowColorTiling = FALSE;
+
#ifdef XF86DRI
if (info->directRenderingEnabled &&
info->pKernelDRMVersion->version_minor < 14) {
@@@ -3813,11 -3710,9 +3912,13 @@@ void RADEONRestoreMemMapRegisters(ScrnI
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
int timeout;
+ CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi;
+
+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc,
+ &mc_agp_loc, &mc_agp_loc_hi);
+ if (info->IsSecondary)
+ return;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONRestoreMemMapRegisters() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@@ -4024,36 -3863,36 +4125,39 @@@
static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 fb, agp;
+ CARD32 fb, agp, agp_hi;
+ int changed;
+ if (info->IsSecondary)
+ return;
+
- fb = INREG(RADEON_MC_FB_LOCATION);
- agp = INREG(RADEON_MC_AGP_LOCATION);
-
- if (fb != info->mc_fb_location || agp != info->mc_agp_location) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "DRI init changed memory map, adjusting ...\n");
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_FB_LOCATION was: 0x%08x is: 0x%08x\n",
- (unsigned)info->mc_fb_location, (unsigned)fb);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_AGP_LOCATION was: 0x%08x is: 0x%08x\n",
- (unsigned)info->mc_agp_location, (unsigned)agp);
- info->mc_fb_location = fb;
- info->mc_agp_location = agp;
- info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
- info->dst_pitch_offset =
- (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
- << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
-
+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi);
+
+ if (fb != info->mc_fb_location || agp != info->mc_agp_location ||
+ agp_hi || info->mc_agp_location_hi)
+ changed = 1;
- RADEONInitMemMapRegisters(pScrn, save, info);
+ if (changed) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "DRI init changed memory map, adjusting ...\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
+ info->mc_fb_location, fb);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
+ info->mc_agp_location, agp);
+ info->mc_fb_location = fb;
+ info->mc_agp_location = agp;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
+ else
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
- /* Adjust the various offsets */
- RADEONRestoreMemMapRegisters(pScrn, save);
+ info->dst_pitch_offset =
+ (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
+ << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
+ RADEONInitMemMapRegisters(pScrn, save, info);
+ RADEONRestoreMemMapRegisters(pScrn, save);
}
#ifdef USE_EXA
@@@ -5769,17 -5302,14 +5876,18 @@@ void RADEONRestore(ScrnInfoPtr pScrn
RADEONBlank(pScrn);
- OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
- RADEONPllErrataAfterIndex(info);
- OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
- OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
- OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
- OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
+ if (IS_AVIVO_VARIANT) {
+ RADEONRestoreMemMapRegisters(pScrn, restore);
+ avivo_restore(pScrn, restore);
+ } else {
+ OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
+ RADEONPllErrataAfterIndex(info);
+ OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
+ OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
+ OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
+ OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
+ if (!info->IsSecondary) {
RADEONRestoreMemMapRegisters(pScrn, restore);
RADEONRestoreCommonRegisters(pScrn, restore);
@@@ -5798,10 -5328,9 +5906,10 @@@
if (info->InternalTVOut)
RADEONRestoreTVRegisters(pScrn, restore);
-
+ }
- RADEONRestoreSurfaces(pScrn, restore);
+ RADEONRestoreSurfaces(pScrn, restore);
+ }
#if 1
/* Temp fix to "solve" VT switch problems. When switching VTs on
diff --cc src/radeon_output.c
index 15b4ddf,ecff799..85f1156
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@@ -1249,14 -1188,11 +1249,14 @@@ legacy_mode_set(xf86OutputPtr output, D
case MT_DFP:
if (radeon_output->TMDSType == TMDS_INT) {
ErrorF("restore FP\n");
- RADEONRestoreFPRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreFPRegisters(pScrn, info->ModeReg);
} else {
ErrorF("restore FP2\n");
- RADEONRestoreDVOChip(pScrn, output);
+ if (info->IsAtomBios)
+ atombios_external_tmds_setup(output, mode);
+ else
+ RADEONRestoreDVOChip(pScrn, output);
- RADEONRestoreFP2Registers(pScrn, &info->ModeReg);
+ RADEONRestoreFP2Registers(pScrn, info->ModeReg);
}
break;
case MT_STV:
diff --cc src/radeon_probe.h
index d01fd8b,d1096fb..a7d873e
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@@ -232,14 -221,181 +232,287 @@@ typedef struct _RADEONOutputPrivateRec
int SupportedTVStds;
Bool tv_on;
int load_detection;
+
+ char *name;
+ int output_id;
+ int devices;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
++struct avivo_pll_state {
++ CARD32 ref_div_src;
++ CARD32 ref_div;
++ CARD32 fb_div;
++ CARD32 post_div_src;
++ CARD32 post_div;
++ CARD32 ext_ppll_cntl;
++ CARD32 pll_cntl;
++ CARD32 int_ss_cntl;
++};
++
++
++struct avivo_crtc_state {
++ CARD32 pll_source;
++ CARD32 h_total;
++ CARD32 h_blank_start_end;
++ CARD32 h_sync_a;
++ CARD32 h_sync_a_cntl;
++ CARD32 h_sync_b;
++ CARD32 h_sync_b_cntl;
++ CARD32 v_total;
++ CARD32 v_blank_start_end;
++ CARD32 v_sync_a;
++ CARD32 v_sync_a_cntl;
++ CARD32 v_sync_b;
++ CARD32 v_sync_b_cntl;
++ CARD32 control;
++ CARD32 blank_control;
++ CARD32 interlace_control;
++ CARD32 stereo_control;
++ CARD32 cursor_control;
++};
++
++struct avivo_grph_state {
++ CARD32 enable;
++ CARD32 control;
++ CARD32 prim_surf_addr;
++ CARD32 sec_surf_addr;
++ CARD32 pitch;
++ CARD32 x_offset;
++ CARD32 y_offset;
++ CARD32 x_start;
++ CARD32 y_start;
++ CARD32 x_end;
++ CARD32 y_end;
++
++ CARD32 viewport_start;
++ CARD32 viewport_size;
++ CARD32 scl_enable;
++};
++
++struct avivo_dac_state {
++ CARD32 enable;
++ CARD32 source_select;
++ CARD32 force_output_cntl;
++ CARD32 powerdown;
++};
++
++struct avivo_dig_state {
++ CARD32 cntl;
++ CARD32 bit_depth_cntl;
++ CARD32 data_sync;
++ CARD32 transmitter_enable;
++ CARD32 transmitter_cntl;
++ CARD32 source_select;
++};
++
++struct avivo_state
++{
++ CARD32 hdp_fb_location;
++ CARD32 mc_memory_map;
++ CARD32 vga_memory_base;
++ CARD32 vga_fb_start;
++
++ CARD32 vga1_cntl;
++ CARD32 vga2_cntl;
++
++ CARD32 crtc_master_en;
++ CARD32 crtc_tv_control;
++
++ CARD32 lvtma_pwrseq_cntl;
++ CARD32 lvtma_pwrseq_state;
++
++ struct avivo_pll_state pll1;
++ struct avivo_pll_state pll2;
++
++ struct avivo_crtc_state crtc1;
++ struct avivo_crtc_state crtc2;
++
++ struct avivo_grph_state grph1;
++ struct avivo_grph_state grph2;
++
++ struct avivo_dac_state daca;
++ struct avivo_dac_state dacb;
++
++ struct avivo_dig_state tmds1;
++ struct avivo_dig_state tmds2;
++
++};
+
+ /*
+ * Maximum length of horizontal/vertical code timing tables for state storage
+ */
+ #define MAX_H_CODE_TIMING_LEN 32
+ #define MAX_V_CODE_TIMING_LEN 32
+
+ typedef struct {
++ struct avivo_state avivo;
++
+ /* Common registers */
+ CARD32 ovr_clr;
+ CARD32 ovr_wid_left_right;
+ CARD32 ovr_wid_top_bottom;
+ CARD32 ov0_scale_cntl;
+ CARD32 mpp_tb_config;
+ CARD32 mpp_gp_config;
+ CARD32 subpic_cntl;
+ CARD32 viph_control;
+ CARD32 i2c_cntl_1;
+ CARD32 gen_int_cntl;
+ CARD32 cap0_trig_cntl;
+ CARD32 cap1_trig_cntl;
+ CARD32 bus_cntl;
+ CARD32 bios_4_scratch;
+ CARD32 bios_5_scratch;
+ CARD32 bios_6_scratch;
+ CARD32 surface_cntl;
+ CARD32 surfaces[8][3];
+ CARD32 mc_agp_location;
++ CARD32 mc_agp_location_hi;
+ CARD32 mc_fb_location;
+ CARD32 display_base_addr;
+ CARD32 display2_base_addr;
+ CARD32 ov0_base_addr;
+
+ /* Other registers to save for VT switches */
+ CARD32 dp_datatype;
+ CARD32 rbbm_soft_reset;
+ CARD32 clock_cntl_index;
+ CARD32 amcgpio_en_reg;
+ CARD32 amcgpio_mask;
+
+ /* CRTC registers */
+ CARD32 crtc_gen_cntl;
+ CARD32 crtc_ext_cntl;
+ CARD32 dac_cntl;
+ CARD32 crtc_h_total_disp;
+ CARD32 crtc_h_sync_strt_wid;
+ CARD32 crtc_v_total_disp;
+ CARD32 crtc_v_sync_strt_wid;
+ CARD32 crtc_offset;
+ CARD32 crtc_offset_cntl;
+ CARD32 crtc_pitch;
+ CARD32 disp_merge_cntl;
+ CARD32 grph_buffer_cntl;
+ CARD32 crtc_more_cntl;
+ CARD32 crtc_tile_x0_y0;
+
+ /* CRTC2 registers */
+ CARD32 crtc2_gen_cntl;
+ CARD32 dac_macro_cntl;
+ CARD32 dac2_cntl;
+ CARD32 disp_output_cntl;
+ CARD32 disp_tv_out_cntl;
+ CARD32 disp_hw_debug;
+ CARD32 disp2_merge_cntl;
+ CARD32 grph2_buffer_cntl;
+ CARD32 crtc2_h_total_disp;
+ CARD32 crtc2_h_sync_strt_wid;
+ CARD32 crtc2_v_total_disp;
+ CARD32 crtc2_v_sync_strt_wid;
+ CARD32 crtc2_offset;
+ CARD32 crtc2_offset_cntl;
+ CARD32 crtc2_pitch;
+ CARD32 crtc2_tile_x0_y0;
+
+ /* Flat panel registers */
+ CARD32 fp_crtc_h_total_disp;
+ CARD32 fp_crtc_v_total_disp;
+ CARD32 fp_gen_cntl;
+ CARD32 fp2_gen_cntl;
+ CARD32 fp_h_sync_strt_wid;
+ CARD32 fp_h2_sync_strt_wid;
+ CARD32 fp_horz_stretch;
+ CARD32 fp_panel_cntl;
+ CARD32 fp_v_sync_strt_wid;
+ CARD32 fp_v2_sync_strt_wid;
+ CARD32 fp_vert_stretch;
+ CARD32 lvds_gen_cntl;
+ CARD32 lvds_pll_cntl;
+ CARD32 tmds_pll_cntl;
+ CARD32 tmds_transmitter_cntl;
+
+ /* Computed values for PLL */
+ CARD32 dot_clock_freq;
+ CARD32 pll_output_freq;
+ int feedback_div;
+ int post_div;
+
+ /* PLL registers */
+ unsigned ppll_ref_div;
+ unsigned ppll_div_3;
+ CARD32 htotal_cntl;
+ CARD32 vclk_ecp_cntl;
+
+ /* Computed values for PLL2 */
+ CARD32 dot_clock_freq_2;
+ CARD32 pll_output_freq_2;
+ int feedback_div_2;
+ int post_div_2;
+
+ /* PLL2 registers */
+ CARD32 p2pll_ref_div;
+ CARD32 p2pll_div_0;
+ CARD32 htotal_cntl2;
+ CARD32 pixclks_cntl;
+
+ /* Pallet */
+ Bool palette_valid;
+ CARD32 palette[256];
+ CARD32 palette2[256];
+
+ CARD32 rs480_unk_e30;
+ CARD32 rs480_unk_e34;
+ CARD32 rs480_unk_e38;
+ CARD32 rs480_unk_e3c;
+
+ /* TV out registers */
+ CARD32 tv_master_cntl;
+ CARD32 tv_htotal;
+ CARD32 tv_hsize;
+ CARD32 tv_hdisp;
+ CARD32 tv_hstart;
+ CARD32 tv_vtotal;
+ CARD32 tv_vdisp;
+ CARD32 tv_timing_cntl;
+ CARD32 tv_vscaler_cntl1;
+ CARD32 tv_vscaler_cntl2;
+ CARD32 tv_sync_size;
+ CARD32 tv_vrestart;
+ CARD32 tv_hrestart;
+ CARD32 tv_frestart;
+ CARD32 tv_ftotal;
+ CARD32 tv_clock_sel_cntl;
+ CARD32 tv_clkout_cntl;
+ CARD32 tv_data_delay_a;
+ CARD32 tv_data_delay_b;
+ CARD32 tv_dac_cntl;
+ CARD32 tv_pll_cntl;
+ CARD32 tv_pll_cntl1;
+ CARD32 tv_pll_fine_cntl;
+ CARD32 tv_modulator_cntl1;
+ CARD32 tv_modulator_cntl2;
+ CARD32 tv_frame_lock_cntl;
+ CARD32 tv_pre_dac_mux_cntl;
+ CARD32 tv_rgb_cntl;
+ CARD32 tv_y_saw_tooth_cntl;
+ CARD32 tv_y_rise_cntl;
+ CARD32 tv_y_fall_cntl;
+ CARD32 tv_uv_adr;
+ CARD32 tv_upsamp_and_gain_cntl;
+ CARD32 tv_gain_limit_settings;
+ CARD32 tv_linear_gain_settings;
+ CARD32 tv_crc_cntl;
+ CARD32 tv_sync_cntl;
+ CARD32 gpiopad_a;
+ CARD32 pll_test_cntl;
+
+ CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
+ CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
+
+ } RADEONSaveRec, *RADEONSavePtr;
+
#define RADEON_MAX_CRTC 2
-#define RADEON_MAX_BIOS_CONNECTOR 8
+#define RADEON_MAX_BIOS_CONNECTOR 16
typedef struct
{
commit 6451ea2dcc4fac762442f699935864f4a8d445f7
Merge: 0d89556... 5896ca4...
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Dec 10 15:08:42 2007 +1000
Merge branch 'master' into atombios-support
commit 5896ca4097d439f59f90f397939132c061c3c364
Author: LisaWu <liswu at ati.com>
Date: Fri Dec 7 09:45:05 2007 +0100
radeon: Use %u instead of %d for unsigned value.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 9bf46ef..50f78eb 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1064,7 +1064,7 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
}
xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "PLL parameters: rf=%d rd=%d min=%d max=%d; xclk=%d\n",
+ "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n",
pll->reference_freq,
pll->reference_div,
(unsigned)pll->min_pll_freq, (unsigned)pll->max_pll_freq,
commit df44f8380268c27d3978c4e91d736f093322b8b8
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Fri Dec 7 09:41:47 2007 +0100
radeon: Use gettimeofday instead of xf86getsecs.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 3422b66..9bf46ef 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -90,7 +90,6 @@
/* X and server generic header files */
#include "xf86.h"
-#include "xf86_ansic.h" /* For xf86getsecs() */
#include "xf86_OSproc.h"
#include "xf86RAC.h"
#include "xf86RandR12.h"
@@ -805,8 +804,8 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
unsigned xclk, tmp, ref_div;
int hTotal, vTotal, num, denom, m, n;
float hz, prev_xtal, vclk, xtal, mpll, spll;
- long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs;
- long to1_secs, to1_usecs, to2_secs, to2_usecs;
+ long total_usecs;
+ struct timeval start, stop, to1, to2;
unsigned int f1, f2, f3;
int tries = 0;
@@ -816,32 +815,32 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
if (++tries > 10)
goto failed;
- xf86getsecs(&to1_secs, &to1_usecs);
+ gettimeofday(&to1, NULL);
f1 = INREG(RADEON_CRTC_CRNT_FRAME);
for (;;) {
f2 = INREG(RADEON_CRTC_CRNT_FRAME);
if (f1 != f2)
break;
- xf86getsecs(&to2_secs, &to2_usecs);
- if ((to2_secs - to1_secs) > 1) {
+ gettimeofday(&to2, NULL);
+ if ((to2.tv_sec - to1.tv_sec) > 1) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n");
goto failed;
}
}
- xf86getsecs(&start_secs, &start_usecs);
+ gettimeofday(&start, NULL);
for(;;) {
f3 = INREG(RADEON_CRTC_CRNT_FRAME);
if (f3 != f2)
break;
- xf86getsecs(&to2_secs, &to2_usecs);
- if ((to2_secs - start_secs) > 1)
+ gettimeofday(&to2, NULL);
+ if ((to2.tv_sec - start.tv_sec) > 1)
goto failed;
}
- xf86getsecs(&stop_secs, &stop_usecs);
+ gettimeofday(&stop, NULL);
- if ((stop_secs - start_secs) != 0)
+ if ((stop.tv_sec - start.tv_sec) != 0)
goto again;
- total_usecs = abs(stop_usecs - start_usecs);
+ total_usecs = abs(stop.tv_usec - start.tv_usec);
if (total_usecs == 0)
goto again;
hz = 1000000.0/(float)total_usecs;
commit cc167b9bb7f1c3b8579e51e7bc2fca2f8eba6bd1
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Dec 7 15:41:36 2007 +1000
disable tiling for zaphod heads
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 0632fd3..35b9a47 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2118,6 +2118,10 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn)
if (!info->allowColorTiling)
return;
+ /* for zaphod disable tiling for now */
+ if (info->IsPrimary || info->IsSecondary)
+ info->allowColorTiling = FALSE;
+
#ifdef XF86DRI
if (info->directRenderingEnabled &&
info->pKernelDRMVersion->version_minor < 14) {
commit 2ce8d192533a8c795714c5a9fb308ec74db40287
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Dec 7 15:35:21 2007 +1000
don't add fboffset to info->FB it already is mapped at the offset
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index b8cfffd..5004b64 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -189,7 +189,7 @@ radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
+ CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset);
int pixel, i;
CURSOR_SWAPPING_DECL_MMIO
@@ -231,7 +231,7 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
+ CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset);
RADEONCTRACE(("RADEONLoadCursorARGB\n"));
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 6db1d96..0632fd3 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -3474,7 +3474,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
"Initializing fb layer\n");
/* Init fb layer */
- if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset,
+ if (!fbScreenInit(pScreen, info->FB,
pScrn->virtualX, pScrn->virtualY,
pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
pScrn->bitsPerPixel))
commit 0dcd926d3092100854b3e362d6659d4950508aeb
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Dec 7 14:45:04 2007 +1000
radeon: bring back zaphod all is forgiven.
You've whined, you've cried, you've nagged, and you're guilt trippin has
made me do it... It actually wasn't as hard as I thought it would be.
Still not perfect, couple of things to fix yet
diff --git a/src/radeon.h b/src/radeon.h
index 529374e..5c3bf86 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -681,6 +681,10 @@ typedef struct {
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
+
+
+ Bool IsSecondary;
+ Bool IsPrimary;
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
@@ -801,7 +805,7 @@ extern void RADEONBlank(ScrnInfoPtr pScrn);
extern void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
int PowerManagementMode,
int flags);
-extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn);
+extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn);
extern int RADEONValidateMergeModes(ScrnInfoPtr pScrn);
extern int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName,
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 718073c..f28bdf7 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -1203,40 +1203,45 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = {
.destroy = NULL, /* XXX */
};
-Bool RADEONAllocateControllers(ScrnInfoPtr pScrn)
+Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- if (pRADEONEnt->Controller[0])
- return TRUE;
+ if (mask & 1) {
+ if (pRADEONEnt->Controller[0])
+ return TRUE;
+
+ pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
+ if (!pRADEONEnt->pCrtc[0])
+ return FALSE;
- pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[0])
- return FALSE;
+ pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
+ if (!pRADEONEnt->Controller[0])
+ return FALSE;
- pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[0])
- return FALSE;
+ pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
+ pRADEONEnt->Controller[0]->crtc_id = 0;
- pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
- pRADEONEnt->Controller[0]->crtc_id = 0;
-
- if (!pRADEONEnt->HasCRTC2)
- return TRUE;
+ }
- pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[1])
- return FALSE;
+ if (mask & 2) {
+ if (!pRADEONEnt->HasCRTC2)
+ return TRUE;
+
+ pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
+ if (!pRADEONEnt->pCrtc[1])
+ return FALSE;
+
+ pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
+ if (!pRADEONEnt->Controller[1])
+ {
+ xfree(pRADEONEnt->Controller[0]);
+ return FALSE;
+ }
- pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[1])
- {
- xfree(pRADEONEnt->Controller[0]);
- return FALSE;
+ pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
+ pRADEONEnt->Controller[1]->crtc_id = 1;
}
-
- pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
- pRADEONEnt->Controller[1]->crtc_id = 1;
return TRUE;
}
diff --git a/src/radeon_display.c b/src/radeon_display.c
index f678dda..07d633f 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -318,7 +318,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
{
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONSavePtr save = &info->ModeReg;
+ RADEONSavePtr save = info->ModeReg;
unsigned char * RADEONMMIO = info->MMIO;
unsigned long tmp;
RADEONOutputPrivatePtr radeon_output;
@@ -773,7 +773,10 @@ void RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
DisplayModePtr mode1, mode2;
int pixel_bytes2 = 0;
- mode1 = info->CurrentLayout.mode;
+ if (info->IsPrimary || info->IsSecondary)
+ mode1 = &xf86_config->crtc[0]->mode;
+ else
+ mode1 = info->CurrentLayout.mode;
mode2 = NULL;
pixel_bytes2 = info->CurrentLayout.pixel_bytes;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index f01c9aa..6db1d96 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1446,6 +1446,21 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, from,
"Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR");
+ if (info->IsPrimary) {
+ pScrn->videoRam /= 2;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Using %dk of videoram for primary head\n",
+ pScrn->videoRam);
+ }
+
+ if (info->IsSecondary) {
+ pScrn->videoRam /= 2;
+ info->LinearAddr += pScrn->videoRam * 1024;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Using %dk of videoram for secondary head\n",
+ pScrn->videoRam);
+ }
+
pScrn->videoRam &= ~1023;
info->FbMapSize = pScrn->videoRam * 1024;
@@ -1881,6 +1896,18 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->pLibDRMVersion = NULL;
info->pKernelDRMVersion = NULL;
+ if (xf86IsEntityShared(info->pEnt->index)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Direct Rendering Disabled -- "
+ "Dual-head configuration is not working with "
+ "DRI at present.\n"
+ "Please use the radeon MergedFB option if you "
+ "want Dual-head with DRI.\n");
+ return FALSE;
+ }
+ if (info->IsSecondary)
+ return FALSE;
+
if (info->Chipset == PCI_CHIP_RN50_515E ||
info->Chipset == PCI_CHIP_RN50_5969 ||
info->Chipset == PCI_CHIP_RC410_5A61 ||
@@ -2311,12 +2338,41 @@ static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
#endif
}
+static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn)
+{
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
+ int i;
+
+ if (info->IsPrimary) {
+ while(config->num_output > 1) {
+ xf86OutputDestroy(config->output[1]);
+ }
+ } else {
+ xf86OutputDestroy(config->output[0]);
+ while(config->num_output > 1) {
+ xf86OutputDestroy(config->output[1]);
+ }
+ }
+}
+
static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
{
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ RADEONInfoPtr info = RADEONPTR(pScrn);
int i;
+ int mask;
- if (!RADEONAllocateControllers(pScrn))
+ if (!info->IsPrimary && !info->IsSecondary)
+ mask = 3;
+ else if (info->IsPrimary)
+ mask = 1;
+ else
+ mask = 2;
+
+ if (!RADEONAllocateControllers(pScrn, mask))
return FALSE;
RADEONGetClockInfo(pScrn);
@@ -2324,6 +2380,11 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
if (!RADEONSetupConnectors(pScrn)) {
return FALSE;
}
+
+ if (info->IsPrimary || info->IsSecondary) {
+ /* fixup outputs for zaphod */
+ RADEONFixZaphodOutputs(pScrn);
+ }
RADEONPrintPortMap(pScrn);
@@ -2382,6 +2443,9 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info = RADEONPTR(pScrn);
info->MMIO = NULL;
+ info->IsSecondary = FALSE;
+ info->IsPrimary = FALSE;
+
info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
if (info->pEnt->location.type != BUS_PCI) goto fail;
@@ -2389,8 +2453,28 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
getRADEONEntityIndex());
pRADEONEnt = pPriv->ptr;
- info->SavedReg = &pRADEONEnt->SavedReg;
- info->ModeReg = &pRADEONEnt->ModeReg;
+ if(xf86IsEntityShared(pScrn->entityList[0]))
+ {
+ if(xf86IsPrimInitDone(pScrn->entityList[0]))
+ {
+ info->IsSecondary = TRUE;
+ pRADEONEnt->pSecondaryScrn = pScrn;
+ info->SavedReg = &pRADEONEnt->SavedReg;
+ info->ModeReg = &pRADEONEnt->ModeReg;
+ }
+ else
+ {
+ info->IsPrimary = TRUE;
+ xf86SetPrimInitDone(pScrn->entityList[0]);
+ pRADEONEnt->pPrimaryScrn = pScrn;
+ pRADEONEnt->HasSecondary = FALSE;
+ info->SavedReg = &pRADEONEnt->SavedReg;
+ info->ModeReg = &pRADEONEnt->ModeReg;
+ }
+ } else {
+ info->SavedReg = &pRADEONEnt->SavedReg;
+ info->ModeReg = &pRADEONEnt->ModeReg;
+ }
info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo),
@@ -2739,10 +2823,11 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
/* Make the change through RandR */
#ifdef RANDR_12_INTERFACE
- RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b);
-#else
- crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256);
+ if (crtc->randr_crtc)
+ RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b);
+ else
#endif
+ crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256);
}
}
@@ -3153,15 +3238,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
char* s;
#endif
-#ifdef XF86DRI
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONScreenInit %lx %ld %d\n",
- pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset);
-#else
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONScreenInit %lx %ld\n",
- pScrn->memPhysBase, pScrn->fbOffset);
-#endif
info->accelOn = FALSE;
#ifdef USE_XAA
@@ -3171,6 +3247,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
pScrn->fbOffset = info->frontOffset;
#endif
+ if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024;
+#ifdef XF86DRI
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "RADEONScreenInit %lx %ld %d\n",
+ pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset);
+#else
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "RADEONScreenInit %lx %ld\n",
+ pScrn->memPhysBase, pScrn->fbOffset);
+#endif
if (!RADEONMapMem(pScrn)) return FALSE;
#ifdef XF86DRI
@@ -3621,6 +3707,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
unsigned char *RADEONMMIO = info->MMIO;
int timeout;
+ if (info->IsSecondary)
+ return;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONRestoreMemMapRegisters() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -3774,6 +3862,9 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
unsigned char *RADEONMMIO = info->MMIO;
CARD32 fb, agp;
+ if (info->IsSecondary)
+ return;
+
fb = INREG(RADEON_MC_FB_LOCATION);
agp = INREG(RADEON_MC_AGP_LOCATION);
@@ -3832,6 +3923,9 @@ void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
+ if (info->IsSecondary)
+ return;
+
OUTREG(RADEON_OVR_CLR, restore->ovr_clr);
OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
@@ -5211,26 +5305,28 @@ void RADEONRestore(ScrnInfoPtr pScrn)
OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
- RADEONRestoreMemMapRegisters(pScrn, restore);
- RADEONRestoreCommonRegisters(pScrn, restore);
+ if (!info->IsSecondary) {
+ RADEONRestoreMemMapRegisters(pScrn, restore);
+ RADEONRestoreCommonRegisters(pScrn, restore);
- if (pRADEONEnt->HasCRTC2) {
- RADEONRestoreCrtc2Registers(pScrn, restore);
- RADEONRestorePLL2Registers(pScrn, restore);
- }
+ if (pRADEONEnt->HasCRTC2) {
+ RADEONRestoreCrtc2Registers(pScrn, restore);
+ RADEONRestorePLL2Registers(pScrn, restore);
+ }
- RADEONRestoreBIOSRegisters(pScrn, restore);
- RADEONRestoreCrtcRegisters(pScrn, restore);
- RADEONRestorePLLRegisters(pScrn, restore);
- RADEONRestoreRMXRegisters(pScrn, restore);
- RADEONRestoreFPRegisters(pScrn, restore);
- RADEONRestoreFP2Registers(pScrn, restore);
- RADEONRestoreLVDSRegisters(pScrn, restore);
+ RADEONRestoreBIOSRegisters(pScrn, restore);
+ RADEONRestoreCrtcRegisters(pScrn, restore);
+ RADEONRestorePLLRegisters(pScrn, restore);
+ RADEONRestoreRMXRegisters(pScrn, restore);
+ RADEONRestoreFPRegisters(pScrn, restore);
+ RADEONRestoreFP2Registers(pScrn, restore);
+ RADEONRestoreLVDSRegisters(pScrn, restore);
- if (info->InternalTVOut)
- RADEONRestoreTVRegisters(pScrn, restore);
+ if (info->InternalTVOut)
+ RADEONRestoreTVRegisters(pScrn, restore);
- RADEONRestoreSurfaces(pScrn, restore);
+ RADEONRestoreSurfaces(pScrn, restore);
+ }
#if 1
/* Temp fix to "solve" VT switch problems. When switching VTs on
@@ -5258,8 +5354,8 @@ void RADEONRestore(ScrnInfoPtr pScrn)
#endif
/* need to make sure we don't enable a crtc by accident or we may get a hang */
- if (pRADEONEnt->HasCRTC2) {
- if (info->crtc2_on) {
+ if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) {
+ if (info->crtc2_on && xf86_config->num_crtc > 1) {
crtc = xf86_config->crtc[1];
crtc->funcs->dpms(crtc, DPMSModeOn);
}
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index baea47c..e0a77e6 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -175,7 +175,7 @@ RADEONProbe(DriverPtr drv, int flags)
DevUnion *pPriv;
RADEONEntPtr pRADEONEnt;
- /*xf86SetEntitySharable(usedChips[i]);*/
+ xf86SetEntitySharable(usedChips[i]);
if (gRADEONEntityIndex == -1)
gRADEONEntityIndex = xf86AllocateEntityPrivateIndex();
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index cdefdf5..d1096fb 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -413,6 +413,9 @@ typedef struct
xf86CrtcPtr pCrtc[RADEON_MAX_CRTC];
RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC];
+ ScrnInfoPtr pSecondaryScrn;
+ ScrnInfoPtr pPrimaryScrn;
+
RADEONSaveRec ModeReg; /* Current mode */
RADEONSaveRec SavedReg; /* Original (text) mode */
commit bb5ede557bf32a42eef158ff0fbcfe1c6ede098a
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Dec 7 14:30:32 2007 +1000
radeon: move savedreg/modereg into entity instead of info
diff --git a/src/radeon.h b/src/radeon.h
index fe491e8..529374e 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -200,169 +200,7 @@ typedef struct {
CARD16 rr4_offset;
} RADEONBIOSInitTable;
-typedef struct {
- /* Common registers */
- CARD32 ovr_clr;
- CARD32 ovr_wid_left_right;
- CARD32 ovr_wid_top_bottom;
- CARD32 ov0_scale_cntl;
- CARD32 mpp_tb_config;
- CARD32 mpp_gp_config;
- CARD32 subpic_cntl;
- CARD32 viph_control;
- CARD32 i2c_cntl_1;
- CARD32 gen_int_cntl;
- CARD32 cap0_trig_cntl;
- CARD32 cap1_trig_cntl;
- CARD32 bus_cntl;
- CARD32 bios_4_scratch;
- CARD32 bios_5_scratch;
- CARD32 bios_6_scratch;
- CARD32 surface_cntl;
- CARD32 surfaces[8][3];
- CARD32 mc_agp_location;
- CARD32 mc_fb_location;
- CARD32 display_base_addr;
- CARD32 display2_base_addr;
- CARD32 ov0_base_addr;
-
- /* Other registers to save for VT switches */
- CARD32 dp_datatype;
- CARD32 rbbm_soft_reset;
- CARD32 clock_cntl_index;
- CARD32 amcgpio_en_reg;
- CARD32 amcgpio_mask;
-
- /* CRTC registers */
- CARD32 crtc_gen_cntl;
- CARD32 crtc_ext_cntl;
- CARD32 dac_cntl;
- CARD32 crtc_h_total_disp;
- CARD32 crtc_h_sync_strt_wid;
- CARD32 crtc_v_total_disp;
- CARD32 crtc_v_sync_strt_wid;
- CARD32 crtc_offset;
- CARD32 crtc_offset_cntl;
- CARD32 crtc_pitch;
- CARD32 disp_merge_cntl;
- CARD32 grph_buffer_cntl;
- CARD32 crtc_more_cntl;
- CARD32 crtc_tile_x0_y0;
-
- /* CRTC2 registers */
- CARD32 crtc2_gen_cntl;
- CARD32 dac_macro_cntl;
- CARD32 dac2_cntl;
- CARD32 disp_output_cntl;
- CARD32 disp_tv_out_cntl;
- CARD32 disp_hw_debug;
- CARD32 disp2_merge_cntl;
- CARD32 grph2_buffer_cntl;
- CARD32 crtc2_h_total_disp;
- CARD32 crtc2_h_sync_strt_wid;
- CARD32 crtc2_v_total_disp;
- CARD32 crtc2_v_sync_strt_wid;
- CARD32 crtc2_offset;
- CARD32 crtc2_offset_cntl;
- CARD32 crtc2_pitch;
- CARD32 crtc2_tile_x0_y0;
-
- /* Flat panel registers */
- CARD32 fp_crtc_h_total_disp;
- CARD32 fp_crtc_v_total_disp;
- CARD32 fp_gen_cntl;
- CARD32 fp2_gen_cntl;
- CARD32 fp_h_sync_strt_wid;
- CARD32 fp_h2_sync_strt_wid;
- CARD32 fp_horz_stretch;
- CARD32 fp_panel_cntl;
- CARD32 fp_v_sync_strt_wid;
- CARD32 fp_v2_sync_strt_wid;
- CARD32 fp_vert_stretch;
- CARD32 lvds_gen_cntl;
- CARD32 lvds_pll_cntl;
- CARD32 tmds_pll_cntl;
- CARD32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- CARD32 dot_clock_freq;
- CARD32 pll_output_freq;
- int feedback_div;
- int post_div;
-
- /* PLL registers */
- unsigned ppll_ref_div;
- unsigned ppll_div_3;
- CARD32 htotal_cntl;
- CARD32 vclk_ecp_cntl;
-
- /* Computed values for PLL2 */
- CARD32 dot_clock_freq_2;
- CARD32 pll_output_freq_2;
- int feedback_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- CARD32 p2pll_ref_div;
- CARD32 p2pll_div_0;
- CARD32 htotal_cntl2;
- CARD32 pixclks_cntl;
-
- /* Pallet */
- Bool palette_valid;
- CARD32 palette[256];
- CARD32 palette2[256];
-
- CARD32 rs480_unk_e30;
- CARD32 rs480_unk_e34;
- CARD32 rs480_unk_e38;
- CARD32 rs480_unk_e3c;
-
- /* TV out registers */
- CARD32 tv_master_cntl;
- CARD32 tv_htotal;
- CARD32 tv_hsize;
- CARD32 tv_hdisp;
- CARD32 tv_hstart;
- CARD32 tv_vtotal;
- CARD32 tv_vdisp;
- CARD32 tv_timing_cntl;
- CARD32 tv_vscaler_cntl1;
- CARD32 tv_vscaler_cntl2;
- CARD32 tv_sync_size;
- CARD32 tv_vrestart;
- CARD32 tv_hrestart;
- CARD32 tv_frestart;
- CARD32 tv_ftotal;
- CARD32 tv_clock_sel_cntl;
- CARD32 tv_clkout_cntl;
- CARD32 tv_data_delay_a;
- CARD32 tv_data_delay_b;
- CARD32 tv_dac_cntl;
- CARD32 tv_pll_cntl;
- CARD32 tv_pll_cntl1;
- CARD32 tv_pll_fine_cntl;
- CARD32 tv_modulator_cntl1;
- CARD32 tv_modulator_cntl2;
- CARD32 tv_frame_lock_cntl;
- CARD32 tv_pre_dac_mux_cntl;
- CARD32 tv_rgb_cntl;
- CARD32 tv_y_saw_tooth_cntl;
- CARD32 tv_y_rise_cntl;
- CARD32 tv_y_fall_cntl;
- CARD32 tv_uv_adr;
- CARD32 tv_upsamp_and_gain_cntl;
- CARD32 tv_gain_limit_settings;
- CARD32 tv_linear_gain_settings;
- CARD32 tv_crc_cntl;
- CARD32 tv_sync_cntl;
- CARD32 gpiopad_a;
- CARD32 pll_test_cntl;
-
- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
-
-} RADEONSaveRec, *RADEONSavePtr;
+
typedef struct {
CARD16 reference_freq;
@@ -522,8 +360,8 @@ typedef struct {
Bool IsDDR;
int DispPriority;
- RADEONSaveRec SavedReg; /* Original (text) mode */
- RADEONSaveRec ModeReg; /* Current mode */
+ RADEONSavePtr SavedReg; /* Original (text) mode */
+ RADEONSavePtr ModeReg; /* Current mode */
Bool (*CloseScreen)(int, ScreenPtr);
void (*BlockHandler)(int, pointer, pointer, pointer);
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 6028aff..7f05578 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -322,7 +322,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn)
#endif
/* Restore SURFACE_CNTL */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
RADEONWaitForFifo(pScrn, 1);
OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index b1d216d..718073c 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -311,7 +311,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
return FALSE;
}
- /*save->bios_4_scratch = info->SavedReg.bios_4_scratch;*/
+ /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/
save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
| RADEON_CRTC_EN
| (format << 8)
@@ -330,7 +330,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
RADEON_CRTC_HSYNC_DIS |
RADEON_CRTC_DISPLAY_DIS);
- save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
+ save->disp_merge_cntl = info->SavedReg->disp_merge_cntl;
save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
save->crtc_more_cntl = 0;
@@ -380,10 +380,10 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
if (info->IsDellServer) {
- save->dac2_cntl = info->SavedReg.dac2_cntl;
- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl;
- save->crtc2_gen_cntl = info->SavedReg.crtc2_gen_cntl;
- save->disp_hw_debug = info->SavedReg.disp_hw_debug;
+ save->dac2_cntl = info->SavedReg->dac2_cntl;
+ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl;
+ save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl;
+ save->disp_hw_debug = info->SavedReg->disp_hw_debug;
save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
@@ -589,7 +589,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
? RADEON_CRTC2_INTERLACE_EN
: 0));
- save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl;
+ save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl;
save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
@@ -687,7 +687,7 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
save->htotal_cntl = 0;
- save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl &
+ save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl &
~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
}
@@ -757,7 +757,7 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
(post_div->bitvalue << 16));
save->htotal_cntl2 = 0;
- save->pixclks_cntl = ((info->SavedReg.pixclks_cntl &
+ save->pixclks_cntl = ((info->SavedReg->pixclks_cntl &
~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
@@ -770,8 +770,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
/* tell the bios not to muck with the hardware on events */
save->bios_4_scratch = 0x4; /* 0x4 needed for backlight */
- save->bios_5_scratch = (info->SavedReg.bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */
- save->bios_6_scratch = info->SavedReg.bios_6_scratch | 0x40000000;
+ save->bios_5_scratch = (info->SavedReg->bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */
+ save->bios_6_scratch = info->SavedReg->bios_6_scratch | 0x40000000;
}
@@ -823,38 +823,38 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
}
if (info->IsMobility)
- RADEONInitBIOSRegisters(pScrn, &info->ModeReg);
+ RADEONInitBIOSRegisters(pScrn, info->ModeReg);
ErrorF("init memmap\n");
- RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info);
+ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
ErrorF("init common\n");
- RADEONInitCommonRegisters(&info->ModeReg, info);
+ RADEONInitCommonRegisters(info->ModeReg, info);
- RADEONInitSurfaceCntl(crtc, &info->ModeReg);
+ RADEONInitSurfaceCntl(crtc, info->ModeReg);
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("init crtc1\n");
- RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode);
- RADEONInitCrtcBase(crtc, &info->ModeReg, x, y);
+ RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode);
+ RADEONInitCrtcBase(crtc, info->ModeReg, x, y);
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, info, &info->ModeReg, &info->pll, dot_clock);
+ RADEONInitPLLRegisters(pScrn, info, info->ModeReg, &info->pll, dot_clock);
} else {
- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
+ info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
+ info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
+ info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl;
}
break;
case 1:
ErrorF("init crtc2\n");
- RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode);
- RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y);
+ RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode);
+ RADEONInitCrtc2Base(crtc, info->ModeReg, x, y);
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, dot_clock, no_odd_post_div);
+ RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, dot_clock, no_odd_post_div);
}
break;
}
@@ -867,13 +867,13 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
switch (radeon_crtc->crtc_id) {
case 0:
- RADEONAdjustCrtcRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
- RADEONAdjustPLLRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
+ RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
+ RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
update_tv_routing = TRUE;
break;
case 1:
- RADEONAdjustCrtc2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
- RADEONAdjustPLL2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
+ RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
+ RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
break;
}
}
@@ -881,31 +881,31 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
}
if (info->IsMobility)
- RADEONRestoreBIOSRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreBIOSRegisters(pScrn, info->ModeReg);
ErrorF("restore memmap\n");
- RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
ErrorF("restore common\n");
- RADEONRestoreCommonRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreCommonRegisters(pScrn, info->ModeReg);
switch (radeon_crtc->crtc_id) {
case 0:
ErrorF("restore crtc1\n");
- RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreCrtcRegisters(pScrn, info->ModeReg);
ErrorF("restore pll1\n");
- RADEONRestorePLLRegisters(pScrn, &info->ModeReg);
+ RADEONRestorePLLRegisters(pScrn, info->ModeReg);
break;
case 1:
ErrorF("restore crtc2\n");
- RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg);
+ RADEONRestoreCrtc2Registers(pScrn, info->ModeReg);
ErrorF("restore pll2\n");
- RADEONRestorePLL2Registers(pScrn, &info->ModeReg);
+ RADEONRestorePLL2Registers(pScrn, info->ModeReg);
break;
}
/* pixclks_cntl handles tv-out clock routing */
if (update_tv_routing)
- radeon_update_tv_routing(pScrn, &info->ModeReg);
+ radeon_update_tv_routing(pScrn, info->ModeReg);
if (info->DispPriority)
RADEONInitDispBandwidth(pScrn);
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 5c4fbfa..f678dda 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -689,7 +689,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
critical_point = 0x10;
}
- temp = info->SavedReg.grph_buffer_cntl;
+ temp = info->SavedReg->grph_buffer_cntl;
temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
temp &= ~(RADEON_GRPH_START_REQ_MASK);
@@ -711,7 +711,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg.grph_buffer_cntl,
+ (unsigned int)info->SavedReg->grph_buffer_cntl,
INREG(RADEON_GRPH_BUFFER_CNTL));
if (mode2) {
@@ -719,7 +719,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
if (stop_req > max_stop_req) stop_req = max_stop_req;
- temp = info->SavedReg.grph2_buffer_cntl;
+ temp = info->SavedReg->grph2_buffer_cntl;
temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
temp &= ~(RADEON_GRPH_START_REQ_MASK);
@@ -761,7 +761,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH2_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg.grph2_buffer_cntl,
+ (unsigned int)info->SavedReg->grph2_buffer_cntl,
INREG(RADEON_GRPH2_BUFFER_CNTL));
}
}
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 7136e4e..dbfa8d9 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -1197,7 +1197,7 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
info->irq = 0;
} else {
unsigned char *RADEONMMIO = info->MMIO;
- info->ModeReg.gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
+ info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
}
}
@@ -1774,7 +1774,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
RADEONDRISetVBlankInterrupt (pScrn, FALSE);
drmCtlUninstHandler(info->drmFD);
info->irq = 0;
- info->ModeReg.gen_int_cntl = 0;
+ info->ModeReg->gen_int_cntl = 0;
}
/* De-allocate vertex buffers */
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 3422b66..f01c9aa 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2370,6 +2370,8 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
void *int10_save = NULL;
const char *s;
int crtc_max_X, crtc_max_Y;
+ RADEONEntPtr pRADEONEnt;
+ DevUnion* pPriv;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONPreInit\n");
@@ -2383,6 +2385,13 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
if (info->pEnt->location.type != BUS_PCI) goto fail;
+ pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
+ getRADEONEntityIndex());
+ pRADEONEnt = pPriv->ptr;
+
+ info->SavedReg = &pRADEONEnt->SavedReg;
+ info->ModeReg = &pRADEONEnt->ModeReg;
+
info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo),
PCI_DEV_DEV(info->PciInfo),
@@ -3469,7 +3478,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
* our local image to make sure we restore them properly on mode
* changes or VT switches
*/
- RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg);
+ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {
/* we need to re-calculate bandwidth because of AGPMode difference. */
@@ -4801,7 +4810,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
}
/* Update surface images */
- RADEONSaveSurfaces(pScrn, &info->ModeReg);
+ RADEONSaveSurfaces(pScrn, info->ModeReg);
}
/* Read memory map */
@@ -5129,7 +5138,7 @@ static void RADEONSave(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr save = &info->SavedReg;
+ RADEONSavePtr save = info->SavedReg;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONSave\n");
@@ -5181,7 +5190,7 @@ void RADEONRestore(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr restore = &info->SavedReg;
+ RADEONSavePtr restore = info->SavedReg;
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
xf86CrtcPtr crtc;
@@ -5585,7 +5594,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
}
- RADEONRestoreSurfaces(pScrn, &info->ModeReg);
+ RADEONRestoreSurfaces(pScrn, info->ModeReg);
#ifdef XF86DRI
if (info->directRenderingEnabled) {
if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize)
@@ -5597,7 +5606,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
/* get the DRI back into shape after resume */
RADEONDRISetVBlankInterrupt (pScrn, TRUE);
RADEONDRIResume(pScrn->pScreen);
- RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg);
+ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
}
#endif
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 11a2a8a..ecff799 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -837,7 +837,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
int i;
- CARD32 tmp = info->SavedReg.tmds_pll_cntl & 0xfffff;
+ CARD32 tmp = info->SavedReg->tmds_pll_cntl & 0xfffff;
for (i=0; i<4; i++) {
if (radeon_output->tmds_pll[i].freq == 0) break;
@@ -851,12 +851,12 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
if (tmp & 0xfff00000)
save->tmds_pll_cntl = tmp;
else {
- save->tmds_pll_cntl = info->SavedReg.tmds_pll_cntl & 0xfff00000;
+ save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000;
save->tmds_pll_cntl |= tmp;
}
} else save->tmds_pll_cntl = tmp;
- save->tmds_transmitter_cntl = info->SavedReg.tmds_transmitter_cntl &
+ save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl &
~(RADEON_TMDS_TRANSMITTER_PLLRST);
if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !pRADEONEnt->HasCRTC2)
@@ -864,7 +864,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
else /* weird, RV chips got this bit reversed? */
save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
- save->fp_gen_cntl = info->SavedReg.fp_gen_cntl |
+ save->fp_gen_cntl = info->SavedReg->fp_gen_cntl |
(RADEON_FP_CRTC_DONT_SHADOW_VPAR |
RADEON_FP_CRTC_DONT_SHADOW_HEND );
@@ -903,10 +903,10 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
if (pScrn->rgbBits == 8)
- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl |
+ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl |
RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
else
- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl &
+ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
save->fp2_gen_cntl &= ~(RADEON_FP2_ON |
@@ -948,12 +948,12 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save,
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- save->lvds_pll_cntl = (info->SavedReg.lvds_pll_cntl |
+ save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl |
RADEON_LVDS_PLL_EN);
save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
- save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl;
+ save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl;
save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
@@ -985,9 +985,9 @@ static void RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save,
int yres = mode->VDisplay;
float Hratio, Vratio;
- save->fp_vert_stretch = info->SavedReg.fp_vert_stretch &
+ save->fp_vert_stretch = info->SavedReg->fp_vert_stretch &
RADEON_VERT_STRETCH_RESERVED;
- save->fp_horz_stretch = info->SavedReg.fp_horz_stretch &
+ save->fp_horz_stretch = info->SavedReg->fp_horz_stretch &
(RADEON_HORZ_FP_LOOP_STRETCH |
RADEON_HORZ_AUTO_RATIO_INC);
@@ -1036,25 +1036,25 @@ static void RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save,
if (IsPrimary) {
if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg.disp_output_cntl &
+ save->disp_output_cntl = info->SavedReg->disp_output_cntl &
~RADEON_DISP_DAC_SOURCE_MASK;
} else {
- save->dac2_cntl = info->SavedReg.dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL);
+ save->dac2_cntl = info->SavedReg->dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL);
}
} else {
if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg.disp_output_cntl &
+ save->disp_output_cntl = info->SavedReg->disp_output_cntl &
~RADEON_DISP_DAC_SOURCE_MASK;
save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
} else {
- save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC_CLK_SEL;
+ save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC_CLK_SEL;
}
}
save->dac_cntl = (RADEON_DAC_MASK_ALL
| RADEON_DAC_VGA_ADR_EN
| (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN));
- save->dac_macro_cntl = info->SavedReg.dac_macro_cntl;
+ save->dac_macro_cntl = info->SavedReg->dac_macro_cntl;
}
static void
@@ -1066,7 +1066,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save)
if (info->ChipFamily == CHIP_FAMILY_R420 ||
info->ChipFamily == CHIP_FAMILY_RV410) {
- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl &
+ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl &
~(RADEON_TV_DAC_STD_MASK |
RADEON_TV_DAC_BGADJ_MASK |
R420_TV_DAC_DACADJ_MASK |
@@ -1075,7 +1075,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save)
R420_TV_DAC_GDACPD |
R420_TV_DAC_TVENABLE);
} else {
- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl &
+ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl &
~(RADEON_TV_DAC_STD_MASK |
RADEON_TV_DAC_BGADJ_MASK |
RADEON_TV_DAC_DACADJ_MASK |
@@ -1101,34 +1101,34 @@ static void RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save,
RADEONInitTvDacCntl(output, save);
if (IS_R300_VARIANT)
- save->gpiopad_a = info->SavedReg.gpiopad_a | 1;
+ save->gpiopad_a = info->SavedReg->gpiopad_a | 1;
- save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL;
+ save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL;
if (IsPrimary) {
if (IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg.disp_output_cntl &
+ save->disp_output_cntl = info->SavedReg->disp_output_cntl &
~RADEON_DISP_TVDAC_SOURCE_MASK;
save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
} else if (info->ChipFamily == CHIP_FAMILY_R200) {
- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl &
+ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
~(R200_FP2_SOURCE_SEL_MASK |
RADEON_FP2_DVO_RATE_SEL_SDR);
} else {
- save->disp_hw_debug = info->SavedReg.disp_hw_debug | RADEON_CRT2_DISP1_SEL;
+ save->disp_hw_debug = info->SavedReg->disp_hw_debug | RADEON_CRT2_DISP1_SEL;
}
} else {
if (IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg.disp_output_cntl &
+ save->disp_output_cntl = info->SavedReg->disp_output_cntl &
~RADEON_DISP_TVDAC_SOURCE_MASK;
save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
} else if (info->ChipFamily == CHIP_FAMILY_R200) {
- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl &
+ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
~(R200_FP2_SOURCE_SEL_MASK |
RADEON_FP2_DVO_RATE_SEL_SDR);
save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
} else {
- save->disp_hw_debug = info->SavedReg.disp_hw_debug &
+ save->disp_hw_debug = info->SavedReg->disp_hw_debug &
~RADEON_CRT2_DISP1_SEL;
}
}
@@ -1175,35 +1175,35 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
xf86CrtcPtr crtc = output->crtc;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInitOutputRegisters(pScrn, &info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id);
+ RADEONInitOutputRegisters(pScrn, info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id);
if (radeon_crtc->crtc_id == 0)
- RADEONRestoreRMXRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreRMXRegisters(pScrn, info->ModeReg);
switch(radeon_output->MonType) {
case MT_LCD:
ErrorF("restore LVDS\n");
- RADEONRestoreLVDSRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreLVDSRegisters(pScrn, info->ModeReg);
break;
case MT_DFP:
if (radeon_output->TMDSType == TMDS_INT) {
ErrorF("restore FP\n");
- RADEONRestoreFPRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreFPRegisters(pScrn, info->ModeReg);
} else {
ErrorF("restore FP2\n");
RADEONRestoreDVOChip(pScrn, output);
- RADEONRestoreFP2Registers(pScrn, &info->ModeReg);
+ RADEONRestoreFP2Registers(pScrn, info->ModeReg);
}
break;
case MT_STV:
case MT_CTV:
ErrorF("restore tv\n");
- RADEONRestoreDACRegisters(pScrn, &info->ModeReg);
- RADEONRestoreTVRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreDACRegisters(pScrn, info->ModeReg);
+ RADEONRestoreTVRegisters(pScrn, info->ModeReg);
break;
default:
ErrorF("restore dac\n");
- RADEONRestoreDACRegisters(pScrn, &info->ModeReg);
+ RADEONRestoreDACRegisters(pScrn, info->ModeReg);
}
}
@@ -1781,7 +1781,7 @@ radeon_create_resources(xf86OutputPtr output)
"RRConfigureOutputProperty error, %d\n", err);
}
/* Set the current value of the backlight property */
- //data = (info->SavedReg.lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT;
+ //data = (info->SavedReg->lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT;
data = RADEON_MAX_BACKLIGHT_LEVEL;
err = RRChangeOutputProperty(output->randr_output, backlight_atom,
XA_INTEGER, 32, PropModeReplace, 1, &data,
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 66ece94..cdefdf5 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -223,6 +223,177 @@ typedef struct _RADEONOutputPrivateRec {
int load_detection;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
+
+/*
+ * Maximum length of horizontal/vertical code timing tables for state storage
+ */
+#define MAX_H_CODE_TIMING_LEN 32
+#define MAX_V_CODE_TIMING_LEN 32
+
+typedef struct {
+ /* Common registers */
+ CARD32 ovr_clr;
+ CARD32 ovr_wid_left_right;
+ CARD32 ovr_wid_top_bottom;
+ CARD32 ov0_scale_cntl;
+ CARD32 mpp_tb_config;
+ CARD32 mpp_gp_config;
+ CARD32 subpic_cntl;
+ CARD32 viph_control;
+ CARD32 i2c_cntl_1;
+ CARD32 gen_int_cntl;
+ CARD32 cap0_trig_cntl;
+ CARD32 cap1_trig_cntl;
+ CARD32 bus_cntl;
+ CARD32 bios_4_scratch;
+ CARD32 bios_5_scratch;
+ CARD32 bios_6_scratch;
+ CARD32 surface_cntl;
+ CARD32 surfaces[8][3];
+ CARD32 mc_agp_location;
+ CARD32 mc_fb_location;
+ CARD32 display_base_addr;
+ CARD32 display2_base_addr;
+ CARD32 ov0_base_addr;
+
+ /* Other registers to save for VT switches */
+ CARD32 dp_datatype;
+ CARD32 rbbm_soft_reset;
+ CARD32 clock_cntl_index;
+ CARD32 amcgpio_en_reg;
+ CARD32 amcgpio_mask;
+
+ /* CRTC registers */
+ CARD32 crtc_gen_cntl;
+ CARD32 crtc_ext_cntl;
+ CARD32 dac_cntl;
+ CARD32 crtc_h_total_disp;
+ CARD32 crtc_h_sync_strt_wid;
+ CARD32 crtc_v_total_disp;
+ CARD32 crtc_v_sync_strt_wid;
+ CARD32 crtc_offset;
+ CARD32 crtc_offset_cntl;
+ CARD32 crtc_pitch;
+ CARD32 disp_merge_cntl;
+ CARD32 grph_buffer_cntl;
+ CARD32 crtc_more_cntl;
+ CARD32 crtc_tile_x0_y0;
+
+ /* CRTC2 registers */
+ CARD32 crtc2_gen_cntl;
+ CARD32 dac_macro_cntl;
+ CARD32 dac2_cntl;
+ CARD32 disp_output_cntl;
+ CARD32 disp_tv_out_cntl;
+ CARD32 disp_hw_debug;
+ CARD32 disp2_merge_cntl;
+ CARD32 grph2_buffer_cntl;
+ CARD32 crtc2_h_total_disp;
+ CARD32 crtc2_h_sync_strt_wid;
+ CARD32 crtc2_v_total_disp;
+ CARD32 crtc2_v_sync_strt_wid;
+ CARD32 crtc2_offset;
+ CARD32 crtc2_offset_cntl;
+ CARD32 crtc2_pitch;
+ CARD32 crtc2_tile_x0_y0;
+
+ /* Flat panel registers */
+ CARD32 fp_crtc_h_total_disp;
+ CARD32 fp_crtc_v_total_disp;
+ CARD32 fp_gen_cntl;
+ CARD32 fp2_gen_cntl;
+ CARD32 fp_h_sync_strt_wid;
+ CARD32 fp_h2_sync_strt_wid;
+ CARD32 fp_horz_stretch;
+ CARD32 fp_panel_cntl;
+ CARD32 fp_v_sync_strt_wid;
+ CARD32 fp_v2_sync_strt_wid;
+ CARD32 fp_vert_stretch;
+ CARD32 lvds_gen_cntl;
+ CARD32 lvds_pll_cntl;
+ CARD32 tmds_pll_cntl;
+ CARD32 tmds_transmitter_cntl;
+
+ /* Computed values for PLL */
+ CARD32 dot_clock_freq;
+ CARD32 pll_output_freq;
+ int feedback_div;
+ int post_div;
+
+ /* PLL registers */
+ unsigned ppll_ref_div;
+ unsigned ppll_div_3;
+ CARD32 htotal_cntl;
+ CARD32 vclk_ecp_cntl;
+
+ /* Computed values for PLL2 */
+ CARD32 dot_clock_freq_2;
+ CARD32 pll_output_freq_2;
+ int feedback_div_2;
+ int post_div_2;
+
+ /* PLL2 registers */
+ CARD32 p2pll_ref_div;
+ CARD32 p2pll_div_0;
+ CARD32 htotal_cntl2;
+ CARD32 pixclks_cntl;
+
+ /* Pallet */
+ Bool palette_valid;
+ CARD32 palette[256];
+ CARD32 palette2[256];
+
+ CARD32 rs480_unk_e30;
+ CARD32 rs480_unk_e34;
+ CARD32 rs480_unk_e38;
+ CARD32 rs480_unk_e3c;
+
+ /* TV out registers */
+ CARD32 tv_master_cntl;
+ CARD32 tv_htotal;
+ CARD32 tv_hsize;
+ CARD32 tv_hdisp;
+ CARD32 tv_hstart;
+ CARD32 tv_vtotal;
+ CARD32 tv_vdisp;
+ CARD32 tv_timing_cntl;
+ CARD32 tv_vscaler_cntl1;
+ CARD32 tv_vscaler_cntl2;
+ CARD32 tv_sync_size;
+ CARD32 tv_vrestart;
+ CARD32 tv_hrestart;
+ CARD32 tv_frestart;
+ CARD32 tv_ftotal;
+ CARD32 tv_clock_sel_cntl;
+ CARD32 tv_clkout_cntl;
+ CARD32 tv_data_delay_a;
+ CARD32 tv_data_delay_b;
+ CARD32 tv_dac_cntl;
+ CARD32 tv_pll_cntl;
+ CARD32 tv_pll_cntl1;
+ CARD32 tv_pll_fine_cntl;
+ CARD32 tv_modulator_cntl1;
+ CARD32 tv_modulator_cntl2;
+ CARD32 tv_frame_lock_cntl;
+ CARD32 tv_pre_dac_mux_cntl;
+ CARD32 tv_rgb_cntl;
+ CARD32 tv_y_saw_tooth_cntl;
+ CARD32 tv_y_rise_cntl;
+ CARD32 tv_y_fall_cntl;
+ CARD32 tv_uv_adr;
+ CARD32 tv_upsamp_and_gain_cntl;
+ CARD32 tv_gain_limit_settings;
+ CARD32 tv_linear_gain_settings;
+ CARD32 tv_crc_cntl;
+ CARD32 tv_sync_cntl;
+ CARD32 gpiopad_a;
+ CARD32 pll_test_cntl;
+
+ CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
+ CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
+
+} RADEONSaveRec, *RADEONSavePtr;
+
#define RADEON_MAX_CRTC 2
#define RADEON_MAX_BIOS_CONNECTOR 8
@@ -242,6 +413,9 @@ typedef struct
xf86CrtcPtr pCrtc[RADEON_MAX_CRTC];
RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC];
+ RADEONSaveRec ModeReg; /* Current mode */
+ RADEONSaveRec SavedReg; /* Original (text) mode */
+
} RADEONEntRec, *RADEONEntPtr;
/* radeon_probe.c */
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 2a8873c..5e9a9c8 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -540,7 +540,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->dac_cntl &= ~RADEON_DAC_TVO_EN;
if (IS_R300_VARIANT)
- save->gpiopad_a = info->SavedReg.gpiopad_a & ~1;
+ save->gpiopad_a = info->SavedReg->gpiopad_a & ~1;
if (IsPrimary) {
save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
@@ -571,7 +571,7 @@ void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
Bool reloadTable;
- RADEONSavePtr restore = &info->ModeReg;
+ RADEONSavePtr restore = info->ModeReg;
reloadTable = RADEONInitTVRestarts(output, restore, mode);
diff --git a/src/radeon_tv.h b/src/radeon_tv.h
index 5c8c8c9..c4b7838 100644
--- a/src/radeon_tv.h
+++ b/src/radeon_tv.h
@@ -3,11 +3,6 @@
* Federico Ulivi <fulivi at lycos.com>
*/
-/*
- * Maximum length of horizontal/vertical code timing tables for state storage
- */
-#define MAX_H_CODE_TIMING_LEN 32
-#define MAX_V_CODE_TIMING_LEN 32
/*
* Limits of h/v positions (hPos & vPos)
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 3f0209e..99b74eb 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -1430,7 +1430,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
* 0 for PIXCLK < 175Mhz, and 1 (divide by 2)
* for higher clocks, sure makes life nicer
*/
- dot_clock = info->ModeReg.dot_clock_freq;
+ dot_clock = info->ModeReg->dot_clock_freq;
if (dot_clock < 17500)
info->ecp_div = 0;
@@ -2552,9 +2552,9 @@ RADEONDisplayVideo(
/* Figure out which head we are on for dot clock */
if (radeon_crtc->crtc_id == 1)
- dot_clock = info->ModeReg.dot_clock_freq_2;
+ dot_clock = info->ModeReg->dot_clock_freq_2;
else
- dot_clock = info->ModeReg.dot_clock_freq;
+ dot_clock = info->ModeReg->dot_clock_freq;
if (dot_clock < 17500)
ecp_div = 0;
commit 64ab1cdf343a9a69e7e9e64f0bba77c54a94e9d0
Author: James Cloos <cloos at jhcloos.com>
Date: Thu Dec 6 15:51:12 2007 -0500
Add missing PHONY line for automatic ChangeLog generation
diff --git a/Makefile.am b/Makefile.am
index 2ae4852..ea2e4a3 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -33,6 +33,8 @@ endif
EXTRA_DIST = README.ati README.r128 README.ati.sgml README.r128.sgml ChangeLog
CLEANFILES = ChangeLog
+.PHONY: ChangeLog
+
ChangeLog:
(GIT_DIR=$(top_srcdir)/.git git-log > .changelog.tmp && mv .changelog.tmp ChangeLog; rm -f .changelog.tmp) || (touch ChangeLog; echo 'git directory not found: installing possibly empty changelog.' >&2)
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