xf86-video-intel: src/i810_reg.h
Keith Packard
keithp at kemper.freedesktop.org
Tue Aug 28 12:32:41 PDT 2007
src/i810_reg.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
New commits:
diff-tree ddd6053987b9ca9bd3722ddbdfd412a3d8d252cf (from 3fbbd0afde49c53a5a8661f75c8c8c4be3020c30)
Author: Keith Packard <keithp at koto.keithp.com>
Date: Tue Aug 28 12:30:46 2007 -0700
Add register defines for hw binning
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 03e10d6..598fc8c 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -346,19 +346,33 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#define IPEIR 0x2088
#define IPEHR 0x208C
#define INST_DONE 0x2090
+#define SCPD0 0x209c /* debug */
#define INST_PS 0x20c4
#define IPEIR_I965 0x2064 /* i965 */
#define IPEHR_I965 0x2068 /* i965 */
#define INST_DONE_I965 0x206c
#define INST_PS_I965 0x2070
+
+/* Current active ring head address:
+ */
#define ACTHD 0x2074
+
+/* Current primary/secondary DMA fetch addresses:
+ */
#define DMA_FADD_P 0x2078
+#define DMA_FADD_S 0x20d4
#define INST_DONE_1 0x207c
#define CACHE_MODE_0 0x2120
#define CACHE_MODE_1 0x2124
#define MI_ARB_STATE 0x20e4
+/* Start addresses for each of the primary rings:
+ */
+#define PR0_STR 0x20f0
+#define PR1_STR 0x20f4
+#define PR2_STR 0x20f8
+
#define WIZ_CTL 0x7c00
#define WIZ_CTL_SINGLE_SUBSPAN (1<<6)
#define WIZ_CTL_IGNORE_STALLS (1<<5)
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