xf86-video-ati: Branch 'master' - 2 commits
Michel Daenzer
daenzer at kemper.freedesktop.org
Fri Aug 24 00:27:28 PDT 2007
configure.ac | 2 -
src/atidri.c | 7 ++-
src/radeon_bios.c | 12 ++++--
src/radeon_crtc.c | 12 +++---
src/radeon_driver.c | 98 +++++++++++++++++++++++++++------------------------
src/radeon_video.c | 15 ++++---
src/theatre.c | 15 +++++--
src/theatre200.c | 19 ++++++---
src/theatre_detect.c | 15 +++++--
9 files changed, 113 insertions(+), 82 deletions(-)
New commits:
diff-tree 71f650d1bc432514516f7ac64a5e8a54c5227881 (from d7230939f523610c57f92bdfc72966bdbc6f1070)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Fri Aug 24 09:21:39 2007 +0200
Require xorg-server >= 1.3 for RandR 1.2.
diff --git a/configure.ac b/configure.ac
index b178224..cdc6377 100644
--- a/configure.ac
+++ b/configure.ac
@@ -71,7 +71,7 @@ XORG_DRIVER_CHECK_EXT(XF86MISC, xf86misc
XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
# Checks for pkg-config packages
-PKG_CHECK_MODULES(XORG, [xorg-server xproto fontsproto $REQUIRED_MODULES])
+PKG_CHECK_MODULES(XORG, [xorg-server >= 1.3 xproto fontsproto $REQUIRED_MODULES])
sdkdir=$(pkg-config --variable=sdkdir xorg-server)
# Checks for libraries.
diff-tree d7230939f523610c57f92bdfc72966bdbc6f1070 (from 91c45fedfd155a153dcd2c3f3e30986bfbd44e6f)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Fri Aug 24 09:21:14 2007 +0200
64 bit warning fixes.
For printf vs. CARD32, use %u or %x and and a cast to unsigned.
diff --git a/src/atidri.c b/src/atidri.c
index d4fbead..07adda7 100644
--- a/src/atidri.c
+++ b/src/atidri.c
@@ -1269,9 +1269,10 @@ Bool ATIDRIScreenInit( ScreenPtr pScreen
ErrorF( "[dri] Data does not fit in SAREA\n" );
return FALSE;
}
- xf86DrvMsg( pScreenInfo->scrnIndex, X_INFO, "[drm] SAREA %d+%d: %d\n",
- sizeof(XF86DRISAREARec), sizeof(ATISAREAPrivRec),
- sizeof(XF86DRISAREARec) + sizeof(ATISAREAPrivRec) );
+ xf86DrvMsg( pScreenInfo->scrnIndex, X_INFO, "[drm] SAREA %u+%u: %u\n",
+ (unsigned)sizeof(XF86DRISAREARec),
+ (unsigned)sizeof(ATISAREAPrivRec),
+ (unsigned)(sizeof(XF86DRISAREARec) + sizeof(ATISAREAPrivRec)) );
pDRIInfo->SAREASize = SAREA_MAX;
pATIDRI = (ATIDRIPtr) xnfcalloc( sizeof(ATIDRIRec), 1 );
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 7dcb5d5..1ef0ff4 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -653,8 +653,11 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInf
if (info->sclk == 0) info->sclk = 200;
if (info->mclk == 0) info->mclk = 200;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %ld, max_pll: %ld, xclk: %d, sclk: %f, mclk: %f\n",
- pll->reference_freq, pll->min_pll_freq, pll->max_pll_freq, pll->xclk, info->sclk, info->mclk);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, "
+ "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n",
+ pll->reference_freq, (unsigned)pll->min_pll_freq,
+ (unsigned)pll->max_pll_freq, pll->xclk, info->sclk,
+ info->mclk);
} else {
pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30);
@@ -839,8 +842,9 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86Outp
((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) |
((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16));
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "TMDS PLL from BIOS: %ld %lx\n",
- radeon_output->tmds_pll[i].freq, radeon_output->tmds_pll[i].value);
+ "TMDS PLL from BIOS: %u %x\n",
+ (unsigned)radeon_output->tmds_pll[i].freq,
+ (unsigned)radeon_output->tmds_pll[i].value);
if (maxfreq == radeon_output->tmds_pll[i].freq) {
radeon_output->tmds_pll[i].freq = 0xffffffff;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 1b9b2fb..6211b02 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -666,9 +666,9 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn
save->post_div = post_div->divider;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "dc=%ld, of=%ld, fd=%d, pd=%d\n",
- save->dot_clock_freq,
- save->pll_output_freq,
+ "dc=%u, of=%u, fd=%d, pd=%d\n",
+ (unsigned)save->dot_clock_freq,
+ (unsigned)save->pll_output_freq,
save->feedback_div,
save->post_div);
@@ -735,9 +735,9 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScr
save->post_div_2 = post_div->divider;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "dc=%ld, of=%ld, fd=%d, pd=%d\n",
- save->dot_clock_freq_2,
- save->pll_output_freq_2,
+ "dc=%u, of=%u, fd=%d, pd=%d\n",
+ (unsigned)save->dot_clock_freq_2,
+ (unsigned)save->pll_output_freq_2,
save->feedback_div_2,
save->post_div_2);
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index c6c7845..a111e0d 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1051,10 +1051,11 @@ static void RADEONGetClockInfo(ScrnInfoP
}
xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "PLL parameters: rf=%d rd=%d min=%ld max=%ld; xclk=%d\n",
+ "PLL parameters: rf=%d rd=%d min=%d max=%d; xclk=%d\n",
pll->reference_freq,
pll->reference_div,
- pll->min_pll_freq, pll->max_pll_freq, pll->xclk);
+ (unsigned)pll->min_pll_freq, (unsigned)pll->max_pll_freq,
+ pll->xclk);
/* (Some?) Radeon BIOSes seem too lie about their minimum dot
* clocks. Allow users to override the detected minimum dot clock
@@ -1182,7 +1183,7 @@ static void RADEONInitMemoryMap(ScrnInfo
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- unsigned long mem_size;
+ CARD32 mem_size;
CARD32 aper_size;
/* Default to existing values */
@@ -1254,11 +1255,12 @@ static void RADEONInitMemoryMap(ScrnInfo
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONInitMemoryMap() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " mem_size : 0x%08lx\n", mem_size);
+ " mem_size : 0x%08x\n", (unsigned)mem_size);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location);
+ " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location);
+ " MC_AGP_LOCATION : 0x%08x\n",
+ (unsigned)info->mc_agp_location);
}
static void RADEONGetVRamType(ScrnInfoPtr pScrn)
@@ -1321,8 +1323,8 @@ static CARD32 RADEONGetAccessibleVRAM(Sc
if (info->directRenderingEnabled &&
info->pKernelDRMVersion->version_minor < 23) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "[dri] limiting video memory to one aperture of %ldK\n",
- aper_size);
+ "[dri] limiting video memory to one aperture of %uK\n",
+ (unsigned)aper_size);
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[dri] detected radeon kernel module version 1.%d but"
" 1.23 or newer is required for full memory mapping.\n",
@@ -1409,8 +1411,8 @@ static Bool RADEONPreInitVRAM(ScrnInfoPt
accessible = bar_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Detected total video RAM=%dK, accessible=%ldK (PCI BAR=%ldK)\n",
- pScrn->videoRam, accessible, bar_size);
+ "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n",
+ pScrn->videoRam, (unsigned)accessible, (unsigned)bar_size);
if (pScrn->videoRam > accessible)
pScrn->videoRam = accessible;
@@ -3248,8 +3250,8 @@ Bool RADEONSetupMemXAA_DRI(int scrnIndex
info->depthOffset);
if (info->cardType==CARD_PCIE)
xf86DrvMsg(scrnIndex, X_INFO,
- "Will use %d kb for PCI GART table at offset 0x%lx\n",
- info->pciGartSize/1024, info->pciGartOffset);
+ "Will use %d kb for PCI GART table at offset 0x%x\n",
+ info->pciGartSize/1024, (unsigned)info->pciGartOffset);
xf86DrvMsg(scrnIndex, X_INFO,
"Will use %d kb for textures at offset 0x%x\n",
info->textureSize/1024, info->textureOffset);
@@ -3772,9 +3774,9 @@ Bool RADEONScreenInit(int scrnIndex, Scr
int width, height;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using hardware cursor (scanline %ld)\n",
- info->cursor_offset / pScrn->displayWidth
- / info->CurrentLayout.pixel_bytes);
+ "Using hardware cursor (scanline %u)\n",
+ (unsigned)(info->cursor_offset / pScrn->displayWidth
+ / info->CurrentLayout.pixel_bytes));
if (xf86QueryLargestOffscreenArea(pScreen, &width, &height,
0, 0, 0)) {
xf86DrvMsg(scrnIndex, X_INFO,
@@ -3852,9 +3854,11 @@ void RADEONRestoreMemMapRegisters(ScrnIn
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONRestoreMemMapRegisters() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location);
+ " MC_FB_LOCATION : 0x%08x\n",
+ (unsigned)restore->mc_fb_location);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location);
+ " MC_AGP_LOCATION : 0x%08x\n",
+ (unsigned)restore->mc_agp_location);
/* Write memory mapping registers only if their value change
* since we must ensure no access is done while they are
@@ -4007,11 +4011,11 @@ static void RADEONAdjustMemMapRegisters(
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"DRI init changed memory map, adjusting ...\n");
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
- info->mc_fb_location, fb);
+ " MC_FB_LOCATION was: 0x%08x is: 0x%08x\n",
+ (unsigned)info->mc_fb_location, (unsigned)fb);
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
- info->mc_agp_location, agp);
+ " MC_AGP_LOCATION was: 0x%08x is: 0x%08x\n",
+ (unsigned)info->mc_agp_location, (unsigned)agp);
info->mc_fb_location = fb;
info->mc_agp_location = agp;
info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
@@ -4156,8 +4160,8 @@ void RADEONRestoreCrtcRegisters(ScrnInfo
unsigned char *RADEONMMIO = info->MMIO;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Programming CRTC1, offset: 0x%08lx\n",
- restore->crtc_offset);
+ "Programming CRTC1, offset: 0x%08x\n",
+ (unsigned)restore->crtc_offset);
/* We prevent the CRTC from hitting the memory controller until
* fully programmed
@@ -4209,8 +4213,8 @@ void RADEONRestoreCrtc2Registers(ScrnInf
/* CARD32 crtc2_gen_cntl;*/
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Programming CRTC2, offset: 0x%08lx\n",
- restore->crtc2_offset);
+ "Programming CRTC2, offset: 0x%08x\n",
+ (unsigned)restore->crtc2_offset);
/* We prevent the CRTC from hitting the memory controller until
* fully programmed
@@ -4762,10 +4766,10 @@ void RADEONRestorePLLRegisters(ScrnInfoP
| RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Wrote: 0x%08x 0x%08x 0x%08lx (0x%08x)\n",
+ "Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
restore->ppll_ref_div,
restore->ppll_div_3,
- restore->htotal_cntl,
+ (unsigned)restore->htotal_cntl,
INPLL(pScrn, RADEON_PPLL_CNTL));
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Wrote: rd=%d, fd=%d, pd=%d\n",
@@ -4835,16 +4839,17 @@ void RADEONRestorePLL2Registers(ScrnInfo
| RADEON_P2PLL_ATOMIC_UPDATE_EN));
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Wrote2: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n",
- restore->p2pll_ref_div,
- restore->p2pll_div_0,
- restore->htotal_cntl2,
+ "Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+ (unsigned)restore->p2pll_ref_div,
+ (unsigned)restore->p2pll_div_0,
+ (unsigned)restore->htotal_cntl2,
INPLL(pScrn, RADEON_P2PLL_CNTL));
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Wrote2: rd=%ld, fd=%ld, pd=%ld\n",
- restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
- restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
- (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16);
+ "Wrote2: rd=%u, fd=%u, pd=%u\n",
+ (unsigned)restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
+ (unsigned)restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
+ (unsigned)((restore->p2pll_div_0 &
+ RADEON_P2PLL_POST0_DIV_MASK) >>16));
usleep(5000); /* Let the clock to lock */
@@ -5320,10 +5325,10 @@ static void RADEONSavePLLRegisters(ScrnI
save->vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Read: 0x%08x 0x%08x 0x%08lx\n",
+ "Read: 0x%08x 0x%08x 0x%08x\n",
save->ppll_ref_div,
save->ppll_div_3,
- save->htotal_cntl);
+ (unsigned)save->htotal_cntl);
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Read: rd=%d, fd=%d, pd=%d\n",
save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
@@ -5340,15 +5345,16 @@ static void RADEONSavePLL2Registers(Scrn
save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Read: 0x%08lx 0x%08lx 0x%08lx\n",
- save->p2pll_ref_div,
- save->p2pll_div_0,
- save->htotal_cntl2);
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Read: rd=%ld, fd=%ld, pd=%ld\n",
- save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
- save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
- (save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >> 16);
+ "Read: 0x%08x 0x%08x 0x%08x\n",
+ (unsigned)save->p2pll_ref_div,
+ (unsigned)save->p2pll_div_0,
+ (unsigned)save->htotal_cntl2);
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Read: rd=%u, fd=%u, pd=%u\n",
+ (unsigned)(save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK),
+ (unsigned)(save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK),
+ (unsigned)((save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK)
+ >> 16));
}
/* Read palette data */
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 7231c1e..5cbe9fc 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -1325,21 +1325,21 @@ static void RADEONSetupTheatre(ScrnInfoP
} else {
t->wComp0Connector=RT_COMP1;
}
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Composite connector is port %ld\n", t->wComp0Connector);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Composite connector is port %u\n", (unsigned)t->wComp0Connector);
break;
case 3: if(a & 0x4){
t->wSVideo0Connector=RT_YCR_COMP4;
} else {
t->wSVideo0Connector=RT_YCF_COMP4;
}
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "SVideo connector is port %ld\n", t->wSVideo0Connector);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "SVideo connector is port %u\n", (unsigned)t->wSVideo0Connector);
break;
default:
break;
}
}
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rage Theatre: Connectors (detected): tuner=%ld, composite=%ld, svideo=%ld\n",
- t->wTunerConnector, t->wComp0Connector, t->wSVideo0Connector);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rage Theatre: Connectors (detected): tuner=%u, composite=%u, svideo=%u\n",
+ (unsigned)t->wTunerConnector, (unsigned)t->wComp0Connector, (unsigned)t->wSVideo0Connector);
}
@@ -1347,8 +1347,8 @@ static void RADEONSetupTheatre(ScrnInfoP
if(info->RageTheatreCompositePort>=0)t->wComp0Connector=info->RageTheatreCompositePort;
if(info->RageTheatreSVideoPort>=0)t->wSVideo0Connector=info->RageTheatreSVideoPort;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RageTheatre: Connectors (using): tuner=%ld, composite=%ld, svideo=%ld\n",
- t->wTunerConnector, t->wComp0Connector, t->wSVideo0Connector);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RageTheatre: Connectors (using): tuner=%u, composite=%u, svideo=%u\n",
+ (unsigned)t->wTunerConnector, (unsigned)t->wComp0Connector, (unsigned)t->wSVideo0Connector);
switch((info->RageTheatreCrystal>=0)?info->RageTheatreCrystal:pll->reference_freq){
case 2700:
@@ -1881,7 +1881,8 @@ RADEONSetPortAttribute(ScrnInfoPtr pScr
else if(attribute == xvAdjustment)
{
pPriv->adjustment=value;
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Setting pPriv->adjustment to %ld\n", pPriv->adjustment);
+ xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Setting pPriv->adjustment to %u\n",
+ (unsigned)pPriv->adjustment);
if(pPriv->tda9885!=0){
pPriv->tda9885->top_adjustment=value;
RADEON_TDA9885_SetEncoding(pPriv);
diff --git a/src/theatre.c b/src/theatre.c
index 0a635fa..a5aadfb 100644
--- a/src/theatre.c
+++ b/src/theatre.c
@@ -1796,7 +1796,9 @@ void RT_SetConnector (TheatrePtr t, CARD
counter++;
}
dwTempContrast = ReadRT_fld (fld_LP_CONTRAST);
- if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Rage Theatre: timeout waiting for line count (%ld)\n", ReadRT_fld (fld_VS_LINE_COUNT));
+ if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
+ "Rage Theatre: timeout waiting for line count (%u)\n",
+ (unsigned)ReadRT_fld (fld_VS_LINE_COUNT));
WriteRT_fld (fld_LP_CONTRAST, 0x0);
@@ -1851,7 +1853,9 @@ void RT_SetConnector (TheatrePtr t, CARD
counter++;
}
WriteRT_fld (fld_LP_CONTRAST, dwTempContrast);
- if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Rage Theatre: timeout waiting for line count (%ld)\n", ReadRT_fld (fld_VS_LINE_COUNT));
+ if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
+ "Rage Theatre: timeout waiting for line count (%u)\n",
+ (unsigned)ReadRT_fld (fld_VS_LINE_COUNT));
@@ -1942,7 +1946,8 @@ void DumpRageTheatreRegs(TheatrePtr t)
for(i=0;i<0x900;i+=4)
{
RT_regr(i, &data);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "register 0x%04x is equal to 0x%08lx\n", i, data);
+ xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
+ "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data);
}
}
@@ -2147,7 +2152,9 @@ void DumpRageTheatreRegsByName(TheatrePt
for(i=0; rt_reg_list[i].name!=NULL;i++){
RT_regr(rt_reg_list[i].addr, &data);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "register (0x%04lx) %s is equal to 0x%08lx\n", rt_reg_list[i].addr, rt_reg_list[i].name, data);
+ xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
+ "register (0x%04lx) %s is equal to 0x%08x\n",
+ rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data);
}
}
diff --git a/src/theatre200.c b/src/theatre200.c
index ff86395..672f01e 100644
--- a/src/theatre200.c
+++ b/src/theatre200.c
@@ -1799,10 +1799,12 @@ void RT_SetConnector (TheatrePtr t, CARD
t->wConnector = wConnector;
theatre_read(t, VIP_GPIO_CNTL, &data);
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %lx\n", data);
+ xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n",
+ (unsigned)data);
theatre_read(t, VIP_GPIO_INOUT, &data);
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %lx\n", data);
+ xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n",
+ (unsigned)data);
switch (wConnector)
{
@@ -1851,10 +1853,12 @@ void RT_SetConnector (TheatrePtr t, CARD
}
theatre_read(t, VIP_GPIO_CNTL, &data);
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %lx\n", data);
+ xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n",
+ (unsigned)data);
theatre_read(t, VIP_GPIO_INOUT, &data);
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %lx\n", data);
+ xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n",
+ (unsigned)data);
dsp_configure_i2s_port(t, 0, 0, 0);
@@ -2007,7 +2011,8 @@ void DumpRageTheatreRegs(TheatrePtr t)
for(i=0;i<0x900;i+=4)
{
RT_regr(i, &data);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "register 0x%04x is equal to 0x%08lx\n", i, data);
+ xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
+ "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data);
}
}
@@ -2212,7 +2217,9 @@ void DumpRageTheatreRegsByName(TheatrePt
for(i=0; rt_reg_list[i].name!=NULL;i++){
RT_regr(rt_reg_list[i].addr, &data);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "register (0x%04lx) %s is equal to 0x%08lx\n", rt_reg_list[i].addr, rt_reg_list[i].name, data);
+ xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
+ "register (0x%04lx) %s is equal to 0x%08x\n",
+ rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data);
}
}
diff --git a/src/theatre_detect.c b/src/theatre_detect.c
index e754832..8770911 100644
--- a/src/theatre_detect.c
+++ b/src/theatre_detect.c
@@ -67,7 +67,7 @@ static Bool theatre_write(TheatrePtr t,C
TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b)
{
TheatrePtr t;
- CARD32 i;
+ int i;
CARD32 val;
char s[20];
@@ -88,7 +88,9 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr
{
if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val))
{
- if(val)xf86DrvMsg(b->scrnIndex, X_INFO, "Device %ld on VIP bus ids as 0x%08lx\n",i,val);
+ if(val)xf86DrvMsg(b->scrnIndex, X_INFO,
+ "Device %d on VIP bus ids as 0x%08x\n", i,
+ (unsigned)val);
if(t->theatre_num>=0)continue; /* already found one instance */
switch(val){
case RT100_ATI_ID:
@@ -101,10 +103,12 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr
break;
}
} else {
- xf86DrvMsg(b->scrnIndex, X_INFO, "No response from device %ld on VIP bus\n",i);
+ xf86DrvMsg(b->scrnIndex, X_INFO, "No response from device %d on VIP bus\n",i);
}
}
- if(t->theatre_num>=0)xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre as device %d on VIP bus with id 0x%08lx\n",t->theatre_num,t->theatre_id);
+ if(t->theatre_num>=0)xf86DrvMsg(b->scrnIndex, X_INFO,
+ "Detected Rage Theatre as device %d on VIP bus with id 0x%08x\n",
+ t->theatre_num, (unsigned)t->theatre_id);
if(t->theatre_num < 0)
{
@@ -113,7 +117,8 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr
}
RT_regr(VIP_VIP_REVISION_ID, &val);
- xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8lX\n", val);
+ xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8X\n",
+ (unsigned)val);
#if 0
DumpRageTheatreRegsByName(t);
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