xf86-video-intel: src/i830_display.c src/i830_exa.c src/i830.h src/i965_render.c src/i965_video.c
Jesse Barnes
jbarnes at kemper.freedesktop.org
Fri Aug 10 12:43:43 PDT 2007
src/i830.h | 2 ++
src/i830_display.c | 22 +++++++++++++++++++++-
src/i830_exa.c | 11 ++++++-----
src/i965_render.c | 26 +++++++++++++++++++++++---
src/i965_video.c | 3 +++
5 files changed, 55 insertions(+), 9 deletions(-)
New commits:
diff-tree e0fcf645a228094620b8f7fdd580963611bdd6ef (from 7b143e5c8397da077c0e02455c21c5a99cf50942)
Author: Jesse Barnes <jesse.barnes at intel.com>
Date: Fri Aug 10 15:43:06 2007 -0400
Tiling fixes for 965
This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text. This
is likely another tiling related problem with the composite hook.
diff --git a/src/i830.h b/src/i830.h
index c2321d4..17dfb72 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -739,6 +739,8 @@ static inline int i830_fb_compression_su
return TRUE;
}
+Bool i830_pixmap_tiled(PixmapPtr p);
+
extern const int I830PatternROP[16];
extern const int I830CopyROP[16];
diff --git a/src/i830_display.c b/src/i830_display.c
index 6fe7be7..d5f7586 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -498,6 +498,23 @@ i830_pipe_a_require_deactivate (ScrnInfo
return;
}
+/* FIXME: use pixmap private instead if possible */
+static Bool
+i830_display_tiled(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
+
+ if (!pI830->tiling)
+ return FALSE;
+
+ /* Rotated data is currently linear, allocated either via XAA or EXA */
+ if (crtc->rotatedData)
+ return FALSE;
+
+ return TRUE;
+}
+
static Bool
i830_use_fb_compression(xf86CrtcPtr crtc)
{
@@ -510,6 +527,9 @@ i830_use_fb_compression(xf86CrtcPtr crtc
if (!pI830->fb_compression)
return FALSE;
+ if (!i830_display_tiled(crtc))
+ return FALSE;
+
/* Pre-965 only supports plane A */
if (!IS_I965GM(pI830) && plane != FBC_CTL_PLANEA)
return FALSE;
@@ -1078,7 +1098,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
else
dspcntr |= DISPPLANE_SEL_PIPE_B;
- if (pI830->tiling)
+ if (IS_I965G(pI830) && i830_display_tiled(crtc))
dspcntr |= DISPLAY_PLANE_TILED;
pipeconf = INREG(pipeconf_reg);
diff --git a/src/i830_exa.c b/src/i830_exa.c
index b0029d1..023a845 100644
--- a/src/i830_exa.c
+++ b/src/i830_exa.c
@@ -97,8 +97,9 @@ const int I830PatternROP[16] =
ROP_1
};
-static Bool
-exaPixmapTiled(PixmapPtr p)
+/* FIXME: use pixmap private instead */
+Bool
+i830_pixmap_tiled(PixmapPtr p)
{
ScreenPtr pScreen = p->drawable.pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
@@ -189,7 +190,7 @@ I830EXASolid(PixmapPtr pPixmap, int x1,
if (pPixmap->drawable.bitsPerPixel == 32)
cmd |= XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
- if (IS_I965G(pI830) && exaPixmapTiled(pPixmap)) {
+ if (IS_I965G(pI830) && i830_pixmap_tiled(pPixmap)) {
assert((pitch % 512) == 0);
pitch >>= 2;
cmd |= XY_COLOR_BLT_TILED;
@@ -274,13 +275,13 @@ I830EXACopy(PixmapPtr pDstPixmap, int sr
cmd |= XY_SRC_COPY_BLT_WRITE_ALPHA | XY_SRC_COPY_BLT_WRITE_RGB;
if (IS_I965G(pI830)) {
- if (exaPixmapTiled(pDstPixmap)) {
+ if (i830_pixmap_tiled(pDstPixmap)) {
assert((dst_pitch % 512) == 0);
dst_pitch >>= 2;
cmd |= XY_SRC_COPY_BLT_DST_TILED;
}
- if (exaPixmapTiled(pI830->pSrcPixmap)) {
+ if (i830_pixmap_tiled(pI830->pSrcPixmap)) {
assert((src_pitch % 512) == 0);
src_pitch >>= 2;
cmd |= XY_SRC_COPY_BLT_SRC_TILED;
diff --git a/src/i965_render.c b/src/i965_render.c
index ec64ddd..ad3b53e 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -392,9 +392,11 @@ i965_prepare_composite(int op, PicturePt
{
ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
- CARD32 src_offset, src_pitch;
- CARD32 mask_offset = 0, mask_pitch = 0;
- CARD32 dst_format, dst_offset, dst_pitch;
+ CARD32 src_offset, src_pitch, src_tile_format = 0, src_tiled = 0;
+ CARD32 mask_offset = 0, mask_pitch = 0, mask_tile_format = 0,
+ mask_tiled = 0;
+ CARD32 dst_format, dst_offset, dst_pitch, dst_tile_format = 0,
+ dst_tiled = 0;
Bool rotation_program = FALSE;
IntelEmitInvarientState(pScrn);
@@ -402,11 +404,23 @@ i965_prepare_composite(int op, PicturePt
src_offset = intel_get_pixmap_offset(pSrc);
src_pitch = intel_get_pixmap_pitch(pSrc);
+ if (i830_pixmap_tiled(pSrc)) {
+ src_tiled = 1;
+ src_tile_format = 0; /* Tiled X */
+ }
dst_offset = intel_get_pixmap_offset(pDst);
dst_pitch = intel_get_pixmap_pitch(pDst);
+ if (i830_pixmap_tiled(pDst)) {
+ dst_tiled = 1;
+ dst_tile_format = 0; /* Tiled X */
+ }
if (pMask) {
mask_offset = intel_get_pixmap_offset(pMask);
mask_pitch = intel_get_pixmap_pitch(pMask);
+ if (i830_pixmap_tiled(pMask)) {
+ mask_tiled = 1;
+ mask_tile_format = 0; /* Tiled X */
+ }
}
pI830->scale_units[0][0] = pSrc->drawable.width;
pI830->scale_units[0][1] = pSrc->drawable.height;
@@ -634,6 +648,8 @@ i965_prepare_composite(int op, PicturePt
dest_surf_state->ss2.mip_count = 0;
dest_surf_state->ss2.render_target_rotation = 0;
dest_surf_state->ss3.pitch = dst_pitch - 1;
+ dest_surf_state->ss3.tile_walk = dst_tile_format;
+ dest_surf_state->ss3.tiled_surface = dst_tiled;
dest_surf_state = (void *)(state_base + dest_surf_offset);
memcpy (dest_surf_state, &dest_surf_state_local, sizeof (dest_surf_state_local));
@@ -660,6 +676,8 @@ i965_prepare_composite(int op, PicturePt
src_surf_state->ss2.mip_count = 0;
src_surf_state->ss2.render_target_rotation = 0;
src_surf_state->ss3.pitch = src_pitch - 1;
+ src_surf_state->ss3.tile_walk = src_tile_format;
+ src_surf_state->ss3.tiled_surface = src_tiled;
src_surf_state = (void *)(state_base + src_surf_offset);
memcpy (src_surf_state, &src_surf_state_local, sizeof (src_surf_state_local));
@@ -688,6 +706,8 @@ i965_prepare_composite(int op, PicturePt
mask_surf_state->ss2.mip_count = 0;
mask_surf_state->ss2.render_target_rotation = 0;
mask_surf_state->ss3.pitch = mask_pitch - 1;
+ mask_surf_state->ss3.tile_walk = mask_tile_format;
+ mask_surf_state->ss3.tiled_surface = mask_tiled;
mask_surf_state = (void *)(state_base + mask_surf_offset);
memcpy (mask_surf_state, &mask_surf_state_local, sizeof (mask_surf_state_local));
diff --git a/src/i965_video.c b/src/i965_video.c
index 3084233..6ed7f01 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -378,6 +378,8 @@ I965DisplayVideoTextured(ScrnInfoPtr pSc
dest_surf_state->ss2.mip_count = 0;
dest_surf_state->ss2.render_target_rotation = 0;
dest_surf_state->ss3.pitch = pPixmap->devKind - 1;
+ dest_surf_state->ss3.tiled_surface = i830_pixmap_tiled(pPixmap);
+ dest_surf_state->ss3.tile_walk = 0; /* TileX */
/* Set up the source surface state buffer */
memset(src_surf_state, 0, sizeof(*src_surf_state));
@@ -408,6 +410,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pSc
src_surf_state->ss2.mip_count = 0;
src_surf_state->ss2.render_target_rotation = 0;
src_surf_state->ss3.pitch = video_pitch - 1;
+ /* FIXME: account for tiling if we ever do it */
/* Set up a binding table for our two surfaces. Only the PS will use it */
/* XXX: are these offset from the right place? */
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