xf86-video-intel: src/i830_render.c

[Zhenyu Wang]

 src/i830_render.c |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

New commits:
diff-tree cebdb8bfc6170a0fb441039f4422917fd0c77e70 (from cca389769001c657435f056e1f1c26b0f52a48bd)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date:   Fri Apr 20 10:54:34 2007 +0800

    EXA: set enabling bits properly for i830
    
    This was found when debug exa on a 865GV, we should set
    pipeline state bits properly, otherwise the engine will hang.

diff --git a/src/i830_render.c b/src/i830_render.c
index 36d41f3..077afa1 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -515,9 +515,16 @@ i830_prepare_composite(int op, PicturePt
 	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(8) | 0);
 	OUT_RING(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | blendctl | 
 		 S8_ENABLE_COLOR_BUFFER_WRITE);
+
+	OUT_RING(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP | 
+		DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS | 
+		DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST | 
+		ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
 	/* We have to explicitly say we don't want write disabled */
-	OUT_RING(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK);
-	OUT_RING(MI_NOOP); 
+	OUT_RING(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
+		DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
+		DISABLE_DITHER | ENABLE_COLOR_WRITE |
+		DISABLE_DEPTH_WRITE);
 	ADVANCE_LP_RING();
     }