xf86-video-intel: 2 commits - man/intel.man src/i830_render.c

[Zhenyu Wang]

 man/intel.man     |    5 +++--
 src/i830_render.c |   52 ++++++++++++++++++++++++----------------------------
 2 files changed, 27 insertions(+), 30 deletions(-)

New commits:
diff-tree 3bcb9a0b4ba7f3df346b5708617a7aafcbe2490a (from 64c30cf896f8bde3ee74c92b970132ab91b418cd)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date:   Mon Apr 16 14:27:49 2007 +0800

    EXA: i830 render misc fix and cleanups
    
    Try to map texture stream when setup texture map, and use
    correct order in load_immediate_1 cmd, which fixed crash on
    845GV. Also remove some flush cmds.

diff --git a/src/i830_render.c b/src/i830_render.c
index d587805..f5e144b 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -305,7 +305,7 @@ i830_texture_setup(PicturePtr pPict, Pix
 	else
 	    format |= MAPSURF_32BIT;
 
-	BEGIN_LP_RING(8);
+	BEGIN_LP_RING(10);
 	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_2 | LOAD_TEXTURE_MAP(unit) | 4);
 	OUT_RING((offset & TM0S0_ADDRESS_MASK) | TM0S0_USE_FENCE); 
 	OUT_RING(((pPix->drawable.height - 1) << TM0S1_HEIGHT_SHIFT) |
@@ -318,7 +318,24 @@ i830_texture_setup(PicturePtr pPict, Pix
 		 TEXCOORDTYPE_CARTESIAN | ENABLE_ADDR_V_CNTL |
 		 TEXCOORD_ADDR_V_MODE(wrap_mode) |
 		 ENABLE_ADDR_U_CNTL | TEXCOORD_ADDR_U_MODE(wrap_mode));
-	OUT_RING(MI_NOOP);
+	/* map texel stream */
+	OUT_RING(_3DSTATE_MAP_COORD_SETBIND_CMD);
+	if (unit == 0)
+	    OUT_RING(TEXBIND_SET0(TEXCOORDSRC_VTXSET_0) |
+		    TEXBIND_SET1(TEXCOORDSRC_KEEP) |
+		    TEXBIND_SET2(TEXCOORDSRC_KEEP) |
+		    TEXBIND_SET3(TEXCOORDSRC_KEEP));
+	else
+	    OUT_RING(TEXBIND_SET0(TEXCOORDSRC_VTXSET_0) |
+		    TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
+		    TEXBIND_SET2(TEXCOORDSRC_KEEP) |
+		    TEXBIND_SET3(TEXCOORDSRC_KEEP));
+	OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD | (unit << 16) |
+		DISABLE_TEX_STREAM_BUMP | 
+		ENABLE_TEX_STREAM_COORD_SET |
+		TEX_STREAM_COORD_SET(unit) |
+		ENABLE_TEX_STREAM_MAP_IDX |
+		TEX_STREAM_MAP_IDX(unit));
 	ADVANCE_LP_RING();
      }
 
@@ -392,7 +409,7 @@ i830_prepare_composite(int op, PicturePt
     {
 	CARD32 cblend, ablend, blendctl, vf2;
 
-	BEGIN_LP_RING(34);
+	BEGIN_LP_RING(26);
 
 	/* color buffer */
 	OUT_RING(_3DSTATE_BUF_INFO_CMD);
@@ -403,8 +420,6 @@ i830_prepare_composite(int op, PicturePt
 	OUT_RING(_3DSTATE_DST_BUF_VARS_CMD);
 	OUT_RING(dst_format);
 
-      	OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
-      	OUT_RING(MI_NOOP);		/* pad to quadword */
 	/* defaults */
 	OUT_RING(_3DSTATE_DFLT_Z_CMD);
 	OUT_RING(0);
@@ -421,32 +436,16 @@ i830_prepare_composite(int op, PicturePt
 	OUT_RING(DRAW_YMAX(pDst->drawable.height - 1) |
 		DRAW_XMAX(pDst->drawable.width - 1));
 	OUT_RING(0); /* yorig, xorig */
-	OUT_RING(MI_NOOP);
 
-	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | 0);
-	OUT_RING((1 << S3_POINT_WIDTH_SHIFT) | (2 << S3_LINE_WIDTH_SHIFT) |
-		S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
-	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) | 0);
+	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) | 
+		I1_LOAD_S(3) | 1);
 	if (pMask)
 	    vf2 = 2 << 12; /* 2 texture coord sets */
 	else
 	    vf2 = 1 << 12;
-	vf2 |= (TEXCOORDFMT_2D << 16);
-	if (pMask)
-	    vf2 |= (TEXCOORDFMT_2D << 18);
-	else
-	    vf2 |= (TEXCOORDFMT_1D << 18);
-
-	vf2 |= (TEXCOORDFMT_1D << 20);
-	vf2 |= (TEXCOORDFMT_1D << 22);
-	vf2 |= (TEXCOORDFMT_1D << 24);
-	vf2 |= (TEXCOORDFMT_1D << 26);
-	vf2 |= (TEXCOORDFMT_1D << 28);
-	vf2 |= (TEXCOORDFMT_1D << 30);
-	OUT_RING(vf2);
+	OUT_RING(vf2); /* TEXCOORDFMT_2D */
+	OUT_RING(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
 
-      	OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
-      	OUT_RING(MI_NOOP);		/* pad to quadword */
 	/* For (src In mask) operation */
 	/* IN operator: Multiply src by mask components or mask alpha.*/
 	/* TEXBLENDOP_MODULE: arg1*arg2 */
@@ -481,9 +480,6 @@ i830_prepare_composite(int op, PicturePt
 	OUT_RING(ablend);
 	OUT_RING(0);
 
-      	OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
-      	OUT_RING(MI_NOOP);		/* pad to quadword */
-
 	blendctl = i830_get_blend_cntl(op, pMaskPicture, pDstPicture->format);
 	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(8) | 0);
 	OUT_RING(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | blendctl | 
diff-tree 64c30cf896f8bde3ee74c92b970132ab91b418cd (from b67adb6de34cede0e31f02f26cd5ec7b1adfa586)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date:   Mon Apr 16 13:58:50 2007 +0800

    Update intel.man with 965GM chipset support

diff --git a/man/intel.man b/man/intel.man
index 80b327d..5ce31ea 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -24,7 +24,7 @@ the 830M and later.
 .SH SUPPORTED HARDWARE
 .B intel
 supports the i810, i810-DC100, i810e, i815, i830M, 845G, 852GM, 855GM,
-865G, 915G, 915GM, 945G, 945GM, 965G, 965Q and 946GZ chipsets.
+865G, 915G, 915GM, 945G, 945GM, 965G, 965Q, 946GZ and 965GM chipsets.
 
 .SH CONFIGURATION DETAILS
 Please refer to __xconfigfile__(__filemansuffix__) for general configuration
@@ -198,4 +198,5 @@ support reworked for XFree86 4.3 by Davi
 Keith Whitwell. Lid status support added by Alan Hourihane. Textured video
 support for 915G and later chips, RandR 1.2 and hardware modesetting added
 by Eric Anholt and Keith Packard. EXA and Render acceleration added by Wang
-Zhenyu. TV out support added by Zou Nan Hai and Keith Packard.
+Zhenyu. TV out support added by Zou Nan Hai and Keith Packard. 965GM support
+added by Wang Zhenyu.