xf86-video-ati: Branch 'master' - 4 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Sun Oct 15 23:41:21 EEST 2006
src/radeon.h | 5
src/radeon_display.c | 53 +++++
src/radeon_driver.c | 507 +++++++++++++++++++++++----------------------------
3 files changed, 283 insertions(+), 282 deletions(-)
New commits:
diff-tree 457178f418983041ea59df703a17513a47d17044 (from 3fb3f410931a13542fdd4c51c4c9ecada7b37d76)
Author: Alex Deucher <alex at t41p.(none)>
Date: Sun Oct 15 16:40:08 2006 -0400
Disable all ouputs on initial mode set. The ones we want will get
enabled by RADEONEnableDisplay().
diff --git a/src/radeon.h b/src/radeon.h
index 705c210..7ff86f9 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -891,6 +891,7 @@ extern Bool RADEONI2cInit(ScrnInf
extern void RADEONSetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag);
extern Bool RADEONMapControllers(ScrnInfoPtr pScrn);
extern void RADEONEnableDisplay(ScrnInfoPtr pScrn, RADEONController* pCRTC, BOOL bEnable);
+extern void RADEONDisableDisplays(ScrnInfoPtr pScrn);
extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn);
extern void RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn);
extern void RADEONUnblank(ScrnInfoPtr pScrn);
diff --git a/src/radeon_display.c b/src/radeon_display.c
index de44b38..58282ef 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -1434,6 +1434,59 @@ static void RADEONDacPowerSet(ScrnInfoPt
}
}
+/* disable all ouputs before enabling the ones we want */
+void RADEONDisableDisplays(ScrnInfoPtr pScrn) {
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char * RADEONMMIO = info->MMIO;
+ unsigned long tmp, tmpPixclksCntl;
+
+
+ /* primary DAC */
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp &= ~RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ RADEONDacPowerSet(pScrn, FALSE, TRUE);
+
+ /* Secondary DAC */
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ }
+ RADEONDacPowerSet(pScrn, FALSE, FALSE);
+
+ /* FP 1 */
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+
+ /* FP 2 */
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+
+ /* LVDS */
+ tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_DISPLAY_DIS);
+ tmp &= ~(RADEON_LVDS_BLON);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ if (info->IsMobility || info->IsIGP) {
+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
+
+}
+
/* This is to be used enable/disable displays dynamically */
void RADEONEnableDisplay(ScrnInfoPtr pScrn, RADEONController* pCRTC, BOOL bEnable)
{
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 97370ca..28a1672 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -5760,6 +5760,12 @@ static void RADEONRestoreMode(ScrnInfoPt
return;
}
+ /* Disable all outputs at initial mode set. the ones we want will
+ get set by RADEONEnableDisplay()
+ */
+ if (!info->IsSwitching && !info->IsSecondary)
+ RADEONDisableDisplays(pScrn);
+
/* When changing mode with Dual-head card, care must be taken for
* the special order in setting registers. CRTC2 has to be set
* before changing CRTC_EXT register. In the dual-head setup, X
diff-tree 3fb3f410931a13542fdd4c51c4c9ecada7b37d76 (from 45e13f3c8786e75276cce85de4af653713d9b4d8)
Author: Alex Deucher <alex at t41p.(none)>
Date: Sun Oct 15 13:29:48 2006 -0400
Rework the output init code. Divide into separate functions
for each output.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index a95087b..97370ca 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -6227,101 +6227,231 @@ static void RADEONInitTvDacCntl(ScrnInfo
static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
DisplayModePtr mode, BOOL IsPrimary)
{
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
- int xres = mode->HDisplay;
- int yres = mode->VDisplay;
- float Hratio, Vratio;
- RADEONMonitorType MonType;
- RADEONTmdsType TmdsType;
+ int i;
+ CARD32 tmp = save->tmds_pll_cntl & 0xfffff;
+
+ for (i=0; i<4; i++) {
+ if (info->tmds_pll[i].freq == 0) break;
+ if ((CARD32)(mode->Clock/10) < info->tmds_pll[i].freq) {
+ tmp = info->tmds_pll[i].value ;
+ break;
+ }
+ }
+
+ if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RV280)) {
+ if (tmp & 0xfff00000)
+ save->tmds_pll_cntl = tmp;
+ else {
+ save->tmds_pll_cntl &= 0xfff00000;
+ save->tmds_pll_cntl |= tmp;
+ }
+ } else save->tmds_pll_cntl = tmp;
+
+ save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST);
+
+ if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !info->HasCRTC2)
+ save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
+ else /* weird, RV chips got this bit reversed? */
+ save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
+
+ save->fp_gen_cntl |= (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
+ RADEON_FP_CRTC_DONT_SHADOW_HEND );
+
+ if (pScrn->rgbBits == 8)
+ save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
+ else
+ save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
+
if (IsPrimary) {
- MonType = pRADEONEnt->Controller[0].pPort->MonType;
- TmdsType = pRADEONEnt->Controller[0].pPort->TMDSType;
+ if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) {
+ save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
+ if (mode->Flags & RADEON_USE_RMX)
+ save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
+ else
+ save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
+ } else
+ save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
} else {
- MonType = pRADEONEnt->Controller[1].pPort->MonType;
- TmdsType = pRADEONEnt->Controller[1].pPort->TMDSType;
+ if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) {
+ save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
+ save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
+ } else
+ save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
}
+}
+
+static void RADEONInitFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
+ DisplayModePtr mode, BOOL IsPrimary)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ if (pScrn->rgbBits == 8)
+ save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
+ else
+ save->fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
+
if (IsPrimary) {
- if (info->PanelXRes == 0 || info->PanelYRes == 0) {
- Hratio = 1.0;
- Vratio = 1.0;
- } else {
- if (xres > info->PanelXRes) xres = info->PanelXRes;
- if (yres > info->PanelYRes) yres = info->PanelYRes;
+ if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
+ save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+ RADEON_FP2_DVO_EN |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+ if (mode->Flags & RADEON_USE_RMX)
+ save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
+ } else {
+ save->fp2_gen_cntl &= ~(RADEON_FP2_SRC_SEL_CRTC2 |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+ }
+ /*save->fp2_gen_cntl |= ( RADEON_FP2_ON |
+ RADEON_FP2_BLANK_EN |
+ RADEON_FP2_DVO_EN);*/
+ } else {
+ if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
+ save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+ save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 /*|
+ RADEON_FP2_PANEL_FORMAT |
+ RADEON_FP2_BLANK_EN |
+ RADEON_FP2_ON |
+ RADEON_FP2_DVO_EN*/);
+ } else {
+ save->fp2_gen_cntl &= ~(RADEON_FP2_DVO_RATE_SEL_SDR);
+ save->fp2_gen_cntl |= (RADEON_FP2_SRC_SEL_CRTC2 /*|
+ RADEON_FP2_PANEL_FORMAT |
+ RADEON_FP2_BLANK_EN |
+ RADEON_FP2_ON |
+ RADEON_FP2_DVO_EN*/);
+ }
+ }
+
+}
+
+static void RADEONInitLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+ DisplayModePtr mode, BOOL IsPrimary)
+{
+
+ if (IsPrimary)
+ save->lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
+ else
+ save->lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
+
+}
+
+static void RADEONInitRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+ DisplayModePtr mode)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ int xres = mode->HDisplay;
+ int yres = mode->VDisplay;
+ float Hratio, Vratio;
+
+
+ if (info->PanelXRes == 0 || info->PanelYRes == 0) {
+ Hratio = 1.0;
+ Vratio = 1.0;
+ } else {
+ if (xres > info->PanelXRes) xres = info->PanelXRes;
+ if (yres > info->PanelYRes) yres = info->PanelYRes;
- Hratio = (float)xres/(float)info->PanelXRes;
- Vratio = (float)yres/(float)info->PanelYRes;
- }
+ Hratio = (float)xres/(float)info->PanelXRes;
+ Vratio = (float)yres/(float)info->PanelYRes;
+ }
- save->fp_vert_stretch &= RADEON_VERT_STRETCH_RESERVED;
- save->fp_horz_stretch &= (RADEON_HORZ_FP_LOOP_STRETCH |
- RADEON_HORZ_AUTO_RATIO_INC);
+ save->fp_vert_stretch &= RADEON_VERT_STRETCH_RESERVED;
+ save->fp_horz_stretch &= (RADEON_HORZ_FP_LOOP_STRETCH |
+ RADEON_HORZ_AUTO_RATIO_INC);
- if (Hratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
- save->fp_horz_stretch |= ((xres/8-1)<<16);
- } else {
- save->fp_horz_stretch |= ((((unsigned long)(Hratio * RADEON_HORZ_STRETCH_RATIO_MAX +
- 0.5)) & RADEON_HORZ_STRETCH_RATIO_MASK) |
- RADEON_HORZ_STRETCH_BLEND |
- RADEON_HORZ_STRETCH_ENABLE |
- ((info->PanelXRes/8-1)<<16));
- }
+ if (Hratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
+ save->fp_horz_stretch |= ((xres/8-1)<<16);
+ } else {
+ save->fp_horz_stretch |= ((((unsigned long)(Hratio * RADEON_HORZ_STRETCH_RATIO_MAX +
+ 0.5)) & RADEON_HORZ_STRETCH_RATIO_MASK) |
+ RADEON_HORZ_STRETCH_BLEND |
+ RADEON_HORZ_STRETCH_ENABLE |
+ ((info->PanelXRes/8-1)<<16));
+ }
- if (Vratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
- save->fp_vert_stretch |= ((yres-1)<<12);
- } else {
- save->fp_vert_stretch |= ((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX +
- 0.5)) & RADEON_VERT_STRETCH_RATIO_MASK) |
+ if (Vratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
+ save->fp_vert_stretch |= ((yres-1)<<12);
+ } else {
+ save->fp_vert_stretch |= ((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX +
+ 0.5)) & RADEON_VERT_STRETCH_RATIO_MASK) |
RADEON_VERT_STRETCH_ENABLE |
RADEON_VERT_STRETCH_BLEND |
((info->PanelYRes-1)<<12));
- }
}
- if (MonType == MT_LCD) {
+}
- /* save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);*/
+static void RADEONInitDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+ DisplayModePtr mode, BOOL IsPrimary)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
- } else if ((MonType == MT_DFP) && (TmdsType == TMDS_INT)) {
- int i;
- CARD32 tmp = save->tmds_pll_cntl & 0xfffff;
- for (i=0; i<4; i++) {
- if (info->tmds_pll[i].freq == 0) break;
- if ((CARD32)(mode->Clock/10) < info->tmds_pll[i].freq) {
- tmp = info->tmds_pll[i].value ;
- break;
- }
- }
- if (IS_R300_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_RV280)) {
- if (tmp & 0xfff00000)
- save->tmds_pll_cntl = tmp;
- else {
- save->tmds_pll_cntl &= 0xfff00000;
- save->tmds_pll_cntl |= tmp;
- }
- } else save->tmds_pll_cntl = tmp;
+ if (IsPrimary) {
+ if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
+ save->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
+ } else {
+ save->dac2_cntl &= ~(RADEON_DAC2_DAC_CLK_SEL);
+ }
+ save->dac_cntl = (RADEON_DAC_MASK_ALL
+ | RADEON_DAC_VGA_ADR_EN
+ | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN));
- save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST);
- if (IS_R300_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_R200) || !info->HasCRTC2)
- save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
- else /* weird, RV chips got this bit reversed? */
- save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
-
- // save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
-
- save->fp_gen_cntl |= (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
- RADEON_FP_CRTC_DONT_SHADOW_HEND );
-
- if (pScrn->rgbBits == 8)
- save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
- else
- save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
+ } else {
+ if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
+ save->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
+ save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
+ } else {
+ save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
}
+ }
+}
+
+static void RADEONInitDAC2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
+ DisplayModePtr mode, BOOL IsPrimary)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ /*0x0028023;*/
+ RADEONInitTvDacCntl(pScrn, save);
+
+ if (IsPrimary) {
+ /*save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;*/
+ save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
+ if (IS_R300_VARIANT) {
+ save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+ save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
+ } else if (info->ChipFamily == CHIP_FAMILY_R200) {
+ save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+ /*save->fp2_gen_cntl |= (RADEON_FP2_ON |
+ RADEON_FP2_BLANK_EN |
+ RADEON_FP2_DVO_EN);*/
+ } else {
+ save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+ }
+ } else {
+ if (IS_R300_VARIANT) {
+ save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
+ save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+ save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
+ } else if (info->ChipFamily == CHIP_FAMILY_R200) {
+ save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+ save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 /*|
+ RADEON_FP2_BLANK_EN |
+ RADEON_FP2_ON |
+ RADEON_FP2_DVO_EN*/);
+ /*save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
+ save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;*/
+ } else {
+ save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
+ save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
+ }
+ }
}
/* Define CRTC registers for requested video mode */
@@ -6466,6 +6596,11 @@ static Bool RADEONInitCrtcRegisters(Scrn
(pScrn->bitsPerPixel * 8));
save->crtc_pitch |= save->crtc_pitch << 16;
+ save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
+ save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
+ save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
+ save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
+
/* Set following registers for all cases first, if a DFP/LCD is connected on
internal TMDS/LVDS port, they will be set by RADEONInitFPRegister
*/
@@ -6478,79 +6613,19 @@ static Bool RADEONInitCrtcRegisters(Scrn
if (pRADEONEnt->Controller[0].pPort->MonType == MT_CRT) {
if (pRADEONEnt->Controller[0].pPort->DACType == DAC_PRIMARY) {
- if((info->ChipFamily == CHIP_FAMILY_R200) ||
- IS_R300_VARIANT) {
- save->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
- } else {
- save->dac2_cntl &= ~(RADEON_DAC2_DAC_CLK_SEL);
- }
- save->dac_cntl = (RADEON_DAC_MASK_ALL
- | RADEON_DAC_VGA_ADR_EN
- | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN));
+ RADEONInitDACRegisters(pScrn, save, mode, TRUE);
} else {
- /*0x0028023;*/
- RADEONInitTvDacCntl(pScrn, save);
- save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
- save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
- if(IS_R300_VARIANT) {
- save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
- save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
- } else if (info->ChipFamily == CHIP_FAMILY_R200) {
- save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- save->fp2_gen_cntl |= (RADEON_FP2_ON |
- RADEON_FP2_BLANK_EN |
- RADEON_FP2_DVO_EN);
- } else {
- save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
- }
+ RADEONInitDAC2Registers(pScrn, save, mode, TRUE);
}
- } else if ((pRADEONEnt->Controller[0].pPort->MonType == MT_DFP) ||
- (pRADEONEnt->Controller[0].pPort->MonType == MT_LCD)) {
-
- save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
- save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
- save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
- save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
-
- RADEONInitFPRegisters(pScrn, save, mode, TRUE);
-
- if ((pRADEONEnt->Controller[0].pPort->TMDSType == TMDS_INT) ||
- (pRADEONEnt->Controller[0].pPort->MonType == MT_LCD)) {
-
- if (pRADEONEnt->Controller[0].pPort->MonType == MT_LCD) {
- save->lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
- } else {
- if ((IS_R300_VARIANT) ||
- (info->ChipFamily == CHIP_FAMILY_R200)) {
- save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
- if (mode->Flags & RADEON_USE_RMX)
- save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
- else
- save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
- } else
- save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
- }
+ } else if (pRADEONEnt->Controller[0].pPort->MonType == MT_LCD) {
+ RADEONInitRMXRegisters(pScrn, save, mode);
+ RADEONInitLVDSRegisters(pScrn, save, mode, TRUE);
+ } else if (pRADEONEnt->Controller[0].pPort->MonType == MT_DFP) {
+ RADEONInitRMXRegisters(pScrn, save, mode);
+ if (pRADEONEnt->Controller[0].pPort->TMDSType == TMDS_INT) {
+ RADEONInitFPRegisters(pScrn, save, mode, TRUE);
} else {
-
- if((info->ChipFamily == CHIP_FAMILY_R200) ||
- IS_R300_VARIANT) {
- save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_EN |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- if (mode->Flags & RADEON_USE_RMX)
- save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
- } else {
- save->fp2_gen_cntl &= ~(RADEON_FP2_SRC_SEL_CRTC2 |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- }
- save->fp2_gen_cntl |= ( RADEON_FP2_ON |
- RADEON_FP2_BLANK_EN |
- RADEON_FP2_DVO_EN);
- if (pScrn->rgbBits == 8)
- save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
- else
- save->fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
+ RADEONInitFP2Registers(pScrn, save, mode, TRUE);
}
}
@@ -6679,80 +6754,22 @@ static Bool RADEONInitCrtc2Registers(Scr
save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl;
save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
+ save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
+ save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
if (pRADEONEnt->Controller[1].pPort->MonType == MT_CRT) {
if (pRADEONEnt->Controller[1].pPort->DACType == DAC_PRIMARY) {
- if((info->ChipFamily == CHIP_FAMILY_R200) ||
- IS_R300_VARIANT) {
- save->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
- save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
- } else {
- save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
- }
+ RADEONInitDACRegisters(pScrn, save, mode, FALSE);
} else {
- /*save->tv_dac_cntl = 0x0028023;*/
- RADEONInitTvDacCntl(pScrn, save);
- if(IS_R300_VARIANT) {
- save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
- save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
- save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
- } else if (info->ChipFamily == CHIP_FAMILY_R200) {
- save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 |
- RADEON_FP2_BLANK_EN |
- RADEON_FP2_ON |
- RADEON_FP2_DVO_EN);
- save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
- save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
- } else {
- save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
- save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
- }
+ RADEONInitDAC2Registers(pScrn, save, mode, FALSE);
}
- } else if ((pRADEONEnt->Controller[1].pPort->MonType == MT_DFP) ||
- (pRADEONEnt->Controller[1].pPort->MonType == MT_LCD)) {
-
- save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
- save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
-
- if ((pRADEONEnt->Controller[1].pPort->TMDSType == TMDS_INT) ||
- (pRADEONEnt->Controller[1].pPort->MonType == MT_LCD)) {
-
- RADEONInitFPRegisters(pScrn, save, mode, FALSE);
-
- if (pRADEONEnt->Controller[1].pPort->MonType == MT_LCD) {
- save->lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
- } else {
- if ((IS_R300_VARIANT) ||
- (info->ChipFamily == CHIP_FAMILY_R200)) {
- save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
- save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
- } else
- save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
- }
+ } else if (pRADEONEnt->Controller[1].pPort->MonType == MT_LCD) {
+ RADEONInitLVDSRegisters(pScrn, save, mode, FALSE);
+ } else if (pRADEONEnt->Controller[1].pPort->MonType == MT_DFP) {
+ if (pRADEONEnt->Controller[1].pPort->TMDSType == TMDS_INT) {
+ RADEONInitFPRegisters(pScrn, save, mode, FALSE);
} else {
- if((info->ChipFamily == CHIP_FAMILY_R200) ||
- IS_R300_VARIANT) {
- save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 |
- RADEON_FP2_PANEL_FORMAT |
- RADEON_FP2_BLANK_EN |
- RADEON_FP2_ON |
- RADEON_FP2_DVO_EN);
- } else {
- save->fp2_gen_cntl &= ~(RADEON_FP2_DVO_RATE_SEL_SDR);
- save->fp2_gen_cntl |= (RADEON_FP2_SRC_SEL_CRTC2 |
- RADEON_FP2_PANEL_FORMAT |
- RADEON_FP2_BLANK_EN |
- RADEON_FP2_ON |
- RADEON_FP2_DVO_EN);
- }
- if (pScrn->rgbBits == 8)
- save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
- else
- save->fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
+ RADEONInitFP2Registers(pScrn, save, mode, FALSE);
}
}
diff-tree 45e13f3c8786e75276cce85de4af653713d9b4d8 (from 4abb5b7afea8d37e95461335e52b16168e555dab)
Author: Alex Deucher <alex at t41p.(none)>
Date: Sun Oct 15 13:18:01 2006 -0400
Remove paneloff option. This is already covered by monitorlayout and
shouldn't be needed with xrandr++.
Also remove commented out Bioshotkey code.
diff --git a/src/radeon.h b/src/radeon.h
index c234f6d..705c210 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -449,7 +449,6 @@ typedef struct {
Bool IsPrimary; /* Primary Screen */
Bool IsSwitching; /* Flag for switching mode */
Bool OverlayOnCRTC2;
- Bool PanelOff; /* Force panel (LCD/DFP) off */
Bool ddc_mode; /* Validate mode by matching exactly
* the modes supported in DDC data
*/
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 4ee6281..a95087b 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -158,7 +158,6 @@ static const OptionInfoRec RADEONOptions
{ OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE },
#endif
#endif
- { OPTION_PANEL_OFF, "PanelOff", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_DDC_MODE, "DDCMode", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_MONITOR_LAYOUT, "MonitorLayout", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE },
@@ -6281,26 +6280,6 @@ static void RADEONInitFPRegisters(ScrnIn
}
}
- info->PanelOff = FALSE;
- /* This option is used to force the ONLY DEVICE in XFConfig to use
- * CRT port, instead of default DVI port.
- */
- if (xf86ReturnOptValBool(info->Options, OPTION_PANEL_OFF, FALSE)) {
- info->PanelOff = TRUE;
- }
-
- if (info->PanelOff && info->MergedFB) {
- info->OverlayOnCRTC2 = TRUE;
- if (MonType == MT_LCD) {
- /* Turning off LVDS_ON seems to make panel white blooming.
- * For now we just turn off display data ???
- */
- save->lvds_gen_cntl |= (RADEON_LVDS_DISPLAY_DIS);
- save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON);
-
- } else if (MonType == MT_DFP)
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- } else {
if (MonType == MT_LCD) {
/* save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
@@ -6343,57 +6322,6 @@ static void RADEONInitFPRegisters(ScrnIn
else
save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
}
- }
-#if 0
- info->BiosHotkeys = FALSE;
- /*
- * Allow the bios to toggle outputs. see below for more.
- */
- if (info->IsMobility) {
- if (xf86ReturnOptValBool(info->Options, OPTION_BIOS_HOTKEYS, FALSE)) {
- info->BiosHotkeys = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIOS HotKeys Enabled\n");
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIOS HotKeys Disabled\n");
- }
- }
-
- if (info->IsMobility && (!info->BiosHotkeys)) {
-
- /* To work correctly with laptop hotkeys.
- * Since there is no machnism for accessing ACPI evnets
- * and the driver currently doesn't know how to validate
- * a mode dynamically, we have to tell BIOS don't do
- * display switching after X has started.
- * If LCD is on, lid close/open should still work
- * with below settings
- */
- if (info->DisplayType == MT_LCD) {
- if (pRADEONEnt->Controller[1].pPort->MonType == MT_CRT)
- save->bios_5_scratch = 0x0201;
- else if (pRADEONEnt->Controller[1].pPort->MonType == MT_DFP)
- save->bios_5_scratch = 0x0801;
- } else {
- if (pRADEONEnt->Controller[1].pPort->MonType == MT_CRT)
- save->bios_5_scratch = 0x0200;
- else if (pRADEONEnt->Controller[1].pPort->MonType == MT_DFP)
- save->bios_5_scratch = 0x0800;
- else
- save->bios_5_scratch = 0x0;
- }
- save->bios_4_scratch = 0x4;
- save->bios_6_scratch |= 0x40000000;
-
- } else if (info->IsMobility && (info->DisplayType == MT_LCD)) {
-
- /* BIOS will use this setting to reset displays upon lid close/open.
- * Here we let BIOS controls LCD, but the driver will control the external CRT.
- */
- if (info->MergedFB || pRADEONEnt->HasSecondary)
- save->bios_5_scratch = 0x01020201;
-
- }
-#endif
}
/* Define CRTC registers for requested video mode */
diff-tree 4abb5b7afea8d37e95461335e52b16168e555dab (from 2933140b5f1f8a6e270460d8918a14943bd0f174)
Author: Alex Deucher <alex at t41p.(none)>
Date: Sun Oct 15 13:10:22 2006 -0400
Remove Bioshotkeys option. Leave the bios as configured at boot.
Most distros enable this option by defalt anyway, and with xrandr++
it won't be an issue anyway.
diff --git a/src/radeon.h b/src/radeon.h
index a97fe49..c234f6d 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -806,9 +806,6 @@ typedef struct {
/* special handlings for DELL triple-head server */
Bool IsDellServer;
- /* enable bios hotkey output switching */
- Bool BiosHotkeys;
-
Bool VGAAccess;
int MaxSurfaceWidth;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 0a0d382..4ee6281 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -193,7 +193,6 @@ static const OptionInfoRec RADEONOptions
#endif
{ OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_DYNAMIC_CLOCKS, "DynamicClocks", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_BIOS_HOTKEYS, "BIOSHotkeys", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE },
{ OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE },
@@ -6345,7 +6344,7 @@ static void RADEONInitFPRegisters(ScrnIn
save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
}
}
-
+#if 0
info->BiosHotkeys = FALSE;
/*
* Allow the bios to toggle outputs. see below for more.
@@ -6394,6 +6393,7 @@ static void RADEONInitFPRegisters(ScrnIn
save->bios_5_scratch = 0x01020201;
}
+#endif
}
/* Define CRTC registers for requested video mode */
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