xf86-video-intel: Branch 'modesetting' - 3 commits - src/i830_display.c src/i830_driver.c

[Keith Packard]

 src/i830_display.c |   25 +++++++++++++------------
 src/i830_driver.c  |    8 ++++++--
 2 files changed, 19 insertions(+), 14 deletions(-)

New commits:
diff-tree fde52de870c84821ab457e17634c334a10cf71ab (from parents)
Merge: 7dbe6c378d1bc0c06ed6be4c1f9ca38ac31a5571 85de8a05804eaebcd61430793ef5406f196f9a95
Author: Keith Packard <keithp at guitar.keithp.com>
Date:   Wed Dec 6 23:40:13 2006 -0800

    Merge branch 'modesetting-origin' into modesetting

diff-tree 7dbe6c378d1bc0c06ed6be4c1f9ca38ac31a5571 (from 28c7002b1cf81e286a083384575d53021d3ce906)
Author: Keith Packard <keithp at guitar.keithp.com>
Date:   Wed Dec 6 23:39:14 2006 -0800

    Move vga restore to end of RestoreHWState.
    
    I was having consistent system lockups when the vga restore
    was first. Moving it to the end has reduced them to an infrequent
    occurrence (but, alas, it has happened once since). This does not
    make me happy.

diff --git a/src/i830_driver.c b/src/i830_driver.c
index 915107f..61ce8ad 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2273,8 +2273,6 @@ RestoreHWState(ScrnInfoPtr pScrn)
 #ifdef XF86DRI
    I830DRISetVBlankInterrupt (pScrn, FALSE);
 #endif
-   vgaHWRestore(pScrn, vgaReg, VGA_SR_FONTS);
-   vgaHWLock(hwp);
 
    /* Disable outputs */
    for (i = 0; i < pI830->xf86_config.num_output; i++) {
@@ -2376,6 +2374,12 @@ RestoreHWState(ScrnInfoPtr pScrn)
    OUTREG(SWF31, pI830->saveSWF[15]);
    OUTREG(SWF32, pI830->saveSWF[16]);
 
+   for (i = 0; i < 2; i++)
+      i830WaitForVblank(pScrn);
+
+   vgaHWRestore(pScrn, vgaReg, VGA_SR_FONTS);
+   vgaHWLock(hwp);
+
    return TRUE;
 }
 
diff-tree 28c7002b1cf81e286a083384575d53021d3ce906 (from 182d2f503a7a1be90d93a4a15059585a564fd3ce)
Author: Keith Packard <keithp at guitar.keithp.com>
Date:   Wed Dec 6 23:35:15 2006 -0800

    Use DOUBLE_WIDE mode on all hardware.
    
    DOUBLE_WIDE mode is needed when the pixel clock is > 90% of the core
    clock rate. The code guesses what the core clock rate is based on
    the bus (AGP -> 133MHz, PCI-E -> 200MHz).

diff --git a/src/i830_display.c b/src/i830_display.c
index 0e5a09a..439c298 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -705,22 +705,23 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
 	dspcntr |= DISPPLANE_SEL_PIPE_B;
 
     pipeconf = INREG(pipeconf_reg);
-    if (!IS_I9XX(pI830) && pipe == 0) {
+    if (pipe == 0) 
+    {
 	/*
 	 * The docs say this is needed when the dot clock is > 90% of the
 	 * core speed. Core speeds are indicated by bits in the PCI
-	 * config space and don't seem to ever be less than 200MHz,
-	 * which is a bit confusing.
-	 *
-	 * However, For one little 855/852 card I have, 135000 requires
-	 * double wide mode, but 108000 does not. That makes no sense
-	 * but we're used to that. It may be affected by pixel size,
-	 * but the BIOS mode setting code doesn't appear to use that.
-	 *
-	 * It doesn't seem to cause any harm, although it
-	 * does restrict some output options.
+	 * config space, but that's a pain to go read, so we just guess
+	 * based on the hardware age. AGP hardware is assumed to run
+	 * at 133MHz while PCI-E hardware is assumed to run at 200MHz
 	 */
-	if (adjusted_mode->Clock > 108000)
+	int core_clock;
+	
+	if (IS_I9XX(pI830))
+	    core_clock = 200000;
+	else
+	    core_clock = 133000;
+	
+	if (mode->Clock > core_clock * 9 / 10)
 	    pipeconf |= PIPEACONF_DOUBLE_WIDE;
 	else
 	    pipeconf &= ~PIPEACONF_DOUBLE_WIDE;