xf86-video-intel: Branch 'modesetting' - 5 commits - src/i830_driver.c src/i830_tv.c
Eric Anholt
anholt at kemper.freedesktop.org
Thu Dec 7 03:11:56 EET 2006
src/i830_driver.c | 234 +++---------------------------------------------------
src/i830_tv.c | 80 +++++++++++++++---
2 files changed, 83 insertions(+), 231 deletions(-)
New commits:
diff-tree 6777d8044d5cc063698e05afb7a93a58a7a3b64a (from c6ce8a3c3355e8a56e86856caa56baf1cd3c0231)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 6 17:10:06 2006 -0800
Harmless warning fix.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 53c0ab8..2f515ed 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2177,7 +2177,6 @@ SaveHWState(ScrnInfoPtr pScrn)
I830Ptr pI830 = I830PTR(pScrn);
vgaHWPtr hwp = VGAHWPTR(pScrn);
vgaRegPtr vgaReg = &hwp->SavedReg;
- CARD32 temp;
int i;
/* Save video mode information for native mode-setting. */
diff-tree c6ce8a3c3355e8a56e86856caa56baf1cd3c0231 (from b23dec37b28a76433ad5d537ab508294e843cabe)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 6 17:07:48 2006 -0800
Reduce dumpregs to X startup, after a mode set, and LeaveVT.
While here, remove some other register dumping that is better done by
i830DumpRegs().
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 9428476..53c0ab8 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1184,6 +1184,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags
/* Some of the probing needs MMIO access, so map it here. */
I830MapMMIO(pScrn);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardware state on X startup:\n");
+ i830DumpRegs (pScrn);
+
i830TakeRegSnapshot(pScrn);
#if 1
@@ -2177,18 +2180,6 @@ SaveHWState(ScrnInfoPtr pScrn)
CARD32 temp;
int i;
- /*
- * Print out the PIPEACONF and PIPEBCONF registers.
- */
- temp = INREG(PIPEACONF);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PIPEACONF is 0x%08lx\n",
- (unsigned long) temp);
- if (pI830->xf86_config.num_crtc == 2) {
- temp = INREG(PIPEBCONF);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PIPEBCONF is 0x%08lx\n",
- (unsigned long) temp);
- }
-
/* Save video mode information for native mode-setting. */
pI830->saveDSPACNTR = INREG(DSPACNTR);
pI830->savePIPEACONF = INREG(PIPEACONF);
@@ -2386,9 +2377,6 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(SWF31, pI830->saveSWF[15]);
OUTREG(SWF32, pI830->saveSWF[16]);
- i830CompareRegsToSnapshot(pScrn, "After RestoreHWState");
- i830DumpRegs (pScrn);
-
return TRUE;
}
@@ -2502,195 +2490,6 @@ I965PrintErrorState(ScrnInfoPtr pScrn)
}
-#ifdef I830DEBUG
-static void
-dump_DSPACNTR(ScrnInfoPtr pScrn)
-{
- I830Ptr pI830 = I830PTR(pScrn);
- unsigned int tmp;
-
- /* Display A Control */
- tmp = INREG(0x70180);
- ErrorF("Display A Plane Control Register (0x%.8x)\n", tmp);
-
- if (tmp & BIT(31))
- ErrorF(" Display Plane A (Primary) Enable\n");
- else
- ErrorF(" Display Plane A (Primary) Disabled\n");
-
- if (tmp & BIT(30))
- ErrorF(" Display A pixel data is gamma corrected\n");
- else
- ErrorF(" Display A pixel data bypasses gamma correction logic (default)\n");
-
- switch ((tmp & 0x3c000000) >> 26) { /* bit 29:26 */
- case 0x00:
- case 0x01:
- case 0x03:
- ErrorF(" Reserved\n");
- break;
- case 0x02:
- ErrorF(" 8-bpp Indexed\n");
- break;
- case 0x04:
- ErrorF(" 15-bit (5-5-5) pixel format (Targa compatible)\n");
- break;
- case 0x05:
- ErrorF(" 16-bit (5-6-5) pixel format (XGA compatible)\n");
- break;
- case 0x06:
- ErrorF(" 32-bit format (X:8:8:8)\n");
- break;
- case 0x07:
- ErrorF(" 32-bit format (8:8:8:8)\n");
- break;
- default:
- ErrorF(" Unknown - Invalid register value maybe?\n");
- }
-
- if (tmp & BIT(25))
- ErrorF(" Stereo Enable\n");
- else
- ErrorF(" Stereo Disable\n");
-
- if (tmp & BIT(24))
- ErrorF(" Display A, Pipe B Select\n");
- else
- ErrorF(" Display A, Pipe A Select\n");
-
- if (tmp & BIT(22))
- ErrorF(" Source key is enabled\n");
- else
- ErrorF(" Source key is disabled\n");
-
- switch ((tmp & 0x00300000) >> 20) { /* bit 21:20 */
- case 0x00:
- ErrorF(" No line duplication\n");
- break;
- case 0x01:
- ErrorF(" Line/pixel Doubling\n");
- break;
- case 0x02:
- case 0x03:
- ErrorF(" Reserved\n");
- break;
- }
-
- if (tmp & BIT(18))
- ErrorF(" Stereo output is high during second image\n");
- else
- ErrorF(" Stereo output is high during first image\n");
-}
-
-static void
-dump_DSPBCNTR(ScrnInfoPtr pScrn)
-{
- I830Ptr pI830 = I830PTR(pScrn);
- unsigned int tmp;
-
- /* Display B/Sprite Control */
- tmp = INREG(0x71180);
- ErrorF("Display B/Sprite Plane Control Register (0x%.8x)\n", tmp);
-
- if (tmp & BIT(31))
- ErrorF(" Display B/Sprite Enable\n");
- else
- ErrorF(" Display B/Sprite Disable\n");
-
- if (tmp & BIT(30))
- ErrorF(" Display B pixel data is gamma corrected\n");
- else
- ErrorF(" Display B pixel data bypasses gamma correction logic (default)\n");
-
- switch ((tmp & 0x3c000000) >> 26) { /* bit 29:26 */
- case 0x00:
- case 0x01:
- case 0x03:
- ErrorF(" Reserved\n");
- break;
- case 0x02:
- ErrorF(" 8-bpp Indexed\n");
- break;
- case 0x04:
- ErrorF(" 15-bit (5-5-5) pixel format (Targa compatible)\n");
- break;
- case 0x05:
- ErrorF(" 16-bit (5-6-5) pixel format (XGA compatible)\n");
- break;
- case 0x06:
- ErrorF(" 32-bit format (X:8:8:8)\n");
- break;
- case 0x07:
- ErrorF(" 32-bit format (8:8:8:8)\n");
- break;
- default:
- ErrorF(" Unknown - Invalid register value maybe?\n");
- }
-
- if (tmp & BIT(25))
- ErrorF(" Stereo is enabled and both start addresses are used in a two frame sequence\n");
- else
- ErrorF(" Stereo disable and only a single start address is used\n");
-
- if (tmp & BIT(24))
- ErrorF(" Display B/Sprite, Pipe B Select\n");
- else
- ErrorF(" Display B/Sprite, Pipe A Select\n");
-
- if (tmp & BIT(22))
- ErrorF(" Sprite source key is enabled\n");
- else
- ErrorF(" Sprite source key is disabled (default)\n");
-
- switch ((tmp & 0x00300000) >> 20) { /* bit 21:20 */
- case 0x00:
- ErrorF(" No line duplication\n");
- break;
- case 0x01:
- ErrorF(" Line/pixel Doubling\n");
- break;
- case 0x02:
- case 0x03:
- ErrorF(" Reserved\n");
- break;
- }
-
- if (tmp & BIT(18))
- ErrorF(" Stereo output is high during second image\n");
- else
- ErrorF(" Stereo output is high during first image\n");
-
- if (tmp & BIT(15))
- ErrorF(" Alpha transfer mode enabled\n");
- else
- ErrorF(" Alpha transfer mode disabled\n");
-
- if (tmp & BIT(0))
- ErrorF(" Sprite is above overlay\n");
- else
- ErrorF(" Sprite is above display A (default)\n");
-}
-
-void
-I830_dump_registers(ScrnInfoPtr pScrn)
-{
- I830Ptr pI830 = I830PTR(pScrn);
- unsigned int i;
-
- ErrorF("%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n");
-
- dump_DSPACNTR(pScrn);
- dump_DSPBCNTR(pScrn);
-
- ErrorF("0x71400 == 0x%.8x\n", INREG(0x71400));
- ErrorF("0x70008 == 0x%.8x\n", INREG(0x70008));
- for (i = 0x71410; i <= 0x71428; i += 4)
- ErrorF("0x%x == 0x%.8x\n", i, INREG(i));
-
- ErrorF("%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n");
-}
-#endif
-
static void
I830PointerMoved(int index, int x, int y)
{
@@ -3302,10 +3101,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr
if (serverGeneration == 1)
xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
-#ifdef I830DEBUG
- I830_dump_registers(pScrn);
-#endif
-
if (IS_I965G(pI830)) {
/* turn off clock gating */
#if 0
@@ -3477,6 +3272,10 @@ I830LeaveVT(int scrnIndex, int flags)
ResetState(pScrn, TRUE);
RestoreHWState(pScrn);
+
+ i830CompareRegsToSnapshot(pScrn, "After LeaveVT");
+ i830DumpRegs (pScrn);
+
if (I830IsPrimary(pScrn))
I830UnbindAGPMemory(pScrn);
if (pI830->AccelInfoRec)
diff-tree b23dec37b28a76433ad5d537ab508294e843cabe (from d3c21c09e3904b3d32aca7563044194b061ac2fa)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 6 16:58:24 2006 -0800
Save/restore registers around calls in PreInit with register side-effects.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index ec41a56..9428476 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1401,12 +1401,10 @@ I830PreInit(ScrnInfoPtr pScrn, int flags
pI830->Clone = TRUE;
}
-
-#if 0
- SaveHWState (pScrn);
-#endif
- /* Perform the pipe assignment of outputs. This is a kludge until
- * we have better configuration support in the generic RandR code
+ SaveHWState(pScrn);
+ /* Do an initial detection of the outputs while none are configured on yet.
+ * This will give us some likely legitimate response for later if both
+ * pipes are already allocated and we're asked to do a detect.
*/
for (i = 0; i < pI830->xf86_config.num_output; i++)
{
@@ -1414,16 +1412,16 @@ I830PreInit(ScrnInfoPtr pScrn, int flags
output->status = (*output->funcs->detect) (output);
}
-#if 0
- RestoreHWState (pScrn);
-#endif
-
+
if (!xf86InitialConfiguration (pScrn))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n");
+ RestoreHWState(pScrn);
PreInitCleanup(pScrn);
return FALSE;
}
+ RestoreHWState(pScrn);
+
pScrn->displayWidth = (pScrn->virtualX + 63) & ~63;
pI830->rotation = RR_Rotate_0;
diff-tree d3c21c09e3904b3d32aca7563044194b061ac2fa (from 9c3e733aaa2068fcb0164577237ed70d177e9b5a)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 6 16:50:52 2006 -0800
Remove stale i830_tv_pre_set_mode. Replaced by generic dpms hook call.
Also replaced by not spamming unrelated ADPA register. At least, it had sure
better not be related.
diff --git a/src/i830_tv.c b/src/i830_tv.c
index 9f92ce0..b6cc2c9 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -287,18 +287,6 @@ i830_tv_mode_valid(xf86OutputPtr output,
return MODE_OK;
}
-static void
-i830_tv_pre_set_mode(xf86OutputPtr output, DisplayModePtr pMode)
-{
- ScrnInfoPtr pScrn = output->scrn;
- I830Ptr pI830 = I830PTR(pScrn);
-
- /* Disable the encoder while we set up the pipe. */
- OUTREG(TV_CTL, INREG(TV_CTL) & ~TV_ENC_ENABLE);
- /* XXX match BIOS for now */
- OUTREG(ADPA, 0x40008C18);
-}
-
static const CARD32 h_luma[60] = {
0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
diff-tree 9c3e733aaa2068fcb0164577237ed70d177e9b5a (from d5ec9d2160f47f21a6015c1cc05b57274cbb0471)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 6 16:36:42 2006 -0800
Save/restore more TV registers.
diff --git a/src/i830_tv.c b/src/i830_tv.c
index d44d58e..9f92ce0 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -59,6 +59,26 @@ struct i830_tv_priv {
CARD32 save_TV_V_CTL_6;
CARD32 save_TV_V_CTL_7;
CARD32 save_TV_SC_CTL_1, save_TV_SC_CTL_2, save_TV_SC_CTL_3;
+
+ CARD32 save_TV_CSC_Y;
+ CARD32 save_TV_CSC_Y2;
+ CARD32 save_TV_CSC_U;
+ CARD32 save_TV_CSC_U2;
+ CARD32 save_TV_CSC_V;
+ CARD32 save_TV_CSC_V2;
+ CARD32 save_TV_CLR_KNOBS;
+ CARD32 save_TV_CLR_LEVEL;
+ CARD32 save_TV_WIN_POS;
+ CARD32 save_TV_WIN_SIZE;
+ CARD32 save_TV_FILTER_CTL_1;
+ CARD32 save_TV_FILTER_CTL_2;
+ CARD32 save_TV_FILTER_CTL_3;
+
+ CARD32 save_TV_H_LUMA[60];
+ CARD32 save_TV_H_CHROMA[60];
+ CARD32 save_TV_V_LUMA[43];
+ CARD32 save_TV_V_CHROMA[43];
+
CARD32 save_TV_DAC;
CARD32 save_TV_CTL;
};
@@ -168,6 +188,7 @@ i830_tv_save(xf86OutputPtr output)
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_tv_priv *dev_priv = intel_output->dev_priv;
+ int i;
dev_priv->save_TV_H_CTL_1 = INREG(TV_H_CTL_1);
dev_priv->save_TV_H_CTL_2 = INREG(TV_H_CTL_2);
@@ -183,6 +204,29 @@ i830_tv_save(xf86OutputPtr output)
dev_priv->save_TV_SC_CTL_2 = INREG(TV_SC_CTL_2);
dev_priv->save_TV_SC_CTL_3 = INREG(TV_SC_CTL_3);
+ dev_priv->save_TV_CSC_Y = INREG(TV_CSC_Y);
+ dev_priv->save_TV_CSC_Y2 = INREG(TV_CSC_Y2);
+ dev_priv->save_TV_CSC_U = INREG(TV_CSC_U);
+ dev_priv->save_TV_CSC_U2 = INREG(TV_CSC_U2);
+ dev_priv->save_TV_CSC_V = INREG(TV_CSC_V);
+ dev_priv->save_TV_CSC_V2 = INREG(TV_CSC_V2);
+ dev_priv->save_TV_CLR_KNOBS = INREG(TV_CLR_KNOBS);
+ dev_priv->save_TV_CLR_LEVEL = INREG(TV_CLR_LEVEL);
+ dev_priv->save_TV_WIN_POS = INREG(TV_WIN_POS);
+ dev_priv->save_TV_WIN_SIZE = INREG(TV_WIN_SIZE);
+ dev_priv->save_TV_FILTER_CTL_1 = INREG(TV_FILTER_CTL_1);
+ dev_priv->save_TV_FILTER_CTL_2 = INREG(TV_FILTER_CTL_2);
+ dev_priv->save_TV_FILTER_CTL_3 = INREG(TV_FILTER_CTL_3);
+
+ for (i = 0; i < 60; i++)
+ dev_priv->save_TV_H_LUMA[i] = INREG(TV_H_LUMA_0 + (i <<2));
+ for (i = 0; i < 60; i++)
+ dev_priv->save_TV_H_CHROMA[i] = INREG(TV_H_CHROMA_0 + (i <<2));
+ for (i = 0; i < 43; i++)
+ dev_priv->save_TV_V_LUMA[i] = INREG(TV_V_LUMA_0 + (i <<2));
+ for (i = 0; i < 43; i++)
+ dev_priv->save_TV_V_CHROMA[i] = INREG(TV_V_CHROMA_0 + (i <<2));
+
dev_priv->save_TV_DAC = INREG(TV_DAC);
dev_priv->save_TV_CTL = INREG(TV_CTL);
}
@@ -194,6 +238,7 @@ i830_tv_restore(xf86OutputPtr output)
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_tv_priv *dev_priv = intel_output->dev_priv;
+ int i;
OUTREG(TV_H_CTL_1, dev_priv->save_TV_H_CTL_1);
OUTREG(TV_H_CTL_2, dev_priv->save_TV_H_CTL_2);
@@ -209,6 +254,29 @@ i830_tv_restore(xf86OutputPtr output)
OUTREG(TV_SC_CTL_2, dev_priv->save_TV_SC_CTL_2);
OUTREG(TV_SC_CTL_3, dev_priv->save_TV_SC_CTL_3);
+ OUTREG(TV_CSC_Y, dev_priv->save_TV_CSC_Y);
+ OUTREG(TV_CSC_Y2, dev_priv->save_TV_CSC_Y2);
+ OUTREG(TV_CSC_U, dev_priv->save_TV_CSC_U);
+ OUTREG(TV_CSC_U2, dev_priv->save_TV_CSC_U2);
+ OUTREG(TV_CSC_V, dev_priv->save_TV_CSC_V);
+ OUTREG(TV_CSC_V2, dev_priv->save_TV_CSC_V2);
+ OUTREG(TV_CLR_KNOBS, dev_priv->save_TV_CLR_KNOBS);
+ OUTREG(TV_CLR_LEVEL, dev_priv->save_TV_CLR_LEVEL);
+ OUTREG(TV_WIN_POS, dev_priv->save_TV_WIN_POS);
+ OUTREG(TV_WIN_SIZE, dev_priv->save_TV_WIN_SIZE);
+ OUTREG(TV_FILTER_CTL_1, dev_priv->save_TV_FILTER_CTL_1);
+ OUTREG(TV_FILTER_CTL_2, dev_priv->save_TV_FILTER_CTL_2);
+ OUTREG(TV_FILTER_CTL_3, dev_priv->save_TV_FILTER_CTL_3);
+
+ for (i = 0; i < 60; i++)
+ OUTREG(TV_H_LUMA_0 + (i <<2), dev_priv->save_TV_H_LUMA[i]);
+ for (i = 0; i < 60; i++)
+ OUTREG(TV_H_CHROMA_0 + (i <<2), dev_priv->save_TV_H_CHROMA[i]);
+ for (i = 0; i < 43; i++)
+ OUTREG(TV_V_LUMA_0 + (i <<2), dev_priv->save_TV_V_LUMA[i]);
+ for (i = 0; i < 43; i++)
+ OUTREG(TV_V_CHROMA_0 + (i <<2), dev_priv->save_TV_V_CHROMA[i]);
+
OUTREG(TV_DAC, dev_priv->save_TV_DAC);
OUTREG(TV_CTL, dev_priv->save_TV_CTL);
}
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