xf86-video-ati: Branch 'master' - 6 commits
George Sapountzis
gsap7 at kemper.freedesktop.org
Sat Aug 5 02:08:15 EEST 2006
src/atii2c.c | 31 ++++-
src/atimach64.c | 3
src/atimach64accel.c | 268 +++++++++++++++++++++++++--------------------------
src/atiregs.h | 13 ++
src/atistruct.h | 28 ++---
5 files changed, 187 insertions(+), 156 deletions(-)
New commits:
diff-tree dc1e289a611a17090e6dc7ae8a8d3f26d20df4eb (from b377f403e0cd5253402ef3945e5944d1a2763a94)
Author: Samuel Thibault <samuel.thibault at ens-lyon.org>
Date: Sat Jul 29 01:05:35 2006 +0300
Bug #6623: Fix I2C bus Mach64 initialisation failure.
diff --git a/src/atii2c.c b/src/atii2c.c
index cb7bc04..35de71f 100644
--- a/src/atii2c.c
+++ b/src/atii2c.c
@@ -117,21 +117,22 @@
/*
- * ATII2CAddress --
+ * ATII2CStart --
*
- * This function puts a Start bit and an 8-bit address on the I2C bus.
+ * This function puts a start signal on the I2C bus.
*/
static Bool
-ATII2CAddress
+ATII2CStart
(
- I2CDevPtr pI2CDev,
- I2CSlaveAddr Address
+ I2CBusPtr pI2CBus,
+ int timeout
)
{
- I2CBusPtr pI2CBus = pI2CDev->pI2CBus;
ATII2CPtr pATII2C = pI2CBus->DriverPrivate.ptr;
ATIPtr pATI = pATII2C->pATI;
+ (void)timeout;
+
/*
* Set I2C line directions to out-bound. SCL will remain out-bound until
* next I2C Stop.
@@ -148,6 +149,23 @@ ATII2CAddress
ATII2CSDABitOff;
ATII2CSCLBitOff;
+ return TRUE;
+}
+
+/*
+ * ATII2CAddress --
+ *
+ * This function puts an 8-bit address on the I2C bus.
+ */
+static Bool
+ATII2CAddress
+(
+ I2CDevPtr pI2CDev,
+ I2CSlaveAddr Address
+)
+{
+ I2CBusPtr pI2CBus = pI2CDev->pI2CBus;
+
/* Send low byte of device address */
if ((*pI2CBus->I2CPutByte)(pI2CDev, (I2CByte)Address))
{
@@ -318,6 +336,7 @@ ATICreateI2CBusRec
pI2CBus->scrnIndex = iScreen;
pI2CBus->I2CAddress = ATII2CAddress;
+ pI2CBus->I2CStart = ATII2CStart;
pI2CBus->I2CStop = ATII2CStop;
pI2CBus->I2CPutByte = ATII2CPutByte;
pI2CBus->I2CGetByte = ATII2CGetByte;
diff-tree b377f403e0cd5253402ef3945e5944d1a2763a94 (from 91b8b0ca41ad0b9659f0982a05148cab8558e9d5)
Author: Marc Aurele La France <tsi at xfree86.org>
Date: Sat Jul 29 01:03:34 2006 +0300
Fix warnings for Option:1 bit fields.
diff --git a/src/atistruct.h b/src/atistruct.h
index 0201042..a84b0e8 100644
--- a/src/atistruct.h
+++ b/src/atistruct.h
@@ -430,16 +430,16 @@ typedef struct _ATIRec
/*
* Driver options.
*/
- CARD8 OptionAccel:1; /* Use hardware draw engine */
- CARD8 OptionBIOSDisplay:1; /* Allow BIOS interference */
- CARD8 OptionBlend:1; /* Force horizontal blending */
- CARD8 OptionCRTDisplay:1; /* Display on both CRT and digital panel */
- CARD8 OptionCSync:1; /* Use composite sync */
- CARD8 OptionDevel:1; /* Intentionally undocumented */
+ unsigned int OptionAccel:1; /* Use hardware draw engine */
+ unsigned int OptionBIOSDisplay:1; /* Allow BIOS interference */
+ unsigned int OptionBlend:1; /* Force horizontal blending */
+ unsigned int OptionCRTDisplay:1; /* Display on both CRT & DFP */
+ unsigned int OptionCSync:1; /* Use composite sync */
+ unsigned int OptionDevel:1; /* Intentionally undocumented */
#ifndef AVOID_CPIO
- CARD8 OptionLinear:1; /* Use linear fb aperture when available */
+ unsigned int OptionLinear:1; /* Use linear aperture if available */
#endif /* AVOID_CPIO */
@@ -450,12 +450,12 @@ typedef struct _ATIRec
#endif /* TV_OUT */
- CARD8 OptionMMIOCache:1; /* Cache MMIO writes */
- CARD8 OptionTestMMIOCache:1;/* Test MMIO cache integrity */
- CARD8 OptionPanelDisplay:1; /* Prefer digital panel over CRT */
- CARD8 OptionProbeClocks:1; /* Force probe for fixed clocks */
- CARD8 OptionShadowFB:1; /* Use shadow frame buffer */
- CARD8 OptionLCDSync:1; /* Temporary */
+ unsigned int OptionMMIOCache:1; /* Cache MMIO writes */
+ unsigned int OptionTestMMIOCache:1;/* Test MMIO cache integrity */
+ unsigned int OptionPanelDisplay:1; /* Prefer digital panel over CRT */
+ unsigned int OptionProbeClocks:1; /* Force probe for fixed clocks */
+ unsigned int OptionShadowFB:1; /* Use shadow frame buffer */
+ unsigned int OptionLCDSync:1; /* Temporary */
/*
* State flags.
diff-tree 91b8b0ca41ad0b9659f0982a05148cab8558e9d5 (from 7800407a2db4b7307192bf3b43fffb9c4748b9c0)
Author: Marc Aurele La France <tsi at xfree86.org>
Date: Sat Jul 29 01:02:48 2006 +0300
Bug #807: copy throttling.
Fix corruption associated with the engine randomly not waiting for a copy
operation to commit its results.
diff --git a/src/atimach64accel.c b/src/atimach64accel.c
index a0a9e17..272de3d 100644
--- a/src/atimach64accel.c
+++ b/src/atimach64accel.c
@@ -481,6 +481,18 @@ ATIMach64SubsequentScreenToScreenCopy
outf(SRC_WIDTH1, w);
outf(DST_Y_X, SetWord(xDst, 1) | SetWord(yDst, 0));
outf(DST_HEIGHT_WIDTH, SetWord(w, 1) | SetWord(h, 0));
+
+ /*
+ * On VTB's and later, the engine will randomly not wait for a copy
+ * operation to commit its results to video memory before starting the next
+ * one. The probability of such occurrences increases with GUI_WB_FLUSH
+ * (or GUI_WB_FLUSH_P) setting, bitsPerPixel and/or CRTC clock. This
+ * would point to some kind of video memory bandwidth problem were it noti
+ * for the fact that the problem occurs less often (but still occurs) when
+ * copying larger rectangles.
+ */
+ if ((pATI->Chip >= ATI_CHIP_264VTB) && !pATI->OptionDevel)
+ ATIMach64Sync(pScreenInfo);
}
/*
diff-tree 7800407a2db4b7307192bf3b43fffb9c4748b9c0 (from 49b11c540d37152eee4907ab30353ede01e4fb56)
Author: Marc Aurele La France <tsi at xfree86.org>
Date: Sat Jul 29 01:00:56 2006 +0300
Bug #807: invalidate read-back cache.
Fix corruption when scaling 1-pixel wide pixmaps, in which case the first CPU
read of the framebuffer will return stale data.
This bug always manifests itself in mach64 EXA (to be committed soon), with
this patch mach64 EXA passes rendercheck.
diff --git a/src/atimach64.c b/src/atimach64.c
index 166aaf0..2cdec78 100644
--- a/src/atimach64.c
+++ b/src/atimach64.c
@@ -183,6 +183,7 @@ ATIMach64PreInit
if (pATI->Chip >= ATI_CHIP_264VTB)
{
+ pATIHW->mem_buf_cntl = inr(MEM_BUF_CNTL) | INVALIDATE_RB_CACHE;
pATIHW->mem_cntl = (pATI->LockData.mem_cntl &
~(CTL_MEM_LOWER_APER_ENDIAN | CTL_MEM_UPPER_APER_ENDIAN)) |
SetBits(CTL_MEM_APER_BYTE_ENDIAN, CTL_MEM_LOWER_APER_ENDIAN);
@@ -424,6 +425,7 @@ ATIMach64Save
if (pATI->Chip >= ATI_CHIP_264VTB)
{
+ pATIHW->mem_buf_cntl = inr(MEM_BUF_CNTL) | INVALIDATE_RB_CACHE;
pATIHW->mem_cntl = inr(MEM_CNTL);
pATIHW->mpp_config = inr(MPP_CONFIG);
pATIHW->mpp_strobe_seq = inr(MPP_STROBE_SEQ);
@@ -1057,6 +1059,7 @@ ATIMach64Set
if (pATI->Chip >= ATI_CHIP_264VTB)
{
+ outr(MEM_BUF_CNTL, pATIHW->mem_buf_cntl);
outr(MEM_CNTL, pATIHW->mem_cntl);
outr(MPP_CONFIG, pATIHW->mpp_config);
outr(MPP_STROBE_SEQ, pATIHW->mpp_strobe_seq);
diff --git a/src/atimach64accel.c b/src/atimach64accel.c
index 932c8c1..a0a9e17 100644
--- a/src/atimach64accel.c
+++ b/src/atimach64accel.c
@@ -245,16 +245,32 @@ ATIMach64Sync
}
}
+ if (pATI->pXAAInfo)
+ pATI->pXAAInfo->NeedToSync = FALSE;
+
+ if (pATI->Chip >= ATI_CHIP_264VTB)
+ {
+ /*
+ * Flush the read-back cache (by turning on INVALIDATE_RB_CACHE),
+ * otherwise the host might get stale data when reading through the
+ * aperture.
+ */
+ outr(MEM_BUF_CNTL, pATI->NewHW.mem_buf_cntl);
+ }
+
/*
+ * Note:
+ * Before actually invalidating the read-back cache, the mach64 driver
+ * was using the trick below which is buggy. The code is left here for
+ * reference, DRI uses this trick and needs updating.
+ *
* For VTB's and later, the first CPU read of the framebuffer will return
* zeroes, so do it here. This appears to be due to some kind of engine
* caching of framebuffer data I haven't found any way of disabling, or
* otherwise circumventing. Thanks to Mark Vojkovich for the suggestion.
+ *
+ * pATI = *(volatile ATIPtr *)pATI->pMemory;
*/
- if (pATI->pXAAInfo)
- pATI->pXAAInfo->NeedToSync = FALSE;
-
- pATI = *(volatile ATIPtr *)pATI->pMemory;
}
static __inline__ void
diff --git a/src/atiregs.h b/src/atiregs.h
index f9730c7..102347b 100644
--- a/src/atiregs.h
+++ b/src/atiregs.h
@@ -692,6 +692,19 @@
/* ? 0xf8000000ul */
#define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */
#define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */
+#define Z_WB_FLUSH 0x00000007ul
+#define Z_WB_FLUSH_P 0x0000000ful /* GTPro */
+#define VID_WB_FLUSH_P 0x000000f0ul /* GTPro */
+#define VID_WB_FLUSH_MSB 0x00000100ul
+#define GUI_WB_FLUSH_P 0x00001f00ul /* GTPro */
+#define HST_WB_FLUSH_P 0x0000e000ul /* GTPro */
+#define SCL_MIN_BURST_LEN 0x001f0000ul
+#define SCL_THRESH 0x003f0000ul /* GTPro */
+/* ? 0x00400000ul */
+#define INVALIDATE_RB_CACHE 0x00800000ul
+#define HST_WB_FLUSH 0x03000000ul
+#define VID_WB_FLUSH 0x1c000000ul
+#define GUI_WB_FLUSH 0xe0000000ul
#define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */
#define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */
#define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GTPro */
diff --git a/src/atistruct.h b/src/atistruct.h
index 0aa37b5..0201042 100644
--- a/src/atistruct.h
+++ b/src/atistruct.h
@@ -110,7 +110,7 @@ typedef struct _ATIHWRec
/* Mach64 CPIO registers */
CARD32 crtc_h_total_disp, crtc_h_sync_strt_wid,
crtc_v_total_disp, crtc_v_sync_strt_wid,
- crtc_off_pitch, crtc_gen_cntl, dsp_config, dsp_on_off,
+ crtc_off_pitch, crtc_gen_cntl, dsp_config, dsp_on_off, mem_buf_cntl,
ovr_clr, ovr_wid_left_right, ovr_wid_top_bottom,
cur_clr0, cur_clr1, cur_offset,
cur_horz_vert_posn, cur_horz_vert_off,
diff-tree 49b11c540d37152eee4907ab30353ede01e4fb56 (from 290c5aaa580428bc4748a47e4b9bcc22b90fc8d4)
Author: George Sapountzis <gsap7 at yahoo.gr>
Date: Sat Jul 29 00:52:28 2006 +0300
Bug #807: split out TestRegisterCaching block for DP regs.
diff --git a/src/atimach64accel.c b/src/atimach64accel.c
index 90fc28d..932c8c1 100644
--- a/src/atimach64accel.c
+++ b/src/atimach64accel.c
@@ -131,6 +131,7 @@ ATIMach64ValidateClip
}
static __inline__ void TestRegisterCachingDP(ScrnInfoPtr pScreenInfo);
+static __inline__ void TestRegisterCachingXV(ScrnInfoPtr pScreenInfo);
/*
* ATIMach64Sync --
@@ -221,58 +222,7 @@ ATIMach64Sync
TestRegisterCaching(CLR_CMP_CLR);
TestRegisterCaching(CLR_CMP_MSK);
- if (pATI->Block1Base)
- {
- TestRegisterCaching(OVERLAY_Y_X_START);
- TestRegisterCaching(OVERLAY_Y_X_END);
-
- TestRegisterCaching(OVERLAY_GRAPHICS_KEY_CLR);
- TestRegisterCaching(OVERLAY_GRAPHICS_KEY_MSK);
-
- TestRegisterCaching(OVERLAY_KEY_CNTL);
-
- TestRegisterCaching(OVERLAY_SCALE_INC);
- TestRegisterCaching(OVERLAY_SCALE_CNTL);
-
- TestRegisterCaching(SCALER_HEIGHT_WIDTH);
-
- TestRegisterCaching(SCALER_TEST);
-
- TestRegisterCaching(VIDEO_FORMAT);
-
- if (pATI->Chip < ATI_CHIP_264VTB)
- {
- TestRegisterCaching(BUF0_OFFSET);
- TestRegisterCaching(BUF0_PITCH);
- TestRegisterCaching(BUF1_OFFSET);
- TestRegisterCaching(BUF1_PITCH);
- }
- else
- {
- TestRegisterCaching(SCALER_BUF0_OFFSET);
- TestRegisterCaching(SCALER_BUF1_OFFSET);
- TestRegisterCaching(SCALER_BUF_PITCH);
-
- TestRegisterCaching(OVERLAY_EXCLUSIVE_HORZ);
- TestRegisterCaching(OVERLAY_EXCLUSIVE_VERT);
-
- if (pATI->Chip >= ATI_CHIP_264GTPRO)
- {
- TestRegisterCaching(SCALER_COLOUR_CNTL);
-
- TestRegisterCaching(SCALER_H_COEFF0);
- TestRegisterCaching(SCALER_H_COEFF1);
- TestRegisterCaching(SCALER_H_COEFF2);
- TestRegisterCaching(SCALER_H_COEFF3);
- TestRegisterCaching(SCALER_H_COEFF4);
-
- TestRegisterCaching(SCALER_BUF0_OFFSET_U);
- TestRegisterCaching(SCALER_BUF0_OFFSET_V);
- TestRegisterCaching(SCALER_BUF1_OFFSET_U);
- TestRegisterCaching(SCALER_BUF1_OFFSET_V);
- }
- }
- }
+ TestRegisterCachingXV(pScreenInfo);
}
pATI->NeedDRISync = FALSE;
@@ -291,58 +241,7 @@ ATIMach64Sync
*/
TestRegisterCachingDP(pScreenInfo);
- if (pATI->Block1Base)
- {
- TestRegisterCaching(OVERLAY_Y_X_START);
- TestRegisterCaching(OVERLAY_Y_X_END);
-
- TestRegisterCaching(OVERLAY_GRAPHICS_KEY_CLR);
- TestRegisterCaching(OVERLAY_GRAPHICS_KEY_MSK);
-
- TestRegisterCaching(OVERLAY_KEY_CNTL);
-
- TestRegisterCaching(OVERLAY_SCALE_INC);
- TestRegisterCaching(OVERLAY_SCALE_CNTL);
-
- TestRegisterCaching(SCALER_HEIGHT_WIDTH);
-
- TestRegisterCaching(SCALER_TEST);
-
- TestRegisterCaching(VIDEO_FORMAT);
-
- if (pATI->Chip < ATI_CHIP_264VTB)
- {
- TestRegisterCaching(BUF0_OFFSET);
- TestRegisterCaching(BUF0_PITCH);
- TestRegisterCaching(BUF1_OFFSET);
- TestRegisterCaching(BUF1_PITCH);
- }
- else
- {
- TestRegisterCaching(SCALER_BUF0_OFFSET);
- TestRegisterCaching(SCALER_BUF1_OFFSET);
- TestRegisterCaching(SCALER_BUF_PITCH);
-
- TestRegisterCaching(OVERLAY_EXCLUSIVE_HORZ);
- TestRegisterCaching(OVERLAY_EXCLUSIVE_VERT);
-
- if (pATI->Chip >= ATI_CHIP_264GTPRO)
- {
- TestRegisterCaching(SCALER_COLOUR_CNTL);
-
- TestRegisterCaching(SCALER_H_COEFF0);
- TestRegisterCaching(SCALER_H_COEFF1);
- TestRegisterCaching(SCALER_H_COEFF2);
- TestRegisterCaching(SCALER_H_COEFF3);
- TestRegisterCaching(SCALER_H_COEFF4);
-
- TestRegisterCaching(SCALER_BUF0_OFFSET_U);
- TestRegisterCaching(SCALER_BUF0_OFFSET_V);
- TestRegisterCaching(SCALER_BUF1_OFFSET_U);
- TestRegisterCaching(SCALER_BUF1_OFFSET_V);
- }
- }
- }
+ TestRegisterCachingXV(pScreenInfo);
}
}
@@ -399,6 +298,65 @@ TestRegisterCachingDP(ScrnInfoPtr pScree
TestRegisterCaching(CLR_CMP_CNTL);
}
+static __inline__ void
+TestRegisterCachingXV(ScrnInfoPtr pScreenInfo)
+{
+ ATIPtr pATI = ATIPTR(pScreenInfo);
+
+ if (!pATI->Block1Base)
+ return;
+
+ TestRegisterCaching(OVERLAY_Y_X_START);
+ TestRegisterCaching(OVERLAY_Y_X_END);
+
+ TestRegisterCaching(OVERLAY_GRAPHICS_KEY_CLR);
+ TestRegisterCaching(OVERLAY_GRAPHICS_KEY_MSK);
+
+ TestRegisterCaching(OVERLAY_KEY_CNTL);
+
+ TestRegisterCaching(OVERLAY_SCALE_INC);
+ TestRegisterCaching(OVERLAY_SCALE_CNTL);
+
+ TestRegisterCaching(SCALER_HEIGHT_WIDTH);
+
+ TestRegisterCaching(SCALER_TEST);
+
+ TestRegisterCaching(VIDEO_FORMAT);
+
+ if (pATI->Chip < ATI_CHIP_264VTB)
+ {
+ TestRegisterCaching(BUF0_OFFSET);
+ TestRegisterCaching(BUF0_PITCH);
+ TestRegisterCaching(BUF1_OFFSET);
+ TestRegisterCaching(BUF1_PITCH);
+
+ return;
+ }
+
+ TestRegisterCaching(SCALER_BUF0_OFFSET);
+ TestRegisterCaching(SCALER_BUF1_OFFSET);
+ TestRegisterCaching(SCALER_BUF_PITCH);
+
+ TestRegisterCaching(OVERLAY_EXCLUSIVE_HORZ);
+ TestRegisterCaching(OVERLAY_EXCLUSIVE_VERT);
+
+ if (pATI->Chip < ATI_CHIP_264GTPRO)
+ return;
+
+ TestRegisterCaching(SCALER_COLOUR_CNTL);
+
+ TestRegisterCaching(SCALER_H_COEFF0);
+ TestRegisterCaching(SCALER_H_COEFF1);
+ TestRegisterCaching(SCALER_H_COEFF2);
+ TestRegisterCaching(SCALER_H_COEFF3);
+ TestRegisterCaching(SCALER_H_COEFF4);
+
+ TestRegisterCaching(SCALER_BUF0_OFFSET_U);
+ TestRegisterCaching(SCALER_BUF0_OFFSET_V);
+ TestRegisterCaching(SCALER_BUF1_OFFSET_U);
+ TestRegisterCaching(SCALER_BUF1_OFFSET_V);
+}
+
/*
* ATIMach64SetupForScreenToScreenCopy --
*
diff-tree 290c5aaa580428bc4748a47e4b9bcc22b90fc8d4 (from fba8c839b47e2c8d6a6d65950c3431ff5b870aa0)
Author: George Sapountzis <gsap7 at yahoo.gr>
Date: Sat Jul 29 00:51:53 2006 +0300
Bug #807: split out TestRegisterCaching block for DP regs.
diff --git a/src/atimach64accel.c b/src/atimach64accel.c
index 1ecb13b..90fc28d 100644
--- a/src/atimach64accel.c
+++ b/src/atimach64accel.c
@@ -130,6 +130,8 @@ ATIMach64ValidateClip
}
}
+static __inline__ void TestRegisterCachingDP(ScrnInfoPtr pScreenInfo);
+
/*
* ATIMach64Sync --
*
@@ -287,40 +289,7 @@ ATIMach64Sync
* For debugging purposes, attempt to verify that each cached register
* should actually be cached.
*/
- TestRegisterCaching(SRC_CNTL);
-
- TestRegisterCaching(HOST_CNTL);
-
- TestRegisterCaching(PAT_REG0);
- TestRegisterCaching(PAT_REG1);
- TestRegisterCaching(PAT_CNTL);
-
- if (RegisterIsCached(SC_LEFT_RIGHT) && /* Special case */
- (CacheSlot(SC_LEFT_RIGHT) !=
- (SetWord(inm(SC_RIGHT), 1) | SetWord(inm(SC_LEFT), 0))))
- {
- UncacheRegister(SC_LEFT_RIGHT);
- xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
- "SC_LEFT_RIGHT write cache disabled!\n");
- }
-
- if (RegisterIsCached(SC_TOP_BOTTOM) && /* Special case */
- (CacheSlot(SC_TOP_BOTTOM) !=
- (SetWord(inm(SC_BOTTOM), 1) | SetWord(inm(SC_TOP), 0))))
- {
- UncacheRegister(SC_TOP_BOTTOM);
- xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
- "SC_TOP_BOTTOM write cache disabled!\n");
- }
-
- TestRegisterCaching(DP_BKGD_CLR);
- TestRegisterCaching(DP_FRGD_CLR);
- TestRegisterCaching(DP_WRITE_MASK);
- TestRegisterCaching(DP_MIX);
-
- TestRegisterCaching(CLR_CMP_CLR);
- TestRegisterCaching(CLR_CMP_MSK);
- TestRegisterCaching(CLR_CMP_CNTL);
+ TestRegisterCachingDP(pScreenInfo);
if (pATI->Block1Base)
{
@@ -389,6 +358,47 @@ ATIMach64Sync
pATI = *(volatile ATIPtr *)pATI->pMemory;
}
+static __inline__ void
+TestRegisterCachingDP(ScrnInfoPtr pScreenInfo)
+{
+ ATIPtr pATI = ATIPTR(pScreenInfo);
+
+ TestRegisterCaching(SRC_CNTL);
+
+ TestRegisterCaching(HOST_CNTL);
+
+ TestRegisterCaching(PAT_REG0);
+ TestRegisterCaching(PAT_REG1);
+ TestRegisterCaching(PAT_CNTL);
+
+ if (RegisterIsCached(SC_LEFT_RIGHT) && /* Special case */
+ (CacheSlot(SC_LEFT_RIGHT) !=
+ (SetWord(inm(SC_RIGHT), 1) | SetWord(inm(SC_LEFT), 0))))
+ {
+ UncacheRegister(SC_LEFT_RIGHT);
+ xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
+ "SC_LEFT_RIGHT write cache disabled!\n");
+ }
+
+ if (RegisterIsCached(SC_TOP_BOTTOM) && /* Special case */
+ (CacheSlot(SC_TOP_BOTTOM) !=
+ (SetWord(inm(SC_BOTTOM), 1) | SetWord(inm(SC_TOP), 0))))
+ {
+ UncacheRegister(SC_TOP_BOTTOM);
+ xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
+ "SC_TOP_BOTTOM write cache disabled!\n");
+ }
+
+ TestRegisterCaching(DP_BKGD_CLR);
+ TestRegisterCaching(DP_FRGD_CLR);
+ TestRegisterCaching(DP_WRITE_MASK);
+ TestRegisterCaching(DP_MIX);
+
+ TestRegisterCaching(CLR_CMP_CLR);
+ TestRegisterCaching(CLR_CMP_MSK);
+ TestRegisterCaching(CLR_CMP_CNTL);
+}
+
/*
* ATIMach64SetupForScreenToScreenCopy --
*
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