xf86-video-intel: Branch 'modesetting' - src/i830_display.c

[Dave Airlie]

 src/i830_display.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

New commits:
diff-tree 729c373121ce2bbb0d813cc923f1254e8b37a025 (from 0ba7b13fb4410c6a48b2fb098d2033e040eca6d2)
Author: Dave Airlie <airlied at linux.ie>
Date:   Thu Apr 20 13:34:55 2006 +1000

    move sdvo output setting
    
    we have to set the sdvo register a lot earlier in order for them to sync
    properly otherwise my monitor doesn't sync unfortunately, also
    disable the sdvo while tweaking the PLLs.
    
    This also comments out a setting that seems to break my system here for
    Eric to look at later.

diff --git a/src/i830_display.c b/src/i830_display.c
index 471b87e..95fa936 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -395,8 +395,9 @@ i830PipeSetMode(ScrnInfoPtr pScrn, Displ
 	sdvoc |= SDVO_ENABLE;
 	if (pipe == 1)
 	    sdvoc |= SDVO_PIPE_B_SELECT;
-	sdvoc |= SDVO_PHASE_SELECT_DEFAULT;
+	//	sdvoc |= SDVO_PHASE_SELECT_DEFAULT;
 	sdvoc |= SDVO_BORDER_ENABLE;
+	OUTREG(SDVOC, INREG(SDVOC) & ~SDVO_ENABLE);
     }
 
     fp = ((n - 2) << 16) | ((m1 - 2) << 8) | (m2 - 2);
@@ -464,6 +465,10 @@ i830PipeSetMode(ScrnInfoPtr pScrn, Displ
 
 	OUTREG(FPA0, fp);
 	OUTREG(DPLL_A, dpll);
+
+	if (is_sdvo)
+	  OUTREG(SDVOC, sdvoc);
+
 	OUTREG(HTOTAL_A, htot);
 	OUTREG(HBLANK_A, hblank);
 	OUTREG(HSYNC_A, hsync);
@@ -553,8 +558,6 @@ i830PipeSetMode(ScrnInfoPtr pScrn, Displ
 
     if (outputs & PIPE_CRT_ACTIVE)
 	OUTREG(ADPA, adpa);
-    if (is_sdvo)
-	OUTREG(SDVOC, sdvoc);
 
     return TRUE;
 }