xf86-video-intel: Branch 'modesetting' - 2 commits - src/i830_display.c

[Eric Anholt]

 src/i830_display.c |   95 ++---------------------------------------------------
 1 files changed, 4 insertions(+), 91 deletions(-)

New commits:
diff-tree a371a04a57620b7128e3c4395bc7c2ac55effe19 (from 33413a3cf34b06e3207fe1cdb733d586d55a4337)
Author: Eric Anholt <anholt at FreeBSD.org>
Date:   Mon Apr 17 14:10:50 2006 -0700

    Use the IS_I9XX macro intead of >= i915G, since by PCI ID number, 855GM > 915.

diff --git a/src/i830_display.c b/src/i830_display.c
index 0e3bb47..8eebfca 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -68,7 +68,7 @@ i830PllIsValid(ScrnInfoPtr pScrn, int ou
     int min_m1, max_m1, min_m2, max_m2, min_m, max_m, min_n, max_n;
     int min_p1, max_p1, min_p, max_p, min_vco, max_vco, min_dot, max_dot;
 
-    if (pI830->PciInfo->chipType >= PCI_CHIP_I915_G) {
+    if (IS_I9XX(pI830)) {
 	min_m1 = 10;
 	max_m1 = 20;
 	min_m2 = 5;
@@ -153,7 +153,7 @@ i830FindBestPLL(ScrnInfoPtr pScrn, int o
     int err = target;
     int min_m1, max_m1, min_m2, max_m2, min_n, max_n, min_p1, max_p1;
 
-    if (pI830->PciInfo->chipType >= PCI_CHIP_I915_G) {
+    if (IS_I9XX(pI830)) {
 	min_m1 = 10;
 	max_m1 = 20;
 	min_m2 = 5;
@@ -332,7 +332,7 @@ i830PipeSetMode(ScrnInfoPtr pScrn, Displ
 	pixel_clock = pI830->panel_fixed_clock;
     }
 
-    if (pI830->PciInfo->chipType >= PCI_CHIP_I915_G) {
+    if (IS_I9XX(pI830)) {
 	refclk = 96000;
     } else {
 	refclk = 48000;
@@ -346,7 +346,7 @@ i830PipeSetMode(ScrnInfoPtr pScrn, Displ
     }
 
     dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
-    if (pI830->PciInfo->chipType >= PCI_CHIP_I915_G) {
+    if (IS_I9XX(pI830)) {
 	if (outputs & PIPE_LCD_ACTIVE)
 	    dpll |= DPLLB_MODE_LVDS;
 	else
diff-tree 33413a3cf34b06e3207fe1cdb733d586d55a4337 (from 365b4a53ee965002a5452e6f6016b528e51cee69)
Author: Eric Anholt <anholt at FreeBSD.org>
Date:   Mon Apr 17 13:42:57 2006 -0700

    Remove some dead code and one particularly useless debug printf.

diff --git a/src/i830_display.c b/src/i830_display.c
index 4cdc2b1..0e3bb47 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -139,81 +139,6 @@ i830PllIsValid(ScrnInfoPtr pScrn, int ou
     return TRUE;
 }
 
-#if 0
-int
-i830ReadAndReportPLL(ScrnInfoPtr pScrn)
-{
-    I830Ptr pI830 = I830PTR(pScrn);
-    CARD32 temp, dpll;
-    int refclk, m1, m2, n, p1, p2;
-
-    refclk = 96000;	/* XXX: The refclk may be 100000 for the LVDS */
-
-    dpll = INREG(DPLL_A);
-    switch ((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 16) {
-    case 0x01:
-	p1 = 1;
-	break;
-    case 0x02:
-	p1 = 2;
-	break;
-    case 0x04:
-	p1 = 3;
-	break;
-    case 0x08:
-	p1 = 4;
-	break;
-    case 0x10:
-	p1 = 5;
-	break;
-    case 0x20:
-	p1 = 6;
-	break;
-    case 0x40:
-	p1 = 7;
-	break;
-    case 0x80:
-	p1 = 8;
-	break;
-    default:
-	FatalError("Unknown p1 clock div: 0x%x\n",
-		   dpll & DPLL_FPA01_P1_POST_DIV_MASK);
-    }
-
-    switch (dpll & DPLL_P2_CLOCK_DIV_MASK) {
-    case DPLL_DAC_SERIAL_P2_CLOCK_DIV_5:
-	p2 = 5;
-	break;
-    case DPLL_DAC_SERIAL_P2_CLOCK_DIV_10:
-	p2 = 10;
-	break;
-/* XXX:
-    case DPLLB_LVDS_P2_CLOCK_DIV_7:
-	p2 = 7;
-	break;
-    case DPLLB_LVDS_P2_CLOCK_DIV_14:
-	p2 = 14;
-	break;
-*/
-    default:
-	FatalError("Unknown p2 clock div: 0x%x\n", dpll & DPLL_P2_CLOCK_DIV_MASK);
-    }
-
-    if (dpll & DISPLAY_RATE_SELECT_FPA1)
-	temp = INREG(FPA1);
-    else
-	temp = INREG(FPA0);
-    n = (temp & FP_N_DIV_MASK) >> 16;
-    m1 = (temp & FP_M1_DIV_MASK) >> 8;
-    m2 = (temp & FP_M2_DIV_MASK);
-
-    i830PrintPll("FPA", refclk, m1, m2, n, p1, p2);
-    ErrorF("clock settings for FPA0 look %s\n",
-	   i830PllIsValid(refclk, m1, m2, n, p1, p2) ? "good" : "bad");
-    ErrorF("clock regs: 0x%08x, 0x%08x\n", dpll, temp);    
-}
-#endif
-
 /**
  * Returns a set of divisors for the desired target clock with the given refclk,
  * or FALSE.  Divisor values are the actual divisors for
@@ -466,19 +391,7 @@ i830PipeSetMode(ScrnInfoPtr pScrn, Displ
 	(int)(vsync & 0xffff) + 1, (int)(vsync >> 16) + 1);
 #endif
 
-    adpa = INREG(ADPA);
-    adpa &= ~(ADPA_HSYNC_ACTIVE_HIGH | ADPA_VSYNC_ACTIVE_HIGH);
-    adpa &= ~(ADPA_VSYNC_CNTL_DISABLE | ADPA_HSYNC_CNTL_DISABLE);
-    adpa |= ADPA_DAC_ENABLE;
-    if (pMode->Flags & V_PHSYNC)
-	adpa |= ADPA_HSYNC_ACTIVE_HIGH;
-    if (pMode->Flags & V_PVSYNC)
-	adpa |= ADPA_VSYNC_ACTIVE_HIGH;
-
     i830PrintPll("chosen", refclk, m1, m2, n, p1, p2);
-    ErrorF("clock settings for chosen look %s\n",
-	   i830PllIsValid(pScrn, outputs, refclk, m1, m2, n, p1, p2) ?
-			  "good" : "bad");
     ErrorF("clock regs: 0x%08x, 0x%08x\n", (int)dpll, (int)fp);
 
     dspcntr = DISPLAY_PLANE_ENABLE;