[ANNOUNCE] xf86-video-intel 2.99.910

Chris Wilson chris at chris-wilson.co.uk
Mon Feb 10 10:42:30 CET 2014

Snapshot 2.99.910 (2013-02-10)
Another latent bug exposed by recent changes merit another snapshot for
final testing.

  * Only discard damage when overwriting the dirty CPU bo, instead
    of discarding damage that will be shown!

  * Reset operation state when switching between glyph caches.

  * Fully reinitialise pixmaps allocated from the freed cache. Fixes
    a potential issue (crash or misrendering) when using some compositors.

  * Do not expose the TexturedVideo adaptor in UXA when it is disabled
    either due to a hung GPU or explicitly disabled by the user.

  * Restore the pipe stall when changing CC state on gen6, otherwise
    the GPU may not flush intermediate results from all EU resulting
    in render corruption (usually the occasional black box).
    Regression from 2.99.906

Complete list of changes since 2.99.910

Chris Wilson (18):
      sna: Undo region translation before returning
      sna: Allow more inplace promotions of CPU to GPU bo
      sna: Skip discarding CPU bo when using as a render target
      sna: Add some more DBG for choosing render targets
      sna: If IGNORE_CPU is not set we must mark the move as MOVE_READ
      sna: Reconstruct damage for the partially replaced discarded CPU bo
      sna/glyphs: Reset composite state between switching glyph formats
      sna/gen4: Disable use of pipecontrol invalidates again
      sna: Rearrange assertion to ease use of substitute cached bo
      sna: Tweak assert_bo_retired() to be callable on cached bo
      sna: Pass read hints from move-to-cpu to wait_for_shadow
      sna: Add some DBG around tiled blts
      sna: Reset composite offsets when reusing freed pixmaps
      sna: Add some DBG to clarify the source pixmap (for tiles)
      uxa: Do not expose TextureVideo Xv adapters when acceleration is disabled
      sna: And clear drawable->id on reused pixmaps
      sna/gen6: Restore stall dropped when not flushing instead
      2.99.910 snapshot

Edward Sheldrake (1):
      sna/gen4,5: Fix setting pipe control cache flush bits

git tag: 2.99.910

MD5:  a9a5c2c15766c06a024381efe0d724bb  xf86-video-intel-2.99.910.tar.bz2
SHA1: 23afc1ffc275a4114461fbf354b33d2287cc57a3  xf86-video-intel-2.99.910.tar.bz2
SHA256: 203d46064449da0e23a111418dfb189422ba96ea08707167c8dee463e2d745b1  xf86-video-intel-2.99.910.tar.bz2

MD5:  1486dfcd4eda31a9c72ec70bbc0cd041  xf86-video-intel-2.99.910.tar.gz
SHA1: 16272838d4a67b5bc88fcaf113db25b946933eaa  xf86-video-intel-2.99.910.tar.gz
SHA256: 7c2dba447c1bf4acb4ec6dcdbc0821a3434ca3cc4869bdbe9f5e96e39a781a19  xf86-video-intel-2.99.910.tar.gz

Chris Wilson, Intel Open Source Technology Centre
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