[ANNOUNCE] xf86-video-intel 2.21.7

Chris Wilson chris at chris-wilson.co.uk
Tue May 21 03:07:53 PDT 2013

Release 2.21.7 (2013-05-21)
A couple of weeks turned into a month and a couple of weeks... Amidst
the usual bug fixes, we have added the complete set of Haswell PCI IDs -
hopefully future proofing ourselves against being surprised by new
products. We can also now use the correct term for the top of the range
Haswell variants, GT3.

 * Fix several assertion failures hit by Jiri Slaby.

 * Allow XvMC to also target overlay/sprite planes.

 * Throw in a paranoid MI_FLUSH between BLT and RENDER operations on

 * Prevent reuse of old framebuffers after a resize.

 * Fix compilation with --enable-valgrind and no --enable-debug

 * Improve partial migration of render sources.

 * Fix origin of trapezoids.

 * Introduce copy-on-write support for cloning pixmaps. The ultimate
   goal here is to efficiently support the TearFree mode of operation,
   but this provides immediate benefits with firefox - most importantly
   because of the inefficient way it now implements scrolling.

Complete list of changes since 2.21.6

Chris Wilson (47):
      sna: Remove assertions for mapped GPU bo if priv->cpu after GPU bo creation
      sna/video: Expand passthrough support for overlay planes
      sna/video: Textured video passthrough no longer relies upon XvMC
      sna: Document fence limits for gen4+
      sna: Add a DBG option for testing userptr more thoroughly
      sna: Suppress hotplug events whilst VT switched away
      sna/xvmc: Wrap each output adaptor
      sna: Align uploads to start on page boundaries
      sna/gen7: Cache our kernels in L3
      sna: Refine assertion about the existence of CPU damage when GPU damaged
      sna/gen5: Force a MI_FLUSH between using the BLT and RENDER engines
      sna: Flush the scanout cache after resizing the display
      sna: Add missing ';'
      sna/xvmc: silence a compiler warning
      sna: Only release the scanout cache whilst DRM_MASTER
      sna: Add VALGRIND_CFLAGS whilst compiling with --enable-valgrind
      Prefer i830_dri.so for gen2 chipsets
      Revert "xgvevent"
      sna: Rephrase initialisation without a specific backend
      sna: Prevent accessing an uninitialised region in move_area_to_gpu()
      uxa/dri: Fix compile error for unknown 'bool'
      Add all reserved PCI-IDs for Haswell
      sna: Page align requests to userptr
      sna: Be careful not to preemptively upload portions of a SHM pixmap
      sna: Do not attempt to clean an active scanout
      sna: Handle cached upload buffers for partial migration to GPU
      sna: Add DBG statements for choice of spans vertex emitter
      sna/gen7: Add DBG for channel setup for render source
      sna: Add more debugging to unaligned trapezoids
      sna/trapezoids: Fix the determination of the trapezoid origin
      sna/gen4: Drop unused gen parameter to SF state setup
      sna/gen4: Tidy testing for an active vertex buffer id
      sna: Attempt to discard overwritten operations before CopyArea
      sna: Propagate clear color when replacing by a CopyArea
      sna: Propagate clears when using the BLT composite routines
      sna: Basic copy-on-write support for cloning pixmaps
      sna: Assert that the mapping is released before closing the GEM handle
      sna: Correct assertions to allow discarding of cpu hint for inplace ops
      sna: Clear mapped hints upon cloning a pair of pixmaps
      sna: Avoid replacing pinned bo when undoing a clone
      sna: Transfer ownership of the cloned bo to the pixmaps
      sna: Undo the clone when replacing the DRI pixmap
      sna: Add the missing ref(bo) when undoing the source clone
      sna: Clear the cow_list when discarding the clone upon pixmap destroy
      sna: Undo a few more overwritten operations upon a bo
      2.21.7 release

Rodrigo Vivi (2):
      Fix Haswell GT3 names.
      Adding more reserved PCI IDs for Haswell.

git tag: 2.21.7

MD5:  c3a8b542fc4787ad17a5f0567a3429fd  xf86-video-intel-2.21.7.tar.bz2
SHA1: 40dfeddc4828ad24d272cc69112202c71855dcdf  xf86-video-intel-2.21.7.tar.bz2
SHA256: faeabba40079c49290f39992542d9b0cfd229bda4e389e1352926903038363d9  xf86-video-intel-2.21.7.tar.bz2

MD5:  437101f023fe23fdd9e65881410ffaaf  xf86-video-intel-2.21.7.tar.gz
SHA1: 6e105fd5b66fbdd2ca9cd576a0f5a16d541a59c2  xf86-video-intel-2.21.7.tar.gz
SHA256: 777d3e0a4c88b065f0b033b405fc67e7f5002fa374eddeedd96f0454d569ed56  xf86-video-intel-2.21.7.tar.gz

Chris Wilson, Intel Open Source Technology Centre
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