[ANNOUNCE] xf86-video-intel 2.20.12

Chris Wilson chris at chris-wilson.co.uk
Sat Oct 20 08:32:48 PDT 2012

More bug reports, more bug fixes! Perhaps the headline feature is
that with secure batches, coming to a 3.8 kernel near you, we may
finally have the ability to perform updates to the scanout synchronized
to the refresh rate on later SandyBridge and IvyBridge chipsets. It comes
at quite a power cost as we need to keep the GPU out of its power saving
modes, but it should allow legacy vsync to function at last. But this
should allow us to address a longstanding issue with tearing on

 * Fix component-alpha rendering on IvyBridge, for example subpixel
   antialiased glyphs.

 * Flush before some "pipelined" state changes on gen4. The evidence is
   that the same flushes as required on gen5+ are also required for gen4.

 * Prevent a potential crash when forcing a stall on a busy CPU bo

[Release 2.20.11 contained a typo causing UXA to fail immediately.]

Chris Wilson (14):
      sna: Drop fake tiled CPU mapping
      sna/gen7: Filter BLEND flags for CA glyphs
      sna/dri: Defensively check for GTT mmap failure during fallback
      sna: Enable support for SECURE batch buffers
      sna: Use the secure batches to program scanline waits on gen6+
      sna/overlay: Move bo out of GTT domain after binding to overlay plane
      sna: secure batches accepted upstream, so simply use runtime detection
      sna/gen4: Presume we need a flush upon state change similar to gen5+
      sna: Reorder final checks for using the BO and setting the damage pointer
      sna: Clear the damage along with the BO when forcing the stall for inplace BLT
      uxa: Disable bo reuse after binding to a scanout
      2.20.11 release
      uxa: Fixup drm_intel_bo_disable_reuse() typo
      2.20.12 release

git tag: 2.20.12

MD5:  6d9565de03c167d8f621315476c20c73  xf86-video-intel-2.20.12.tar.bz2
SHA1: 472e7b1a9bf299089bb7fbfbb3d37d1ee6b20db6  xf86-video-intel-2.20.12.tar.bz2
SHA256: 39e02b7f90a2665efe5483075f93b1c87d24f48070d5de783dd41e20d9eb0c7c  xf86-video-intel-2.20.12.tar.bz2

MD5:  fd4e13711d8098d8dcf41b07eeb16572  xf86-video-intel-2.20.12.tar.gz
SHA1: aa4580712775041224ed3ecd191ae5283230371a  xf86-video-intel-2.20.12.tar.gz
SHA256: b4eb1b6d4aecc0d6306ad21530c57d3e6e19e8220efa351e16a8985f2afdb28a  xf86-video-intel-2.20.12.tar.gz

Chris Wilson, Intel Open Source Technology Centre
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