[ANNOUNCE] xf86-video-intel 1.6.4

Eric Anholt eric at anholt.net
Wed Aug 9 13:31:11 PDT 2006

New release providing i965 support.

git tag x86-video-intel-1.6.4


SHA1 (xf86-video-i810-1.6.4.tar.bz2) = 3b2e2c591139019bb942aacb5001e13c1b45c860
SHA1 (xf86-video-i810-1.6.4.tar.gz) = 5b79a9373cf864905475514025bf2f0834b0ab82
MD5 (xf86-video-i810-1.6.4.tar.bz2) = 56e24a79cccb1d3828de48cb9a7a61b6
MD5 (xf86-video-i810-1.6.4.tar.gz) = ff1f4c3ea5504cc52d1886fd3b793d4f

Changes since xf86-video-intel-1.6.3:
Alan Hourihane:
      Add current Tungsten Graphics code drop for i965 support.
      Intel bug #35: Fix accelerator syncing with DGA.

Eric Anholt:
      First pass of integrating the Tungsten Graphics driver for Broadwater.  This
      Re-add authorship note in i830_driver.c accidentally left out of last commit.
      Start fixing up the build and remove a regression from master (I think) in
      Revert internal shadow module changes back like master, along with RandR
      Make the intel_acpi.c code non-modular and make it compile.  I think we'll end
      Remove intel_randr.c and stick with the previous code.  Broadwater shouldn't be
      Do a couple of reverts to get the DRI code building.  At this point, the whole
      Remove the code that changes our behavior based on whether a magic file exists
      Remove the local, renamed copy of lnx_agp.c.  The diff between lnx_agp.c and it
      Convert magic numbers in i915 rotation 3D state to symbolic names.
      Add initial textured XV support for i915, which can do YUY2 and UYVY, but fails
      More magic number reduction in rotation code.
      Commit a WIP implementation of the planar video shader that does the
      Add a couple of macros to simplify writing of video pixel shaders.
      Do a separate BEGIN/ADVANCE_LP_RING set in the planar vs packed blocks, so I
      Experimental work to use a full pixel shader for planar to YUV conversion, which
      Merge textured-video-wip to textured-video-planar-full.
      Divide width by 2 in planar-to-packed conversion loop, since each pass through
      Fix the planar formats to display correctly in textured mode. Still has issues
      Correct drawing issues with planar formats when top or left != 0, and Y didn't
      Enable overlay and/or textured video at runtime according to hardware
      Relax the alignment requirements for textured video.
      For textured video, disable double buffering and sync before uploading new video
      Use linear min/mag blending.
      Turn debugging back off.
      Flag the 3D state as dirty when we draw textured video, which should help
      Merge branch 'textured-video' into broadwater-video
      Turn off overlay video on BW until we have stable PCI IDs so we can know whether
      Start laying out some of the bits that need to be done for BW textured video.
      Checkpoint of BW textured video work, filling out vertex submission stuff and
      Checkpoint for filling out more 3D state.
      Set up the state buffer in framebuffer.
      Put in code for idling accelerator on subsequent cliprects.
      Replace SF kernel with the one from broadwater-video HEAD.
      Move the WM kernel to a separate file.
      Updated grf/urb state for WM.
      Updated WM kernel to load video and do colorspace conversion.
      Allocate space for the 965's state at the end of the video buffer.
      Fix wm prog to correct the ordering of the Cr and Cb channels.
      Remove the VS kernel and binding table.
      Reduce URB_VS_ENTRY_SIZE to 1 as our vertices are under 8 floats.
      No GS URB allocation is necessary when the function is disabled.
      We only need 3 vertices to fit in the URB, since we only dispatch 3.
      Remove CS URB allocation since we don't use any constants.
      Replace the SF max threads setting with a define for easier tweaking.
      Correct the VS setup, and allocate a correct, minimal number of URB entries.
      Remove the clip URB allocation.
      Crank down the SF allocation and comment on why this is a fine lower limit.
      Clean up GRF allocation (which was wrong at 16-register boundaries).
      Set the WM scratch space that we had already allocated.
      Remove some stale XXX-prefixed comments.
      Make the sampler's payload be the WM payload rather than uninitialized data.
      Bump PS_MAX_THREADS to 32 now that the program doesn't fail.
      Merge branch 'broadwater-video-rehash' into broadwater
      Merge branch 'broadwater-video-rehash' into i965
      Turn off video debugging now that it appears to work fine.
      Add parenthesis so that IS_I965G doesn't make the test pass for 8-bit.
      Disable dynamic front buffer mapping on i965.
      Intel bug #49: Fix video output at 32bpp by using B8G8R8A8 instead of B8G8R8X8.
      Merge branch 'i965', adding i965G support.
      Update the README.sgml file for the upcoming release.
      Bump to 1.6.4 for release.

Keith his master's voice Packard:
      Scale video source vertices. Allocate space for kernels
      Prepare real SF kernel and fake WM kernel
      Use broadwater video code on broadwater hardware. Pad ring to even length. compute state base as address rather than offset
      Rename BRW instructions, check video instruction generation. Doesnt lock up, but doesnt display anything either
      flesh out cc state. set cull mode to none. enable sf kernel
      Push all of the obvious Mesa state setting into the video code
      dump out piles of debug. Create VS thread just to see how it works
      Lots more debug code. Appears to execute pixel shader thread now though. hurray!
      Using tiny rectangle, still locks up in pixel shader program somehow
      Ok, finally something sensible up on the screen.
      Nice texture coordinate gradient, broken slightly in y

Keith Packard:
      Update manual page to include i945 and later details.
      Reformat README
      Use double quotes to avoid sgml syntax error
      Add missing headers to i810_drv_la_SOURCES

Wang Zhenyu:
      Disable error register dumping in dri TransitionTo2d. This's for

Eric Anholt                             anholt at FreeBSD.org
eric at anholt.net                         eric.anholt at intel.com
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