[Mesa-dev] [PATCH] intel/blorp: Support blits and clears on surfaces with offsets
Kenneth Graunke
kenneth at whitecape.org
Fri May 25 19:53:13 UTC 2018
On Friday, May 25, 2018 12:31:03 PM PDT Jason Ekstrand wrote:
> For certain EGLImage cases, we represent a single slice or LOD of an
> image with a byte offset to a tile and X/Y intratile offsets to the
> given slice. Most of i965 is fine with this but it breaks blorp. This
> is a terrible way to represent slices of a surface in EGL and we should
> stop some day but that's a very scary and thorny path. This gets blorp
> to start working with those surfaces and fixes some dEQP EGL test bugs.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629
> Cc: mesa-stable at lists.freedesktop.org
> ---
> src/intel/blorp/blorp.c | 22 ++++++++++++++++++++++
> src/intel/blorp/blorp.h | 3 +++
> src/intel/blorp/blorp_blit.c | 4 +++-
> src/intel/blorp/blorp_clear.c | 9 +++++++++
> src/mesa/drivers/dri/i965/brw_blorp.c | 2 ++
> 5 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
> index e348caf..73f8c67 100644
> --- a/src/intel/blorp/blorp.c
> +++ b/src/intel/blorp/blorp.c
> @@ -137,6 +137,28 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
> */
> if (is_render_target && blorp->isl_dev->info->gen <= 6)
> info->view.array_len = MIN2(info->view.array_len, 512);
> +
> + if (surf->tile_x_sa || surf->tile_y_sa) {
> + /* This is only allowed on simple 2D surfaces without MSAA */
> + assert(info->surf.dim == ISL_SURF_DIM_2D);
> + assert(info->surf.samples == 1);
> + assert(info->surf.levels == 1);
> + assert(info->surf.logical_level0_px.array_len == 1);
> + assert(info->aux_usage == ISL_AUX_USAGE_NONE);
> +
> + info->tile_x_sa = surf->tile_x_sa;
> + info->tile_y_sa = surf->tile_y_sa;
> +
> + /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
> + * place the image at the tile boundary and offset our sampling or
> + * rendering. For this reason, we need to grow the image by the offset
> + * to ensure that the hardware doesn't think we've gone past the edge.
> + */
> + info->surf.logical_level0_px.w += surf->tile_x_sa;
> + info->surf.logical_level0_px.h += surf->tile_y_sa;
> + info->surf.phys_level0_sa.w += surf->tile_x_sa;
> + info->surf.phys_level0_sa.h += surf->tile_y_sa;
> + }
> }
>
>
> diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
> index f22110b..0a10ff9 100644
> --- a/src/intel/blorp/blorp.h
> +++ b/src/intel/blorp/blorp.h
> @@ -114,6 +114,9 @@ struct blorp_surf
> * that it contains a swizzle of RGBA and resource min LOD of 0.
> */
> struct blorp_address clear_color_addr;
> +
> + /* Only allowed for simple 2D non-MSAA surfaces */
> + uint32_t tile_x_sa, tile_y_sa;
> };
>
> void
> diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
> index 67d4266..68e6d4e 100644
> --- a/src/intel/blorp/blorp_blit.c
> +++ b/src/intel/blorp/blorp_blit.c
> @@ -2510,7 +2510,9 @@ blorp_copy(struct blorp_batch *batch,
> dst_layer, ISL_FORMAT_UNSUPPORTED, true);
>
> struct brw_blorp_blit_prog_key wm_prog_key = {
> - .shader_type = BLORP_SHADER_TYPE_BLIT
> + .shader_type = BLORP_SHADER_TYPE_BLIT,
> + .need_src_offset = src_surf->tile_x_sa || src_surf->tile_y_sa,
> + .need_dst_offset = dst_surf->tile_x_sa || dst_surf->tile_y_sa,
> };
>
> const struct isl_format_layout *src_fmtl =
> diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
> index 832e8ee..4d3125a 100644
> --- a/src/intel/blorp/blorp_clear.c
> +++ b/src/intel/blorp/blorp_clear.c
> @@ -438,6 +438,15 @@ blorp_clear(struct blorp_batch *batch,
> params.x1 = x1;
> params.y1 = y1;
>
> + if (params.dst.tile_x_sa || params.dst.tile_y_sa) {
> + assert(params.dst.surf.samples == 1);
> + assert(num_layers == 1);
> + params.x0 += params.dst.tile_x_sa;
> + params.y0 += params.dst.tile_y_sa;
> + params.x1 += params.dst.tile_x_sa;
> + params.y1 += params.dst.tile_y_sa;
> + }
> +
> /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
> * Convert them to a single slice on gen4.
> */
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
> index d7a2cb2..8c6d77e 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -152,6 +152,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
> .mocs = brw_get_bo_mocs(devinfo, mt->bo),
> },
> .aux_usage = aux_usage,
> + .tile_x_sa = mt->level[*level].level_x,
> + .tile_y_sa = mt->level[*level].level_y,
> };
>
> if (mt->format == MESA_FORMAT_S_UINT8 && is_render_target &&
>
Hopefully we don't run afoul of surface width/height limits. Probably
won't, hard to imagine offsetting into something that's already max
dimensions...
Strange that this only happens on Gen6-8 and not Gen9+. I wonder what
changed?
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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