[Mesa-dev] [PATCH 22/53] intel/fs: Disable SIMD32 dispatch on Gen4-6 with control flow
Jason Ekstrand
jason at jlekstrand.net
Thu May 24 21:56:04 UTC 2018
From: Francisco Jerez <currojerez at riseup.net>
The hardware's control flow logic is 16-wide so we're out of luck
here. We could, in theory, support SIMD32 if we know the control-flow
is uniform but we don't have that information at this point.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
---
src/intel/compiler/brw_fs_nir.cpp | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index e287f11..1168365 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -385,6 +385,10 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
nir_emit_cf_list(&if_stmt->else_list);
bld.emit(BRW_OPCODE_ENDIF);
+
+ if (devinfo->gen < 7)
+ limit_dispatch_width(16, "Non-uniform control flow unsupported "
+ "in SIMD32 mode.");
}
void
@@ -395,6 +399,10 @@ fs_visitor::nir_emit_loop(nir_loop *loop)
nir_emit_cf_list(&loop->body);
bld.emit(BRW_OPCODE_WHILE);
+
+ if (devinfo->gen < 7)
+ limit_dispatch_width(16, "Non-uniform control flow unsupported "
+ "in SIMD32 mode.");
}
void
--
2.5.0.400.gff86faf
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