[Mesa-dev] [PATCH 33/47] (0032b) Fixes to compile

[Shaofeng Tang]

From: Kevin Rogovin <kevin.rogovin at intel.com>

Change-Id: Ifff2bb9d7daa0243af532baefafa29a10c679ea1
---
 Notes.txt                     | 3 +++
 src/intel/compiler/brw_fs.cpp | 6 +++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/Notes.txt b/Notes.txt
index 8be39d9..1142bf7 100644
--- a/Notes.txt
+++ b/Notes.txt
@@ -7,3 +7,6 @@ Patch 0011 i965/eu: Emit JMPI with exec_size 1 already applied in Mesa-master
 Patch 0018 i965/fs: Rework FB write header setup for SIMD32 and better scheduling.
    Needed to change allocate_registers(false) to allocate_registers(16, false)
    in fs_generator::emit_repclear_shader()
+
+Patch 0032 965/fs: Implement 32-wide FS payload setup on Gen6+.
+   Needed to change nir->info->XXX to nir->info.XXX in fs_vistor::setup_fs_payload_gen6().
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 612f674..5f35a58 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6033,10 +6033,10 @@ fs_visitor::setup_fs_payload_gen6()
    assert(devinfo->gen >= 6);
 
    prog_data->uses_src_depth = prog_data->uses_src_w =
-      (nir->info->inputs_read & (1 << VARYING_SLOT_POS)) != 0;
+      (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
 
    prog_data->uses_sample_mask =
-      (nir->info->system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0;
+      (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0;
 
    /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
     *
@@ -6048,7 +6048,7 @@ fs_visitor::setup_fs_payload_gen6()
     * persample dispatch, we hard-code it to 0.5.
     */
    prog_data->uses_pos_offset = prog_data->persample_dispatch &&
-      (nir->info->system_values_read & SYSTEM_BIT_SAMPLE_POS);
+      (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
 
    /* R0: PS thread payload header. */
    payload.num_regs++;
-- 
2.7.4