[Mesa-dev] [PATCH] ac/nir: expand 64-bit vec3 loads to fix shuffling.
Samuel Pitoiset
samuel.pitoiset at gmail.com
Mon Apr 30 07:33:41 UTC 2018
On 04/30/2018 04:47 AM, Dave Airlie wrote:
> From: Dave Airlie <airlied at redhat.com>
>
> If loading 64-bit vec3 values, a 4 component load would be followed
> by a 2 component load and the resulting shuffle would fail as it
> requires 2 4 components. This just expands the second results
> vector out to 4 components.
>
> This fixes 100 CTS tests:
> dEQP-VK.spirv_assembly.type.vec3.*64*
I wasn't aware of these fails. What chip?
They don't fail on polaris and vega here.
> ---
> src/amd/common/ac_nir_to_llvm.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index e4ae6ef49ad..b77d62a39b0 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -1572,6 +1572,11 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
> LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
> };
>
> + if (num_components == 6) {
> + /* we end up with a v4f32 and v2f32 but shuffle fails on that */
> + results[1] = ac_build_expand_to_vec4(&ctx->ac, results[1], 4);
> + }
> +
> LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
> ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
> results[num_components > 4 ? 1 : 0], swizzle, "");
>
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