[Mesa-dev] [PATCH 09/10] gallium: add PIPE_CAP_TRANSFER_USER_STRIDE_ALIGNMENT

[Marek Olšák]

On Thu, Apr 26, 2018 at 6:27 AM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:

> On 25.04.2018 23:29, Roland Scheidegger wrote:
>
>> Am 25.04.2018 um 23:16 schrieb Marek Olšák:
>>
>>> From: Marek Olšák <marek.olsak at amd.com>
>>>
>>> ---
>>>   src/gallium/docs/source/screen.rst               | 3 +++
>>>   src/gallium/drivers/etnaviv/etnaviv_screen.c     | 1 +
>>>   src/gallium/drivers/freedreno/freedreno_screen.c | 1 +
>>>   src/gallium/drivers/i915/i915_screen.c           | 1 +
>>>   src/gallium/drivers/llvmpipe/lp_screen.c         | 1 +
>>>   src/gallium/drivers/nouveau/nv30/nv30_screen.c   | 1 +
>>>   src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 1 +
>>>   src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 1 +
>>>   src/gallium/drivers/r300/r300_screen.c           | 1 +
>>>   src/gallium/drivers/r600/r600_pipe.c             | 1 +
>>>   src/gallium/drivers/radeonsi/si_get.c            | 3 +++
>>>   src/gallium/drivers/softpipe/sp_screen.c         | 1 +
>>>   src/gallium/drivers/svga/svga_screen.c           | 1 +
>>>   src/gallium/drivers/swr/swr_screen.cpp           | 1 +
>>>   src/gallium/drivers/vc4/vc4_screen.c             | 1 +
>>>   src/gallium/drivers/vc5/vc5_screen.c             | 1 +
>>>   src/gallium/drivers/virgl/virgl_screen.c         | 1 +
>>>   src/gallium/include/pipe/p_defines.h             | 1 +
>>>   18 files changed, 22 insertions(+)
>>>
>>> diff --git a/src/gallium/docs/source/screen.rst
>>> b/src/gallium/docs/source/screen.rst
>>> index 3837360fb40..7cc6d378306 100644
>>> --- a/src/gallium/docs/source/screen.rst
>>> +++ b/src/gallium/docs/source/screen.rst
>>> @@ -413,20 +413,23 @@ The integer capabilities:
>>>     supported priority levels.  A driver that does not support
>>> prioritized
>>>     contexts can return 0.
>>>   * ``PIPE_CAP_FENCE_SIGNAL``: True if the driver supports signaling
>>> semaphores
>>>     using fence_server_signal().
>>>   * ``PIPE_CAP_CONSTBUF0_FLAGS``: The bits of pipe_resource::flags that
>>> must be
>>>     set when binding that buffer as constant buffer 0. If the buffer
>>> doesn't have
>>>     those bits set, pipe_context::set_constant_buffer(.., 0, ..) is
>>> ignored
>>>     by the driver, and the driver can throw assertion failures.
>>>   * ``PIPE_CAP_PACKED_UNIFORMS``: True if the driver supports packed
>>> uniforms
>>>     as opposed to padding to vec4s.
>>> +* ``PIPE_CAP_TRANSFER_USER_STRIDE_ALIGNMENT``: The minimum supported
>>> alignment of
>>> +  the user_stride parameter of transfer_map. If 0, the user-specified
>>> stride
>>> +  is unsupported and the user_stride parameter is ignored.
>>>
>> Does this really make a whole lot of sense? What if the minimum stride
>> natively supported isn't always the same? What happens if the stride
>> requested is larger than what the hw usually would do, does that need to
>> be honored as well - it certainly looks like the cap query here wouldn't
>> answer that?
>>
>
> It really doesn't make much sense, but unfortunately the ChromeOS gralloc
> is just completely braindead. It basically assumes that tilings don't
> exist. You have to give it a stride when a texture is allocated, and that
> is the stride that has to be there whenever the texture is mapped for a
> transfer.
>
So we give it the right stride at allocation: aligned to 64 or 256.

Marek
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