[Mesa-dev] [PATCH 08/11] intel/compiler: fix brw_negate_immediate for 16-bit types
Chema Casanova
jmcasanova at igalia.com
Thu Apr 26 12:36:42 UTC 2018
El 24/04/18 a las 23:55, Jason Ekstrand escribió:
> On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga <itoral at igalia.com
> <mailto:itoral at igalia.com>> wrote:
>
> From: Jose Maria Casanova Crespo <jmcasanova at igalia.com
> <mailto:jmcasanova at igalia.com>>
>
> 16-bit immediates are replicated in each word of a 32-bit value
> so we need to negate both.
> ---
> src/intel/compiler/brw_shader.cpp | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/src/intel/compiler/brw_shader.cpp
> b/src/intel/compiler/brw_shader.cpp
> index 9cdf9fcb23d..c7edc60b63d 100644
> --- a/src/intel/compiler/brw_shader.cpp
> +++ b/src/intel/compiler/brw_shader.cpp
> @@ -581,7 +581,8 @@ brw_negate_immediate(enum brw_reg_type type,
> struct brw_reg *reg)
> return true;
> case BRW_REGISTER_TYPE_W:
> case BRW_REGISTER_TYPE_UW:
> - reg->d = -(int16_t)reg->ud;
> + case BRW_REGISTER_TYPE_HF:
> + reg->ud ^= 0x80008000;
>
>
> This is not correct for integers. We need to keep two separate cases.
That's true, I've forgotten about two's complement representation. For
this series v2 I will send:
case BRW_REGISTER_TYPE_UW:
- reg->d = -(int16_t)reg->ud;
+ uint16_t value = -(int16_t)reg->ud;
+ reg->ud = value | value << 16;
+ return true;
+ case BRW_REGISTER_TYPE_HF:
+ reg->ud ^= 0x80008000;
I'm including for v2 also a new patch for solving a problem with
negative values at brw_imm_w that is replicating the 16-bit value
wrongly because of sign extension.
>
>
> return true;
> case BRW_REGISTER_TYPE_F:
> reg->f = -reg->f;
> @@ -602,8 +603,6 @@ brw_negate_immediate(enum brw_reg_type type,
> struct brw_reg *reg)
> case BRW_REGISTER_TYPE_UV:
> case BRW_REGISTER_TYPE_V:
> assert(!"unimplemented: negate UV/V immediate");
> - case BRW_REGISTER_TYPE_HF:
> - assert(!"unimplemented: negate HF immediate");
> case BRW_REGISTER_TYPE_NF:
> unreachable("no NF immediates");
> }
> --
> 2.14.1
>
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