[Mesa-dev] [PATCH 07/10] ac/surface: don't apply the 256-byte alignment to staging surfaces

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Having the over-alignment on staging surfaces breaks the user_stride
mechanism.

v2: Add a new SURF flag.
---
 src/amd/common/ac_surface.c               | 5 ++++-
 src/amd/common/ac_surface.h               | 1 +
 src/gallium/drivers/radeonsi/si_texture.c | 3 +++
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index a23952717e3..9595298055b 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -266,22 +266,25 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
 {
 	struct legacy_surf_level *surf_level;
 	ADDR_E_RETURNCODE ret;
 
 	AddrSurfInfoIn->mipLevel = level;
 	AddrSurfInfoIn->width = u_minify(config->info.width, level);
 	AddrSurfInfoIn->height = u_minify(config->info.height, level);
 
 	/* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
 	 * because GFX9 needs linear alignment of 256 bytes.
+	 *
+	 * This should not be applied to staging surfaces.
 	 */
-	if (config->info.levels == 1 &&
+	if (!(surf->flags & RADEON_SURF_TRANSFER_STAGING) &&
+	    config->info.levels == 1 &&
 	    AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
 	    AddrSurfInfoIn->bpp) {
 		unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
 
 		assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp));
 		AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
 	}
 
 	if (config->is_3d)
 		AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 37df859e6de..4060b84edab 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -61,20 +61,21 @@ enum radeon_micro_mode {
 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 #define RADEON_SURF_SBUFFER                     (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 #define RADEON_SURF_SHAREABLE                   (1 << 26)
+#define RADEON_SURF_TRANSFER_STAGING            (1 << 27)
 
 struct legacy_surf_level {
     uint64_t                    offset;
     uint32_t                    slice_size_dw; /* in dwords; max = 4GB / 4. */
     uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
     uint32_t                    dcc_fast_clear_size;
     unsigned                    nblk_x:15;
     unsigned                    nblk_y:15;
     enum radeon_surf_mode       mode:2;
 };
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 368fb034977..4ac284bb9d4 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -295,20 +295,23 @@ static int si_init_surface(struct si_screen *sscreen,
 		flags |= RADEON_SURF_SCANOUT;
 	}
 
 	if (ptex->bind & PIPE_BIND_SHARED)
 		flags |= RADEON_SURF_SHAREABLE;
 	if (is_imported)
 		flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
 	if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_TILING))
 		flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
+	if (ptex->flags & SI_RESOURCE_FLAG_TRANSFER)
+		flags |= RADEON_SURF_TRANSFER_STAGING;
+
 	r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
 				      array_mode, surface);
 	if (r) {
 		return r;
 	}
 
 	unsigned pitch = pitch_in_bytes_override / bpe;
 
 	if (sscreen->info.chip_class >= GFX9) {
 		if (pitch) {
-- 
2.17.0