[Mesa-dev] [PATCH 05/11] intel/compiler: implement conversions from 16-bit int/float to bool
Jason Ekstrand
jason at jlekstrand.net
Tue Apr 24 21:50:52 UTC 2018
On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga <itoral at igalia.com>
wrote:
> ---
> src/intel/compiler/brw_fs_nir.cpp | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index 5c414e45b61..ad31f7c82dc 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -1162,8 +1162,9 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
> break;
>
> case nir_op_i2b:
> - case nir_op_f2b:
> - if (nir_src_bit_size(instr->src[0].src) == 64) {
> + case nir_op_f2b: {
> + uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
> + if (bit_size == 64) {
> /* two-argument instructions can't take 64-bit immediates */
> fs_reg zero;
> fs_reg tmp;
> @@ -1185,13 +1186,18 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
> bld.CMP(tmp, op[0], zero, BRW_CONDITIONAL_NZ);
> bld.MOV(result, subscript(tmp, BRW_REGISTER_TYPE_UD, 0));
> } else {
> - if (instr->op == nir_op_f2b) {
> - bld.CMP(result, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);
> + fs_reg zero;
> + if (bit_size == 32) {
> + zero = instr->op == nir_op_f2b ? brw_imm_f(0.0f) :
> brw_imm_d(0);
> } else {
> - bld.CMP(result, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ);
> + assert(bit_size == 16);
> + zero = instr->op == nir_op_f2b ?
> + retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF) : brw_imm_w(0);
>
I really wish there were some better way of building immediates. Oh, well,
we can fix that later.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
> }
> + bld.CMP(result, op[0], zero, BRW_CONDITIONAL_NZ);
> }
> break;
> + }
>
> case nir_op_ftrunc:
> inst = bld.RNDZ(result, op[0]);
> --
> 2.14.1
>
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>
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