[Mesa-dev] [PATCH 4/4] intel/compiler: Add scheduler deps for instructions that implicitly read g0

[Ian Romanick]

On 04/23/2018 09:19 AM, Mark Janes wrote:
> I enabled these tests, and could not make them fail in CI.

Can I consider that a Tested-by?

> This bug may also be related:
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=95009

If none of these tests fail with this patch, I'm included to close them
with a note to re-open if the failures return.

I also plan to nominate this for stable.  I forgot to do that when I
sent the patch originally.

> Ian Romanick <idr at freedesktop.org> writes:
> 
>> From: Ian Romanick <ian.d.romanick at intel.com>
>>
>> Otherwise the scheduler can move the writes after the reads.
>>
>> Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012
>> Cc: Mark Janes <mark.a.janes at intel.com>
>> Cc: Clayton A Craft <clayton.a.craft at intel.com>
>> ---
>> I'd really like to have this run on the CI with the tests from bugzill
>> #95012 re-enabled.  I don't know how to do this on my own.  This series
>> is also available at:
>>
>>     https://cgit.freedesktop.org/~idr/mesa/log/?h=bug-95012.
>>
>>  src/intel/compiler/brw_ir_vec4.h                 | 25 ++++++++++++++++++++++++
>>  src/intel/compiler/brw_schedule_instructions.cpp |  3 +++
>>  2 files changed, 28 insertions(+)
>>
>> diff --git a/src/intel/compiler/brw_ir_vec4.h b/src/intel/compiler/brw_ir_vec4.h
>> index 95c5119c6c0..e401d8b4d16 100644
>> --- a/src/intel/compiler/brw_ir_vec4.h
>> +++ b/src/intel/compiler/brw_ir_vec4.h
>> @@ -334,6 +334,31 @@ public:
>>                                    opcode != BRW_OPCODE_IF &&
>>                                    opcode != BRW_OPCODE_WHILE));
>>     }
>> +
>> +   bool reads_g0_implicitly() const
>> +   {
>> +      switch (opcode) {
>> +      case SHADER_OPCODE_TEX:
>> +      case SHADER_OPCODE_TXL:
>> +      case SHADER_OPCODE_TXD:
>> +      case SHADER_OPCODE_TXF:
>> +      case SHADER_OPCODE_TXF_CMS_W:
>> +      case SHADER_OPCODE_TXF_CMS:
>> +      case SHADER_OPCODE_TXF_MCS:
>> +      case SHADER_OPCODE_TXS:
>> +      case SHADER_OPCODE_TG4:
>> +      case SHADER_OPCODE_TG4_OFFSET:
>> +      case SHADER_OPCODE_SAMPLEINFO:
>> +      case VS_OPCODE_PULL_CONSTANT_LOAD:
>> +      case GS_OPCODE_SET_PRIMITIVE_ID:
>> +      case GS_OPCODE_GET_INSTANCE_ID:
>> +      case SHADER_OPCODE_GEN4_SCRATCH_READ:
>> +      case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
>> +         return true;
>> +      default:
>> +         return false;
>> +      }
>> +   }
>>  };
>>  
>>  /**
>> diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
>> index fa85045de74..f817142a8b5 100644
>> --- a/src/intel/compiler/brw_schedule_instructions.cpp
>> +++ b/src/intel/compiler/brw_schedule_instructions.cpp
>> @@ -1267,6 +1267,9 @@ vec4_instruction_scheduler::calculate_deps()
>>           }
>>        }
>>  
>> +      if (inst->reads_g0_implicitly())
>> +         add_dep(last_fixed_grf_write, n);
>> +
>>        if (!inst->is_send_from_grf()) {
>>           for (int i = 0; i < inst->mlen; i++) {
>>              /* It looks like the MRF regs are released in the send
>> -- 
>> 2.14.3