[Mesa-dev] [PATCH v2] i965: Add and use a single miptree aux_buf field

Jason Ekstrand jason at jlekstrand.net
Tue Apr 24 00:56:07 UTC 2018


Rb

On April 23, 2018 20:14:36 Nanley Chery <nanleychery at gmail.com> wrote:

> We want to add and use a function that accesses the auxiliary buffer's
> clear_color_bo and doesn't care if it has an MCS or HiZ buffer
> specifically.
>
> v2 (Jason Ekstrand):
> * Drop intel_miptree_get_aux_buffer().
> * Mention CCS in the aux_buf field.
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c            |  16 ++--
> src/mesa/drivers/dri/i965/brw_clear.c            |   4 +-
> src/mesa/drivers/dri/i965/brw_wm.c               |   2 +-
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  11 ++-
> src/mesa/drivers/dri/i965/gen6_depth_state.c     |   6 +-
> src/mesa/drivers/dri/i965/gen7_misc_state.c      |   4 +-
> src/mesa/drivers/dri/i965/gen8_depth_state.c     |   6 +-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c    | 106 +++++++++++------------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h    |  53 +++++-------
> src/mesa/drivers/dri/i965/intel_tex_image.c      |   2 +-
> 10 files changed, 96 insertions(+), 114 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 962a316c5cf..37fca5e9d31 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -168,21 +168,19 @@ blorp_surf_for_miptree(struct brw_context *brw,
>        */
>       surf->clear_color = mt->fast_clear_color;
>
> -      struct intel_miptree_aux_buffer *aux_buf =
> -         intel_miptree_get_aux_buffer(mt);
> -      surf->aux_surf = &aux_buf->surf;
> +      surf->aux_surf = &mt->aux_buf->surf;
>       surf->aux_addr = (struct blorp_address) {
>          .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
>          .mocs = surf->addr.mocs,
>       };
>
> -      surf->aux_addr.buffer = aux_buf->bo;
> -      surf->aux_addr.offset = aux_buf->offset;
> +      surf->aux_addr.buffer = mt->aux_buf->bo;
> +      surf->aux_addr.offset = mt->aux_buf->offset;
>
>       if (devinfo->gen >= 10) {
>          surf->clear_color_addr = (struct blorp_address) {
> -            .buffer = aux_buf->clear_color_bo,
> -            .offset = aux_buf->clear_color_offset,
> +            .buffer = mt->aux_buf->clear_color_bo,
> +            .offset = mt->aux_buf->clear_color_offset,
>          };
>       }
>    } else {
> @@ -1212,7 +1210,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
> gl_framebuffer *fb,
>
>    /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
>     */
> -   if (can_fast_clear && !irb->mt->mcs_buf) {
> +   if (can_fast_clear && !irb->mt->aux_buf) {
>       assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
>       if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
>          /* There are a few reasons in addition to out-of-memory, that can
> @@ -1611,7 +1609,7 @@ intel_hiz_exec(struct brw_context *brw, struct 
> intel_mipmap_tree *mt,
>        brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
>    }
>
> -   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->hiz_buf);
> +   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);
>
>    struct isl_surf isl_tmp[2];
>    struct blorp_surf surf;
> diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
> b/src/mesa/drivers/dri/i965/brw_clear.c
> index 487de9b8997..3d540d6d905 100644
> --- a/src/mesa/drivers/dri/i965/brw_clear.c
> +++ b/src/mesa/drivers/dri/i965/brw_clear.c
> @@ -240,7 +240,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
>           * buffer when doing a fast clear. Since we are skipping the fast
>           * clear here, we need to update the clear color ourselves.
>           */
> -         uint32_t clear_offset = mt->hiz_buf->clear_color_offset;
> +         uint32_t clear_offset = mt->aux_buf->clear_color_offset;
>          union isl_color_value clear_color = { .f32 = { clear_value, } };
>
>          /* We can't update the clear color while the hardware is still using
> @@ -249,7 +249,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
>           */
>          brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
>          for (int i = 0; i < 4; i++) {
> -            brw_store_data_imm32(brw, mt->hiz_buf->clear_color_bo,
> +            brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
>                                  clear_offset + i * 4, clear_color.u32[i]);
>          }
>          brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
> diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
> b/src/mesa/drivers/dri/i965/brw_wm.c
> index 68d4ab88d77..94048cd758f 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm.c
> @@ -384,7 +384,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
>          if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) {
>             assert(devinfo->gen >= 7);
>             assert(intel_tex->mt->surf.samples > 1);
> -            assert(intel_tex->mt->mcs_buf);
> +            assert(intel_tex->mt->aux_buf);
>             assert(intel_tex->mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
>             key->compressed_multisample_layout_mask |= 1 << s;
>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 06f739faf61..8025ec128b1 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -155,12 +155,11 @@ brw_emit_surface_state(struct brw_context *brw,
>    struct brw_bo *aux_bo = NULL;
>    struct isl_surf *aux_surf = NULL;
>    uint64_t aux_offset = 0;
> -   struct intel_miptree_aux_buffer *aux_buf = 
> intel_miptree_get_aux_buffer(mt);
>
>    if (aux_usage != ISL_AUX_USAGE_NONE) {
> -      aux_surf = &aux_buf->surf;
> -      aux_bo = aux_buf->bo;
> -      aux_offset = aux_buf->offset;
> +      aux_surf = &mt->aux_buf->surf;
> +      aux_bo = mt->aux_buf->bo;
> +      aux_offset = mt->aux_buf->offset;
>
>       /* We only really need a clear color if we also have an auxiliary
>        * surface.  Without one, it does nothing.
> @@ -178,8 +177,8 @@ brw_emit_surface_state(struct brw_context *brw,
>    struct brw_bo *clear_bo = NULL;
>    uint32_t clear_offset = 0;
>    if (use_clear_address) {
> -      clear_bo = aux_buf->clear_color_bo;
> -      clear_offset = aux_buf->clear_color_offset;
> +      clear_bo = mt->aux_buf->clear_color_bo;
> +      clear_offset = mt->aux_buf->clear_color_offset;
>    }
>
>    isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view,
> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
> b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> index 3a66b42fec1..8a1d5808051 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> @@ -160,13 +160,13 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>          assert(depth_mt);
>
>          uint32_t offset;
> -         isl_surf_get_image_offset_B_tile_sa(&depth_mt->hiz_buf->surf,
> +         isl_surf_get_image_offset_B_tile_sa(&depth_mt->aux_buf->surf,
>                                              lod, 0, 0, &offset, NULL, NULL);
>
> 	 BEGIN_BATCH(3);
> 	 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
> -	 OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
> -	 OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, offset);
> +	 OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1);
> +	 OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset);
> 	 ADVANCE_BATCH();
>       } else {
> 	 BEGIN_BATCH(3);
> diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c 
> b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> index 58f0a1bdbfd..1ce76585f2b 100644
> --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> @@ -149,8 +149,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
>       BEGIN_BATCH(3);
>       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
>       OUT_BATCH((mocs << 25) |
> -                (depth_mt->hiz_buf->pitch - 1));
> -      OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, 0);
> +                (depth_mt->aux_buf->pitch - 1));
> +      OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
>       ADVANCE_BATCH();
>    }
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index 27705d35df9..0fc027313b4 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -94,9 +94,9 @@ emit_depth_packets(struct brw_context *brw,
>       assert(depth_mt);
>       BEGIN_BATCH(5);
>       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
> -      OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25);
> -      OUT_RELOC64(depth_mt->hiz_buf->bo, RELOC_WRITE, 0);
> -      OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2);
> +      OUT_BATCH((depth_mt->aux_buf->pitch - 1) | mocs_wb << 25);
> +      OUT_RELOC64(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
> +      OUT_BATCH(depth_mt->aux_buf->qpitch >> 2);
>       ADVANCE_BATCH();
>    }
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 3cb6f70a6ce..139f3f0c194 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -950,7 +950,7 @@ create_ccs_buf_for_image(struct brw_context *brw,
>    assert(mt->last_level == 0);
>
>    /* We shouldn't already have a CCS */
> -   assert(!mt->mcs_buf);
> +   assert(!mt->aux_buf);
>
>    if (!isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, &temp_ccs_surf,
>                               image->aux_pitch))
> @@ -959,14 +959,14 @@ create_ccs_buf_for_image(struct brw_context *brw,
>    assert(image->aux_offset < image->bo->size);
>    assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
>
> -   mt->mcs_buf = calloc(sizeof(*mt->mcs_buf), 1);
> -   if (mt->mcs_buf == NULL)
> +   mt->aux_buf = calloc(sizeof(*mt->aux_buf), 1);
> +   if (mt->aux_buf == NULL)
>       return false;
>
>    mt->aux_state = create_aux_state_map(mt, initial_state);
>    if (!mt->aux_state) {
> -      free(mt->mcs_buf);
> -      mt->mcs_buf = NULL;
> +      free(mt->aux_buf);
> +      mt->aux_buf = NULL;
>       return false;
>    }
>
> @@ -977,24 +977,24 @@ create_ccs_buf_for_image(struct brw_context *brw,
>     */
>    const struct gen_device_info *devinfo = &brw->screen->devinfo;
>    if (devinfo->gen >= 10) {
> -      mt->mcs_buf->clear_color_bo =
> +      mt->aux_buf->clear_color_bo =
>          brw_bo_alloc(brw->bufmgr, "clear_color_bo",
>                       brw->isl_dev.ss.clear_color_state_size);
> -      if (!mt->mcs_buf->clear_color_bo) {
> -         free(mt->mcs_buf);
> -         mt->mcs_buf = NULL;
> +      if (!mt->aux_buf->clear_color_bo) {
> +         free(mt->aux_buf);
> +         mt->aux_buf = NULL;
>          return false;
>       }
>    }
>
> -   mt->mcs_buf->bo = image->bo;
> +   mt->aux_buf->bo = image->bo;
>    brw_bo_reference(image->bo);
>
> -   mt->mcs_buf->offset = image->aux_offset;
> -   mt->mcs_buf->size = image->bo->size - image->aux_offset;
> -   mt->mcs_buf->pitch = image->aux_pitch;
> -   mt->mcs_buf->qpitch = 0;
> -   mt->mcs_buf->surf = temp_ccs_surf;
> +   mt->aux_buf->offset = image->aux_offset;
> +   mt->aux_buf->size = image->bo->size - image->aux_offset;
> +   mt->aux_buf->pitch = image->aux_pitch;
> +   mt->aux_buf->qpitch = 0;
> +   mt->aux_buf->surf = temp_ccs_surf;
>
>    return true;
> }
> @@ -1249,7 +1249,7 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
>       brw_bo_unreference((*mt)->bo);
>       intel_miptree_release(&(*mt)->stencil_mt);
>       intel_miptree_release(&(*mt)->r8stencil_mt);
> -      intel_miptree_aux_buffer_free(intel_miptree_get_aux_buffer(*mt));
> +      intel_miptree_aux_buffer_free((*mt)->aux_buf);
>       free_aux_state_map((*mt)->aux_state);
>
>       intel_miptree_release(&(*mt)->plane[0]);
> @@ -1660,7 +1660,7 @@ intel_miptree_init_mcs(struct brw_context *brw,
>                        struct intel_mipmap_tree *mt,
>                        int init_value)
> {
> -   assert(mt->mcs_buf != NULL);
> +   assert(mt->aux_buf != NULL);
>
>    /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
>     *
> @@ -1672,16 +1672,16 @@ intel_miptree_init_mcs(struct brw_context *brw,
>     *
>     * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
>     */
> -   void *map = brw_bo_map(brw, mt->mcs_buf->bo, MAP_WRITE | MAP_RAW);
> +   void *map = brw_bo_map(brw, mt->aux_buf->bo, MAP_WRITE | MAP_RAW);
>    if (unlikely(map == NULL)) {
>       fprintf(stderr, "Failed to map mcs buffer into GTT\n");
> -      brw_bo_unreference(mt->mcs_buf->bo);
> -      free(mt->mcs_buf);
> +      brw_bo_unreference(mt->aux_buf->bo);
> +      free(mt->aux_buf);
>       return;
>    }
>    void *data = map;
> -   memset(data, init_value, mt->mcs_buf->size);
> -   brw_bo_unmap(mt->mcs_buf->bo);
> +   memset(data, init_value, mt->aux_buf->size);
> +   brw_bo_unmap(mt->aux_buf->bo);
> }
>
> static struct intel_miptree_aux_buffer *
> @@ -1737,7 +1737,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
>                         GLuint num_samples)
> {
>    assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
> -   assert(mt->mcs_buf == NULL);
> +   assert(mt->aux_buf == NULL);
>    assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
>
>    /* Multisampled miptrees are only supported for single level. */
> @@ -1759,9 +1759,9 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
>     * to be just used by the GPU.
>     */
>    const uint32_t alloc_flags = 0;
> -   mt->mcs_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
> +   mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
>                                         &temp_mcs_surf, alloc_flags, mt);
> -   if (!mt->mcs_buf) {
> +   if (!mt->aux_buf) {
>       free(aux_state);
>       return false;
>    }
> @@ -1777,7 +1777,7 @@ bool
> intel_miptree_alloc_ccs(struct brw_context *brw,
>                         struct intel_mipmap_tree *mt)
> {
> -   assert(mt->mcs_buf == NULL);
> +   assert(mt->aux_buf == NULL);
>    assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
>           mt->aux_usage == ISL_AUX_USAGE_CCS_D);
>
> @@ -1808,9 +1808,9 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
>     */
>    const uint32_t alloc_flags = mt->aux_usage == ISL_AUX_USAGE_CCS_E ?
>                                 BO_ALLOC_ZEROED : BO_ALLOC_BUSY;
> -   mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
> +   mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
>                                         &temp_ccs_surf, alloc_flags, mt);
> -   if (!mt->mcs_buf) {
> +   if (!mt->aux_buf) {
>       free(aux_state);
>       return false;
>    }
> @@ -1832,7 +1832,7 @@ intel_miptree_level_enable_hiz(struct brw_context *brw,
> {
>    const struct gen_device_info *devinfo = &brw->screen->devinfo;
>
> -   assert(mt->hiz_buf);
> +   assert(mt->aux_buf);
>    assert(mt->surf.size > 0);
>
>    if (devinfo->gen >= 8 || devinfo->is_haswell) {
> @@ -1860,7 +1860,7 @@ bool
> intel_miptree_alloc_hiz(struct brw_context *brw,
> 			struct intel_mipmap_tree *mt)
> {
> -   assert(mt->hiz_buf == NULL);
> +   assert(mt->aux_buf == NULL);
>    assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);
>
>    enum isl_aux_state **aux_state =
> @@ -1875,10 +1875,10 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
>    assert(ok);
>
>    const uint32_t alloc_flags = BO_ALLOC_BUSY;
> -   mt->hiz_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",
> +   mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",
>                                         &temp_hiz_surf, alloc_flags, mt);
>
> -   if (!mt->hiz_buf) {
> +   if (!mt->aux_buf) {
>       free(aux_state);
>       return false;
>    }
> @@ -1951,7 +1951,7 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
>       return false;
>    }
>
> -   if (!mt->hiz_buf) {
> +   if (!mt->aux_buf) {
>       return false;
>    }
>
> @@ -2031,7 +2031,7 @@ intel_miptree_has_color_unresolved(const struct 
> intel_mipmap_tree *mt,
> {
>    assert(_mesa_is_format_color_format(mt->format));
>
> -   if (!mt->mcs_buf)
> +   if (!mt->aux_buf)
>       return false;
>
>    /* Clamp the level range to fit the miptree */
> @@ -2058,7 +2058,7 @@ intel_miptree_check_color_resolve(const struct 
> brw_context *brw,
>                                   const struct intel_mipmap_tree *mt,
>                                   unsigned level, unsigned layer)
> {
> -   if (!mt->mcs_buf)
> +   if (!mt->aux_buf)
>       return;
>
>    /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
> @@ -2450,7 +2450,7 @@ intel_miptree_prepare_access(struct brw_context *brw,
>       break;
>
>    case ISL_AUX_USAGE_MCS:
> -      assert(mt->mcs_buf);
> +      assert(mt->aux_buf);
>       assert(start_level == 0 && num_levels == 1);
>       const uint32_t level_layers =
>          miptree_layer_range_length(mt, 0, start_layer, num_layers);
> @@ -2462,7 +2462,7 @@ intel_miptree_prepare_access(struct brw_context *brw,
>
>    case ISL_AUX_USAGE_CCS_D:
>    case ISL_AUX_USAGE_CCS_E:
> -      if (!mt->mcs_buf)
> +      if (!mt->aux_buf)
>          return;
>
>       for (uint32_t l = 0; l < num_levels; l++) {
> @@ -2478,7 +2478,7 @@ intel_miptree_prepare_access(struct brw_context *brw,
>       break;
>
>    case ISL_AUX_USAGE_HIZ:
> -      assert(mt->hiz_buf);
> +      assert(mt->aux_buf);
>       for (uint32_t l = 0; l < num_levels; l++) {
>          const uint32_t level = start_level + l;
>          if (!intel_miptree_level_has_hiz(mt, level))
> @@ -2512,7 +2512,7 @@ intel_miptree_finish_write(struct brw_context *brw,
>       break;
>
>    case ISL_AUX_USAGE_MCS:
> -      assert(mt->mcs_buf);
> +      assert(mt->aux_buf);
>       for (uint32_t a = 0; a < num_layers; a++) {
>          intel_miptree_finish_mcs_write(brw, mt, start_layer + a,
>                                         aux_usage);
> @@ -2521,7 +2521,7 @@ intel_miptree_finish_write(struct brw_context *brw,
>
>    case ISL_AUX_USAGE_CCS_D:
>    case ISL_AUX_USAGE_CCS_E:
> -      if (!mt->mcs_buf)
> +      if (!mt->aux_buf)
>          return;
>
>       for (uint32_t a = 0; a < num_layers; a++) {
> @@ -2552,7 +2552,7 @@ intel_miptree_get_aux_state(const struct 
> intel_mipmap_tree *mt,
>    intel_miptree_check_level_layer(mt, level, layer);
>
>    if (_mesa_is_format_color_format(mt->format)) {
> -      assert(mt->mcs_buf != NULL);
> +      assert(mt->aux_buf != NULL);
>       assert(mt->surf.samples == 1 ||
>              mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
>    } else if (mt->format == MESA_FORMAT_S_UINT8) {
> @@ -2573,7 +2573,7 @@ intel_miptree_set_aux_state(struct brw_context *brw,
>    num_layers = miptree_layer_range_length(mt, level, start_layer, num_layers);
>
>    if (_mesa_is_format_color_format(mt->format)) {
> -      assert(mt->mcs_buf != NULL);
> +      assert(mt->aux_buf != NULL);
>       assert(mt->surf.samples == 1 ||
>              mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
>    } else if (mt->format == MESA_FORMAT_S_UINT8) {
> @@ -2636,7 +2636,7 @@ intel_miptree_texture_aux_usage(struct brw_context *brw,
>
>    case ISL_AUX_USAGE_CCS_D:
>    case ISL_AUX_USAGE_CCS_E:
> -      if (!mt->mcs_buf) {
> +      if (!mt->aux_buf) {
>          assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
>          return ISL_AUX_USAGE_NONE;
>       }
> @@ -2724,12 +2724,12 @@ intel_miptree_render_aux_usage(struct brw_context *brw,
>
>    switch (mt->aux_usage) {
>    case ISL_AUX_USAGE_MCS:
> -      assert(mt->mcs_buf);
> +      assert(mt->aux_buf);
>       return ISL_AUX_USAGE_MCS;
>
>    case ISL_AUX_USAGE_CCS_D:
>    case ISL_AUX_USAGE_CCS_E:
> -      if (!mt->mcs_buf) {
> +      if (!mt->aux_buf) {
>          assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
>          return ISL_AUX_USAGE_NONE;
>       }
> @@ -2784,7 +2784,7 @@ intel_miptree_prepare_depth(struct brw_context *brw,
>                             uint32_t start_layer, uint32_t layer_count)
> {
>    intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
> -                                mt->aux_usage, mt->hiz_buf != NULL);
> +                                mt->aux_usage, mt->aux_buf != NULL);
> }
>
> void
> @@ -2795,7 +2795,7 @@ intel_miptree_finish_depth(struct brw_context *brw,
> {
>    if (depth_written) {
>       intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
> -                                 mt->hiz_buf != NULL);
> +                                 mt->aux_buf != NULL);
>    }
> }
>
> @@ -2819,7 +2819,7 @@ intel_miptree_prepare_external(struct brw_context *brw,
>       assert(mt->surf.logical_level0_px.depth == 1);
>       assert(mt->surf.logical_level0_px.array_len == 1);
>       assert(mt->surf.samples == 1);
> -      assert(mt->mcs_buf != NULL);
> +      assert(mt->aux_buf != NULL);
>
>       aux_usage = mod_info->aux_usage;
>       supports_fast_clear = mod_info->supports_clear_color;
> @@ -2834,7 +2834,7 @@ void
> intel_miptree_finish_external(struct brw_context *brw,
>                               struct intel_mipmap_tree *mt)
> {
> -   if (!mt->mcs_buf)
> +   if (!mt->aux_buf)
>       return;
>
>    /* We don't know the actual aux state of the aux surface.  The previous
> @@ -2875,11 +2875,9 @@ intel_miptree_make_shareable(struct brw_context *brw,
>                                 0, INTEL_REMAINING_LAYERS,
>                                 ISL_AUX_USAGE_NONE, false);
>
> -   struct intel_miptree_aux_buffer *aux_buf = 
> intel_miptree_get_aux_buffer(mt);
> -   if (aux_buf) {
> -      intel_miptree_aux_buffer_free(aux_buf);
> -      mt->mcs_buf = NULL;
> -      mt->hiz_buf = NULL;
> +   if (mt->aux_buf) {
> +      intel_miptree_aux_buffer_free(mt->aux_buf);
> +      mt->aux_buf = NULL;
>
>       /* Make future calls of intel_miptree_level_has_hiz() return false. */
>       for (uint32_t l = mt->first_level; l <= mt->last_level; ++l) {
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 8fe5c4add67..241832f686f 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -272,16 +272,6 @@ struct intel_mipmap_tree
>     */
>    uint32_t offset;
>
> -   /**
> -    * \brief HiZ aux buffer
> -    *
> -    * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
> -    *
> -    * To determine if hiz is enabled, do not check this pointer. Instead, use
> -    * intel_miptree_level_has_hiz().
> -    */
> -   struct intel_miptree_aux_buffer *hiz_buf;
> -
>    /**
>     * \brief The type of auxiliary compression used by this miptree.
>     *
> @@ -335,15 +325,29 @@ struct intel_mipmap_tree
>    bool r8stencil_needs_update;
>
>    /**
> -    * \brief MCS auxiliary buffer.
> +    * \brief CCS, MCS, or HiZ auxiliary buffer.
> +    *
> +    * NULL if no auxiliary buffer is in use for this surface.
>     *
> -    * This buffer contains the "multisample control surface", which stores
> -    * the necessary information to implement compressed MSAA
> -    * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
> +    * For single-sampled color miptrees:
> +    *    This buffer contains the Color Control Surface, which stores the
> +    *    necessary information to implement lossless color compression (CCS_E)
> +    *    and "fast color clear" (CCS_D) behaviour.
>     *
> -    * NULL if no MCS buffer is in use for this surface.
> +    * For multi-sampled color miptrees:
> +    *    This buffer contains the Multisample Control Surface, which 
> stores the
> +    *    necessary information to implement compressed MSAA
> +    *    (INTEL_MSAA_FORMAT_CMS).
> +    *
> +    * For depth miptrees:
> +    *    This buffer contains the Hierarchical Depth Buffer, which stores the
> +    *    necessary information to implement lossless depth compression and 
> fast
> +    *    depth clear behavior.
> +    *
> +    *    To determine if HiZ is enabled, do not check this pointer. Instead,
> +    *    use intel_miptree_level_has_hiz().
>     */
> -   struct intel_miptree_aux_buffer *mcs_buf;
> +   struct intel_miptree_aux_buffer *aux_buf;
>
>    /**
>     * Planes 1 and 2 in case this is a planar surface.
> @@ -485,23 +489,6 @@ enum isl_dim_layout
> get_isl_dim_layout(const struct gen_device_info *devinfo,
>                    enum isl_tiling tiling, GLenum target);
>
> -static inline struct intel_miptree_aux_buffer *
> -intel_miptree_get_aux_buffer(const struct intel_mipmap_tree *mt)
> -{
> -   switch (mt->aux_usage) {
> -   case ISL_AUX_USAGE_MCS:
> -   case ISL_AUX_USAGE_CCS_D:
> -   case ISL_AUX_USAGE_CCS_E:
> -      return mt->mcs_buf;
> -   case ISL_AUX_USAGE_HIZ:
> -      return mt->hiz_buf;
> -   case ISL_AUX_USAGE_NONE:
> -      return NULL;
> -   default:
> -      unreachable("Invalid aux_usage!\n");
> -   }
> -}
> -
> void
> intel_get_image_dims(struct gl_texture_image *image,
>                      int *width, int *height, int *depth);
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
> b/src/mesa/drivers/dri/i965/intel_tex_image.c
> index e25bc9a0c08..3fd227ad05d 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
> @@ -543,7 +543,7 @@ intelReleaseTexBuffer(__DRIcontext *pDRICtx, GLint target,
>     * should be a no-op in almost all cases.  On the off chance that someone
>     * ever triggers this, we should at least warn them.
>     */
> -   if (intel_tex->mt->mcs_buf &&
> +   if (intel_tex->mt->aux_buf &&
>        intel_miptree_get_aux_state(intel_tex->mt, 0, 0) !=
>        isl_drm_modifier_get_default_aux_state(intel_tex->mt->drm_modifier)) {
>       _mesa_warning(ctx, "Aux state changed between BindTexImage and "
> --
> 2.16.2





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