[Mesa-dev] [PATCH 7/7] radeonsi/gfx9: workaround for INTERP with indirect indexing

[Nicolai Hähnle]

Patches 2, 3, 4, 6, 7:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>


On 17.04.2018 02:41, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> and clean up the conditions.
> 
> We might just simplify this because the only stage that can return
> 0 or 1 is VS.
> ---
>   src/gallium/drivers/radeonsi/si_get.c | 19 +++++++++++++------
>   1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
> index fb1c6eca135..47dca742b75 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -469,26 +469,33 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
>   	case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
>   	case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
>   	case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
>   	case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
>   	case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
>   	case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
>   		return 1;
>   
>   	case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
>   		/* TODO: Indirect indexing of GS inputs is unimplemented. */
> -		return shader != PIPE_SHADER_GEOMETRY &&
> -		       (sscreen->llvm_has_working_vgpr_indexing ||
> -			/* TCS and TES load inputs directly from LDS or
> -			 * offchip memory, so indirect indexing is trivial. */
> -			shader == PIPE_SHADER_TESS_CTRL ||
> -			shader == PIPE_SHADER_TESS_EVAL);
> +		if (shader == PIPE_SHADER_GEOMETRY)
> +			return 0;
> +
> +		if (shader == PIPE_SHADER_VERTEX &&
> +		    !sscreen->llvm_has_working_vgpr_indexing)
> +			return 0;
> +
> +		/* TCS and TES load inputs directly from LDS or offchip
> +		 * memory, so indirect indexing is always supported.
> +		 * PS has to support indirect indexing, because we can't
> +		 * lower that to TEMPs for INTERP instructions.
> +		 */
> +		return 1;
>   
>   	case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
>   		return sscreen->llvm_has_working_vgpr_indexing ||
>   		       /* TCS stores outputs directly to memory. */
>   		       shader == PIPE_SHADER_TESS_CTRL;
>   
>   	/* Unsupported boolean features. */
>   	case PIPE_SHADER_CAP_SUBROUTINES:
>   	case PIPE_SHADER_CAP_SUPPORTED_IRS:
>   	case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
> 


-- 
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Aber vergiss niemals, wie sie sein sollte.