[Mesa-dev] [PATCH 7/9] radeonsi: remove unused atom parameter from si_atom::emit
Marek Olšák
maraeo at gmail.com
Tue Apr 17 00:42:09 UTC 2018
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_compute.c | 3 +--
src/gallium/drivers/radeonsi/si_descriptors.c | 3 +--
src/gallium/drivers/radeonsi/si_query.c | 3 +--
src/gallium/drivers/radeonsi/si_state.c | 21 +++++++++----------
src/gallium/drivers/radeonsi/si_state.h | 7 +++----
.../drivers/radeonsi/si_state_binning.c | 2 +-
src/gallium/drivers/radeonsi/si_state_draw.c | 8 +++----
.../drivers/radeonsi/si_state_shaders.c | 5 ++---
.../drivers/radeonsi/si_state_streamout.c | 5 ++---
.../drivers/radeonsi/si_state_viewport.c | 5 ++---
10 files changed, 26 insertions(+), 36 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index e7867e7fe4f..f77367aef7f 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -857,22 +857,21 @@ static void si_launch_grid(
si_emit_cache_flush(sctx);
if (!si_switch_compute_shader(sctx, program, &program->shader,
code_object, info->pc))
return;
si_upload_compute_shader_descriptors(sctx);
si_emit_compute_shader_pointers(sctx);
if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
- sctx->atoms.s.render_cond.emit(sctx,
- &sctx->atoms.s.render_cond);
+ sctx->atoms.s.render_cond.emit(sctx);
si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
}
if ((program->input_size ||
program->ir_type == PIPE_SHADER_IR_NATIVE) &&
unlikely(!si_upload_compute_input(sctx, code_object, info))) {
return;
}
/* Global buffers */
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 8bb2a5d95d8..a030cbe8229 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -2146,22 +2146,21 @@ static void si_emit_global_shader_pointers(struct si_context *sctx,
si_emit_shader_pointer(sctx, descs,
R_00B330_SPI_SHADER_USER_DATA_ES_0);
si_emit_shader_pointer(sctx, descs,
R_00B230_SPI_SHADER_USER_DATA_GS_0);
si_emit_shader_pointer(sctx, descs,
R_00B430_SPI_SHADER_USER_DATA_HS_0);
si_emit_shader_pointer(sctx, descs,
R_00B530_SPI_SHADER_USER_DATA_LS_0);
}
-void si_emit_graphics_shader_pointers(struct si_context *sctx,
- struct si_atom *atom)
+void si_emit_graphics_shader_pointers(struct si_context *sctx)
{
uint32_t *sh_base = sctx->shader_pointers.sh_base;
if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
si_emit_global_shader_pointers(sctx,
&sctx->descriptors[SI_DESCS_RW_BUFFERS]);
}
si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(VERTEX),
sh_base[PIPE_SHADER_VERTEX]);
diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c
index d1b519e5508..d621f22f46b 100644
--- a/src/gallium/drivers/radeonsi/si_query.c
+++ b/src/gallium/drivers/radeonsi/si_query.c
@@ -929,22 +929,21 @@ static void emit_set_predicate(struct si_context *ctx,
radeon_emit(cs, va >> 32);
} else {
radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
radeon_emit(cs, va);
radeon_emit(cs, op | ((va >> 32) & 0xFF));
}
radeon_add_to_buffer_list(ctx, ctx->gfx_cs, buf, RADEON_USAGE_READ,
RADEON_PRIO_QUERY);
}
-static void si_emit_query_predication(struct si_context *ctx,
- struct si_atom *atom)
+static void si_emit_query_predication(struct si_context *ctx)
{
struct si_query_hw *query = (struct si_query_hw *)ctx->render_cond;
struct si_query_buffer *qbuf;
uint32_t op;
bool flag_wait, invert;
if (!query)
return;
invert = ctx->render_cond_invert;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 928b465fe25..da254f2ba73 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -57,21 +57,21 @@ static unsigned si_pack_float_12p4(float x)
return x <= 0 ? 0 :
x >= 4096 ? 0xffff : x * 16;
}
/*
* Inferred framebuffer and blender state.
*
* CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
* if there is not enough PS outputs.
*/
-static void si_emit_cb_render_state(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_cb_render_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_state_blend *blend = sctx->queued.named.blend;
/* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
* but you never know. */
uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
unsigned i;
if (blend)
cb_target_mask &= blend->cb_target_mask;
@@ -690,21 +690,21 @@ static void si_set_blend_color(struct pipe_context *ctx,
const struct pipe_blend_color *state)
{
struct si_context *sctx = (struct si_context *)ctx;
static const struct pipe_blend_color zeros;
sctx->blend_color.state = *state;
sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
}
-static void si_emit_blend_color(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_blend_color(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
}
/*
* Clipping
*/
@@ -724,29 +724,29 @@ static void si_set_clip_state(struct pipe_context *ctx,
si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
cb.buffer = NULL;
cb.user_buffer = state->ucp;
cb.buffer_offset = 0;
cb.buffer_size = 4*4*8;
si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
pipe_resource_reference(&cb.buffer, NULL);
}
-static void si_emit_clip_state(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_clip_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
}
-static void si_emit_clip_regs(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_clip_regs(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *vs = si_get_vs_state(sctx);
struct si_shader_selector *vs_sel = vs->selector;
struct tgsi_shader_info *info = &vs_sel->info;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
unsigned window_space =
info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
unsigned clipdist_mask = vs_sel->clipdist_mask;
unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
@@ -1046,21 +1046,21 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state)
if (sctx->queued.named.rasterizer == state)
si_pm4_bind_state(sctx, poly_offset, NULL);
FREE(rs->pm4_poly_offset);
si_pm4_delete_state(sctx, rasterizer, rs);
}
/*
* infeered state between dsa and stencil ref
*/
-static void si_emit_stencil_ref(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_stencil_ref(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
S_028430_STENCILMASK(dsa->valuemask[0]) |
S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
S_028430_STENCILOPVAL(1));
@@ -1334,21 +1334,21 @@ void si_set_occlusion_query_state(struct si_context *sctx,
}
void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
{
st->saved_compute = sctx->cs_shader_state.program;
si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
}
-static void si_emit_db_render_state(struct si_context *sctx, struct si_atom *state)
+static void si_emit_db_render_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
unsigned db_shader_control;
radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
/* DB_RENDER_CONTROL */
if (sctx->dbcb_depth_copy_enabled ||
sctx->dbcb_stencil_copy_enabled) {
@@ -2926,21 +2926,21 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
sctx->do_update_shaders = true;
if (!sctx->decompression_enabled) {
/* Prevent textures decompression when the framebuffer state
* changes come from the decompression passes themselves.
*/
sctx->need_check_render_feedback = true;
}
}
-static void si_emit_framebuffer_state(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_framebuffer_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
unsigned i, nr_cbufs = state->nr_cbufs;
struct r600_texture *tex = NULL;
struct r600_surface *cb = NULL;
unsigned cb_color_info = 0;
/* Colorbuffers. */
for (i = 0; i < nr_cbufs; i++) {
@@ -3183,22 +3183,21 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct si_atom *a
if (sctx->screen->dfsm_allowed) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
}
sctx->framebuffer.dirty_cbufs = 0;
sctx->framebuffer.dirty_zsbuf = false;
}
-static void si_emit_msaa_sample_locs(struct si_context *sctx,
- struct si_atom *atom)
+static void si_emit_msaa_sample_locs(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned nr_samples = sctx->framebuffer.nr_samples;
bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
/* Smoothing (only possible with nr_samples == 1) uses the same
* sample locations as the MSAA it simulates.
*/
if (nr_samples <= 1 && sctx->smoothing_enabled)
nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
@@ -3295,21 +3294,21 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
}
if (colormask & ~blendmask) {
if (!dsa_order_invariant.pass_last)
return false;
}
return true;
}
-static void si_emit_msaa_config(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_msaa_config(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
/* 33% faster rendering to linear color buffers */
bool dst_is_linear = sctx->framebuffer.any_dst_linear;
bool out_of_order_rast = si_out_of_order_rasterization(sctx);
unsigned sc_mode_cntl_1 =
S_028A4C_WALK_SIZE(dst_is_linear) |
S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
@@ -4151,21 +4150,21 @@ static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
{
struct si_context *sctx = (struct si_context *)ctx;
if (sctx->sample_mask == (uint16_t)sample_mask)
return;
sctx->sample_mask = sample_mask;
si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
}
-static void si_emit_sample_mask(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_sample_mask(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned mask = sctx->sample_mask;
/* Needed for line and polygon smoothing as well as for the Polaris
* small primitive filter. We expect the state tracker to take care of
* this for us.
*/
assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
(mask & 1 && sctx->blitter->running));
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 5e3c543f579..d235f31c792 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -42,21 +42,21 @@
struct si_screen;
struct si_shader;
struct si_shader_selector;
struct r600_texture;
struct si_qbo_state;
/* State atoms are callbacks which write a sequence of packets into a GPU
* command buffer (AKA indirect buffer, AKA IB, AKA command stream, AKA CS).
*/
struct si_atom {
- void (*emit)(struct si_context *ctx, struct si_atom *state);
+ void (*emit)(struct si_context *ctx);
};
struct si_state_blend {
struct si_pm4_state pm4;
uint32_t cb_target_mask;
/* Set 0xf or 0x0 (4 bits) per render target if the following is
* true. ANDed with spi_shader_col_format.
*/
unsigned cb_target_enabled_4bit;
unsigned blend_enable_4bit;
@@ -354,22 +354,21 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
bool si_upload_compute_shader_descriptors(struct si_context *sctx);
void si_release_all_descriptors(struct si_context *sctx);
void si_all_descriptors_begin_new_cs(struct si_context *sctx);
void si_all_resident_buffers_begin_new_cs(struct si_context *sctx);
void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
const uint8_t *ptr, unsigned size, uint32_t *const_offset);
void si_update_all_texture_descriptors(struct si_context *sctx);
void si_shader_change_notify(struct si_context *sctx);
void si_update_needs_color_decompress_masks(struct si_context *sctx);
-void si_emit_graphics_shader_pointers(struct si_context *sctx,
- struct si_atom *atom);
+void si_emit_graphics_shader_pointers(struct si_context *sctx);
void si_emit_compute_shader_pointers(struct si_context *sctx);
void si_set_rw_buffer(struct si_context *sctx,
uint slot, const struct pipe_constant_buffer *input);
void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
uint64_t new_active_mask);
void si_set_active_descriptors_for_shader(struct si_context *sctx,
struct si_shader_selector *sel);
bool si_bindless_descriptor_can_reclaim_slab(void *priv,
struct pb_slab_entry *entry);
struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
@@ -404,21 +403,21 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
const struct pipe_sampler_view *state,
unsigned width0, unsigned height0,
unsigned force_level);
void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
void si_update_ps_iter_samples(struct si_context *sctx);
void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
void si_set_occlusion_query_state(struct si_context *sctx,
bool old_perfect_enable);
/* si_state_binning.c */
-void si_emit_dpbb_state(struct si_context *sctx, struct si_atom *state);
+void si_emit_dpbb_state(struct si_context *sctx);
/* si_state_shaders.c */
bool si_update_shaders(struct si_context *sctx);
void si_init_shader_functions(struct si_context *sctx);
bool si_init_shader_cache(struct si_screen *sscreen);
void si_destroy_shader_cache(struct si_screen *sscreen);
void si_get_active_slot_masks(const struct tgsi_shader_info *info,
uint32_t *const_and_shader_buffers,
uint64_t *samplers_and_images);
void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 6c702c0e687..80b1137fd0c 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -327,21 +327,21 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
S_028C44_DISABLE_START_OF_PRIM(1));
radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
}
-void si_emit_dpbb_state(struct si_context *sctx, struct si_atom *state)
+void si_emit_dpbb_state(struct si_context *sctx)
{
struct si_screen *sscreen = sctx->screen;
struct si_state_blend *blend = sctx->queued.named.blend;
struct si_state_dsa *dsa = sctx->queued.named.dsa;
unsigned db_shader_control = sctx->ps_db_shader_control;
assert(sctx->chip_class >= GFX9);
if (!sscreen->dpbb_allowed || !blend || !dsa) {
si_emit_dpbb_disable(sctx);
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 6f827fa45a6..9b7a4869ba5 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1173,25 +1173,23 @@ static void si_get_draw_start_count(struct si_context *sctx,
*start = info->start;
*count = info->count;
}
}
static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
unsigned skip_atom_mask)
{
/* Emit state atoms. */
unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
- while (mask) {
- struct si_atom *atom = &sctx->atoms.array[u_bit_scan(&mask)];
+ while (mask)
+ sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
- atom->emit(sctx, atom);
- }
sctx->dirty_atoms &= skip_atom_mask;
/* Emit states. */
mask = sctx->dirty_states;
while (mask) {
unsigned i = u_bit_scan(&mask);
struct si_pm4_state *state = sctx->queued.array[i];
if (!state || sctx->emitted.array[i] == state)
continue;
@@ -1439,21 +1437,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
if (!si_upload_graphics_shader_descriptors(sctx))
return;
/* Emit all states except possibly render condition. */
si_emit_all_states(sctx, info, masked_atoms);
si_emit_cache_flush(sctx);
/* <-- CUs are idle here. */
if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
- sctx->atoms.s.render_cond.emit(sctx, NULL);
+ sctx->atoms.s.render_cond.emit(sctx);
sctx->dirty_atoms = 0;
si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
/* <-- CUs are busy here. */
/* Start prefetches after the draw has been started. Both will run
* in parallel, but starting the draw first is more important.
*/
if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
cik_emit_prefetch_L2(sctx, false);
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index c073b8ddf60..943c58cbf9f 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2591,21 +2591,21 @@ static unsigned si_get_ps_input_cntl(struct si_context *sctx,
* Don't set any other bits.
* (FLAT_SHADE=1 completely changes behavior) */
ps_input_cntl = S_028644_OFFSET(0x20);
/* D3D 9 behaviour. GL is undefined */
if (name == TGSI_SEMANTIC_COLOR && index == 0)
ps_input_cntl |= S_028644_DEFAULT_VAL(3);
}
return ps_input_cntl;
}
-static void si_emit_spi_map(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_spi_map(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *ps = sctx->ps_shader.current;
struct si_shader *vs = si_get_vs_state(sctx);
struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
unsigned i, num_interp, num_written = 0, bcol_interp[2];
if (!ps || !ps->selector->info.num_inputs)
return;
@@ -3321,22 +3321,21 @@ bool si_update_shaders(struct si_context *sctx)
if (si_pm4_state_enabled_and_changed(sctx, ps))
sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
else if (!sctx->queued.named.ps)
sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
}
sctx->do_update_shaders = false;
return true;
}
-static void si_emit_scratch_state(struct si_context *sctx,
- struct si_atom *atom)
+static void si_emit_scratch_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
sctx->spi_tmpring_size);
if (sctx->scratch_buffer) {
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
sctx->scratch_buffer, RADEON_USAGE_READWRITE,
RADEON_PRIO_SCRATCH_BUFFER);
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c
index 328a0cc7a7f..3fd92889364 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -247,21 +247,21 @@ static void si_flush_vgt_streamout(struct si_context *sctx)
radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
radeon_emit(cs, 0);
radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
radeon_emit(cs, 4); /* poll interval */
}
-static void si_emit_streamout_begin(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_streamout_begin(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_streamout_target **t = sctx->streamout.targets;
uint16_t *stride_in_dw = sctx->streamout.stride_in_dw;
unsigned i;
si_flush_vgt_streamout(sctx);
for (i = 0; i < sctx->streamout.num_targets; i++) {
if (!t[i])
@@ -349,22 +349,21 @@ void si_emit_streamout_end(struct si_context *sctx)
sctx->streamout.begin_emitted = false;
}
/* STREAMOUT CONFIG DERIVED STATE
*
* Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
* The buffer mask is an independent state, so no writes occur if there
* are no buffers bound.
*/
-static void si_emit_streamout_enable(struct si_context *sctx,
- struct si_atom *atom)
+static void si_emit_streamout_enable(struct si_context *sctx)
{
radeon_set_context_reg_seq(sctx->gfx_cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
radeon_emit(sctx->gfx_cs,
S_028B94_STREAMOUT_0_EN(si_get_strmout_en(sctx)) |
S_028B94_RAST_STREAM(0) |
S_028B94_STREAMOUT_1_EN(si_get_strmout_en(sctx)) |
S_028B94_STREAMOUT_2_EN(si_get_strmout_en(sctx)) |
S_028B94_STREAMOUT_3_EN(si_get_strmout_en(sctx)));
radeon_emit(sctx->gfx_cs,
sctx->streamout.hw_enabled_mask &
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c
index a84f0e1f9f2..bffb1f91827 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -203,21 +203,21 @@ static void si_emit_guardband(struct si_context *ctx,
/* If any of the GB registers is updated, all of them must be updated. */
radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
radeon_emit(cs, fui(discard_y)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
radeon_emit(cs, fui(discard_x)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
}
-static void si_emit_scissors(struct si_context *ctx, struct si_atom *atom)
+static void si_emit_scissors(struct si_context *ctx)
{
struct radeon_winsys_cs *cs = ctx->gfx_cs;
struct pipe_scissor_state *states = ctx->scissors.states;
unsigned mask = ctx->scissors.dirty_mask;
bool scissor_enabled = false;
struct si_signed_scissor max_vp_scissor;
int i;
if (ctx->queued.named.rasterizer)
scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
@@ -375,22 +375,21 @@ static void si_emit_depth_ranges(struct si_context *ctx)
for (i = start; i < start+count; i++) {
si_viewport_zmin_zmax(&states[i], clip_halfz, window_space,
&zmin, &zmax);
radeon_emit(cs, fui(zmin));
radeon_emit(cs, fui(zmax));
}
}
ctx->viewports.depth_range_dirty_mask = 0;
}
-static void si_emit_viewport_states(struct si_context *ctx,
- struct si_atom *atom)
+static void si_emit_viewport_states(struct si_context *ctx)
{
si_emit_viewports(ctx);
si_emit_depth_ranges(ctx);
}
/**
* This reacts to 2 state changes:
* - VS.writes_viewport_index
* - VS output position in window space (enable/disable)
*
--
2.17.0
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