[Mesa-dev] [PATCH] radv: fix radv_layout_dcc_compressed() when image doesn't have DCC
Mark Janes
mark.a.janes at intel.com
Fri Apr 13 20:55:25 UTC 2018
Hi Samuel,
When this patch is applied directly to the 18.0 branch, I get a mesa
compile error:
radv_image.c:1175:9: error: implicit declaration of function
‘radv_image_has_dcc’; did you mean ‘radv_image_alloc_dcc’?
Is there another patch that this is dependent on?
-Mark
Samuel Pitoiset <samuel.pitoiset at gmail.com> writes:
> num_dcc_levels means that DCC is supported, but this doesn't
> mean that it's enabled by the driver. Instead, we should rely
> on radv_image_has_dcc().
>
> This fixes some multisample regressions since 0babc8e5d66
> ("radv: fix picking the method for resolve subpass") on Vega.
> This is because the resolve method changed from HW to FS, but
> those fails are totally unexpected, so there might some
> differences between Polaris and Vega here.
>
> Fixes: 44fcf587445 ("radv: Disable DCC for GENERAL layout and compute transfer dest.")
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
> src/amd/vulkan/radv_image.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index acb569203d4..a14e7c18b29 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -1241,7 +1241,7 @@ bool radv_layout_dcc_compressed(const struct radv_image *image,
> (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
> return false;
>
> - return image->surface.num_dcc_levels > 0 && layout != VK_IMAGE_LAYOUT_GENERAL;
> + return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
> }
>
>
> --
> 2.17.0
>
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